rustc_ast_lowering/
asm.rs

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1use std::collections::hash_map::Entry;
2use std::fmt::Write;
3
4use rustc_ast::*;
5use rustc_data_structures::fx::{FxHashMap, FxHashSet, FxIndexMap};
6use rustc_hir as hir;
7use rustc_hir::def::{DefKind, Res};
8use rustc_session::parse::feature_err;
9use rustc_span::{Span, sym};
10use rustc_target::asm;
11
12use super::LoweringContext;
13use super::errors::{
14    AbiSpecifiedMultipleTimes, AttSyntaxOnlyX86, ClobberAbiNotSupported,
15    InlineAsmUnsupportedTarget, InvalidAbiClobberAbi, InvalidAsmTemplateModifierConst,
16    InvalidAsmTemplateModifierLabel, InvalidAsmTemplateModifierRegClass,
17    InvalidAsmTemplateModifierRegClassSub, InvalidAsmTemplateModifierSym, InvalidRegister,
18    InvalidRegisterClass, RegisterClassOnlyClobber, RegisterClassOnlyClobberStable,
19    RegisterConflict,
20};
21use crate::{
22    AllowReturnTypeNotation, ImplTraitContext, ImplTraitPosition, ParamMode,
23    ResolverAstLoweringExt, fluent_generated as fluent,
24};
25
26impl<'a, 'hir> LoweringContext<'a, 'hir> {
27    pub(crate) fn lower_inline_asm(
28        &mut self,
29        sp: Span,
30        asm: &InlineAsm,
31    ) -> &'hir hir::InlineAsm<'hir> {
32        // Rustdoc needs to support asm! from foreign architectures: don't try
33        // lowering the register constraints in this case.
34        let asm_arch =
35            if self.tcx.sess.opts.actually_rustdoc { None } else { self.tcx.sess.asm_arch };
36        if asm_arch.is_none() && !self.tcx.sess.opts.actually_rustdoc {
37            self.dcx().emit_err(InlineAsmUnsupportedTarget { span: sp });
38        }
39        if let Some(asm_arch) = asm_arch {
40            // Inline assembly is currently only stable for these architectures.
41            // (See also compiletest's `has_asm_support`.)
42            let is_stable = matches!(
43                asm_arch,
44                asm::InlineAsmArch::X86
45                    | asm::InlineAsmArch::X86_64
46                    | asm::InlineAsmArch::Arm
47                    | asm::InlineAsmArch::AArch64
48                    | asm::InlineAsmArch::Arm64EC
49                    | asm::InlineAsmArch::RiscV32
50                    | asm::InlineAsmArch::RiscV64
51                    | asm::InlineAsmArch::LoongArch64
52                    | asm::InlineAsmArch::S390x
53            );
54            if !is_stable && !self.tcx.features().asm_experimental_arch() {
55                feature_err(
56                    &self.tcx.sess,
57                    sym::asm_experimental_arch,
58                    sp,
59                    fluent::ast_lowering_unstable_inline_assembly,
60                )
61                .emit();
62            }
63        }
64        let allow_experimental_reg = self.tcx.features().asm_experimental_reg();
65        if asm.options.contains(InlineAsmOptions::ATT_SYNTAX)
66            && !matches!(asm_arch, Some(asm::InlineAsmArch::X86 | asm::InlineAsmArch::X86_64))
67            && !self.tcx.sess.opts.actually_rustdoc
68        {
69            self.dcx().emit_err(AttSyntaxOnlyX86 { span: sp });
70        }
71        if asm.options.contains(InlineAsmOptions::MAY_UNWIND) && !self.tcx.features().asm_unwind() {
72            feature_err(
73                &self.tcx.sess,
74                sym::asm_unwind,
75                sp,
76                fluent::ast_lowering_unstable_may_unwind,
77            )
78            .emit();
79        }
80
81        let mut clobber_abis = FxIndexMap::default();
82        if let Some(asm_arch) = asm_arch {
83            for (abi_name, abi_span) in &asm.clobber_abis {
84                match asm::InlineAsmClobberAbi::parse(
85                    asm_arch,
86                    &self.tcx.sess.target,
87                    &self.tcx.sess.unstable_target_features,
88                    *abi_name,
89                ) {
90                    Ok(abi) => {
91                        // If the abi was already in the list, emit an error
92                        match clobber_abis.get(&abi) {
93                            Some((prev_name, prev_sp)) => {
94                                // Multiple different abi names may actually be the same ABI
95                                // If the specified ABIs are not the same name, alert the user that they resolve to the same ABI
96                                let source_map = self.tcx.sess.source_map();
97                                let equivalent = source_map.span_to_snippet(*prev_sp)
98                                    != source_map.span_to_snippet(*abi_span);
99
100                                self.dcx().emit_err(AbiSpecifiedMultipleTimes {
101                                    abi_span: *abi_span,
102                                    prev_name: *prev_name,
103                                    prev_span: *prev_sp,
104                                    equivalent,
105                                });
106                            }
107                            None => {
108                                clobber_abis.insert(abi, (*abi_name, *abi_span));
109                            }
110                        }
111                    }
112                    Err(&[]) => {
113                        self.dcx().emit_err(ClobberAbiNotSupported { abi_span: *abi_span });
114                    }
115                    Err(supported_abis) => {
116                        let mut abis = format!("`{}`", supported_abis[0]);
117                        for m in &supported_abis[1..] {
118                            let _ = write!(abis, ", `{m}`");
119                        }
120                        self.dcx().emit_err(InvalidAbiClobberAbi {
121                            abi_span: *abi_span,
122                            supported_abis: abis,
123                        });
124                    }
125                }
126            }
127        }
128
129        // Lower operands to HIR. We use dummy register classes if an error
130        // occurs during lowering because we still need to be able to produce a
131        // valid HIR.
132        let sess = self.tcx.sess;
133        let mut operands: Vec<_> = asm
134            .operands
135            .iter()
136            .map(|(op, op_sp)| {
137                let lower_reg = |&reg: &_| match reg {
138                    InlineAsmRegOrRegClass::Reg(reg) => {
139                        asm::InlineAsmRegOrRegClass::Reg(if let Some(asm_arch) = asm_arch {
140                            asm::InlineAsmReg::parse(asm_arch, reg).unwrap_or_else(|error| {
141                                self.dcx().emit_err(InvalidRegister {
142                                    op_span: *op_sp,
143                                    reg,
144                                    error,
145                                });
146                                asm::InlineAsmReg::Err
147                            })
148                        } else {
149                            asm::InlineAsmReg::Err
150                        })
151                    }
152                    InlineAsmRegOrRegClass::RegClass(reg_class) => {
153                        asm::InlineAsmRegOrRegClass::RegClass(if let Some(asm_arch) = asm_arch {
154                            asm::InlineAsmRegClass::parse(asm_arch, reg_class).unwrap_or_else(
155                                |supported_register_classes| {
156                                    let mut register_classes =
157                                        format!("`{}`", supported_register_classes[0]);
158                                    for m in &supported_register_classes[1..] {
159                                        let _ = write!(register_classes, ", `{m}`");
160                                    }
161                                    self.dcx().emit_err(InvalidRegisterClass {
162                                        op_span: *op_sp,
163                                        reg_class,
164                                        supported_register_classes: register_classes,
165                                    });
166                                    asm::InlineAsmRegClass::Err
167                                },
168                            )
169                        } else {
170                            asm::InlineAsmRegClass::Err
171                        })
172                    }
173                };
174
175                let op = match op {
176                    InlineAsmOperand::In { reg, expr } => hir::InlineAsmOperand::In {
177                        reg: lower_reg(reg),
178                        expr: self.lower_expr(expr),
179                    },
180                    InlineAsmOperand::Out { reg, late, expr } => hir::InlineAsmOperand::Out {
181                        reg: lower_reg(reg),
182                        late: *late,
183                        expr: expr.as_ref().map(|expr| self.lower_expr(expr)),
184                    },
185                    InlineAsmOperand::InOut { reg, late, expr } => hir::InlineAsmOperand::InOut {
186                        reg: lower_reg(reg),
187                        late: *late,
188                        expr: self.lower_expr(expr),
189                    },
190                    InlineAsmOperand::SplitInOut { reg, late, in_expr, out_expr } => {
191                        hir::InlineAsmOperand::SplitInOut {
192                            reg: lower_reg(reg),
193                            late: *late,
194                            in_expr: self.lower_expr(in_expr),
195                            out_expr: out_expr.as_ref().map(|expr| self.lower_expr(expr)),
196                        }
197                    }
198                    InlineAsmOperand::Const { anon_const } => hir::InlineAsmOperand::Const {
199                        anon_const: self.lower_const_block(anon_const),
200                    },
201                    InlineAsmOperand::Sym { sym } => {
202                        let static_def_id = self
203                            .resolver
204                            .get_partial_res(sym.id)
205                            .and_then(|res| res.full_res())
206                            .and_then(|res| match res {
207                                Res::Def(DefKind::Static { .. }, def_id) => Some(def_id),
208                                _ => None,
209                            });
210
211                        if let Some(def_id) = static_def_id {
212                            let path = self.lower_qpath(
213                                sym.id,
214                                &sym.qself,
215                                &sym.path,
216                                ParamMode::Optional,
217                                AllowReturnTypeNotation::No,
218                                ImplTraitContext::Disallowed(ImplTraitPosition::Path),
219                                None,
220                            );
221                            hir::InlineAsmOperand::SymStatic { path, def_id }
222                        } else {
223                            // Replace the InlineAsmSym AST node with an
224                            // Expr using the name node id.
225                            let expr = Expr {
226                                id: sym.id,
227                                kind: ExprKind::Path(sym.qself.clone(), sym.path.clone()),
228                                span: *op_sp,
229                                attrs: AttrVec::new(),
230                                tokens: None,
231                            };
232
233                            hir::InlineAsmOperand::SymFn { expr: self.lower_expr(&expr) }
234                        }
235                    }
236                    InlineAsmOperand::Label { block } => {
237                        hir::InlineAsmOperand::Label { block: self.lower_block(block, false) }
238                    }
239                };
240                (op, self.lower_span(*op_sp))
241            })
242            .collect();
243
244        // Validate template modifiers against the register classes for the operands
245        for p in &asm.template {
246            if let InlineAsmTemplatePiece::Placeholder {
247                operand_idx,
248                modifier: Some(modifier),
249                span: placeholder_span,
250            } = *p
251            {
252                let op_sp = asm.operands[operand_idx].1;
253                match &operands[operand_idx].0 {
254                    hir::InlineAsmOperand::In { reg, .. }
255                    | hir::InlineAsmOperand::Out { reg, .. }
256                    | hir::InlineAsmOperand::InOut { reg, .. }
257                    | hir::InlineAsmOperand::SplitInOut { reg, .. } => {
258                        let class = reg.reg_class();
259                        if class == asm::InlineAsmRegClass::Err {
260                            continue;
261                        }
262                        let valid_modifiers = class.valid_modifiers(asm_arch.unwrap());
263                        if !valid_modifiers.contains(&modifier) {
264                            let sub = if !valid_modifiers.is_empty() {
265                                let mut mods = format!("`{}`", valid_modifiers[0]);
266                                for m in &valid_modifiers[1..] {
267                                    let _ = write!(mods, ", `{m}`");
268                                }
269                                InvalidAsmTemplateModifierRegClassSub::SupportModifier {
270                                    class_name: class.name(),
271                                    modifiers: mods,
272                                }
273                            } else {
274                                InvalidAsmTemplateModifierRegClassSub::DoesNotSupportModifier {
275                                    class_name: class.name(),
276                                }
277                            };
278                            self.dcx().emit_err(InvalidAsmTemplateModifierRegClass {
279                                placeholder_span,
280                                op_span: op_sp,
281                                sub,
282                            });
283                        }
284                    }
285                    hir::InlineAsmOperand::Const { .. } => {
286                        self.dcx().emit_err(InvalidAsmTemplateModifierConst {
287                            placeholder_span,
288                            op_span: op_sp,
289                        });
290                    }
291                    hir::InlineAsmOperand::SymFn { .. }
292                    | hir::InlineAsmOperand::SymStatic { .. } => {
293                        self.dcx().emit_err(InvalidAsmTemplateModifierSym {
294                            placeholder_span,
295                            op_span: op_sp,
296                        });
297                    }
298                    hir::InlineAsmOperand::Label { .. } => {
299                        self.dcx().emit_err(InvalidAsmTemplateModifierLabel {
300                            placeholder_span,
301                            op_span: op_sp,
302                        });
303                    }
304                }
305            }
306        }
307
308        let mut used_input_regs = FxHashMap::default();
309        let mut used_output_regs = FxHashMap::default();
310
311        for (idx, &(ref op, op_sp)) in operands.iter().enumerate() {
312            if let Some(reg) = op.reg() {
313                let reg_class = reg.reg_class();
314                if reg_class == asm::InlineAsmRegClass::Err {
315                    continue;
316                }
317
318                // Some register classes can only be used as clobbers. This
319                // means that we disallow passing a value in/out of the asm and
320                // require that the operand name an explicit register, not a
321                // register class.
322                if reg_class.is_clobber_only(asm_arch.unwrap(), allow_experimental_reg)
323                    && !op.is_clobber()
324                {
325                    if allow_experimental_reg || reg_class.is_clobber_only(asm_arch.unwrap(), true)
326                    {
327                        // always clobber-only
328                        self.dcx().emit_err(RegisterClassOnlyClobber {
329                            op_span: op_sp,
330                            reg_class_name: reg_class.name(),
331                        });
332                    } else {
333                        // clobber-only in stable
334                        self.tcx
335                            .sess
336                            .create_feature_err(
337                                RegisterClassOnlyClobberStable {
338                                    op_span: op_sp,
339                                    reg_class_name: reg_class.name(),
340                                },
341                                sym::asm_experimental_reg,
342                            )
343                            .emit();
344                    }
345                    continue;
346                }
347
348                // Check for conflicts between explicit register operands.
349                if let asm::InlineAsmRegOrRegClass::Reg(reg) = reg {
350                    let (input, output) = match op {
351                        hir::InlineAsmOperand::In { .. } => (true, false),
352
353                        // Late output do not conflict with inputs, but normal outputs do
354                        hir::InlineAsmOperand::Out { late, .. } => (!late, true),
355
356                        hir::InlineAsmOperand::InOut { .. }
357                        | hir::InlineAsmOperand::SplitInOut { .. } => (true, true),
358
359                        hir::InlineAsmOperand::Const { .. }
360                        | hir::InlineAsmOperand::SymFn { .. }
361                        | hir::InlineAsmOperand::SymStatic { .. }
362                        | hir::InlineAsmOperand::Label { .. } => {
363                            unreachable!("{op:?} is not a register operand");
364                        }
365                    };
366
367                    // Flag to output the error only once per operand
368                    let mut skip = false;
369
370                    let mut check = |used_regs: &mut FxHashMap<asm::InlineAsmReg, usize>,
371                                     input,
372                                     r: asm::InlineAsmReg| {
373                        match used_regs.entry(r) {
374                            Entry::Occupied(o) => {
375                                if skip {
376                                    return;
377                                }
378                                skip = true;
379
380                                let idx2 = *o.get();
381                                let (ref op2, op_sp2) = operands[idx2];
382
383                                let in_out = match (op, op2) {
384                                    (
385                                        hir::InlineAsmOperand::In { .. },
386                                        hir::InlineAsmOperand::Out { late, .. },
387                                    )
388                                    | (
389                                        hir::InlineAsmOperand::Out { late, .. },
390                                        hir::InlineAsmOperand::In { .. },
391                                    ) => {
392                                        assert!(!*late);
393                                        let out_op_sp = if input { op_sp2 } else { op_sp };
394                                        Some(out_op_sp)
395                                    }
396                                    _ => None,
397                                };
398                                let reg_str = |idx| -> &str {
399                                    // HIR asm doesn't preserve the original alias string of the explicit register,
400                                    // so we have to retrieve it from AST
401                                    let (op, _): &(InlineAsmOperand, Span) = &asm.operands[idx];
402                                    if let Some(ast::InlineAsmRegOrRegClass::Reg(reg_sym)) =
403                                        op.reg()
404                                    {
405                                        reg_sym.as_str()
406                                    } else {
407                                        unreachable!("{op:?} is not a register operand");
408                                    }
409                                };
410
411                                self.dcx().emit_err(RegisterConflict {
412                                    op_span1: op_sp,
413                                    op_span2: op_sp2,
414                                    reg1_name: reg_str(idx),
415                                    reg2_name: reg_str(idx2),
416                                    in_out,
417                                });
418                            }
419                            Entry::Vacant(v) => {
420                                if r == reg {
421                                    v.insert(idx);
422                                }
423                            }
424                        }
425                    };
426                    let mut overlapping_with = vec![];
427                    reg.overlapping_regs(|r| {
428                        overlapping_with.push(r);
429                    });
430                    for r in overlapping_with {
431                        if input {
432                            check(&mut used_input_regs, true, r);
433                        }
434                        if output {
435                            check(&mut used_output_regs, false, r);
436                        }
437                    }
438                }
439            }
440        }
441
442        // If a clobber_abi is specified, add the necessary clobbers to the
443        // operands list.
444        let mut clobbered = FxHashSet::default();
445        for (abi, (_, abi_span)) in clobber_abis {
446            for &clobber in abi.clobbered_regs() {
447                // Don't emit a clobber for a register already clobbered
448                if clobbered.contains(&clobber) {
449                    continue;
450                }
451
452                let mut overlapping_with = vec![];
453                clobber.overlapping_regs(|reg| {
454                    overlapping_with.push(reg);
455                });
456                let output_used =
457                    overlapping_with.iter().any(|reg| used_output_regs.contains_key(&reg));
458
459                if !output_used {
460                    operands.push((
461                        hir::InlineAsmOperand::Out {
462                            reg: asm::InlineAsmRegOrRegClass::Reg(clobber),
463                            late: true,
464                            expr: None,
465                        },
466                        self.lower_span(abi_span),
467                    ));
468                    clobbered.insert(clobber);
469                }
470            }
471        }
472
473        // Feature gate checking for `asm_goto_with_outputs`.
474        if let Some((_, op_sp)) =
475            operands.iter().find(|(op, _)| matches!(op, hir::InlineAsmOperand::Label { .. }))
476        {
477            // Check if an output operand is used.
478            let output_operand_used = operands.iter().any(|(op, _)| {
479                matches!(
480                    op,
481                    hir::InlineAsmOperand::Out { expr: Some(_), .. }
482                        | hir::InlineAsmOperand::InOut { .. }
483                        | hir::InlineAsmOperand::SplitInOut { out_expr: Some(_), .. }
484                )
485            });
486            if output_operand_used && !self.tcx.features().asm_goto_with_outputs() {
487                feature_err(
488                    sess,
489                    sym::asm_goto_with_outputs,
490                    *op_sp,
491                    fluent::ast_lowering_unstable_inline_assembly_label_operand_with_outputs,
492                )
493                .emit();
494            }
495        }
496
497        let operands = self.arena.alloc_from_iter(operands);
498        let template = self.arena.alloc_from_iter(asm.template.iter().cloned());
499        let template_strs = self.arena.alloc_from_iter(
500            asm.template_strs
501                .iter()
502                .map(|(sym, snippet, span)| (*sym, *snippet, self.lower_span(*span))),
503        );
504        let line_spans =
505            self.arena.alloc_from_iter(asm.line_spans.iter().map(|span| self.lower_span(*span)));
506        let hir_asm = hir::InlineAsm {
507            asm_macro: asm.asm_macro,
508            template,
509            template_strs,
510            operands,
511            options: asm.options,
512            line_spans,
513        };
514        self.arena.alloc(hir_asm)
515    }
516}
rustc_ast_lowering/asm.rs

rustc_ast_lowering/
asm.rs
