1use std::fmt;
2
3use rustc_span::Symbol;
4
5use super::{InlineAsmArch, InlineAsmType, ModifierInfo};
6
7#[allow(non_camel_case_types)]
pub enum HexagonInlineAsmRegClass { reg, preg, }
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::marker::Copy for HexagonInlineAsmRegClass { }
#[automatically_derived]
#[doc(hidden)]
#[allow(non_camel_case_types)]
unsafe impl ::core::clone::TrivialClone for HexagonInlineAsmRegClass { }
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::clone::Clone for HexagonInlineAsmRegClass {
#[inline]
fn clone(&self) -> HexagonInlineAsmRegClass { *self }
}
const _: () =
{
impl<__E: ::rustc_span::SpanEncoder> ::rustc_serialize::Encodable<__E>
for HexagonInlineAsmRegClass {
fn encode(&self, __encoder: &mut __E) {
let disc =
match *self {
HexagonInlineAsmRegClass::reg => { 0usize }
HexagonInlineAsmRegClass::preg => { 1usize }
};
::rustc_serialize::Encoder::emit_u8(__encoder, disc as u8);
match *self {
HexagonInlineAsmRegClass::reg => {}
HexagonInlineAsmRegClass::preg => {}
}
}
}
};
const _: () =
{
impl<__D: ::rustc_span::SpanDecoder> ::rustc_serialize::Decodable<__D>
for HexagonInlineAsmRegClass {
fn decode(__decoder: &mut __D) -> Self {
match ::rustc_serialize::Decoder::read_u8(__decoder) as usize
{
0usize => { HexagonInlineAsmRegClass::reg }
1usize => { HexagonInlineAsmRegClass::preg }
n => {
::core::panicking::panic_fmt(format_args!("invalid enum variant tag while decoding `HexagonInlineAsmRegClass`, expected 0..2, actual {0}",
n));
}
}
}
}
};
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::fmt::Debug for HexagonInlineAsmRegClass {
#[inline]
fn fmt(&self, f: &mut ::core::fmt::Formatter) -> ::core::fmt::Result {
::core::fmt::Formatter::write_str(f,
match self {
HexagonInlineAsmRegClass::reg => "reg",
HexagonInlineAsmRegClass::preg => "preg",
})
}
}
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::cmp::Eq for HexagonInlineAsmRegClass {
#[inline]
#[doc(hidden)]
#[coverage(off)]
fn assert_receiver_is_total_eq(&self) {}
}
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::marker::StructuralPartialEq for HexagonInlineAsmRegClass { }
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::cmp::PartialEq for HexagonInlineAsmRegClass {
#[inline]
fn eq(&self, other: &HexagonInlineAsmRegClass) -> bool {
let __self_discr = ::core::intrinsics::discriminant_value(self);
let __arg1_discr = ::core::intrinsics::discriminant_value(other);
__self_discr == __arg1_discr
}
}
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::cmp::PartialOrd for HexagonInlineAsmRegClass {
#[inline]
fn partial_cmp(&self, other: &HexagonInlineAsmRegClass)
-> ::core::option::Option<::core::cmp::Ordering> {
let __self_discr = ::core::intrinsics::discriminant_value(self);
let __arg1_discr = ::core::intrinsics::discriminant_value(other);
::core::cmp::PartialOrd::partial_cmp(&__self_discr, &__arg1_discr)
}
}
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::hash::Hash for HexagonInlineAsmRegClass {
#[inline]
fn hash<__H: ::core::hash::Hasher>(&self, state: &mut __H) {
let __self_discr = ::core::intrinsics::discriminant_value(self);
::core::hash::Hash::hash(&__self_discr, state)
}
}
const _: () =
{
impl<__CTX> ::rustc_data_structures::stable_hasher::HashStable<__CTX>
for HexagonInlineAsmRegClass where __CTX: crate::HashStableContext
{
#[inline]
fn hash_stable(&self, __hcx: &mut __CTX,
__hasher:
&mut ::rustc_data_structures::stable_hasher::StableHasher) {
::std::mem::discriminant(self).hash_stable(__hcx, __hasher);
match *self {
HexagonInlineAsmRegClass::reg => {}
HexagonInlineAsmRegClass::preg => {}
}
}
}
};
impl HexagonInlineAsmRegClass {
pub fn name(self) -> rustc_span::Symbol {
match self {
Self::reg => rustc_span::sym::reg,
Self::preg => rustc_span::sym::preg,
}
}
pub fn parse(name: rustc_span::Symbol)
-> Result<Self, &'static [rustc_span::Symbol]> {
match name {
rustc_span::sym::reg => Ok(Self::reg),
rustc_span::sym::preg => Ok(Self::preg),
_ => Err(&[rustc_span::sym::reg, rustc_span::sym::preg]),
}
}
}
pub(super) fn regclass_map()
->
rustc_data_structures::fx::FxHashMap<super::InlineAsmRegClass,
rustc_data_structures::fx::FxIndexSet<super::InlineAsmReg>> {
use rustc_data_structures::fx::FxHashMap;
use rustc_data_structures::fx::FxIndexSet;
use super::InlineAsmRegClass;
let mut map = FxHashMap::default();
map.insert(InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg),
FxIndexSet::default());
map.insert(InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::preg),
FxIndexSet::default());
map
}def_reg_class! {
8 Hexagon HexagonInlineAsmRegClass {
9 reg,
10 preg,
11 }
12}
13
14impl HexagonInlineAsmRegClass {
15 pub fn valid_modifiers(self, _arch: super::InlineAsmArch) -> &'static [char] {
16 &[]
17 }
18
19 pub fn suggest_class(self, _arch: InlineAsmArch, _ty: InlineAsmType) -> Option<Self> {
20 None
21 }
22
23 pub fn suggest_modifier(
24 self,
25 _arch: InlineAsmArch,
26 _ty: InlineAsmType,
27 ) -> Option<ModifierInfo> {
28 None
29 }
30
31 pub fn default_modifier(self, _arch: InlineAsmArch) -> Option<ModifierInfo> {
32 None
33 }
34
35 pub fn supported_types(
36 self,
37 _arch: InlineAsmArch,
38 ) -> &'static [(InlineAsmType, Option<Symbol>)] {
39 match self {
40 Self::reg => {
use super::InlineAsmType::*;
&[(I8, None), (I16, None), (I32, None), (F32, None)]
}types! { _: I8, I16, I32, F32; },
41 Self::preg => &[],
42 }
43 }
44}
45
46#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
pub enum HexagonInlineAsmReg {
r0,
r1,
r2,
r3,
r4,
r5,
r6,
r7,
r8,
r9,
r10,
r11,
r12,
r13,
r14,
r15,
r16,
r17,
r18,
r20,
r21,
r22,
r23,
r24,
r25,
r26,
r27,
r28,
p0,
p1,
p2,
p3,
}
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::marker::Copy for HexagonInlineAsmReg { }
#[automatically_derived]
#[doc(hidden)]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
unsafe impl ::core::clone::TrivialClone for HexagonInlineAsmReg { }
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::clone::Clone for HexagonInlineAsmReg {
#[inline]
fn clone(&self) -> HexagonInlineAsmReg { *self }
}
const _: () =
{
impl<__E: ::rustc_span::SpanEncoder> ::rustc_serialize::Encodable<__E>
for HexagonInlineAsmReg {
fn encode(&self, __encoder: &mut __E) {
let disc =
match *self {
HexagonInlineAsmReg::r0 => { 0usize }
HexagonInlineAsmReg::r1 => { 1usize }
HexagonInlineAsmReg::r2 => { 2usize }
HexagonInlineAsmReg::r3 => { 3usize }
HexagonInlineAsmReg::r4 => { 4usize }
HexagonInlineAsmReg::r5 => { 5usize }
HexagonInlineAsmReg::r6 => { 6usize }
HexagonInlineAsmReg::r7 => { 7usize }
HexagonInlineAsmReg::r8 => { 8usize }
HexagonInlineAsmReg::r9 => { 9usize }
HexagonInlineAsmReg::r10 => { 10usize }
HexagonInlineAsmReg::r11 => { 11usize }
HexagonInlineAsmReg::r12 => { 12usize }
HexagonInlineAsmReg::r13 => { 13usize }
HexagonInlineAsmReg::r14 => { 14usize }
HexagonInlineAsmReg::r15 => { 15usize }
HexagonInlineAsmReg::r16 => { 16usize }
HexagonInlineAsmReg::r17 => { 17usize }
HexagonInlineAsmReg::r18 => { 18usize }
HexagonInlineAsmReg::r20 => { 19usize }
HexagonInlineAsmReg::r21 => { 20usize }
HexagonInlineAsmReg::r22 => { 21usize }
HexagonInlineAsmReg::r23 => { 22usize }
HexagonInlineAsmReg::r24 => { 23usize }
HexagonInlineAsmReg::r25 => { 24usize }
HexagonInlineAsmReg::r26 => { 25usize }
HexagonInlineAsmReg::r27 => { 26usize }
HexagonInlineAsmReg::r28 => { 27usize }
HexagonInlineAsmReg::p0 => { 28usize }
HexagonInlineAsmReg::p1 => { 29usize }
HexagonInlineAsmReg::p2 => { 30usize }
HexagonInlineAsmReg::p3 => { 31usize }
};
::rustc_serialize::Encoder::emit_u8(__encoder, disc as u8);
match *self {
HexagonInlineAsmReg::r0 => {}
HexagonInlineAsmReg::r1 => {}
HexagonInlineAsmReg::r2 => {}
HexagonInlineAsmReg::r3 => {}
HexagonInlineAsmReg::r4 => {}
HexagonInlineAsmReg::r5 => {}
HexagonInlineAsmReg::r6 => {}
HexagonInlineAsmReg::r7 => {}
HexagonInlineAsmReg::r8 => {}
HexagonInlineAsmReg::r9 => {}
HexagonInlineAsmReg::r10 => {}
HexagonInlineAsmReg::r11 => {}
HexagonInlineAsmReg::r12 => {}
HexagonInlineAsmReg::r13 => {}
HexagonInlineAsmReg::r14 => {}
HexagonInlineAsmReg::r15 => {}
HexagonInlineAsmReg::r16 => {}
HexagonInlineAsmReg::r17 => {}
HexagonInlineAsmReg::r18 => {}
HexagonInlineAsmReg::r20 => {}
HexagonInlineAsmReg::r21 => {}
HexagonInlineAsmReg::r22 => {}
HexagonInlineAsmReg::r23 => {}
HexagonInlineAsmReg::r24 => {}
HexagonInlineAsmReg::r25 => {}
HexagonInlineAsmReg::r26 => {}
HexagonInlineAsmReg::r27 => {}
HexagonInlineAsmReg::r28 => {}
HexagonInlineAsmReg::p0 => {}
HexagonInlineAsmReg::p1 => {}
HexagonInlineAsmReg::p2 => {}
HexagonInlineAsmReg::p3 => {}
}
}
}
};
const _: () =
{
impl<__D: ::rustc_span::SpanDecoder> ::rustc_serialize::Decodable<__D>
for HexagonInlineAsmReg {
fn decode(__decoder: &mut __D) -> Self {
match ::rustc_serialize::Decoder::read_u8(__decoder) as usize
{
0usize => { HexagonInlineAsmReg::r0 }
1usize => { HexagonInlineAsmReg::r1 }
2usize => { HexagonInlineAsmReg::r2 }
3usize => { HexagonInlineAsmReg::r3 }
4usize => { HexagonInlineAsmReg::r4 }
5usize => { HexagonInlineAsmReg::r5 }
6usize => { HexagonInlineAsmReg::r6 }
7usize => { HexagonInlineAsmReg::r7 }
8usize => { HexagonInlineAsmReg::r8 }
9usize => { HexagonInlineAsmReg::r9 }
10usize => { HexagonInlineAsmReg::r10 }
11usize => { HexagonInlineAsmReg::r11 }
12usize => { HexagonInlineAsmReg::r12 }
13usize => { HexagonInlineAsmReg::r13 }
14usize => { HexagonInlineAsmReg::r14 }
15usize => { HexagonInlineAsmReg::r15 }
16usize => { HexagonInlineAsmReg::r16 }
17usize => { HexagonInlineAsmReg::r17 }
18usize => { HexagonInlineAsmReg::r18 }
19usize => { HexagonInlineAsmReg::r20 }
20usize => { HexagonInlineAsmReg::r21 }
21usize => { HexagonInlineAsmReg::r22 }
22usize => { HexagonInlineAsmReg::r23 }
23usize => { HexagonInlineAsmReg::r24 }
24usize => { HexagonInlineAsmReg::r25 }
25usize => { HexagonInlineAsmReg::r26 }
26usize => { HexagonInlineAsmReg::r27 }
27usize => { HexagonInlineAsmReg::r28 }
28usize => { HexagonInlineAsmReg::p0 }
29usize => { HexagonInlineAsmReg::p1 }
30usize => { HexagonInlineAsmReg::p2 }
31usize => { HexagonInlineAsmReg::p3 }
n => {
::core::panicking::panic_fmt(format_args!("invalid enum variant tag while decoding `HexagonInlineAsmReg`, expected 0..32, actual {0}",
n));
}
}
}
}
};
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::fmt::Debug for HexagonInlineAsmReg {
#[inline]
fn fmt(&self, f: &mut ::core::fmt::Formatter) -> ::core::fmt::Result {
::core::fmt::Formatter::write_str(f,
match self {
HexagonInlineAsmReg::r0 => "r0",
HexagonInlineAsmReg::r1 => "r1",
HexagonInlineAsmReg::r2 => "r2",
HexagonInlineAsmReg::r3 => "r3",
HexagonInlineAsmReg::r4 => "r4",
HexagonInlineAsmReg::r5 => "r5",
HexagonInlineAsmReg::r6 => "r6",
HexagonInlineAsmReg::r7 => "r7",
HexagonInlineAsmReg::r8 => "r8",
HexagonInlineAsmReg::r9 => "r9",
HexagonInlineAsmReg::r10 => "r10",
HexagonInlineAsmReg::r11 => "r11",
HexagonInlineAsmReg::r12 => "r12",
HexagonInlineAsmReg::r13 => "r13",
HexagonInlineAsmReg::r14 => "r14",
HexagonInlineAsmReg::r15 => "r15",
HexagonInlineAsmReg::r16 => "r16",
HexagonInlineAsmReg::r17 => "r17",
HexagonInlineAsmReg::r18 => "r18",
HexagonInlineAsmReg::r20 => "r20",
HexagonInlineAsmReg::r21 => "r21",
HexagonInlineAsmReg::r22 => "r22",
HexagonInlineAsmReg::r23 => "r23",
HexagonInlineAsmReg::r24 => "r24",
HexagonInlineAsmReg::r25 => "r25",
HexagonInlineAsmReg::r26 => "r26",
HexagonInlineAsmReg::r27 => "r27",
HexagonInlineAsmReg::r28 => "r28",
HexagonInlineAsmReg::p0 => "p0",
HexagonInlineAsmReg::p1 => "p1",
HexagonInlineAsmReg::p2 => "p2",
HexagonInlineAsmReg::p3 => "p3",
})
}
}
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::cmp::Eq for HexagonInlineAsmReg {
#[inline]
#[doc(hidden)]
#[coverage(off)]
fn assert_receiver_is_total_eq(&self) {}
}
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::marker::StructuralPartialEq for HexagonInlineAsmReg { }
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::cmp::PartialEq for HexagonInlineAsmReg {
#[inline]
fn eq(&self, other: &HexagonInlineAsmReg) -> bool {
let __self_discr = ::core::intrinsics::discriminant_value(self);
let __arg1_discr = ::core::intrinsics::discriminant_value(other);
__self_discr == __arg1_discr
}
}
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::cmp::PartialOrd for HexagonInlineAsmReg {
#[inline]
fn partial_cmp(&self, other: &HexagonInlineAsmReg)
-> ::core::option::Option<::core::cmp::Ordering> {
let __self_discr = ::core::intrinsics::discriminant_value(self);
let __arg1_discr = ::core::intrinsics::discriminant_value(other);
::core::cmp::PartialOrd::partial_cmp(&__self_discr, &__arg1_discr)
}
}
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::hash::Hash for HexagonInlineAsmReg {
#[inline]
fn hash<__H: ::core::hash::Hasher>(&self, state: &mut __H) {
let __self_discr = ::core::intrinsics::discriminant_value(self);
::core::hash::Hash::hash(&__self_discr, state)
}
}
const _: () =
{
impl<__CTX> ::rustc_data_structures::stable_hasher::HashStable<__CTX>
for HexagonInlineAsmReg where __CTX: crate::HashStableContext {
#[inline]
fn hash_stable(&self, __hcx: &mut __CTX,
__hasher:
&mut ::rustc_data_structures::stable_hasher::StableHasher) {
::std::mem::discriminant(self).hash_stable(__hcx, __hasher);
match *self {
HexagonInlineAsmReg::r0 => {}
HexagonInlineAsmReg::r1 => {}
HexagonInlineAsmReg::r2 => {}
HexagonInlineAsmReg::r3 => {}
HexagonInlineAsmReg::r4 => {}
HexagonInlineAsmReg::r5 => {}
HexagonInlineAsmReg::r6 => {}
HexagonInlineAsmReg::r7 => {}
HexagonInlineAsmReg::r8 => {}
HexagonInlineAsmReg::r9 => {}
HexagonInlineAsmReg::r10 => {}
HexagonInlineAsmReg::r11 => {}
HexagonInlineAsmReg::r12 => {}
HexagonInlineAsmReg::r13 => {}
HexagonInlineAsmReg::r14 => {}
HexagonInlineAsmReg::r15 => {}
HexagonInlineAsmReg::r16 => {}
HexagonInlineAsmReg::r17 => {}
HexagonInlineAsmReg::r18 => {}
HexagonInlineAsmReg::r20 => {}
HexagonInlineAsmReg::r21 => {}
HexagonInlineAsmReg::r22 => {}
HexagonInlineAsmReg::r23 => {}
HexagonInlineAsmReg::r24 => {}
HexagonInlineAsmReg::r25 => {}
HexagonInlineAsmReg::r26 => {}
HexagonInlineAsmReg::r27 => {}
HexagonInlineAsmReg::r28 => {}
HexagonInlineAsmReg::p0 => {}
HexagonInlineAsmReg::p1 => {}
HexagonInlineAsmReg::p2 => {}
HexagonInlineAsmReg::p3 => {}
}
}
}
};
impl HexagonInlineAsmReg {
pub fn name(self) -> &'static str {
match self {
Self::r0 => "r0",
Self::r1 => "r1",
Self::r2 => "r2",
Self::r3 => "r3",
Self::r4 => "r4",
Self::r5 => "r5",
Self::r6 => "r6",
Self::r7 => "r7",
Self::r8 => "r8",
Self::r9 => "r9",
Self::r10 => "r10",
Self::r11 => "r11",
Self::r12 => "r12",
Self::r13 => "r13",
Self::r14 => "r14",
Self::r15 => "r15",
Self::r16 => "r16",
Self::r17 => "r17",
Self::r18 => "r18",
Self::r20 => "r20",
Self::r21 => "r21",
Self::r22 => "r22",
Self::r23 => "r23",
Self::r24 => "r24",
Self::r25 => "r25",
Self::r26 => "r26",
Self::r27 => "r27",
Self::r28 => "r28",
Self::p0 => "p0",
Self::p1 => "p1",
Self::p2 => "p2",
Self::p3 => "p3",
}
}
pub fn reg_class(self) -> HexagonInlineAsmRegClass {
match self {
Self::r0 => HexagonInlineAsmRegClass::reg,
Self::r1 => HexagonInlineAsmRegClass::reg,
Self::r2 => HexagonInlineAsmRegClass::reg,
Self::r3 => HexagonInlineAsmRegClass::reg,
Self::r4 => HexagonInlineAsmRegClass::reg,
Self::r5 => HexagonInlineAsmRegClass::reg,
Self::r6 => HexagonInlineAsmRegClass::reg,
Self::r7 => HexagonInlineAsmRegClass::reg,
Self::r8 => HexagonInlineAsmRegClass::reg,
Self::r9 => HexagonInlineAsmRegClass::reg,
Self::r10 => HexagonInlineAsmRegClass::reg,
Self::r11 => HexagonInlineAsmRegClass::reg,
Self::r12 => HexagonInlineAsmRegClass::reg,
Self::r13 => HexagonInlineAsmRegClass::reg,
Self::r14 => HexagonInlineAsmRegClass::reg,
Self::r15 => HexagonInlineAsmRegClass::reg,
Self::r16 => HexagonInlineAsmRegClass::reg,
Self::r17 => HexagonInlineAsmRegClass::reg,
Self::r18 => HexagonInlineAsmRegClass::reg,
Self::r20 => HexagonInlineAsmRegClass::reg,
Self::r21 => HexagonInlineAsmRegClass::reg,
Self::r22 => HexagonInlineAsmRegClass::reg,
Self::r23 => HexagonInlineAsmRegClass::reg,
Self::r24 => HexagonInlineAsmRegClass::reg,
Self::r25 => HexagonInlineAsmRegClass::reg,
Self::r26 => HexagonInlineAsmRegClass::reg,
Self::r27 => HexagonInlineAsmRegClass::reg,
Self::r28 => HexagonInlineAsmRegClass::reg,
Self::p0 => HexagonInlineAsmRegClass::preg,
Self::p1 => HexagonInlineAsmRegClass::preg,
Self::p2 => HexagonInlineAsmRegClass::preg,
Self::p3 => HexagonInlineAsmRegClass::preg,
}
}
pub fn parse(name: &str) -> Result<Self, &'static str> {
match name {
"r0" => Ok(Self::r0),
"r1" => Ok(Self::r1),
"r2" => Ok(Self::r2),
"r3" => Ok(Self::r3),
"r4" => Ok(Self::r4),
"r5" => Ok(Self::r5),
"r6" => Ok(Self::r6),
"r7" => Ok(Self::r7),
"r8" => Ok(Self::r8),
"r9" => Ok(Self::r9),
"r10" => Ok(Self::r10),
"r11" => Ok(Self::r11),
"r12" => Ok(Self::r12),
"r13" => Ok(Self::r13),
"r14" => Ok(Self::r14),
"r15" => Ok(Self::r15),
"r16" => Ok(Self::r16),
"r17" => Ok(Self::r17),
"r18" => Ok(Self::r18),
"r20" => Ok(Self::r20),
"r21" => Ok(Self::r21),
"r22" => Ok(Self::r22),
"r23" => Ok(Self::r23),
"r24" => Ok(Self::r24),
"r25" => Ok(Self::r25),
"r26" => Ok(Self::r26),
"r27" => Ok(Self::r27),
"r28" => Ok(Self::r28),
"p0" => Ok(Self::p0),
"p1" => Ok(Self::p1),
"p2" => Ok(Self::p2),
"p3" => Ok(Self::p3),
"r19" =>
Err("r19 is used internally by LLVM and cannot be used as an operand for inline asm"),
"r29" | "sp" =>
Err("the stack pointer cannot be used as an operand for inline asm"),
"r30" | "fr" =>
Err("the frame register cannot be used as an operand for inline asm"),
"r31" | "lr" =>
Err("the link register cannot be used as an operand for inline asm"),
_ => Err("unknown register"),
}
}
pub fn validate(self, _arch: super::InlineAsmArch,
_reloc_model: crate::spec::RelocModel,
_target_features: &rustc_data_structures::fx::FxIndexSet<Symbol>,
_target: &crate::spec::Target, _is_clobber: bool)
-> Result<(), &'static str> {
match self {
Self::r0 => { Ok(()) }
Self::r1 => { Ok(()) }
Self::r2 => { Ok(()) }
Self::r3 => { Ok(()) }
Self::r4 => { Ok(()) }
Self::r5 => { Ok(()) }
Self::r6 => { Ok(()) }
Self::r7 => { Ok(()) }
Self::r8 => { Ok(()) }
Self::r9 => { Ok(()) }
Self::r10 => { Ok(()) }
Self::r11 => { Ok(()) }
Self::r12 => { Ok(()) }
Self::r13 => { Ok(()) }
Self::r14 => { Ok(()) }
Self::r15 => { Ok(()) }
Self::r16 => { Ok(()) }
Self::r17 => { Ok(()) }
Self::r18 => { Ok(()) }
Self::r20 => { Ok(()) }
Self::r21 => { Ok(()) }
Self::r22 => { Ok(()) }
Self::r23 => { Ok(()) }
Self::r24 => { Ok(()) }
Self::r25 => { Ok(()) }
Self::r26 => { Ok(()) }
Self::r27 => { Ok(()) }
Self::r28 => { Ok(()) }
Self::p0 => { Ok(()) }
Self::p1 => { Ok(()) }
Self::p2 => { Ok(()) }
Self::p3 => { Ok(()) }
}
}
}
pub(super) fn fill_reg_map(_arch: super::InlineAsmArch,
_reloc_model: crate::spec::RelocModel,
_target_features: &rustc_data_structures::fx::FxIndexSet<Symbol>,
_target: &crate::spec::Target,
_map:
&mut rustc_data_structures::fx::FxHashMap<super::InlineAsmRegClass,
rustc_data_structures::fx::FxIndexSet<super::InlineAsmReg>>) {
#[allow(unused_imports)]
use super::{InlineAsmReg, InlineAsmRegClass};
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg))
{
set.insert(InlineAsmReg::Hexagon(HexagonInlineAsmReg::r0));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg))
{
set.insert(InlineAsmReg::Hexagon(HexagonInlineAsmReg::r1));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg))
{
set.insert(InlineAsmReg::Hexagon(HexagonInlineAsmReg::r2));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg))
{
set.insert(InlineAsmReg::Hexagon(HexagonInlineAsmReg::r3));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg))
{
set.insert(InlineAsmReg::Hexagon(HexagonInlineAsmReg::r4));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg))
{
set.insert(InlineAsmReg::Hexagon(HexagonInlineAsmReg::r5));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg))
{
set.insert(InlineAsmReg::Hexagon(HexagonInlineAsmReg::r6));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg))
{
set.insert(InlineAsmReg::Hexagon(HexagonInlineAsmReg::r7));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg))
{
set.insert(InlineAsmReg::Hexagon(HexagonInlineAsmReg::r8));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg))
{
set.insert(InlineAsmReg::Hexagon(HexagonInlineAsmReg::r9));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg))
{
set.insert(InlineAsmReg::Hexagon(HexagonInlineAsmReg::r10));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg))
{
set.insert(InlineAsmReg::Hexagon(HexagonInlineAsmReg::r11));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg))
{
set.insert(InlineAsmReg::Hexagon(HexagonInlineAsmReg::r12));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg))
{
set.insert(InlineAsmReg::Hexagon(HexagonInlineAsmReg::r13));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg))
{
set.insert(InlineAsmReg::Hexagon(HexagonInlineAsmReg::r14));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg))
{
set.insert(InlineAsmReg::Hexagon(HexagonInlineAsmReg::r15));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg))
{
set.insert(InlineAsmReg::Hexagon(HexagonInlineAsmReg::r16));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg))
{
set.insert(InlineAsmReg::Hexagon(HexagonInlineAsmReg::r17));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg))
{
set.insert(InlineAsmReg::Hexagon(HexagonInlineAsmReg::r18));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg))
{
set.insert(InlineAsmReg::Hexagon(HexagonInlineAsmReg::r20));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg))
{
set.insert(InlineAsmReg::Hexagon(HexagonInlineAsmReg::r21));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg))
{
set.insert(InlineAsmReg::Hexagon(HexagonInlineAsmReg::r22));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg))
{
set.insert(InlineAsmReg::Hexagon(HexagonInlineAsmReg::r23));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg))
{
set.insert(InlineAsmReg::Hexagon(HexagonInlineAsmReg::r24));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg))
{
set.insert(InlineAsmReg::Hexagon(HexagonInlineAsmReg::r25));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg))
{
set.insert(InlineAsmReg::Hexagon(HexagonInlineAsmReg::r26));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg))
{
set.insert(InlineAsmReg::Hexagon(HexagonInlineAsmReg::r27));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg))
{
set.insert(InlineAsmReg::Hexagon(HexagonInlineAsmReg::r28));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::preg))
{
set.insert(InlineAsmReg::Hexagon(HexagonInlineAsmReg::p0));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::preg))
{
set.insert(InlineAsmReg::Hexagon(HexagonInlineAsmReg::p1));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::preg))
{
set.insert(InlineAsmReg::Hexagon(HexagonInlineAsmReg::p2));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::preg))
{
set.insert(InlineAsmReg::Hexagon(HexagonInlineAsmReg::p3));
}
}
}def_regs! {
47 Hexagon HexagonInlineAsmReg HexagonInlineAsmRegClass {
48 r0: reg = ["r0"],
49 r1: reg = ["r1"],
50 r2: reg = ["r2"],
51 r3: reg = ["r3"],
52 r4: reg = ["r4"],
53 r5: reg = ["r5"],
54 r6: reg = ["r6"],
55 r7: reg = ["r7"],
56 r8: reg = ["r8"],
57 r9: reg = ["r9"],
58 r10: reg = ["r10"],
59 r11: reg = ["r11"],
60 r12: reg = ["r12"],
61 r13: reg = ["r13"],
62 r14: reg = ["r14"],
63 r15: reg = ["r15"],
64 r16: reg = ["r16"],
65 r17: reg = ["r17"],
66 r18: reg = ["r18"],
67 r20: reg = ["r20"],
68 r21: reg = ["r21"],
69 r22: reg = ["r22"],
70 r23: reg = ["r23"],
71 r24: reg = ["r24"],
72 r25: reg = ["r25"],
73 r26: reg = ["r26"],
74 r27: reg = ["r27"],
75 r28: reg = ["r28"],
76 p0: preg = ["p0"],
77 p1: preg = ["p1"],
78 p2: preg = ["p2"],
79 p3: preg = ["p3"],
80 #error = ["r19"] =>
81 "r19 is used internally by LLVM and cannot be used as an operand for inline asm",
82 #error = ["r29", "sp"] =>
83 "the stack pointer cannot be used as an operand for inline asm",
84 #error = ["r30", "fr"] =>
85 "the frame register cannot be used as an operand for inline asm",
86 #error = ["r31", "lr"] =>
87 "the link register cannot be used as an operand for inline asm",
88 }
89}
90
91impl HexagonInlineAsmReg {
92 pub fn emit(
93 self,
94 out: &mut dyn fmt::Write,
95 _arch: InlineAsmArch,
96 _modifier: Option<char>,
97 ) -> fmt::Result {
98 out.write_str(self.name())
99 }
100
101 pub fn overlapping_regs(self, mut _cb: impl FnMut(HexagonInlineAsmReg)) {}
102}