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rustc_target/asm/
avr.rs

1use std::fmt;
2
3use rustc_span::Symbol;
4
5use super::{InlineAsmArch, InlineAsmType, ModifierInfo};
6
7#[allow(non_camel_case_types)]
pub enum AvrInlineAsmRegClass { reg, reg_upper, reg_pair, reg_iw, reg_ptr, }
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::marker::Copy for AvrInlineAsmRegClass { }
#[automatically_derived]
#[doc(hidden)]
#[allow(non_camel_case_types)]
unsafe impl ::core::clone::TrivialClone for AvrInlineAsmRegClass { }
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::clone::Clone for AvrInlineAsmRegClass {
    #[inline]
    fn clone(&self) -> AvrInlineAsmRegClass { *self }
}
const _: () =
    {
        impl<__E: ::rustc_span::SpanEncoder> ::rustc_serialize::Encodable<__E>
            for AvrInlineAsmRegClass {
            fn encode(&self, __encoder: &mut __E) {
                let disc =
                    match *self {
                        AvrInlineAsmRegClass::reg => { 0usize }
                        AvrInlineAsmRegClass::reg_upper => { 1usize }
                        AvrInlineAsmRegClass::reg_pair => { 2usize }
                        AvrInlineAsmRegClass::reg_iw => { 3usize }
                        AvrInlineAsmRegClass::reg_ptr => { 4usize }
                    };
                ::rustc_serialize::Encoder::emit_u8(__encoder, disc as u8);
                match *self {
                    AvrInlineAsmRegClass::reg => {}
                    AvrInlineAsmRegClass::reg_upper => {}
                    AvrInlineAsmRegClass::reg_pair => {}
                    AvrInlineAsmRegClass::reg_iw => {}
                    AvrInlineAsmRegClass::reg_ptr => {}
                }
            }
        }
    };
const _: () =
    {
        impl<__D: ::rustc_span::SpanDecoder> ::rustc_serialize::Decodable<__D>
            for AvrInlineAsmRegClass {
            fn decode(__decoder: &mut __D) -> Self {
                match ::rustc_serialize::Decoder::read_u8(__decoder) as usize
                    {
                    0usize => { AvrInlineAsmRegClass::reg }
                    1usize => { AvrInlineAsmRegClass::reg_upper }
                    2usize => { AvrInlineAsmRegClass::reg_pair }
                    3usize => { AvrInlineAsmRegClass::reg_iw }
                    4usize => { AvrInlineAsmRegClass::reg_ptr }
                    n => {
                        ::core::panicking::panic_fmt(format_args!("invalid enum variant tag while decoding `AvrInlineAsmRegClass`, expected 0..5, actual {0}",
                                n));
                    }
                }
            }
        }
    };
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::fmt::Debug for AvrInlineAsmRegClass {
    #[inline]
    fn fmt(&self, f: &mut ::core::fmt::Formatter) -> ::core::fmt::Result {
        ::core::fmt::Formatter::write_str(f,
            match self {
                AvrInlineAsmRegClass::reg => "reg",
                AvrInlineAsmRegClass::reg_upper => "reg_upper",
                AvrInlineAsmRegClass::reg_pair => "reg_pair",
                AvrInlineAsmRegClass::reg_iw => "reg_iw",
                AvrInlineAsmRegClass::reg_ptr => "reg_ptr",
            })
    }
}
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::cmp::Eq for AvrInlineAsmRegClass {
    #[inline]
    #[doc(hidden)]
    #[coverage(off)]
    fn assert_receiver_is_total_eq(&self) {}
}
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::marker::StructuralPartialEq for AvrInlineAsmRegClass { }
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::cmp::PartialEq for AvrInlineAsmRegClass {
    #[inline]
    fn eq(&self, other: &AvrInlineAsmRegClass) -> bool {
        let __self_discr = ::core::intrinsics::discriminant_value(self);
        let __arg1_discr = ::core::intrinsics::discriminant_value(other);
        __self_discr == __arg1_discr
    }
}
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::cmp::PartialOrd for AvrInlineAsmRegClass {
    #[inline]
    fn partial_cmp(&self, other: &AvrInlineAsmRegClass)
        -> ::core::option::Option<::core::cmp::Ordering> {
        let __self_discr = ::core::intrinsics::discriminant_value(self);
        let __arg1_discr = ::core::intrinsics::discriminant_value(other);
        ::core::cmp::PartialOrd::partial_cmp(&__self_discr, &__arg1_discr)
    }
}
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::hash::Hash for AvrInlineAsmRegClass {
    #[inline]
    fn hash<__H: ::core::hash::Hasher>(&self, state: &mut __H) {
        let __self_discr = ::core::intrinsics::discriminant_value(self);
        ::core::hash::Hash::hash(&__self_discr, state)
    }
}
const _: () =
    {
        impl<__CTX> ::rustc_data_structures::stable_hasher::HashStable<__CTX>
            for AvrInlineAsmRegClass where __CTX: crate::HashStableContext {
            #[inline]
            fn hash_stable(&self, __hcx: &mut __CTX,
                __hasher:
                    &mut ::rustc_data_structures::stable_hasher::StableHasher) {
                ::std::mem::discriminant(self).hash_stable(__hcx, __hasher);
                match *self {
                    AvrInlineAsmRegClass::reg => {}
                    AvrInlineAsmRegClass::reg_upper => {}
                    AvrInlineAsmRegClass::reg_pair => {}
                    AvrInlineAsmRegClass::reg_iw => {}
                    AvrInlineAsmRegClass::reg_ptr => {}
                }
            }
        }
    };
impl AvrInlineAsmRegClass {
    pub fn name(self) -> rustc_span::Symbol {
        match self {
            Self::reg => rustc_span::sym::reg,
            Self::reg_upper => rustc_span::sym::reg_upper,
            Self::reg_pair => rustc_span::sym::reg_pair,
            Self::reg_iw => rustc_span::sym::reg_iw,
            Self::reg_ptr => rustc_span::sym::reg_ptr,
        }
    }
    pub fn parse(name: rustc_span::Symbol)
        -> Result<Self, &'static [rustc_span::Symbol]> {
        match name {
            rustc_span::sym::reg => Ok(Self::reg),
            rustc_span::sym::reg_upper => Ok(Self::reg_upper),
            rustc_span::sym::reg_pair => Ok(Self::reg_pair),
            rustc_span::sym::reg_iw => Ok(Self::reg_iw),
            rustc_span::sym::reg_ptr => Ok(Self::reg_ptr),
            _ =>
                Err(&[rustc_span::sym::reg, rustc_span::sym::reg_upper,
                                rustc_span::sym::reg_pair, rustc_span::sym::reg_iw,
                                rustc_span::sym::reg_ptr]),
        }
    }
}
pub(super) fn regclass_map()
    ->
        rustc_data_structures::fx::FxHashMap<super::InlineAsmRegClass,
        rustc_data_structures::fx::FxIndexSet<super::InlineAsmReg>> {
    use rustc_data_structures::fx::FxHashMap;
    use rustc_data_structures::fx::FxIndexSet;
    use super::InlineAsmRegClass;
    let mut map = FxHashMap::default();
    map.insert(InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg),
        FxIndexSet::default());
    map.insert(InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_upper),
        FxIndexSet::default());
    map.insert(InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_pair),
        FxIndexSet::default());
    map.insert(InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_iw),
        FxIndexSet::default());
    map.insert(InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_ptr),
        FxIndexSet::default());
    map
}def_reg_class! {
8    Avr AvrInlineAsmRegClass {
9        reg,
10        reg_upper,
11        reg_pair,
12        reg_iw,
13        reg_ptr,
14    }
15}
16
17impl AvrInlineAsmRegClass {
18    pub fn valid_modifiers(self, _arch: InlineAsmArch) -> &'static [char] {
19        match self {
20            Self::reg_pair | Self::reg_iw | Self::reg_ptr => &['h', 'l'],
21            _ => &[],
22        }
23    }
24
25    pub fn suggest_class(self, _arch: InlineAsmArch, _ty: InlineAsmType) -> Option<Self> {
26        None
27    }
28
29    pub fn suggest_modifier(
30        self,
31        _arch: InlineAsmArch,
32        _ty: InlineAsmType,
33    ) -> Option<ModifierInfo> {
34        None
35    }
36
37    pub fn default_modifier(self, _arch: InlineAsmArch) -> Option<ModifierInfo> {
38        None
39    }
40
41    pub fn supported_types(
42        self,
43        _arch: InlineAsmArch,
44    ) -> &'static [(InlineAsmType, Option<Symbol>)] {
45        match self {
46            Self::reg => {
    use super::InlineAsmType::*;
    &[(I8, None)]
}types! { _: I8; },
47            Self::reg_upper => {
    use super::InlineAsmType::*;
    &[(I8, None)]
}types! { _: I8; },
48            Self::reg_pair => {
    use super::InlineAsmType::*;
    &[(I16, None)]
}types! { _: I16; },
49            Self::reg_iw => {
    use super::InlineAsmType::*;
    &[(I16, None)]
}types! { _: I16; },
50            Self::reg_ptr => {
    use super::InlineAsmType::*;
    &[(I16, None)]
}types! { _: I16; },
51        }
52    }
53}
54
55#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
pub enum AvrInlineAsmReg {
    r2,
    r3,
    r4,
    r5,
    r6,
    r7,
    r8,
    r9,
    r10,
    r11,
    r12,
    r13,
    r14,
    r15,
    r16,
    r17,
    r18,
    r19,
    r20,
    r21,
    r22,
    r23,
    r24,
    r25,
    r26,
    r27,
    r30,
    r31,
    r3r2,
    r5r4,
    r7r6,
    r9r8,
    r11r10,
    r13r12,
    r15r14,
    r17r16,
    r19r18,
    r21r20,
    r23r22,
    r25r24,
    X,
    Z,
}
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::marker::Copy for AvrInlineAsmReg { }
#[automatically_derived]
#[doc(hidden)]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
unsafe impl ::core::clone::TrivialClone for AvrInlineAsmReg { }
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::clone::Clone for AvrInlineAsmReg {
    #[inline]
    fn clone(&self) -> AvrInlineAsmReg { *self }
}
const _: () =
    {
        impl<__E: ::rustc_span::SpanEncoder> ::rustc_serialize::Encodable<__E>
            for AvrInlineAsmReg {
            fn encode(&self, __encoder: &mut __E) {
                let disc =
                    match *self {
                        AvrInlineAsmReg::r2 => { 0usize }
                        AvrInlineAsmReg::r3 => { 1usize }
                        AvrInlineAsmReg::r4 => { 2usize }
                        AvrInlineAsmReg::r5 => { 3usize }
                        AvrInlineAsmReg::r6 => { 4usize }
                        AvrInlineAsmReg::r7 => { 5usize }
                        AvrInlineAsmReg::r8 => { 6usize }
                        AvrInlineAsmReg::r9 => { 7usize }
                        AvrInlineAsmReg::r10 => { 8usize }
                        AvrInlineAsmReg::r11 => { 9usize }
                        AvrInlineAsmReg::r12 => { 10usize }
                        AvrInlineAsmReg::r13 => { 11usize }
                        AvrInlineAsmReg::r14 => { 12usize }
                        AvrInlineAsmReg::r15 => { 13usize }
                        AvrInlineAsmReg::r16 => { 14usize }
                        AvrInlineAsmReg::r17 => { 15usize }
                        AvrInlineAsmReg::r18 => { 16usize }
                        AvrInlineAsmReg::r19 => { 17usize }
                        AvrInlineAsmReg::r20 => { 18usize }
                        AvrInlineAsmReg::r21 => { 19usize }
                        AvrInlineAsmReg::r22 => { 20usize }
                        AvrInlineAsmReg::r23 => { 21usize }
                        AvrInlineAsmReg::r24 => { 22usize }
                        AvrInlineAsmReg::r25 => { 23usize }
                        AvrInlineAsmReg::r26 => { 24usize }
                        AvrInlineAsmReg::r27 => { 25usize }
                        AvrInlineAsmReg::r30 => { 26usize }
                        AvrInlineAsmReg::r31 => { 27usize }
                        AvrInlineAsmReg::r3r2 => { 28usize }
                        AvrInlineAsmReg::r5r4 => { 29usize }
                        AvrInlineAsmReg::r7r6 => { 30usize }
                        AvrInlineAsmReg::r9r8 => { 31usize }
                        AvrInlineAsmReg::r11r10 => { 32usize }
                        AvrInlineAsmReg::r13r12 => { 33usize }
                        AvrInlineAsmReg::r15r14 => { 34usize }
                        AvrInlineAsmReg::r17r16 => { 35usize }
                        AvrInlineAsmReg::r19r18 => { 36usize }
                        AvrInlineAsmReg::r21r20 => { 37usize }
                        AvrInlineAsmReg::r23r22 => { 38usize }
                        AvrInlineAsmReg::r25r24 => { 39usize }
                        AvrInlineAsmReg::X => { 40usize }
                        AvrInlineAsmReg::Z => { 41usize }
                    };
                ::rustc_serialize::Encoder::emit_u8(__encoder, disc as u8);
                match *self {
                    AvrInlineAsmReg::r2 => {}
                    AvrInlineAsmReg::r3 => {}
                    AvrInlineAsmReg::r4 => {}
                    AvrInlineAsmReg::r5 => {}
                    AvrInlineAsmReg::r6 => {}
                    AvrInlineAsmReg::r7 => {}
                    AvrInlineAsmReg::r8 => {}
                    AvrInlineAsmReg::r9 => {}
                    AvrInlineAsmReg::r10 => {}
                    AvrInlineAsmReg::r11 => {}
                    AvrInlineAsmReg::r12 => {}
                    AvrInlineAsmReg::r13 => {}
                    AvrInlineAsmReg::r14 => {}
                    AvrInlineAsmReg::r15 => {}
                    AvrInlineAsmReg::r16 => {}
                    AvrInlineAsmReg::r17 => {}
                    AvrInlineAsmReg::r18 => {}
                    AvrInlineAsmReg::r19 => {}
                    AvrInlineAsmReg::r20 => {}
                    AvrInlineAsmReg::r21 => {}
                    AvrInlineAsmReg::r22 => {}
                    AvrInlineAsmReg::r23 => {}
                    AvrInlineAsmReg::r24 => {}
                    AvrInlineAsmReg::r25 => {}
                    AvrInlineAsmReg::r26 => {}
                    AvrInlineAsmReg::r27 => {}
                    AvrInlineAsmReg::r30 => {}
                    AvrInlineAsmReg::r31 => {}
                    AvrInlineAsmReg::r3r2 => {}
                    AvrInlineAsmReg::r5r4 => {}
                    AvrInlineAsmReg::r7r6 => {}
                    AvrInlineAsmReg::r9r8 => {}
                    AvrInlineAsmReg::r11r10 => {}
                    AvrInlineAsmReg::r13r12 => {}
                    AvrInlineAsmReg::r15r14 => {}
                    AvrInlineAsmReg::r17r16 => {}
                    AvrInlineAsmReg::r19r18 => {}
                    AvrInlineAsmReg::r21r20 => {}
                    AvrInlineAsmReg::r23r22 => {}
                    AvrInlineAsmReg::r25r24 => {}
                    AvrInlineAsmReg::X => {}
                    AvrInlineAsmReg::Z => {}
                }
            }
        }
    };
const _: () =
    {
        impl<__D: ::rustc_span::SpanDecoder> ::rustc_serialize::Decodable<__D>
            for AvrInlineAsmReg {
            fn decode(__decoder: &mut __D) -> Self {
                match ::rustc_serialize::Decoder::read_u8(__decoder) as usize
                    {
                    0usize => { AvrInlineAsmReg::r2 }
                    1usize => { AvrInlineAsmReg::r3 }
                    2usize => { AvrInlineAsmReg::r4 }
                    3usize => { AvrInlineAsmReg::r5 }
                    4usize => { AvrInlineAsmReg::r6 }
                    5usize => { AvrInlineAsmReg::r7 }
                    6usize => { AvrInlineAsmReg::r8 }
                    7usize => { AvrInlineAsmReg::r9 }
                    8usize => { AvrInlineAsmReg::r10 }
                    9usize => { AvrInlineAsmReg::r11 }
                    10usize => { AvrInlineAsmReg::r12 }
                    11usize => { AvrInlineAsmReg::r13 }
                    12usize => { AvrInlineAsmReg::r14 }
                    13usize => { AvrInlineAsmReg::r15 }
                    14usize => { AvrInlineAsmReg::r16 }
                    15usize => { AvrInlineAsmReg::r17 }
                    16usize => { AvrInlineAsmReg::r18 }
                    17usize => { AvrInlineAsmReg::r19 }
                    18usize => { AvrInlineAsmReg::r20 }
                    19usize => { AvrInlineAsmReg::r21 }
                    20usize => { AvrInlineAsmReg::r22 }
                    21usize => { AvrInlineAsmReg::r23 }
                    22usize => { AvrInlineAsmReg::r24 }
                    23usize => { AvrInlineAsmReg::r25 }
                    24usize => { AvrInlineAsmReg::r26 }
                    25usize => { AvrInlineAsmReg::r27 }
                    26usize => { AvrInlineAsmReg::r30 }
                    27usize => { AvrInlineAsmReg::r31 }
                    28usize => { AvrInlineAsmReg::r3r2 }
                    29usize => { AvrInlineAsmReg::r5r4 }
                    30usize => { AvrInlineAsmReg::r7r6 }
                    31usize => { AvrInlineAsmReg::r9r8 }
                    32usize => { AvrInlineAsmReg::r11r10 }
                    33usize => { AvrInlineAsmReg::r13r12 }
                    34usize => { AvrInlineAsmReg::r15r14 }
                    35usize => { AvrInlineAsmReg::r17r16 }
                    36usize => { AvrInlineAsmReg::r19r18 }
                    37usize => { AvrInlineAsmReg::r21r20 }
                    38usize => { AvrInlineAsmReg::r23r22 }
                    39usize => { AvrInlineAsmReg::r25r24 }
                    40usize => { AvrInlineAsmReg::X }
                    41usize => { AvrInlineAsmReg::Z }
                    n => {
                        ::core::panicking::panic_fmt(format_args!("invalid enum variant tag while decoding `AvrInlineAsmReg`, expected 0..42, actual {0}",
                                n));
                    }
                }
            }
        }
    };
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::fmt::Debug for AvrInlineAsmReg {
    #[inline]
    fn fmt(&self, f: &mut ::core::fmt::Formatter) -> ::core::fmt::Result {
        ::core::fmt::Formatter::write_str(f,
            match self {
                AvrInlineAsmReg::r2 => "r2",
                AvrInlineAsmReg::r3 => "r3",
                AvrInlineAsmReg::r4 => "r4",
                AvrInlineAsmReg::r5 => "r5",
                AvrInlineAsmReg::r6 => "r6",
                AvrInlineAsmReg::r7 => "r7",
                AvrInlineAsmReg::r8 => "r8",
                AvrInlineAsmReg::r9 => "r9",
                AvrInlineAsmReg::r10 => "r10",
                AvrInlineAsmReg::r11 => "r11",
                AvrInlineAsmReg::r12 => "r12",
                AvrInlineAsmReg::r13 => "r13",
                AvrInlineAsmReg::r14 => "r14",
                AvrInlineAsmReg::r15 => "r15",
                AvrInlineAsmReg::r16 => "r16",
                AvrInlineAsmReg::r17 => "r17",
                AvrInlineAsmReg::r18 => "r18",
                AvrInlineAsmReg::r19 => "r19",
                AvrInlineAsmReg::r20 => "r20",
                AvrInlineAsmReg::r21 => "r21",
                AvrInlineAsmReg::r22 => "r22",
                AvrInlineAsmReg::r23 => "r23",
                AvrInlineAsmReg::r24 => "r24",
                AvrInlineAsmReg::r25 => "r25",
                AvrInlineAsmReg::r26 => "r26",
                AvrInlineAsmReg::r27 => "r27",
                AvrInlineAsmReg::r30 => "r30",
                AvrInlineAsmReg::r31 => "r31",
                AvrInlineAsmReg::r3r2 => "r3r2",
                AvrInlineAsmReg::r5r4 => "r5r4",
                AvrInlineAsmReg::r7r6 => "r7r6",
                AvrInlineAsmReg::r9r8 => "r9r8",
                AvrInlineAsmReg::r11r10 => "r11r10",
                AvrInlineAsmReg::r13r12 => "r13r12",
                AvrInlineAsmReg::r15r14 => "r15r14",
                AvrInlineAsmReg::r17r16 => "r17r16",
                AvrInlineAsmReg::r19r18 => "r19r18",
                AvrInlineAsmReg::r21r20 => "r21r20",
                AvrInlineAsmReg::r23r22 => "r23r22",
                AvrInlineAsmReg::r25r24 => "r25r24",
                AvrInlineAsmReg::X => "X",
                AvrInlineAsmReg::Z => "Z",
            })
    }
}
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::cmp::Eq for AvrInlineAsmReg {
    #[inline]
    #[doc(hidden)]
    #[coverage(off)]
    fn assert_receiver_is_total_eq(&self) {}
}
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::marker::StructuralPartialEq for AvrInlineAsmReg { }
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::cmp::PartialEq for AvrInlineAsmReg {
    #[inline]
    fn eq(&self, other: &AvrInlineAsmReg) -> bool {
        let __self_discr = ::core::intrinsics::discriminant_value(self);
        let __arg1_discr = ::core::intrinsics::discriminant_value(other);
        __self_discr == __arg1_discr
    }
}
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::cmp::PartialOrd for AvrInlineAsmReg {
    #[inline]
    fn partial_cmp(&self, other: &AvrInlineAsmReg)
        -> ::core::option::Option<::core::cmp::Ordering> {
        let __self_discr = ::core::intrinsics::discriminant_value(self);
        let __arg1_discr = ::core::intrinsics::discriminant_value(other);
        ::core::cmp::PartialOrd::partial_cmp(&__self_discr, &__arg1_discr)
    }
}
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::hash::Hash for AvrInlineAsmReg {
    #[inline]
    fn hash<__H: ::core::hash::Hasher>(&self, state: &mut __H) {
        let __self_discr = ::core::intrinsics::discriminant_value(self);
        ::core::hash::Hash::hash(&__self_discr, state)
    }
}
const _: () =
    {
        impl<__CTX> ::rustc_data_structures::stable_hasher::HashStable<__CTX>
            for AvrInlineAsmReg where __CTX: crate::HashStableContext {
            #[inline]
            fn hash_stable(&self, __hcx: &mut __CTX,
                __hasher:
                    &mut ::rustc_data_structures::stable_hasher::StableHasher) {
                ::std::mem::discriminant(self).hash_stable(__hcx, __hasher);
                match *self {
                    AvrInlineAsmReg::r2 => {}
                    AvrInlineAsmReg::r3 => {}
                    AvrInlineAsmReg::r4 => {}
                    AvrInlineAsmReg::r5 => {}
                    AvrInlineAsmReg::r6 => {}
                    AvrInlineAsmReg::r7 => {}
                    AvrInlineAsmReg::r8 => {}
                    AvrInlineAsmReg::r9 => {}
                    AvrInlineAsmReg::r10 => {}
                    AvrInlineAsmReg::r11 => {}
                    AvrInlineAsmReg::r12 => {}
                    AvrInlineAsmReg::r13 => {}
                    AvrInlineAsmReg::r14 => {}
                    AvrInlineAsmReg::r15 => {}
                    AvrInlineAsmReg::r16 => {}
                    AvrInlineAsmReg::r17 => {}
                    AvrInlineAsmReg::r18 => {}
                    AvrInlineAsmReg::r19 => {}
                    AvrInlineAsmReg::r20 => {}
                    AvrInlineAsmReg::r21 => {}
                    AvrInlineAsmReg::r22 => {}
                    AvrInlineAsmReg::r23 => {}
                    AvrInlineAsmReg::r24 => {}
                    AvrInlineAsmReg::r25 => {}
                    AvrInlineAsmReg::r26 => {}
                    AvrInlineAsmReg::r27 => {}
                    AvrInlineAsmReg::r30 => {}
                    AvrInlineAsmReg::r31 => {}
                    AvrInlineAsmReg::r3r2 => {}
                    AvrInlineAsmReg::r5r4 => {}
                    AvrInlineAsmReg::r7r6 => {}
                    AvrInlineAsmReg::r9r8 => {}
                    AvrInlineAsmReg::r11r10 => {}
                    AvrInlineAsmReg::r13r12 => {}
                    AvrInlineAsmReg::r15r14 => {}
                    AvrInlineAsmReg::r17r16 => {}
                    AvrInlineAsmReg::r19r18 => {}
                    AvrInlineAsmReg::r21r20 => {}
                    AvrInlineAsmReg::r23r22 => {}
                    AvrInlineAsmReg::r25r24 => {}
                    AvrInlineAsmReg::X => {}
                    AvrInlineAsmReg::Z => {}
                }
            }
        }
    };
impl AvrInlineAsmReg {
    pub fn name(self) -> &'static str {
        match self {
            Self::r2 => "r2",
            Self::r3 => "r3",
            Self::r4 => "r4",
            Self::r5 => "r5",
            Self::r6 => "r6",
            Self::r7 => "r7",
            Self::r8 => "r8",
            Self::r9 => "r9",
            Self::r10 => "r10",
            Self::r11 => "r11",
            Self::r12 => "r12",
            Self::r13 => "r13",
            Self::r14 => "r14",
            Self::r15 => "r15",
            Self::r16 => "r16",
            Self::r17 => "r17",
            Self::r18 => "r18",
            Self::r19 => "r19",
            Self::r20 => "r20",
            Self::r21 => "r21",
            Self::r22 => "r22",
            Self::r23 => "r23",
            Self::r24 => "r24",
            Self::r25 => "r25",
            Self::r26 => "r26",
            Self::r27 => "r27",
            Self::r30 => "r30",
            Self::r31 => "r31",
            Self::r3r2 => "r3r2",
            Self::r5r4 => "r5r4",
            Self::r7r6 => "r7r6",
            Self::r9r8 => "r9r8",
            Self::r11r10 => "r11r10",
            Self::r13r12 => "r13r12",
            Self::r15r14 => "r15r14",
            Self::r17r16 => "r17r16",
            Self::r19r18 => "r19r18",
            Self::r21r20 => "r21r20",
            Self::r23r22 => "r23r22",
            Self::r25r24 => "r25r24",
            Self::X => "r27r26",
            Self::Z => "r31r30",
        }
    }
    pub fn reg_class(self) -> AvrInlineAsmRegClass {
        match self {
            Self::r2 => AvrInlineAsmRegClass::reg,
            Self::r3 => AvrInlineAsmRegClass::reg,
            Self::r4 => AvrInlineAsmRegClass::reg,
            Self::r5 => AvrInlineAsmRegClass::reg,
            Self::r6 => AvrInlineAsmRegClass::reg,
            Self::r7 => AvrInlineAsmRegClass::reg,
            Self::r8 => AvrInlineAsmRegClass::reg,
            Self::r9 => AvrInlineAsmRegClass::reg,
            Self::r10 => AvrInlineAsmRegClass::reg,
            Self::r11 => AvrInlineAsmRegClass::reg,
            Self::r12 => AvrInlineAsmRegClass::reg,
            Self::r13 => AvrInlineAsmRegClass::reg,
            Self::r14 => AvrInlineAsmRegClass::reg,
            Self::r15 => AvrInlineAsmRegClass::reg,
            Self::r16 => AvrInlineAsmRegClass::reg,
            Self::r17 => AvrInlineAsmRegClass::reg,
            Self::r18 => AvrInlineAsmRegClass::reg,
            Self::r19 => AvrInlineAsmRegClass::reg,
            Self::r20 => AvrInlineAsmRegClass::reg,
            Self::r21 => AvrInlineAsmRegClass::reg,
            Self::r22 => AvrInlineAsmRegClass::reg,
            Self::r23 => AvrInlineAsmRegClass::reg,
            Self::r24 => AvrInlineAsmRegClass::reg,
            Self::r25 => AvrInlineAsmRegClass::reg,
            Self::r26 => AvrInlineAsmRegClass::reg,
            Self::r27 => AvrInlineAsmRegClass::reg,
            Self::r30 => AvrInlineAsmRegClass::reg,
            Self::r31 => AvrInlineAsmRegClass::reg,
            Self::r3r2 => AvrInlineAsmRegClass::reg_pair,
            Self::r5r4 => AvrInlineAsmRegClass::reg_pair,
            Self::r7r6 => AvrInlineAsmRegClass::reg_pair,
            Self::r9r8 => AvrInlineAsmRegClass::reg_pair,
            Self::r11r10 => AvrInlineAsmRegClass::reg_pair,
            Self::r13r12 => AvrInlineAsmRegClass::reg_pair,
            Self::r15r14 => AvrInlineAsmRegClass::reg_pair,
            Self::r17r16 => AvrInlineAsmRegClass::reg_pair,
            Self::r19r18 => AvrInlineAsmRegClass::reg_pair,
            Self::r21r20 => AvrInlineAsmRegClass::reg_pair,
            Self::r23r22 => AvrInlineAsmRegClass::reg_pair,
            Self::r25r24 => AvrInlineAsmRegClass::reg_iw,
            Self::X => AvrInlineAsmRegClass::reg_ptr,
            Self::Z => AvrInlineAsmRegClass::reg_ptr,
        }
    }
    pub fn parse(name: &str) -> Result<Self, &'static str> {
        match name {
            "r2" => Ok(Self::r2),
            "r3" => Ok(Self::r3),
            "r4" => Ok(Self::r4),
            "r5" => Ok(Self::r5),
            "r6" => Ok(Self::r6),
            "r7" => Ok(Self::r7),
            "r8" => Ok(Self::r8),
            "r9" => Ok(Self::r9),
            "r10" => Ok(Self::r10),
            "r11" => Ok(Self::r11),
            "r12" => Ok(Self::r12),
            "r13" => Ok(Self::r13),
            "r14" => Ok(Self::r14),
            "r15" => Ok(Self::r15),
            "r16" => Ok(Self::r16),
            "r17" => Ok(Self::r17),
            "r18" => Ok(Self::r18),
            "r19" => Ok(Self::r19),
            "r20" => Ok(Self::r20),
            "r21" => Ok(Self::r21),
            "r22" => Ok(Self::r22),
            "r23" => Ok(Self::r23),
            "r24" => Ok(Self::r24),
            "r25" => Ok(Self::r25),
            "XL" | "r26" => Ok(Self::r26),
            "XH" | "r27" => Ok(Self::r27),
            "ZL" | "r30" => Ok(Self::r30),
            "ZH" | "r31" => Ok(Self::r31),
            "r3r2" => Ok(Self::r3r2),
            "r5r4" => Ok(Self::r5r4),
            "r7r6" => Ok(Self::r7r6),
            "r9r8" => Ok(Self::r9r8),
            "r11r10" => Ok(Self::r11r10),
            "r13r12" => Ok(Self::r13r12),
            "r15r14" => Ok(Self::r15r14),
            "r17r16" => Ok(Self::r17r16),
            "r19r18" => Ok(Self::r19r18),
            "r21r20" => Ok(Self::r21r20),
            "r23r22" => Ok(Self::r23r22),
            "r25r24" => Ok(Self::r25r24),
            "X" | "r27r26" => Ok(Self::X),
            "Z" | "r31r30" => Ok(Self::Z),
            "Y" | "YL" | "YH" =>
                Err("the frame pointer cannot be used as an operand for inline asm"),
            "SP" | "SPL" | "SPH" =>
                Err("the stack pointer cannot be used as an operand for inline asm"),
            "r0" | "r1" | "r1r0" =>
                Err("LLVM reserves r0 (scratch register) and r1 (zero register)"),
            _ => Err("unknown register"),
        }
    }
    pub fn validate(self, _arch: super::InlineAsmArch,
        _reloc_model: crate::spec::RelocModel,
        _target_features: &rustc_data_structures::fx::FxIndexSet<Symbol>,
        _target: &crate::spec::Target, _is_clobber: bool)
        -> Result<(), &'static str> {
        match self {
            Self::r2 => { Ok(()) }
            Self::r3 => { Ok(()) }
            Self::r4 => { Ok(()) }
            Self::r5 => { Ok(()) }
            Self::r6 => { Ok(()) }
            Self::r7 => { Ok(()) }
            Self::r8 => { Ok(()) }
            Self::r9 => { Ok(()) }
            Self::r10 => { Ok(()) }
            Self::r11 => { Ok(()) }
            Self::r12 => { Ok(()) }
            Self::r13 => { Ok(()) }
            Self::r14 => { Ok(()) }
            Self::r15 => { Ok(()) }
            Self::r16 => { Ok(()) }
            Self::r17 => { Ok(()) }
            Self::r18 => { Ok(()) }
            Self::r19 => { Ok(()) }
            Self::r20 => { Ok(()) }
            Self::r21 => { Ok(()) }
            Self::r22 => { Ok(()) }
            Self::r23 => { Ok(()) }
            Self::r24 => { Ok(()) }
            Self::r25 => { Ok(()) }
            Self::r26 => { Ok(()) }
            Self::r27 => { Ok(()) }
            Self::r30 => { Ok(()) }
            Self::r31 => { Ok(()) }
            Self::r3r2 => { Ok(()) }
            Self::r5r4 => { Ok(()) }
            Self::r7r6 => { Ok(()) }
            Self::r9r8 => { Ok(()) }
            Self::r11r10 => { Ok(()) }
            Self::r13r12 => { Ok(()) }
            Self::r15r14 => { Ok(()) }
            Self::r17r16 => { Ok(()) }
            Self::r19r18 => { Ok(()) }
            Self::r21r20 => { Ok(()) }
            Self::r23r22 => { Ok(()) }
            Self::r25r24 => { Ok(()) }
            Self::X => { Ok(()) }
            Self::Z => { Ok(()) }
        }
    }
}
pub(super) fn fill_reg_map(_arch: super::InlineAsmArch,
    _reloc_model: crate::spec::RelocModel,
    _target_features: &rustc_data_structures::fx::FxIndexSet<Symbol>,
    _target: &crate::spec::Target,
    _map:
        &mut rustc_data_structures::fx::FxHashMap<super::InlineAsmRegClass,
        rustc_data_structures::fx::FxIndexSet<super::InlineAsmReg>>) {
    #[allow(unused_imports)]
    use super::{InlineAsmReg, InlineAsmRegClass};
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r2));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r3));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r4));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r5));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r6));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r7));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r8));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r9));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r10));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r11));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r12));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r13));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r14));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r15));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r16));
        }
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_upper))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r16));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r17));
        }
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_upper))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r17));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r18));
        }
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_upper))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r18));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r19));
        }
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_upper))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r19));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r20));
        }
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_upper))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r20));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r21));
        }
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_upper))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r21));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r22));
        }
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_upper))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r22));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r23));
        }
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_upper))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r23));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r24));
        }
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_upper))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r24));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r25));
        }
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_upper))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r25));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r26));
        }
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_upper))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r26));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r27));
        }
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_upper))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r27));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r30));
        }
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_upper))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r30));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r31));
        }
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_upper))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r31));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_pair))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r3r2));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_pair))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r5r4));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_pair))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r7r6));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_pair))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r9r8));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_pair))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r11r10));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_pair))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r13r12));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_pair))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r15r14));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_pair))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r17r16));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_pair))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r19r18));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_pair))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r21r20));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_pair))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r23r22));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_iw))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r25r24));
        }
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_pair))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::r25r24));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_ptr))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::X));
        }
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_iw))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::X));
        }
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_pair))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::X));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_ptr))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::Z));
        }
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_iw))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::Z));
        }
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_pair))
            {
            set.insert(InlineAsmReg::Avr(AvrInlineAsmReg::Z));
        }
    }
}def_regs! {
56    Avr AvrInlineAsmReg AvrInlineAsmRegClass {
57        r2: reg = ["r2"],
58        r3: reg = ["r3"],
59        r4: reg = ["r4"],
60        r5: reg = ["r5"],
61        r6: reg = ["r6"],
62        r7: reg = ["r7"],
63        r8: reg = ["r8"],
64        r9: reg = ["r9"],
65        r10: reg = ["r10"],
66        r11: reg = ["r11"],
67        r12: reg = ["r12"],
68        r13: reg = ["r13"],
69        r14: reg = ["r14"],
70        r15: reg = ["r15"],
71        r16: reg, reg_upper = ["r16"],
72        r17: reg, reg_upper = ["r17"],
73        r18: reg, reg_upper = ["r18"],
74        r19: reg, reg_upper = ["r19"],
75        r20: reg, reg_upper = ["r20"],
76        r21: reg, reg_upper = ["r21"],
77        r22: reg, reg_upper = ["r22"],
78        r23: reg, reg_upper = ["r23"],
79        r24: reg, reg_upper = ["r24"],
80        r25: reg, reg_upper = ["r25"],
81        r26: reg, reg_upper = ["r26", "XL"],
82        r27: reg, reg_upper = ["r27", "XH"],
83        r30: reg, reg_upper = ["r30", "ZL"],
84        r31: reg, reg_upper = ["r31", "ZH"],
85
86        r3r2: reg_pair = ["r3r2"],
87        r5r4: reg_pair = ["r5r4"],
88        r7r6: reg_pair = ["r7r6"],
89        r9r8: reg_pair = ["r9r8"],
90        r11r10: reg_pair = ["r11r10"],
91        r13r12: reg_pair = ["r13r12"],
92        r15r14: reg_pair = ["r15r14"],
93        r17r16: reg_pair = ["r17r16"],
94        r19r18: reg_pair = ["r19r18"],
95        r21r20: reg_pair = ["r21r20"],
96        r23r22: reg_pair = ["r23r22"],
97
98        r25r24: reg_iw, reg_pair = ["r25r24"],
99
100        X: reg_ptr, reg_iw, reg_pair = ["r27r26", "X"],
101        Z: reg_ptr, reg_iw, reg_pair = ["r31r30", "Z"],
102
103        #error = ["Y", "YL", "YH"] =>
104            "the frame pointer cannot be used as an operand for inline asm",
105        #error = ["SP", "SPL", "SPH"] =>
106            "the stack pointer cannot be used as an operand for inline asm",
107        #error = ["r0", "r1", "r1r0"] =>
108            "LLVM reserves r0 (scratch register) and r1 (zero register)",
109            // If this changes within LLVM, the compiler might use the registers
110            // in the future. This must be reflected in the set of clobbered
111            // registers, else the clobber ABI implementation is *unsound*, as
112            // this generates invalid code (register is not marked as clobbered
113            // but may change the register content).
114    }
115}
116
117macro_rules! emit_pairs {
118    (
119        $self:ident $modifier:ident,
120        $($pair:ident $name:literal $hi:literal $lo:literal,)*
121    ) => {
122        match ($self, $modifier) {
123            $(
124                (AvrInlineAsmReg::$pair, Some('h')) => $hi,
125                (AvrInlineAsmReg::$pair, Some('l')) => $lo,
126                (AvrInlineAsmReg::$pair, _) => $name,
127            )*
128            _ => $self.name(),
129        }
130    };
131}
132
133impl AvrInlineAsmReg {
134    pub fn emit(
135        self,
136        out: &mut dyn fmt::Write,
137        _arch: InlineAsmArch,
138        modifier: Option<char>,
139    ) -> fmt::Result {
140        let name = match (self, modifier) {
    (AvrInlineAsmReg::Z, Some('h')) => "ZH",
    (AvrInlineAsmReg::Z, Some('l')) => "ZL",
    (AvrInlineAsmReg::Z, _) => "Z",
    (AvrInlineAsmReg::X, Some('h')) => "XH",
    (AvrInlineAsmReg::X, Some('l')) => "XL",
    (AvrInlineAsmReg::X, _) => "X",
    (AvrInlineAsmReg::r25r24, Some('h')) => "r25",
    (AvrInlineAsmReg::r25r24, Some('l')) => "r24",
    (AvrInlineAsmReg::r25r24, _) => "r25:r24",
    (AvrInlineAsmReg::r23r22, Some('h')) => "r23",
    (AvrInlineAsmReg::r23r22, Some('l')) => "r22",
    (AvrInlineAsmReg::r23r22, _) => "r23:r22",
    (AvrInlineAsmReg::r21r20, Some('h')) => "r21",
    (AvrInlineAsmReg::r21r20, Some('l')) => "r20",
    (AvrInlineAsmReg::r21r20, _) => "r21:r20",
    (AvrInlineAsmReg::r19r18, Some('h')) => "r19",
    (AvrInlineAsmReg::r19r18, Some('l')) => "r18",
    (AvrInlineAsmReg::r19r18, _) => "r19:r18",
    (AvrInlineAsmReg::r17r16, Some('h')) => "r17",
    (AvrInlineAsmReg::r17r16, Some('l')) => "r16",
    (AvrInlineAsmReg::r17r16, _) => "r17:r16",
    (AvrInlineAsmReg::r15r14, Some('h')) => "r15",
    (AvrInlineAsmReg::r15r14, Some('l')) => "r14",
    (AvrInlineAsmReg::r15r14, _) => "r15:r14",
    (AvrInlineAsmReg::r13r12, Some('h')) => "r13",
    (AvrInlineAsmReg::r13r12, Some('l')) => "r12",
    (AvrInlineAsmReg::r13r12, _) => "r13:r12",
    (AvrInlineAsmReg::r11r10, Some('h')) => "r11",
    (AvrInlineAsmReg::r11r10, Some('l')) => "r10",
    (AvrInlineAsmReg::r11r10, _) => "r11:r10",
    (AvrInlineAsmReg::r9r8, Some('h')) => "r9",
    (AvrInlineAsmReg::r9r8, Some('l')) => "r8",
    (AvrInlineAsmReg::r9r8, _) => "r9:r8",
    (AvrInlineAsmReg::r7r6, Some('h')) => "r7",
    (AvrInlineAsmReg::r7r6, Some('l')) => "r6",
    (AvrInlineAsmReg::r7r6, _) => "r7:r6",
    (AvrInlineAsmReg::r5r4, Some('h')) => "r5",
    (AvrInlineAsmReg::r5r4, Some('l')) => "r4",
    (AvrInlineAsmReg::r5r4, _) => "r5:r4",
    (AvrInlineAsmReg::r3r2, Some('h')) => "r3",
    (AvrInlineAsmReg::r3r2, Some('l')) => "r2",
    (AvrInlineAsmReg::r3r2, _) => "r3:r2",
    _ => self.name(),
}emit_pairs! {
141            self modifier,
142            Z "Z" "ZH" "ZL",
143            X "X" "XH" "XL",
144            r25r24 "r25:r24" "r25" "r24",
145            r23r22 "r23:r22" "r23" "r22",
146            r21r20 "r21:r20" "r21" "r20",
147            r19r18 "r19:r18" "r19" "r18",
148            r17r16 "r17:r16" "r17" "r16",
149            r15r14 "r15:r14" "r15" "r14",
150            r13r12 "r13:r12" "r13" "r12",
151            r11r10 "r11:r10" "r11" "r10",
152            r9r8 "r9:r8" "r9" "r8",
153            r7r6 "r7:r6" "r7" "r6",
154            r5r4 "r5:r4" "r5" "r4",
155            r3r2 "r3:r2" "r3" "r2",
156        };
157        out.write_str(name)
158    }
159
160    pub fn overlapping_regs(self, mut cb: impl FnMut(AvrInlineAsmReg)) {
161        cb(self);
162
163        macro_rules! reg_conflicts {
164            (
165                $(
166                    $pair:ident : $hi:ident $lo:ident,
167                )*
168            ) => {
169                match self {
170                    $(
171                        Self::$pair => {
172                            cb(Self::$hi);
173                            cb(Self::$lo);
174                        }
175                        Self::$hi => {
176                            cb(Self::$pair);
177                        }
178                        Self::$lo => {
179                            cb(Self::$pair);
180                        }
181                    )*
182                }
183            };
184        }
185
186        match self {
    Self::Z => { cb(Self::r31); cb(Self::r30); }
    Self::r31 => { cb(Self::Z); }
    Self::r30 => { cb(Self::Z); }
    Self::X => { cb(Self::r27); cb(Self::r26); }
    Self::r27 => { cb(Self::X); }
    Self::r26 => { cb(Self::X); }
    Self::r25r24 => { cb(Self::r25); cb(Self::r24); }
    Self::r25 => { cb(Self::r25r24); }
    Self::r24 => { cb(Self::r25r24); }
    Self::r23r22 => { cb(Self::r23); cb(Self::r22); }
    Self::r23 => { cb(Self::r23r22); }
    Self::r22 => { cb(Self::r23r22); }
    Self::r21r20 => { cb(Self::r21); cb(Self::r20); }
    Self::r21 => { cb(Self::r21r20); }
    Self::r20 => { cb(Self::r21r20); }
    Self::r19r18 => { cb(Self::r19); cb(Self::r18); }
    Self::r19 => { cb(Self::r19r18); }
    Self::r18 => { cb(Self::r19r18); }
    Self::r17r16 => { cb(Self::r17); cb(Self::r16); }
    Self::r17 => { cb(Self::r17r16); }
    Self::r16 => { cb(Self::r17r16); }
    Self::r15r14 => { cb(Self::r15); cb(Self::r14); }
    Self::r15 => { cb(Self::r15r14); }
    Self::r14 => { cb(Self::r15r14); }
    Self::r13r12 => { cb(Self::r13); cb(Self::r12); }
    Self::r13 => { cb(Self::r13r12); }
    Self::r12 => { cb(Self::r13r12); }
    Self::r11r10 => { cb(Self::r11); cb(Self::r10); }
    Self::r11 => { cb(Self::r11r10); }
    Self::r10 => { cb(Self::r11r10); }
    Self::r9r8 => { cb(Self::r9); cb(Self::r8); }
    Self::r9 => { cb(Self::r9r8); }
    Self::r8 => { cb(Self::r9r8); }
    Self::r7r6 => { cb(Self::r7); cb(Self::r6); }
    Self::r7 => { cb(Self::r7r6); }
    Self::r6 => { cb(Self::r7r6); }
    Self::r5r4 => { cb(Self::r5); cb(Self::r4); }
    Self::r5 => { cb(Self::r5r4); }
    Self::r4 => { cb(Self::r5r4); }
    Self::r3r2 => { cb(Self::r3); cb(Self::r2); }
    Self::r3 => { cb(Self::r3r2); }
    Self::r2 => { cb(Self::r3r2); }
}reg_conflicts! {
187            Z : r31 r30,
188            X : r27 r26,
189            r25r24 : r25 r24,
190            r23r22 : r23 r22,
191            r21r20 : r21 r20,
192            r19r18 : r19 r18,
193            r17r16 : r17 r16,
194            r15r14 : r15 r14,
195            r13r12 : r13 r12,
196            r11r10 : r11 r10,
197            r9r8 : r9 r8,
198            r7r6 : r7 r6,
199            r5r4 : r5 r4,
200            r3r2 : r3 r2,
201        }
202    }
203}