rustc_target/spec/targets/armv8r_none_eabihf.rs
1// Targets the Little-endian Cortex-R52 processor (ARMv8-R)
2
3use crate::spec::{
4 Cc, FloatAbi, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetMetadata,
5 TargetOptions,
6};
7
8pub(crate) fn target() -> Target {
9 Target {
10 llvm_target: "armv8r-none-eabihf".into(),
11 metadata: TargetMetadata {
12 description: Some("Bare Armv8-R, hardfloat".into()),
13 tier: Some(3),
14 host_tools: Some(false),
15 std: Some(false),
16 },
17 pointer_width: 32,
18 data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
19 arch: "arm".into(),
20
21 options: TargetOptions {
22 abi: "eabihf".into(),
23 llvm_floatabi: Some(FloatAbi::Hard),
24 linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
25 linker: Some("rust-lld".into()),
26 relocation_model: RelocModel::Static,
27 panic_strategy: PanicStrategy::Abort,
28 // Armv8-R requires a minimum set of floating-point features equivalent to:
29 // fp-armv8, SP-only, with 16 DP (32 SP) registers
30 // LLVM defines Armv8-R to include these features automatically.
31 //
32 // The Cortex-R52 supports these default features and optionally includes:
33 // neon-fp-armv8, SP+DP, with 32 DP registers
34 //
35 // Reference:
36 // Arm Cortex-R52 Processor Technical Reference Manual
37 // - Chapter 15 Advanced SIMD and floating-point support
38 max_atomic_width: Some(64),
39 emit_debug_gdb_scripts: false,
40 // GCC defaults to 8 for arm-none here.
41 c_enum_min_bits: Some(8),
42 ..Default::default()
43 },
44 }
45}