1use std::fmt;
2
3use rustc_span::Symbol;
4
5use super::{InlineAsmArch, InlineAsmType, ModifierInfo};
6
7#[allow(non_camel_case_types)]
pub enum BpfInlineAsmRegClass { reg, wreg, }
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::marker::Copy for BpfInlineAsmRegClass { }
#[automatically_derived]
#[doc(hidden)]
#[allow(non_camel_case_types)]
unsafe impl ::core::clone::TrivialClone for BpfInlineAsmRegClass { }
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::clone::Clone for BpfInlineAsmRegClass {
#[inline]
fn clone(&self) -> BpfInlineAsmRegClass { *self }
}
const _: () =
{
impl<__E: ::rustc_span::SpanEncoder> ::rustc_serialize::Encodable<__E>
for BpfInlineAsmRegClass {
fn encode(&self, __encoder: &mut __E) {
let disc =
match *self {
BpfInlineAsmRegClass::reg => { 0usize }
BpfInlineAsmRegClass::wreg => { 1usize }
};
::rustc_serialize::Encoder::emit_u8(__encoder, disc as u8);
match *self {
BpfInlineAsmRegClass::reg => {}
BpfInlineAsmRegClass::wreg => {}
}
}
}
};
const _: () =
{
impl<__D: ::rustc_span::SpanDecoder> ::rustc_serialize::Decodable<__D>
for BpfInlineAsmRegClass {
fn decode(__decoder: &mut __D) -> Self {
match ::rustc_serialize::Decoder::read_u8(__decoder) as usize
{
0usize => { BpfInlineAsmRegClass::reg }
1usize => { BpfInlineAsmRegClass::wreg }
n => {
::core::panicking::panic_fmt(format_args!("invalid enum variant tag while decoding `BpfInlineAsmRegClass`, expected 0..2, actual {0}",
n));
}
}
}
}
};
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::fmt::Debug for BpfInlineAsmRegClass {
#[inline]
fn fmt(&self, f: &mut ::core::fmt::Formatter) -> ::core::fmt::Result {
::core::fmt::Formatter::write_str(f,
match self {
BpfInlineAsmRegClass::reg => "reg",
BpfInlineAsmRegClass::wreg => "wreg",
})
}
}
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::cmp::Eq for BpfInlineAsmRegClass {
#[inline]
#[doc(hidden)]
#[coverage(off)]
fn assert_receiver_is_total_eq(&self) {}
}
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::marker::StructuralPartialEq for BpfInlineAsmRegClass { }
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::cmp::PartialEq for BpfInlineAsmRegClass {
#[inline]
fn eq(&self, other: &BpfInlineAsmRegClass) -> bool {
let __self_discr = ::core::intrinsics::discriminant_value(self);
let __arg1_discr = ::core::intrinsics::discriminant_value(other);
__self_discr == __arg1_discr
}
}
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::cmp::PartialOrd for BpfInlineAsmRegClass {
#[inline]
fn partial_cmp(&self, other: &BpfInlineAsmRegClass)
-> ::core::option::Option<::core::cmp::Ordering> {
let __self_discr = ::core::intrinsics::discriminant_value(self);
let __arg1_discr = ::core::intrinsics::discriminant_value(other);
::core::cmp::PartialOrd::partial_cmp(&__self_discr, &__arg1_discr)
}
}
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::hash::Hash for BpfInlineAsmRegClass {
#[inline]
fn hash<__H: ::core::hash::Hasher>(&self, state: &mut __H) {
let __self_discr = ::core::intrinsics::discriminant_value(self);
::core::hash::Hash::hash(&__self_discr, state)
}
}
const _: () =
{
impl<__CTX> ::rustc_data_structures::stable_hasher::HashStable<__CTX>
for BpfInlineAsmRegClass where __CTX: crate::HashStableContext {
#[inline]
fn hash_stable(&self, __hcx: &mut __CTX,
__hasher:
&mut ::rustc_data_structures::stable_hasher::StableHasher) {
::std::mem::discriminant(self).hash_stable(__hcx, __hasher);
match *self {
BpfInlineAsmRegClass::reg => {}
BpfInlineAsmRegClass::wreg => {}
}
}
}
};
impl BpfInlineAsmRegClass {
pub fn name(self) -> rustc_span::Symbol {
match self {
Self::reg => rustc_span::sym::reg,
Self::wreg => rustc_span::sym::wreg,
}
}
pub fn parse(name: rustc_span::Symbol)
-> Result<Self, &'static [rustc_span::Symbol]> {
match name {
rustc_span::sym::reg => Ok(Self::reg),
rustc_span::sym::wreg => Ok(Self::wreg),
_ => Err(&[rustc_span::sym::reg, rustc_span::sym::wreg]),
}
}
}
pub(super) fn regclass_map()
->
rustc_data_structures::fx::FxHashMap<super::InlineAsmRegClass,
rustc_data_structures::fx::FxIndexSet<super::InlineAsmReg>> {
use rustc_data_structures::fx::FxHashMap;
use rustc_data_structures::fx::FxIndexSet;
use super::InlineAsmRegClass;
let mut map = FxHashMap::default();
map.insert(InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::reg),
FxIndexSet::default());
map.insert(InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::wreg),
FxIndexSet::default());
map
}def_reg_class! {
8 Bpf BpfInlineAsmRegClass {
9 reg,
10 wreg,
11 }
12}
13
14impl BpfInlineAsmRegClass {
15 pub fn valid_modifiers(self, _arch: InlineAsmArch) -> &'static [char] {
16 &[]
17 }
18
19 pub fn suggest_class(self, _arch: InlineAsmArch, _ty: InlineAsmType) -> Option<Self> {
20 None
21 }
22
23 pub fn suggest_modifier(
24 self,
25 _arch: InlineAsmArch,
26 _ty: InlineAsmType,
27 ) -> Option<ModifierInfo> {
28 None
29 }
30
31 pub fn default_modifier(self, _arch: InlineAsmArch) -> Option<ModifierInfo> {
32 None
33 }
34
35 pub fn supported_types(
36 self,
37 _arch: InlineAsmArch,
38 ) -> &'static [(InlineAsmType, Option<Symbol>)] {
39 match self {
40 Self::reg => {
use super::InlineAsmType::*;
&[(I8, None), (I16, None), (I32, None), (I64, None)]
}types! { _: I8, I16, I32, I64; },
41 Self::wreg => {
use super::InlineAsmType::*;
&[(I8, Some(rustc_span::sym::alu32)), (I16, Some(rustc_span::sym::alu32)),
(I32, Some(rustc_span::sym::alu32))]
}types! { alu32: I8, I16, I32; },
42 }
43 }
44}
45
46#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
pub enum BpfInlineAsmReg {
r0,
r1,
r2,
r3,
r4,
r5,
r6,
r7,
r8,
r9,
w0,
w1,
w2,
w3,
w4,
w5,
w6,
w7,
w8,
w9,
}
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::marker::Copy for BpfInlineAsmReg { }
#[automatically_derived]
#[doc(hidden)]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
unsafe impl ::core::clone::TrivialClone for BpfInlineAsmReg { }
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::clone::Clone for BpfInlineAsmReg {
#[inline]
fn clone(&self) -> BpfInlineAsmReg { *self }
}
const _: () =
{
impl<__E: ::rustc_span::SpanEncoder> ::rustc_serialize::Encodable<__E>
for BpfInlineAsmReg {
fn encode(&self, __encoder: &mut __E) {
let disc =
match *self {
BpfInlineAsmReg::r0 => { 0usize }
BpfInlineAsmReg::r1 => { 1usize }
BpfInlineAsmReg::r2 => { 2usize }
BpfInlineAsmReg::r3 => { 3usize }
BpfInlineAsmReg::r4 => { 4usize }
BpfInlineAsmReg::r5 => { 5usize }
BpfInlineAsmReg::r6 => { 6usize }
BpfInlineAsmReg::r7 => { 7usize }
BpfInlineAsmReg::r8 => { 8usize }
BpfInlineAsmReg::r9 => { 9usize }
BpfInlineAsmReg::w0 => { 10usize }
BpfInlineAsmReg::w1 => { 11usize }
BpfInlineAsmReg::w2 => { 12usize }
BpfInlineAsmReg::w3 => { 13usize }
BpfInlineAsmReg::w4 => { 14usize }
BpfInlineAsmReg::w5 => { 15usize }
BpfInlineAsmReg::w6 => { 16usize }
BpfInlineAsmReg::w7 => { 17usize }
BpfInlineAsmReg::w8 => { 18usize }
BpfInlineAsmReg::w9 => { 19usize }
};
::rustc_serialize::Encoder::emit_u8(__encoder, disc as u8);
match *self {
BpfInlineAsmReg::r0 => {}
BpfInlineAsmReg::r1 => {}
BpfInlineAsmReg::r2 => {}
BpfInlineAsmReg::r3 => {}
BpfInlineAsmReg::r4 => {}
BpfInlineAsmReg::r5 => {}
BpfInlineAsmReg::r6 => {}
BpfInlineAsmReg::r7 => {}
BpfInlineAsmReg::r8 => {}
BpfInlineAsmReg::r9 => {}
BpfInlineAsmReg::w0 => {}
BpfInlineAsmReg::w1 => {}
BpfInlineAsmReg::w2 => {}
BpfInlineAsmReg::w3 => {}
BpfInlineAsmReg::w4 => {}
BpfInlineAsmReg::w5 => {}
BpfInlineAsmReg::w6 => {}
BpfInlineAsmReg::w7 => {}
BpfInlineAsmReg::w8 => {}
BpfInlineAsmReg::w9 => {}
}
}
}
};
const _: () =
{
impl<__D: ::rustc_span::SpanDecoder> ::rustc_serialize::Decodable<__D>
for BpfInlineAsmReg {
fn decode(__decoder: &mut __D) -> Self {
match ::rustc_serialize::Decoder::read_u8(__decoder) as usize
{
0usize => { BpfInlineAsmReg::r0 }
1usize => { BpfInlineAsmReg::r1 }
2usize => { BpfInlineAsmReg::r2 }
3usize => { BpfInlineAsmReg::r3 }
4usize => { BpfInlineAsmReg::r4 }
5usize => { BpfInlineAsmReg::r5 }
6usize => { BpfInlineAsmReg::r6 }
7usize => { BpfInlineAsmReg::r7 }
8usize => { BpfInlineAsmReg::r8 }
9usize => { BpfInlineAsmReg::r9 }
10usize => { BpfInlineAsmReg::w0 }
11usize => { BpfInlineAsmReg::w1 }
12usize => { BpfInlineAsmReg::w2 }
13usize => { BpfInlineAsmReg::w3 }
14usize => { BpfInlineAsmReg::w4 }
15usize => { BpfInlineAsmReg::w5 }
16usize => { BpfInlineAsmReg::w6 }
17usize => { BpfInlineAsmReg::w7 }
18usize => { BpfInlineAsmReg::w8 }
19usize => { BpfInlineAsmReg::w9 }
n => {
::core::panicking::panic_fmt(format_args!("invalid enum variant tag while decoding `BpfInlineAsmReg`, expected 0..20, actual {0}",
n));
}
}
}
}
};
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::fmt::Debug for BpfInlineAsmReg {
#[inline]
fn fmt(&self, f: &mut ::core::fmt::Formatter) -> ::core::fmt::Result {
::core::fmt::Formatter::write_str(f,
match self {
BpfInlineAsmReg::r0 => "r0",
BpfInlineAsmReg::r1 => "r1",
BpfInlineAsmReg::r2 => "r2",
BpfInlineAsmReg::r3 => "r3",
BpfInlineAsmReg::r4 => "r4",
BpfInlineAsmReg::r5 => "r5",
BpfInlineAsmReg::r6 => "r6",
BpfInlineAsmReg::r7 => "r7",
BpfInlineAsmReg::r8 => "r8",
BpfInlineAsmReg::r9 => "r9",
BpfInlineAsmReg::w0 => "w0",
BpfInlineAsmReg::w1 => "w1",
BpfInlineAsmReg::w2 => "w2",
BpfInlineAsmReg::w3 => "w3",
BpfInlineAsmReg::w4 => "w4",
BpfInlineAsmReg::w5 => "w5",
BpfInlineAsmReg::w6 => "w6",
BpfInlineAsmReg::w7 => "w7",
BpfInlineAsmReg::w8 => "w8",
BpfInlineAsmReg::w9 => "w9",
})
}
}
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::cmp::Eq for BpfInlineAsmReg {
#[inline]
#[doc(hidden)]
#[coverage(off)]
fn assert_receiver_is_total_eq(&self) {}
}
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::marker::StructuralPartialEq for BpfInlineAsmReg { }
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::cmp::PartialEq for BpfInlineAsmReg {
#[inline]
fn eq(&self, other: &BpfInlineAsmReg) -> bool {
let __self_discr = ::core::intrinsics::discriminant_value(self);
let __arg1_discr = ::core::intrinsics::discriminant_value(other);
__self_discr == __arg1_discr
}
}
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::cmp::PartialOrd for BpfInlineAsmReg {
#[inline]
fn partial_cmp(&self, other: &BpfInlineAsmReg)
-> ::core::option::Option<::core::cmp::Ordering> {
let __self_discr = ::core::intrinsics::discriminant_value(self);
let __arg1_discr = ::core::intrinsics::discriminant_value(other);
::core::cmp::PartialOrd::partial_cmp(&__self_discr, &__arg1_discr)
}
}
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::hash::Hash for BpfInlineAsmReg {
#[inline]
fn hash<__H: ::core::hash::Hasher>(&self, state: &mut __H) {
let __self_discr = ::core::intrinsics::discriminant_value(self);
::core::hash::Hash::hash(&__self_discr, state)
}
}
const _: () =
{
impl<__CTX> ::rustc_data_structures::stable_hasher::HashStable<__CTX>
for BpfInlineAsmReg where __CTX: crate::HashStableContext {
#[inline]
fn hash_stable(&self, __hcx: &mut __CTX,
__hasher:
&mut ::rustc_data_structures::stable_hasher::StableHasher) {
::std::mem::discriminant(self).hash_stable(__hcx, __hasher);
match *self {
BpfInlineAsmReg::r0 => {}
BpfInlineAsmReg::r1 => {}
BpfInlineAsmReg::r2 => {}
BpfInlineAsmReg::r3 => {}
BpfInlineAsmReg::r4 => {}
BpfInlineAsmReg::r5 => {}
BpfInlineAsmReg::r6 => {}
BpfInlineAsmReg::r7 => {}
BpfInlineAsmReg::r8 => {}
BpfInlineAsmReg::r9 => {}
BpfInlineAsmReg::w0 => {}
BpfInlineAsmReg::w1 => {}
BpfInlineAsmReg::w2 => {}
BpfInlineAsmReg::w3 => {}
BpfInlineAsmReg::w4 => {}
BpfInlineAsmReg::w5 => {}
BpfInlineAsmReg::w6 => {}
BpfInlineAsmReg::w7 => {}
BpfInlineAsmReg::w8 => {}
BpfInlineAsmReg::w9 => {}
}
}
}
};
impl BpfInlineAsmReg {
pub fn name(self) -> &'static str {
match self {
Self::r0 => "r0",
Self::r1 => "r1",
Self::r2 => "r2",
Self::r3 => "r3",
Self::r4 => "r4",
Self::r5 => "r5",
Self::r6 => "r6",
Self::r7 => "r7",
Self::r8 => "r8",
Self::r9 => "r9",
Self::w0 => "w0",
Self::w1 => "w1",
Self::w2 => "w2",
Self::w3 => "w3",
Self::w4 => "w4",
Self::w5 => "w5",
Self::w6 => "w6",
Self::w7 => "w7",
Self::w8 => "w8",
Self::w9 => "w9",
}
}
pub fn reg_class(self) -> BpfInlineAsmRegClass {
match self {
Self::r0 => BpfInlineAsmRegClass::reg,
Self::r1 => BpfInlineAsmRegClass::reg,
Self::r2 => BpfInlineAsmRegClass::reg,
Self::r3 => BpfInlineAsmRegClass::reg,
Self::r4 => BpfInlineAsmRegClass::reg,
Self::r5 => BpfInlineAsmRegClass::reg,
Self::r6 => BpfInlineAsmRegClass::reg,
Self::r7 => BpfInlineAsmRegClass::reg,
Self::r8 => BpfInlineAsmRegClass::reg,
Self::r9 => BpfInlineAsmRegClass::reg,
Self::w0 => BpfInlineAsmRegClass::wreg,
Self::w1 => BpfInlineAsmRegClass::wreg,
Self::w2 => BpfInlineAsmRegClass::wreg,
Self::w3 => BpfInlineAsmRegClass::wreg,
Self::w4 => BpfInlineAsmRegClass::wreg,
Self::w5 => BpfInlineAsmRegClass::wreg,
Self::w6 => BpfInlineAsmRegClass::wreg,
Self::w7 => BpfInlineAsmRegClass::wreg,
Self::w8 => BpfInlineAsmRegClass::wreg,
Self::w9 => BpfInlineAsmRegClass::wreg,
}
}
pub fn parse(name: &str) -> Result<Self, &'static str> {
match name {
"r0" => Ok(Self::r0),
"r1" => Ok(Self::r1),
"r2" => Ok(Self::r2),
"r3" => Ok(Self::r3),
"r4" => Ok(Self::r4),
"r5" => Ok(Self::r5),
"r6" => Ok(Self::r6),
"r7" => Ok(Self::r7),
"r8" => Ok(Self::r8),
"r9" => Ok(Self::r9),
"w0" => Ok(Self::w0),
"w1" => Ok(Self::w1),
"w2" => Ok(Self::w2),
"w3" => Ok(Self::w3),
"w4" => Ok(Self::w4),
"w5" => Ok(Self::w5),
"w6" => Ok(Self::w6),
"w7" => Ok(Self::w7),
"w8" => Ok(Self::w8),
"w9" => Ok(Self::w9),
"r10" | "w10" =>
Err("the stack pointer cannot be used as an operand for inline asm"),
_ => Err("unknown register"),
}
}
pub fn validate(self, _arch: super::InlineAsmArch,
_reloc_model: crate::spec::RelocModel,
_target_features: &rustc_data_structures::fx::FxIndexSet<Symbol>,
_target: &crate::spec::Target, _is_clobber: bool)
-> Result<(), &'static str> {
match self {
Self::r0 => { Ok(()) }
Self::r1 => { Ok(()) }
Self::r2 => { Ok(()) }
Self::r3 => { Ok(()) }
Self::r4 => { Ok(()) }
Self::r5 => { Ok(()) }
Self::r6 => { Ok(()) }
Self::r7 => { Ok(()) }
Self::r8 => { Ok(()) }
Self::r9 => { Ok(()) }
Self::w0 => { Ok(()) }
Self::w1 => { Ok(()) }
Self::w2 => { Ok(()) }
Self::w3 => { Ok(()) }
Self::w4 => { Ok(()) }
Self::w5 => { Ok(()) }
Self::w6 => { Ok(()) }
Self::w7 => { Ok(()) }
Self::w8 => { Ok(()) }
Self::w9 => { Ok(()) }
}
}
}
pub(super) fn fill_reg_map(_arch: super::InlineAsmArch,
_reloc_model: crate::spec::RelocModel,
_target_features: &rustc_data_structures::fx::FxIndexSet<Symbol>,
_target: &crate::spec::Target,
_map:
&mut rustc_data_structures::fx::FxHashMap<super::InlineAsmRegClass,
rustc_data_structures::fx::FxIndexSet<super::InlineAsmReg>>) {
#[allow(unused_imports)]
use super::{InlineAsmReg, InlineAsmRegClass};
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::reg))
{
set.insert(InlineAsmReg::Bpf(BpfInlineAsmReg::r0));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::reg))
{
set.insert(InlineAsmReg::Bpf(BpfInlineAsmReg::r1));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::reg))
{
set.insert(InlineAsmReg::Bpf(BpfInlineAsmReg::r2));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::reg))
{
set.insert(InlineAsmReg::Bpf(BpfInlineAsmReg::r3));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::reg))
{
set.insert(InlineAsmReg::Bpf(BpfInlineAsmReg::r4));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::reg))
{
set.insert(InlineAsmReg::Bpf(BpfInlineAsmReg::r5));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::reg))
{
set.insert(InlineAsmReg::Bpf(BpfInlineAsmReg::r6));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::reg))
{
set.insert(InlineAsmReg::Bpf(BpfInlineAsmReg::r7));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::reg))
{
set.insert(InlineAsmReg::Bpf(BpfInlineAsmReg::r8));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::reg))
{
set.insert(InlineAsmReg::Bpf(BpfInlineAsmReg::r9));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::wreg))
{
set.insert(InlineAsmReg::Bpf(BpfInlineAsmReg::w0));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::wreg))
{
set.insert(InlineAsmReg::Bpf(BpfInlineAsmReg::w1));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::wreg))
{
set.insert(InlineAsmReg::Bpf(BpfInlineAsmReg::w2));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::wreg))
{
set.insert(InlineAsmReg::Bpf(BpfInlineAsmReg::w3));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::wreg))
{
set.insert(InlineAsmReg::Bpf(BpfInlineAsmReg::w4));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::wreg))
{
set.insert(InlineAsmReg::Bpf(BpfInlineAsmReg::w5));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::wreg))
{
set.insert(InlineAsmReg::Bpf(BpfInlineAsmReg::w6));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::wreg))
{
set.insert(InlineAsmReg::Bpf(BpfInlineAsmReg::w7));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::wreg))
{
set.insert(InlineAsmReg::Bpf(BpfInlineAsmReg::w8));
}
}
if true {
if let Some(set) =
_map.get_mut(&InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::wreg))
{
set.insert(InlineAsmReg::Bpf(BpfInlineAsmReg::w9));
}
}
}def_regs! {
47 Bpf BpfInlineAsmReg BpfInlineAsmRegClass {
48 r0: reg = ["r0"],
49 r1: reg = ["r1"],
50 r2: reg = ["r2"],
51 r3: reg = ["r3"],
52 r4: reg = ["r4"],
53 r5: reg = ["r5"],
54 r6: reg = ["r6"],
55 r7: reg = ["r7"],
56 r8: reg = ["r8"],
57 r9: reg = ["r9"],
58 w0: wreg = ["w0"],
59 w1: wreg = ["w1"],
60 w2: wreg = ["w2"],
61 w3: wreg = ["w3"],
62 w4: wreg = ["w4"],
63 w5: wreg = ["w5"],
64 w6: wreg = ["w6"],
65 w7: wreg = ["w7"],
66 w8: wreg = ["w8"],
67 w9: wreg = ["w9"],
68
69 #error = ["r10", "w10"] =>
70 "the stack pointer cannot be used as an operand for inline asm",
71 }
72}
73
74impl BpfInlineAsmReg {
75 pub fn emit(
76 self,
77 out: &mut dyn fmt::Write,
78 _arch: InlineAsmArch,
79 _modifier: Option<char>,
80 ) -> fmt::Result {
81 out.write_str(self.name())
82 }
83
84 pub fn overlapping_regs(self, mut cb: impl FnMut(BpfInlineAsmReg)) {
85 cb(self);
86
87 macro_rules! reg_conflicts {
88 (
89 $(
90 $r:ident : $w:ident
91 ),*
92 ) => {
93 match self {
94 $(
95 Self::$r => {
96 cb(Self::$w);
97 }
98 Self::$w => {
99 cb(Self::$r);
100 }
101 )*
102 }
103 };
104 }
105
106 match self {
Self::r0 => { cb(Self::w0); }
Self::w0 => { cb(Self::r0); }
Self::r1 => { cb(Self::w1); }
Self::w1 => { cb(Self::r1); }
Self::r2 => { cb(Self::w2); }
Self::w2 => { cb(Self::r2); }
Self::r3 => { cb(Self::w3); }
Self::w3 => { cb(Self::r3); }
Self::r4 => { cb(Self::w4); }
Self::w4 => { cb(Self::r4); }
Self::r5 => { cb(Self::w5); }
Self::w5 => { cb(Self::r5); }
Self::r6 => { cb(Self::w6); }
Self::w6 => { cb(Self::r6); }
Self::r7 => { cb(Self::w7); }
Self::w7 => { cb(Self::r7); }
Self::r8 => { cb(Self::w8); }
Self::w8 => { cb(Self::r8); }
Self::r9 => { cb(Self::w9); }
Self::w9 => { cb(Self::r9); }
}reg_conflicts! {
107 r0 : w0,
108 r1 : w1,
109 r2 : w2,
110 r3 : w3,
111 r4 : w4,
112 r5 : w5,
113 r6 : w6,
114 r7 : w7,
115 r8 : w8,
116 r9 : w9
117 }
118 }
119}