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rustc_target/asm/
loongarch.rs

1use std::fmt;
2
3use rustc_span::Symbol;
4
5use super::{InlineAsmArch, InlineAsmType, ModifierInfo};
6
7#[allow(non_camel_case_types)]
pub enum LoongArchInlineAsmRegClass { reg, freg, }
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::marker::Copy for LoongArchInlineAsmRegClass { }
#[automatically_derived]
#[doc(hidden)]
#[allow(non_camel_case_types)]
unsafe impl ::core::clone::TrivialClone for LoongArchInlineAsmRegClass { }
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::clone::Clone for LoongArchInlineAsmRegClass {
    #[inline]
    fn clone(&self) -> LoongArchInlineAsmRegClass { *self }
}
const _: () =
    {
        impl<__E: ::rustc_span::SpanEncoder> ::rustc_serialize::Encodable<__E>
            for LoongArchInlineAsmRegClass {
            fn encode(&self, __encoder: &mut __E) {
                let disc =
                    match *self {
                        LoongArchInlineAsmRegClass::reg => { 0usize }
                        LoongArchInlineAsmRegClass::freg => { 1usize }
                    };
                ::rustc_serialize::Encoder::emit_u8(__encoder, disc as u8);
                match *self {
                    LoongArchInlineAsmRegClass::reg => {}
                    LoongArchInlineAsmRegClass::freg => {}
                }
            }
        }
    };
const _: () =
    {
        impl<__D: ::rustc_span::SpanDecoder> ::rustc_serialize::Decodable<__D>
            for LoongArchInlineAsmRegClass {
            fn decode(__decoder: &mut __D) -> Self {
                match ::rustc_serialize::Decoder::read_u8(__decoder) as usize
                    {
                    0usize => { LoongArchInlineAsmRegClass::reg }
                    1usize => { LoongArchInlineAsmRegClass::freg }
                    n => {
                        ::core::panicking::panic_fmt(format_args!("invalid enum variant tag while decoding `LoongArchInlineAsmRegClass`, expected 0..2, actual {0}",
                                n));
                    }
                }
            }
        }
    };
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::fmt::Debug for LoongArchInlineAsmRegClass {
    #[inline]
    fn fmt(&self, f: &mut ::core::fmt::Formatter) -> ::core::fmt::Result {
        ::core::fmt::Formatter::write_str(f,
            match self {
                LoongArchInlineAsmRegClass::reg => "reg",
                LoongArchInlineAsmRegClass::freg => "freg",
            })
    }
}
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::cmp::Eq for LoongArchInlineAsmRegClass {
    #[inline]
    #[doc(hidden)]
    #[coverage(off)]
    fn assert_receiver_is_total_eq(&self) {}
}
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::marker::StructuralPartialEq for LoongArchInlineAsmRegClass { }
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::cmp::PartialEq for LoongArchInlineAsmRegClass {
    #[inline]
    fn eq(&self, other: &LoongArchInlineAsmRegClass) -> bool {
        let __self_discr = ::core::intrinsics::discriminant_value(self);
        let __arg1_discr = ::core::intrinsics::discriminant_value(other);
        __self_discr == __arg1_discr
    }
}
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::cmp::PartialOrd for LoongArchInlineAsmRegClass {
    #[inline]
    fn partial_cmp(&self, other: &LoongArchInlineAsmRegClass)
        -> ::core::option::Option<::core::cmp::Ordering> {
        let __self_discr = ::core::intrinsics::discriminant_value(self);
        let __arg1_discr = ::core::intrinsics::discriminant_value(other);
        ::core::cmp::PartialOrd::partial_cmp(&__self_discr, &__arg1_discr)
    }
}
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::hash::Hash for LoongArchInlineAsmRegClass {
    #[inline]
    fn hash<__H: ::core::hash::Hasher>(&self, state: &mut __H) {
        let __self_discr = ::core::intrinsics::discriminant_value(self);
        ::core::hash::Hash::hash(&__self_discr, state)
    }
}
const _: () =
    {
        impl<__CTX> ::rustc_data_structures::stable_hasher::HashStable<__CTX>
            for LoongArchInlineAsmRegClass where
            __CTX: crate::HashStableContext {
            #[inline]
            fn hash_stable(&self, __hcx: &mut __CTX,
                __hasher:
                    &mut ::rustc_data_structures::stable_hasher::StableHasher) {
                ::std::mem::discriminant(self).hash_stable(__hcx, __hasher);
                match *self {
                    LoongArchInlineAsmRegClass::reg => {}
                    LoongArchInlineAsmRegClass::freg => {}
                }
            }
        }
    };
impl LoongArchInlineAsmRegClass {
    pub fn name(self) -> rustc_span::Symbol {
        match self {
            Self::reg => rustc_span::sym::reg,
            Self::freg => rustc_span::sym::freg,
        }
    }
    pub fn parse(name: rustc_span::Symbol)
        -> Result<Self, &'static [rustc_span::Symbol]> {
        match name {
            rustc_span::sym::reg => Ok(Self::reg),
            rustc_span::sym::freg => Ok(Self::freg),
            _ => Err(&[rustc_span::sym::reg, rustc_span::sym::freg]),
        }
    }
}
pub(super) fn regclass_map()
    ->
        rustc_data_structures::fx::FxHashMap<super::InlineAsmRegClass,
        rustc_data_structures::fx::FxIndexSet<super::InlineAsmReg>> {
    use rustc_data_structures::fx::FxHashMap;
    use rustc_data_structures::fx::FxIndexSet;
    use super::InlineAsmRegClass;
    let mut map = FxHashMap::default();
    map.insert(InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::reg),
        FxIndexSet::default());
    map.insert(InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg),
        FxIndexSet::default());
    map
}def_reg_class! {
8    LoongArch LoongArchInlineAsmRegClass {
9        reg,
10        freg,
11    }
12}
13
14impl LoongArchInlineAsmRegClass {
15    pub fn valid_modifiers(self, _arch: super::InlineAsmArch) -> &'static [char] {
16        &[]
17    }
18
19    pub fn suggest_class(self, _arch: InlineAsmArch, _ty: InlineAsmType) -> Option<Self> {
20        None
21    }
22
23    pub fn suggest_modifier(
24        self,
25        _arch: InlineAsmArch,
26        _ty: InlineAsmType,
27    ) -> Option<ModifierInfo> {
28        None
29    }
30
31    pub fn default_modifier(self, _arch: InlineAsmArch) -> Option<ModifierInfo> {
32        None
33    }
34
35    pub fn supported_types(
36        self,
37        arch: InlineAsmArch,
38    ) -> &'static [(InlineAsmType, Option<Symbol>)] {
39        match (self, arch) {
40            (Self::reg, InlineAsmArch::LoongArch64) => {
41                {
    use super::InlineAsmType::*;
    &[(I8, None), (I16, None), (I32, None), (I64, None), (F16, None),
                (F32, None), (F64, None)]
}types! { _: I8, I16, I32, I64, F16, F32, F64; }
42            }
43            (Self::reg, InlineAsmArch::LoongArch32) => {
    use super::InlineAsmType::*;
    &[(I8, None), (I16, None), (I32, None), (F16, None), (F32, None)]
}types! { _: I8, I16, I32, F16, F32; },
44            (Self::freg, _) => {
    use super::InlineAsmType::*;
    &[(F16, Some(rustc_span::sym::f)), (F32, Some(rustc_span::sym::f)),
                (F64, Some(rustc_span::sym::d))]
}types! { f: F16, F32; d: F64; },
45            _ => {
    ::core::panicking::panic_fmt(format_args!("internal error: entered unreachable code: {0}",
            format_args!("unsupported register class")));
}unreachable!("unsupported register class"),
46        }
47    }
48}
49
50// The reserved registers are taken from <https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.cpp#79>
51#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
pub enum LoongArchInlineAsmReg {
    r1,
    r4,
    r5,
    r6,
    r7,
    r8,
    r9,
    r10,
    r11,
    r12,
    r13,
    r14,
    r15,
    r16,
    r17,
    r18,
    r19,
    r20,
    r23,
    r24,
    r25,
    r26,
    r27,
    r28,
    r29,
    r30,
    f0,
    f1,
    f2,
    f3,
    f4,
    f5,
    f6,
    f7,
    f8,
    f9,
    f10,
    f11,
    f12,
    f13,
    f14,
    f15,
    f16,
    f17,
    f18,
    f19,
    f20,
    f21,
    f22,
    f23,
    f24,
    f25,
    f26,
    f27,
    f28,
    f29,
    f30,
    f31,
}
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::marker::Copy for LoongArchInlineAsmReg { }
#[automatically_derived]
#[doc(hidden)]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
unsafe impl ::core::clone::TrivialClone for LoongArchInlineAsmReg { }
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::clone::Clone for LoongArchInlineAsmReg {
    #[inline]
    fn clone(&self) -> LoongArchInlineAsmReg { *self }
}
const _: () =
    {
        impl<__E: ::rustc_span::SpanEncoder> ::rustc_serialize::Encodable<__E>
            for LoongArchInlineAsmReg {
            fn encode(&self, __encoder: &mut __E) {
                let disc =
                    match *self {
                        LoongArchInlineAsmReg::r1 => { 0usize }
                        LoongArchInlineAsmReg::r4 => { 1usize }
                        LoongArchInlineAsmReg::r5 => { 2usize }
                        LoongArchInlineAsmReg::r6 => { 3usize }
                        LoongArchInlineAsmReg::r7 => { 4usize }
                        LoongArchInlineAsmReg::r8 => { 5usize }
                        LoongArchInlineAsmReg::r9 => { 6usize }
                        LoongArchInlineAsmReg::r10 => { 7usize }
                        LoongArchInlineAsmReg::r11 => { 8usize }
                        LoongArchInlineAsmReg::r12 => { 9usize }
                        LoongArchInlineAsmReg::r13 => { 10usize }
                        LoongArchInlineAsmReg::r14 => { 11usize }
                        LoongArchInlineAsmReg::r15 => { 12usize }
                        LoongArchInlineAsmReg::r16 => { 13usize }
                        LoongArchInlineAsmReg::r17 => { 14usize }
                        LoongArchInlineAsmReg::r18 => { 15usize }
                        LoongArchInlineAsmReg::r19 => { 16usize }
                        LoongArchInlineAsmReg::r20 => { 17usize }
                        LoongArchInlineAsmReg::r23 => { 18usize }
                        LoongArchInlineAsmReg::r24 => { 19usize }
                        LoongArchInlineAsmReg::r25 => { 20usize }
                        LoongArchInlineAsmReg::r26 => { 21usize }
                        LoongArchInlineAsmReg::r27 => { 22usize }
                        LoongArchInlineAsmReg::r28 => { 23usize }
                        LoongArchInlineAsmReg::r29 => { 24usize }
                        LoongArchInlineAsmReg::r30 => { 25usize }
                        LoongArchInlineAsmReg::f0 => { 26usize }
                        LoongArchInlineAsmReg::f1 => { 27usize }
                        LoongArchInlineAsmReg::f2 => { 28usize }
                        LoongArchInlineAsmReg::f3 => { 29usize }
                        LoongArchInlineAsmReg::f4 => { 30usize }
                        LoongArchInlineAsmReg::f5 => { 31usize }
                        LoongArchInlineAsmReg::f6 => { 32usize }
                        LoongArchInlineAsmReg::f7 => { 33usize }
                        LoongArchInlineAsmReg::f8 => { 34usize }
                        LoongArchInlineAsmReg::f9 => { 35usize }
                        LoongArchInlineAsmReg::f10 => { 36usize }
                        LoongArchInlineAsmReg::f11 => { 37usize }
                        LoongArchInlineAsmReg::f12 => { 38usize }
                        LoongArchInlineAsmReg::f13 => { 39usize }
                        LoongArchInlineAsmReg::f14 => { 40usize }
                        LoongArchInlineAsmReg::f15 => { 41usize }
                        LoongArchInlineAsmReg::f16 => { 42usize }
                        LoongArchInlineAsmReg::f17 => { 43usize }
                        LoongArchInlineAsmReg::f18 => { 44usize }
                        LoongArchInlineAsmReg::f19 => { 45usize }
                        LoongArchInlineAsmReg::f20 => { 46usize }
                        LoongArchInlineAsmReg::f21 => { 47usize }
                        LoongArchInlineAsmReg::f22 => { 48usize }
                        LoongArchInlineAsmReg::f23 => { 49usize }
                        LoongArchInlineAsmReg::f24 => { 50usize }
                        LoongArchInlineAsmReg::f25 => { 51usize }
                        LoongArchInlineAsmReg::f26 => { 52usize }
                        LoongArchInlineAsmReg::f27 => { 53usize }
                        LoongArchInlineAsmReg::f28 => { 54usize }
                        LoongArchInlineAsmReg::f29 => { 55usize }
                        LoongArchInlineAsmReg::f30 => { 56usize }
                        LoongArchInlineAsmReg::f31 => { 57usize }
                    };
                ::rustc_serialize::Encoder::emit_u8(__encoder, disc as u8);
                match *self {
                    LoongArchInlineAsmReg::r1 => {}
                    LoongArchInlineAsmReg::r4 => {}
                    LoongArchInlineAsmReg::r5 => {}
                    LoongArchInlineAsmReg::r6 => {}
                    LoongArchInlineAsmReg::r7 => {}
                    LoongArchInlineAsmReg::r8 => {}
                    LoongArchInlineAsmReg::r9 => {}
                    LoongArchInlineAsmReg::r10 => {}
                    LoongArchInlineAsmReg::r11 => {}
                    LoongArchInlineAsmReg::r12 => {}
                    LoongArchInlineAsmReg::r13 => {}
                    LoongArchInlineAsmReg::r14 => {}
                    LoongArchInlineAsmReg::r15 => {}
                    LoongArchInlineAsmReg::r16 => {}
                    LoongArchInlineAsmReg::r17 => {}
                    LoongArchInlineAsmReg::r18 => {}
                    LoongArchInlineAsmReg::r19 => {}
                    LoongArchInlineAsmReg::r20 => {}
                    LoongArchInlineAsmReg::r23 => {}
                    LoongArchInlineAsmReg::r24 => {}
                    LoongArchInlineAsmReg::r25 => {}
                    LoongArchInlineAsmReg::r26 => {}
                    LoongArchInlineAsmReg::r27 => {}
                    LoongArchInlineAsmReg::r28 => {}
                    LoongArchInlineAsmReg::r29 => {}
                    LoongArchInlineAsmReg::r30 => {}
                    LoongArchInlineAsmReg::f0 => {}
                    LoongArchInlineAsmReg::f1 => {}
                    LoongArchInlineAsmReg::f2 => {}
                    LoongArchInlineAsmReg::f3 => {}
                    LoongArchInlineAsmReg::f4 => {}
                    LoongArchInlineAsmReg::f5 => {}
                    LoongArchInlineAsmReg::f6 => {}
                    LoongArchInlineAsmReg::f7 => {}
                    LoongArchInlineAsmReg::f8 => {}
                    LoongArchInlineAsmReg::f9 => {}
                    LoongArchInlineAsmReg::f10 => {}
                    LoongArchInlineAsmReg::f11 => {}
                    LoongArchInlineAsmReg::f12 => {}
                    LoongArchInlineAsmReg::f13 => {}
                    LoongArchInlineAsmReg::f14 => {}
                    LoongArchInlineAsmReg::f15 => {}
                    LoongArchInlineAsmReg::f16 => {}
                    LoongArchInlineAsmReg::f17 => {}
                    LoongArchInlineAsmReg::f18 => {}
                    LoongArchInlineAsmReg::f19 => {}
                    LoongArchInlineAsmReg::f20 => {}
                    LoongArchInlineAsmReg::f21 => {}
                    LoongArchInlineAsmReg::f22 => {}
                    LoongArchInlineAsmReg::f23 => {}
                    LoongArchInlineAsmReg::f24 => {}
                    LoongArchInlineAsmReg::f25 => {}
                    LoongArchInlineAsmReg::f26 => {}
                    LoongArchInlineAsmReg::f27 => {}
                    LoongArchInlineAsmReg::f28 => {}
                    LoongArchInlineAsmReg::f29 => {}
                    LoongArchInlineAsmReg::f30 => {}
                    LoongArchInlineAsmReg::f31 => {}
                }
            }
        }
    };
const _: () =
    {
        impl<__D: ::rustc_span::SpanDecoder> ::rustc_serialize::Decodable<__D>
            for LoongArchInlineAsmReg {
            fn decode(__decoder: &mut __D) -> Self {
                match ::rustc_serialize::Decoder::read_u8(__decoder) as usize
                    {
                    0usize => { LoongArchInlineAsmReg::r1 }
                    1usize => { LoongArchInlineAsmReg::r4 }
                    2usize => { LoongArchInlineAsmReg::r5 }
                    3usize => { LoongArchInlineAsmReg::r6 }
                    4usize => { LoongArchInlineAsmReg::r7 }
                    5usize => { LoongArchInlineAsmReg::r8 }
                    6usize => { LoongArchInlineAsmReg::r9 }
                    7usize => { LoongArchInlineAsmReg::r10 }
                    8usize => { LoongArchInlineAsmReg::r11 }
                    9usize => { LoongArchInlineAsmReg::r12 }
                    10usize => { LoongArchInlineAsmReg::r13 }
                    11usize => { LoongArchInlineAsmReg::r14 }
                    12usize => { LoongArchInlineAsmReg::r15 }
                    13usize => { LoongArchInlineAsmReg::r16 }
                    14usize => { LoongArchInlineAsmReg::r17 }
                    15usize => { LoongArchInlineAsmReg::r18 }
                    16usize => { LoongArchInlineAsmReg::r19 }
                    17usize => { LoongArchInlineAsmReg::r20 }
                    18usize => { LoongArchInlineAsmReg::r23 }
                    19usize => { LoongArchInlineAsmReg::r24 }
                    20usize => { LoongArchInlineAsmReg::r25 }
                    21usize => { LoongArchInlineAsmReg::r26 }
                    22usize => { LoongArchInlineAsmReg::r27 }
                    23usize => { LoongArchInlineAsmReg::r28 }
                    24usize => { LoongArchInlineAsmReg::r29 }
                    25usize => { LoongArchInlineAsmReg::r30 }
                    26usize => { LoongArchInlineAsmReg::f0 }
                    27usize => { LoongArchInlineAsmReg::f1 }
                    28usize => { LoongArchInlineAsmReg::f2 }
                    29usize => { LoongArchInlineAsmReg::f3 }
                    30usize => { LoongArchInlineAsmReg::f4 }
                    31usize => { LoongArchInlineAsmReg::f5 }
                    32usize => { LoongArchInlineAsmReg::f6 }
                    33usize => { LoongArchInlineAsmReg::f7 }
                    34usize => { LoongArchInlineAsmReg::f8 }
                    35usize => { LoongArchInlineAsmReg::f9 }
                    36usize => { LoongArchInlineAsmReg::f10 }
                    37usize => { LoongArchInlineAsmReg::f11 }
                    38usize => { LoongArchInlineAsmReg::f12 }
                    39usize => { LoongArchInlineAsmReg::f13 }
                    40usize => { LoongArchInlineAsmReg::f14 }
                    41usize => { LoongArchInlineAsmReg::f15 }
                    42usize => { LoongArchInlineAsmReg::f16 }
                    43usize => { LoongArchInlineAsmReg::f17 }
                    44usize => { LoongArchInlineAsmReg::f18 }
                    45usize => { LoongArchInlineAsmReg::f19 }
                    46usize => { LoongArchInlineAsmReg::f20 }
                    47usize => { LoongArchInlineAsmReg::f21 }
                    48usize => { LoongArchInlineAsmReg::f22 }
                    49usize => { LoongArchInlineAsmReg::f23 }
                    50usize => { LoongArchInlineAsmReg::f24 }
                    51usize => { LoongArchInlineAsmReg::f25 }
                    52usize => { LoongArchInlineAsmReg::f26 }
                    53usize => { LoongArchInlineAsmReg::f27 }
                    54usize => { LoongArchInlineAsmReg::f28 }
                    55usize => { LoongArchInlineAsmReg::f29 }
                    56usize => { LoongArchInlineAsmReg::f30 }
                    57usize => { LoongArchInlineAsmReg::f31 }
                    n => {
                        ::core::panicking::panic_fmt(format_args!("invalid enum variant tag while decoding `LoongArchInlineAsmReg`, expected 0..58, actual {0}",
                                n));
                    }
                }
            }
        }
    };
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::fmt::Debug for LoongArchInlineAsmReg {
    #[inline]
    fn fmt(&self, f: &mut ::core::fmt::Formatter) -> ::core::fmt::Result {
        ::core::fmt::Formatter::write_str(f,
            match self {
                LoongArchInlineAsmReg::r1 => "r1",
                LoongArchInlineAsmReg::r4 => "r4",
                LoongArchInlineAsmReg::r5 => "r5",
                LoongArchInlineAsmReg::r6 => "r6",
                LoongArchInlineAsmReg::r7 => "r7",
                LoongArchInlineAsmReg::r8 => "r8",
                LoongArchInlineAsmReg::r9 => "r9",
                LoongArchInlineAsmReg::r10 => "r10",
                LoongArchInlineAsmReg::r11 => "r11",
                LoongArchInlineAsmReg::r12 => "r12",
                LoongArchInlineAsmReg::r13 => "r13",
                LoongArchInlineAsmReg::r14 => "r14",
                LoongArchInlineAsmReg::r15 => "r15",
                LoongArchInlineAsmReg::r16 => "r16",
                LoongArchInlineAsmReg::r17 => "r17",
                LoongArchInlineAsmReg::r18 => "r18",
                LoongArchInlineAsmReg::r19 => "r19",
                LoongArchInlineAsmReg::r20 => "r20",
                LoongArchInlineAsmReg::r23 => "r23",
                LoongArchInlineAsmReg::r24 => "r24",
                LoongArchInlineAsmReg::r25 => "r25",
                LoongArchInlineAsmReg::r26 => "r26",
                LoongArchInlineAsmReg::r27 => "r27",
                LoongArchInlineAsmReg::r28 => "r28",
                LoongArchInlineAsmReg::r29 => "r29",
                LoongArchInlineAsmReg::r30 => "r30",
                LoongArchInlineAsmReg::f0 => "f0",
                LoongArchInlineAsmReg::f1 => "f1",
                LoongArchInlineAsmReg::f2 => "f2",
                LoongArchInlineAsmReg::f3 => "f3",
                LoongArchInlineAsmReg::f4 => "f4",
                LoongArchInlineAsmReg::f5 => "f5",
                LoongArchInlineAsmReg::f6 => "f6",
                LoongArchInlineAsmReg::f7 => "f7",
                LoongArchInlineAsmReg::f8 => "f8",
                LoongArchInlineAsmReg::f9 => "f9",
                LoongArchInlineAsmReg::f10 => "f10",
                LoongArchInlineAsmReg::f11 => "f11",
                LoongArchInlineAsmReg::f12 => "f12",
                LoongArchInlineAsmReg::f13 => "f13",
                LoongArchInlineAsmReg::f14 => "f14",
                LoongArchInlineAsmReg::f15 => "f15",
                LoongArchInlineAsmReg::f16 => "f16",
                LoongArchInlineAsmReg::f17 => "f17",
                LoongArchInlineAsmReg::f18 => "f18",
                LoongArchInlineAsmReg::f19 => "f19",
                LoongArchInlineAsmReg::f20 => "f20",
                LoongArchInlineAsmReg::f21 => "f21",
                LoongArchInlineAsmReg::f22 => "f22",
                LoongArchInlineAsmReg::f23 => "f23",
                LoongArchInlineAsmReg::f24 => "f24",
                LoongArchInlineAsmReg::f25 => "f25",
                LoongArchInlineAsmReg::f26 => "f26",
                LoongArchInlineAsmReg::f27 => "f27",
                LoongArchInlineAsmReg::f28 => "f28",
                LoongArchInlineAsmReg::f29 => "f29",
                LoongArchInlineAsmReg::f30 => "f30",
                LoongArchInlineAsmReg::f31 => "f31",
            })
    }
}
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::cmp::Eq for LoongArchInlineAsmReg {
    #[inline]
    #[doc(hidden)]
    #[coverage(off)]
    fn assert_receiver_is_total_eq(&self) {}
}
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::marker::StructuralPartialEq for LoongArchInlineAsmReg { }
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::cmp::PartialEq for LoongArchInlineAsmReg {
    #[inline]
    fn eq(&self, other: &LoongArchInlineAsmReg) -> bool {
        let __self_discr = ::core::intrinsics::discriminant_value(self);
        let __arg1_discr = ::core::intrinsics::discriminant_value(other);
        __self_discr == __arg1_discr
    }
}
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::cmp::PartialOrd for LoongArchInlineAsmReg {
    #[inline]
    fn partial_cmp(&self, other: &LoongArchInlineAsmReg)
        -> ::core::option::Option<::core::cmp::Ordering> {
        let __self_discr = ::core::intrinsics::discriminant_value(self);
        let __arg1_discr = ::core::intrinsics::discriminant_value(other);
        ::core::cmp::PartialOrd::partial_cmp(&__self_discr, &__arg1_discr)
    }
}
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::hash::Hash for LoongArchInlineAsmReg {
    #[inline]
    fn hash<__H: ::core::hash::Hasher>(&self, state: &mut __H) {
        let __self_discr = ::core::intrinsics::discriminant_value(self);
        ::core::hash::Hash::hash(&__self_discr, state)
    }
}
const _: () =
    {
        impl<__CTX> ::rustc_data_structures::stable_hasher::HashStable<__CTX>
            for LoongArchInlineAsmReg where __CTX: crate::HashStableContext {
            #[inline]
            fn hash_stable(&self, __hcx: &mut __CTX,
                __hasher:
                    &mut ::rustc_data_structures::stable_hasher::StableHasher) {
                ::std::mem::discriminant(self).hash_stable(__hcx, __hasher);
                match *self {
                    LoongArchInlineAsmReg::r1 => {}
                    LoongArchInlineAsmReg::r4 => {}
                    LoongArchInlineAsmReg::r5 => {}
                    LoongArchInlineAsmReg::r6 => {}
                    LoongArchInlineAsmReg::r7 => {}
                    LoongArchInlineAsmReg::r8 => {}
                    LoongArchInlineAsmReg::r9 => {}
                    LoongArchInlineAsmReg::r10 => {}
                    LoongArchInlineAsmReg::r11 => {}
                    LoongArchInlineAsmReg::r12 => {}
                    LoongArchInlineAsmReg::r13 => {}
                    LoongArchInlineAsmReg::r14 => {}
                    LoongArchInlineAsmReg::r15 => {}
                    LoongArchInlineAsmReg::r16 => {}
                    LoongArchInlineAsmReg::r17 => {}
                    LoongArchInlineAsmReg::r18 => {}
                    LoongArchInlineAsmReg::r19 => {}
                    LoongArchInlineAsmReg::r20 => {}
                    LoongArchInlineAsmReg::r23 => {}
                    LoongArchInlineAsmReg::r24 => {}
                    LoongArchInlineAsmReg::r25 => {}
                    LoongArchInlineAsmReg::r26 => {}
                    LoongArchInlineAsmReg::r27 => {}
                    LoongArchInlineAsmReg::r28 => {}
                    LoongArchInlineAsmReg::r29 => {}
                    LoongArchInlineAsmReg::r30 => {}
                    LoongArchInlineAsmReg::f0 => {}
                    LoongArchInlineAsmReg::f1 => {}
                    LoongArchInlineAsmReg::f2 => {}
                    LoongArchInlineAsmReg::f3 => {}
                    LoongArchInlineAsmReg::f4 => {}
                    LoongArchInlineAsmReg::f5 => {}
                    LoongArchInlineAsmReg::f6 => {}
                    LoongArchInlineAsmReg::f7 => {}
                    LoongArchInlineAsmReg::f8 => {}
                    LoongArchInlineAsmReg::f9 => {}
                    LoongArchInlineAsmReg::f10 => {}
                    LoongArchInlineAsmReg::f11 => {}
                    LoongArchInlineAsmReg::f12 => {}
                    LoongArchInlineAsmReg::f13 => {}
                    LoongArchInlineAsmReg::f14 => {}
                    LoongArchInlineAsmReg::f15 => {}
                    LoongArchInlineAsmReg::f16 => {}
                    LoongArchInlineAsmReg::f17 => {}
                    LoongArchInlineAsmReg::f18 => {}
                    LoongArchInlineAsmReg::f19 => {}
                    LoongArchInlineAsmReg::f20 => {}
                    LoongArchInlineAsmReg::f21 => {}
                    LoongArchInlineAsmReg::f22 => {}
                    LoongArchInlineAsmReg::f23 => {}
                    LoongArchInlineAsmReg::f24 => {}
                    LoongArchInlineAsmReg::f25 => {}
                    LoongArchInlineAsmReg::f26 => {}
                    LoongArchInlineAsmReg::f27 => {}
                    LoongArchInlineAsmReg::f28 => {}
                    LoongArchInlineAsmReg::f29 => {}
                    LoongArchInlineAsmReg::f30 => {}
                    LoongArchInlineAsmReg::f31 => {}
                }
            }
        }
    };
impl LoongArchInlineAsmReg {
    pub fn name(self) -> &'static str {
        match self {
            Self::r1 => "$r1",
            Self::r4 => "$r4",
            Self::r5 => "$r5",
            Self::r6 => "$r6",
            Self::r7 => "$r7",
            Self::r8 => "$r8",
            Self::r9 => "$r9",
            Self::r10 => "$r10",
            Self::r11 => "$r11",
            Self::r12 => "$r12",
            Self::r13 => "$r13",
            Self::r14 => "$r14",
            Self::r15 => "$r15",
            Self::r16 => "$r16",
            Self::r17 => "$r17",
            Self::r18 => "$r18",
            Self::r19 => "$r19",
            Self::r20 => "$r20",
            Self::r23 => "$r23",
            Self::r24 => "$r24",
            Self::r25 => "$r25",
            Self::r26 => "$r26",
            Self::r27 => "$r27",
            Self::r28 => "$r28",
            Self::r29 => "$r29",
            Self::r30 => "$r30",
            Self::f0 => "$f0",
            Self::f1 => "$f1",
            Self::f2 => "$f2",
            Self::f3 => "$f3",
            Self::f4 => "$f4",
            Self::f5 => "$f5",
            Self::f6 => "$f6",
            Self::f7 => "$f7",
            Self::f8 => "$f8",
            Self::f9 => "$f9",
            Self::f10 => "$f10",
            Self::f11 => "$f11",
            Self::f12 => "$f12",
            Self::f13 => "$f13",
            Self::f14 => "$f14",
            Self::f15 => "$f15",
            Self::f16 => "$f16",
            Self::f17 => "$f17",
            Self::f18 => "$f18",
            Self::f19 => "$f19",
            Self::f20 => "$f20",
            Self::f21 => "$f21",
            Self::f22 => "$f22",
            Self::f23 => "$f23",
            Self::f24 => "$f24",
            Self::f25 => "$f25",
            Self::f26 => "$f26",
            Self::f27 => "$f27",
            Self::f28 => "$f28",
            Self::f29 => "$f29",
            Self::f30 => "$f30",
            Self::f31 => "$f31",
        }
    }
    pub fn reg_class(self) -> LoongArchInlineAsmRegClass {
        match self {
            Self::r1 => LoongArchInlineAsmRegClass::reg,
            Self::r4 => LoongArchInlineAsmRegClass::reg,
            Self::r5 => LoongArchInlineAsmRegClass::reg,
            Self::r6 => LoongArchInlineAsmRegClass::reg,
            Self::r7 => LoongArchInlineAsmRegClass::reg,
            Self::r8 => LoongArchInlineAsmRegClass::reg,
            Self::r9 => LoongArchInlineAsmRegClass::reg,
            Self::r10 => LoongArchInlineAsmRegClass::reg,
            Self::r11 => LoongArchInlineAsmRegClass::reg,
            Self::r12 => LoongArchInlineAsmRegClass::reg,
            Self::r13 => LoongArchInlineAsmRegClass::reg,
            Self::r14 => LoongArchInlineAsmRegClass::reg,
            Self::r15 => LoongArchInlineAsmRegClass::reg,
            Self::r16 => LoongArchInlineAsmRegClass::reg,
            Self::r17 => LoongArchInlineAsmRegClass::reg,
            Self::r18 => LoongArchInlineAsmRegClass::reg,
            Self::r19 => LoongArchInlineAsmRegClass::reg,
            Self::r20 => LoongArchInlineAsmRegClass::reg,
            Self::r23 => LoongArchInlineAsmRegClass::reg,
            Self::r24 => LoongArchInlineAsmRegClass::reg,
            Self::r25 => LoongArchInlineAsmRegClass::reg,
            Self::r26 => LoongArchInlineAsmRegClass::reg,
            Self::r27 => LoongArchInlineAsmRegClass::reg,
            Self::r28 => LoongArchInlineAsmRegClass::reg,
            Self::r29 => LoongArchInlineAsmRegClass::reg,
            Self::r30 => LoongArchInlineAsmRegClass::reg,
            Self::f0 => LoongArchInlineAsmRegClass::freg,
            Self::f1 => LoongArchInlineAsmRegClass::freg,
            Self::f2 => LoongArchInlineAsmRegClass::freg,
            Self::f3 => LoongArchInlineAsmRegClass::freg,
            Self::f4 => LoongArchInlineAsmRegClass::freg,
            Self::f5 => LoongArchInlineAsmRegClass::freg,
            Self::f6 => LoongArchInlineAsmRegClass::freg,
            Self::f7 => LoongArchInlineAsmRegClass::freg,
            Self::f8 => LoongArchInlineAsmRegClass::freg,
            Self::f9 => LoongArchInlineAsmRegClass::freg,
            Self::f10 => LoongArchInlineAsmRegClass::freg,
            Self::f11 => LoongArchInlineAsmRegClass::freg,
            Self::f12 => LoongArchInlineAsmRegClass::freg,
            Self::f13 => LoongArchInlineAsmRegClass::freg,
            Self::f14 => LoongArchInlineAsmRegClass::freg,
            Self::f15 => LoongArchInlineAsmRegClass::freg,
            Self::f16 => LoongArchInlineAsmRegClass::freg,
            Self::f17 => LoongArchInlineAsmRegClass::freg,
            Self::f18 => LoongArchInlineAsmRegClass::freg,
            Self::f19 => LoongArchInlineAsmRegClass::freg,
            Self::f20 => LoongArchInlineAsmRegClass::freg,
            Self::f21 => LoongArchInlineAsmRegClass::freg,
            Self::f22 => LoongArchInlineAsmRegClass::freg,
            Self::f23 => LoongArchInlineAsmRegClass::freg,
            Self::f24 => LoongArchInlineAsmRegClass::freg,
            Self::f25 => LoongArchInlineAsmRegClass::freg,
            Self::f26 => LoongArchInlineAsmRegClass::freg,
            Self::f27 => LoongArchInlineAsmRegClass::freg,
            Self::f28 => LoongArchInlineAsmRegClass::freg,
            Self::f29 => LoongArchInlineAsmRegClass::freg,
            Self::f30 => LoongArchInlineAsmRegClass::freg,
            Self::f31 => LoongArchInlineAsmRegClass::freg,
        }
    }
    pub fn parse(name: &str) -> Result<Self, &'static str> {
        match name {
            "$ra" | "$r1" => Ok(Self::r1),
            "$a0" | "$r4" => Ok(Self::r4),
            "$a1" | "$r5" => Ok(Self::r5),
            "$a2" | "$r6" => Ok(Self::r6),
            "$a3" | "$r7" => Ok(Self::r7),
            "$a4" | "$r8" => Ok(Self::r8),
            "$a5" | "$r9" => Ok(Self::r9),
            "$a6" | "$r10" => Ok(Self::r10),
            "$a7" | "$r11" => Ok(Self::r11),
            "$t0" | "$r12" => Ok(Self::r12),
            "$t1" | "$r13" => Ok(Self::r13),
            "$t2" | "$r14" => Ok(Self::r14),
            "$t3" | "$r15" => Ok(Self::r15),
            "$t4" | "$r16" => Ok(Self::r16),
            "$t5" | "$r17" => Ok(Self::r17),
            "$t6" | "$r18" => Ok(Self::r18),
            "$t7" | "$r19" => Ok(Self::r19),
            "$t8" | "$r20" => Ok(Self::r20),
            "$s0" | "$r23" => Ok(Self::r23),
            "$s1" | "$r24" => Ok(Self::r24),
            "$s2" | "$r25" => Ok(Self::r25),
            "$s3" | "$r26" => Ok(Self::r26),
            "$s4" | "$r27" => Ok(Self::r27),
            "$s5" | "$r28" => Ok(Self::r28),
            "$s6" | "$r29" => Ok(Self::r29),
            "$s7" | "$r30" => Ok(Self::r30),
            "$fa0" | "$f0" => Ok(Self::f0),
            "$fa1" | "$f1" => Ok(Self::f1),
            "$fa2" | "$f2" => Ok(Self::f2),
            "$fa3" | "$f3" => Ok(Self::f3),
            "$fa4" | "$f4" => Ok(Self::f4),
            "$fa5" | "$f5" => Ok(Self::f5),
            "$fa6" | "$f6" => Ok(Self::f6),
            "$fa7" | "$f7" => Ok(Self::f7),
            "$ft0" | "$f8" => Ok(Self::f8),
            "$ft1" | "$f9" => Ok(Self::f9),
            "$ft2" | "$f10" => Ok(Self::f10),
            "$ft3" | "$f11" => Ok(Self::f11),
            "$ft4" | "$f12" => Ok(Self::f12),
            "$ft5" | "$f13" => Ok(Self::f13),
            "$ft6" | "$f14" => Ok(Self::f14),
            "$ft7" | "$f15" => Ok(Self::f15),
            "$ft8" | "$f16" => Ok(Self::f16),
            "$ft9" | "$f17" => Ok(Self::f17),
            "$ft10" | "$f18" => Ok(Self::f18),
            "$ft11" | "$f19" => Ok(Self::f19),
            "$ft12" | "$f20" => Ok(Self::f20),
            "$ft13" | "$f21" => Ok(Self::f21),
            "$ft14" | "$f22" => Ok(Self::f22),
            "$ft15" | "$f23" => Ok(Self::f23),
            "$fs0" | "$f24" => Ok(Self::f24),
            "$fs1" | "$f25" => Ok(Self::f25),
            "$fs2" | "$f26" => Ok(Self::f26),
            "$fs3" | "$f27" => Ok(Self::f27),
            "$fs4" | "$f28" => Ok(Self::f28),
            "$fs5" | "$f29" => Ok(Self::f29),
            "$fs6" | "$f30" => Ok(Self::f30),
            "$fs7" | "$f31" => Ok(Self::f31),
            "$r0" | "$zero" =>
                Err("constant zero cannot be used as an operand for inline asm"),
            "$r2" | "$tp" => Err("reserved for TLS"),
            "$r3" | "$sp" =>
                Err("the stack pointer cannot be used as an operand for inline asm"),
            "$r21" => Err("reserved by the ABI"),
            "$r22" | "$fp" =>
                Err("the frame pointer cannot be used as an operand for inline asm"),
            "$r31" | "$s8" =>
                Err("$r31 is used internally by LLVM and cannot be used as an operand for inline asm"),
            _ => Err("unknown register"),
        }
    }
    pub fn validate(self, _arch: super::InlineAsmArch,
        _reloc_model: crate::spec::RelocModel,
        _target_features: &rustc_data_structures::fx::FxIndexSet<Symbol>,
        _target: &crate::spec::Target, _is_clobber: bool)
        -> Result<(), &'static str> {
        match self {
            Self::r1 => { Ok(()) }
            Self::r4 => { Ok(()) }
            Self::r5 => { Ok(()) }
            Self::r6 => { Ok(()) }
            Self::r7 => { Ok(()) }
            Self::r8 => { Ok(()) }
            Self::r9 => { Ok(()) }
            Self::r10 => { Ok(()) }
            Self::r11 => { Ok(()) }
            Self::r12 => { Ok(()) }
            Self::r13 => { Ok(()) }
            Self::r14 => { Ok(()) }
            Self::r15 => { Ok(()) }
            Self::r16 => { Ok(()) }
            Self::r17 => { Ok(()) }
            Self::r18 => { Ok(()) }
            Self::r19 => { Ok(()) }
            Self::r20 => { Ok(()) }
            Self::r23 => { Ok(()) }
            Self::r24 => { Ok(()) }
            Self::r25 => { Ok(()) }
            Self::r26 => { Ok(()) }
            Self::r27 => { Ok(()) }
            Self::r28 => { Ok(()) }
            Self::r29 => { Ok(()) }
            Self::r30 => { Ok(()) }
            Self::f0 => { Ok(()) }
            Self::f1 => { Ok(()) }
            Self::f2 => { Ok(()) }
            Self::f3 => { Ok(()) }
            Self::f4 => { Ok(()) }
            Self::f5 => { Ok(()) }
            Self::f6 => { Ok(()) }
            Self::f7 => { Ok(()) }
            Self::f8 => { Ok(()) }
            Self::f9 => { Ok(()) }
            Self::f10 => { Ok(()) }
            Self::f11 => { Ok(()) }
            Self::f12 => { Ok(()) }
            Self::f13 => { Ok(()) }
            Self::f14 => { Ok(()) }
            Self::f15 => { Ok(()) }
            Self::f16 => { Ok(()) }
            Self::f17 => { Ok(()) }
            Self::f18 => { Ok(()) }
            Self::f19 => { Ok(()) }
            Self::f20 => { Ok(()) }
            Self::f21 => { Ok(()) }
            Self::f22 => { Ok(()) }
            Self::f23 => { Ok(()) }
            Self::f24 => { Ok(()) }
            Self::f25 => { Ok(()) }
            Self::f26 => { Ok(()) }
            Self::f27 => { Ok(()) }
            Self::f28 => { Ok(()) }
            Self::f29 => { Ok(()) }
            Self::f30 => { Ok(()) }
            Self::f31 => { Ok(()) }
        }
    }
}
pub(super) fn fill_reg_map(_arch: super::InlineAsmArch,
    _reloc_model: crate::spec::RelocModel,
    _target_features: &rustc_data_structures::fx::FxIndexSet<Symbol>,
    _target: &crate::spec::Target,
    _map:
        &mut rustc_data_structures::fx::FxHashMap<super::InlineAsmRegClass,
        rustc_data_structures::fx::FxIndexSet<super::InlineAsmReg>>) {
    #[allow(unused_imports)]
    use super::{InlineAsmReg, InlineAsmRegClass};
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::r1));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::r4));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::r5));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::r6));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::r7));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::r8));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::r9));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::r10));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::r11));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::r12));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::r13));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::r14));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::r15));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::r16));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::r17));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::r18));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::r19));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::r20));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::r23));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::r24));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::r25));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::r26));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::r27));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::r28));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::r29));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::r30));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::f0));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::f1));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::f2));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::f3));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::f4));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::f5));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::f6));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::f7));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::f8));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::f9));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::f10));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::f11));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::f12));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::f13));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::f14));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::f15));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::f16));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::f17));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::f18));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::f19));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::f20));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::f21));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::f22));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::f23));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::f24));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::f25));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::f26));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::f27));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::f28));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::f29));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::f30));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::LoongArch(LoongArchInlineAsmReg::f31));
        }
    }
}def_regs! {
52    LoongArch LoongArchInlineAsmReg LoongArchInlineAsmRegClass {
53        r1: reg = ["$r1","$ra"],
54        r4: reg = ["$r4","$a0"],
55        r5: reg = ["$r5","$a1"],
56        r6: reg = ["$r6","$a2"],
57        r7: reg = ["$r7","$a3"],
58        r8: reg = ["$r8","$a4"],
59        r9: reg = ["$r9","$a5"],
60        r10: reg = ["$r10","$a6"],
61        r11: reg = ["$r11","$a7"],
62        r12: reg = ["$r12","$t0"],
63        r13: reg = ["$r13","$t1"],
64        r14: reg = ["$r14","$t2"],
65        r15: reg = ["$r15","$t3"],
66        r16: reg = ["$r16","$t4"],
67        r17: reg = ["$r17","$t5"],
68        r18: reg = ["$r18","$t6"],
69        r19: reg = ["$r19","$t7"],
70        r20: reg = ["$r20","$t8"],
71        r23: reg = ["$r23","$s0"],
72        r24: reg = ["$r24","$s1"],
73        r25: reg = ["$r25","$s2"],
74        r26: reg = ["$r26","$s3"],
75        r27: reg = ["$r27","$s4"],
76        r28: reg = ["$r28","$s5"],
77        r29: reg = ["$r29","$s6"],
78        r30: reg = ["$r30","$s7"],
79        f0: freg = ["$f0","$fa0"],
80        f1: freg = ["$f1","$fa1"],
81        f2: freg = ["$f2","$fa2"],
82        f3: freg = ["$f3","$fa3"],
83        f4: freg = ["$f4","$fa4"],
84        f5: freg = ["$f5","$fa5"],
85        f6: freg = ["$f6","$fa6"],
86        f7: freg = ["$f7","$fa7"],
87        f8: freg = ["$f8","$ft0"],
88        f9: freg = ["$f9","$ft1"],
89        f10: freg = ["$f10","$ft2"],
90        f11: freg = ["$f11","$ft3"],
91        f12: freg = ["$f12","$ft4"],
92        f13: freg = ["$f13","$ft5"],
93        f14: freg = ["$f14","$ft6"],
94        f15: freg = ["$f15","$ft7"],
95        f16: freg = ["$f16","$ft8"],
96        f17: freg = ["$f17","$ft9"],
97        f18: freg = ["$f18","$ft10"],
98        f19: freg = ["$f19","$ft11"],
99        f20: freg = ["$f20","$ft12"],
100        f21: freg = ["$f21","$ft13"],
101        f22: freg = ["$f22","$ft14"],
102        f23: freg = ["$f23","$ft15"],
103        f24: freg = ["$f24","$fs0"],
104        f25: freg = ["$f25","$fs1"],
105        f26: freg = ["$f26","$fs2"],
106        f27: freg = ["$f27","$fs3"],
107        f28: freg = ["$f28","$fs4"],
108        f29: freg = ["$f29","$fs5"],
109        f30: freg = ["$f30","$fs6"],
110        f31: freg = ["$f31","$fs7"],
111        #error = ["$r0","$zero"] =>
112            "constant zero cannot be used as an operand for inline asm",
113        #error = ["$r2","$tp"] =>
114            "reserved for TLS",
115        #error = ["$r3","$sp"] =>
116            "the stack pointer cannot be used as an operand for inline asm",
117        #error = ["$r21"] =>
118            "reserved by the ABI",
119        #error = ["$r22","$fp"] =>
120            "the frame pointer cannot be used as an operand for inline asm",
121        #error = ["$r31","$s8"] =>
122            "$r31 is used internally by LLVM and cannot be used as an operand for inline asm",
123    }
124}
125
126impl LoongArchInlineAsmReg {
127    pub fn emit(
128        self,
129        out: &mut dyn fmt::Write,
130        _arch: InlineAsmArch,
131        _modifier: Option<char>,
132    ) -> fmt::Result {
133        out.write_str(self.name())
134    }
135}