rustc_target/spec/targets/
armv8r_none_eabihf.rs

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1// Targets the Little-endian Cortex-R52 processor (ARMv8-R)
2
3use crate::spec::{
4    Cc, FloatAbi, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetOptions,
5};
6
7pub(crate) fn target() -> Target {
8    Target {
9        llvm_target: "armv8r-none-eabihf".into(),
10        metadata: crate::spec::TargetMetadata {
11            description: Some("Bare Armv8-R, hardfloat".into()),
12            tier: Some(3),
13            host_tools: Some(false),
14            std: Some(false),
15        },
16        pointer_width: 32,
17        data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
18        arch: "arm".into(),
19
20        options: TargetOptions {
21            abi: "eabihf".into(),
22            llvm_floatabi: Some(FloatAbi::Hard),
23            linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
24            linker: Some("rust-lld".into()),
25            relocation_model: RelocModel::Static,
26            panic_strategy: PanicStrategy::Abort,
27            // Armv8-R requires a minimum set of floating-point features equivalent to:
28            // fp-armv8, SP-only, with 16 DP (32 SP) registers
29            // LLVM defines Armv8-R to include these features automatically.
30            //
31            // The Cortex-R52 supports these default features and optionally includes:
32            // neon-fp-armv8, SP+DP, with 32 DP registers
33            //
34            // Reference:
35            // Arm Cortex-R52 Processor Technical Reference Manual
36            // - Chapter 15 Advanced SIMD and floating-point support
37            max_atomic_width: Some(64),
38            emit_debug_gdb_scripts: false,
39            // GCC defaults to 8 for arm-none here.
40            c_enum_min_bits: Some(8),
41            ..Default::default()
42        },
43    }
44}
rustc_target/spec/targets/armv8r_none_eabihf.rs

rustc_target/spec/targets/
armv8r_none_eabihf.rs
