rustc_target/asm/
csky.rs

1use std::fmt;
2
3use rustc_span::Symbol;
4
5use super::{InlineAsmArch, InlineAsmType, ModifierInfo};
6
7#[allow(non_camel_case_types)]
pub enum CSKYInlineAsmRegClass { reg, freg, }
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::marker::Copy for CSKYInlineAsmRegClass { }
#[automatically_derived]
#[doc(hidden)]
#[allow(non_camel_case_types)]
unsafe impl ::core::clone::TrivialClone for CSKYInlineAsmRegClass { }
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::clone::Clone for CSKYInlineAsmRegClass {
    #[inline]
    fn clone(&self) -> CSKYInlineAsmRegClass { *self }
}
const _: () =
    {
        impl<__E: ::rustc_span::SpanEncoder> ::rustc_serialize::Encodable<__E>
            for CSKYInlineAsmRegClass {
            fn encode(&self, __encoder: &mut __E) {
                let disc =
                    match *self {
                        CSKYInlineAsmRegClass::reg => { 0usize }
                        CSKYInlineAsmRegClass::freg => { 1usize }
                    };
                ::rustc_serialize::Encoder::emit_u8(__encoder, disc as u8);
                match *self {
                    CSKYInlineAsmRegClass::reg => {}
                    CSKYInlineAsmRegClass::freg => {}
                }
            }
        }
    };
const _: () =
    {
        impl<__D: ::rustc_span::SpanDecoder> ::rustc_serialize::Decodable<__D>
            for CSKYInlineAsmRegClass {
            fn decode(__decoder: &mut __D) -> Self {
                match ::rustc_serialize::Decoder::read_u8(__decoder) as usize
                    {
                    0usize => { CSKYInlineAsmRegClass::reg }
                    1usize => { CSKYInlineAsmRegClass::freg }
                    n => {
                        ::core::panicking::panic_fmt(format_args!("invalid enum variant tag while decoding `CSKYInlineAsmRegClass`, expected 0..2, actual {0}",
                                n));
                    }
                }
            }
        }
    };
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::fmt::Debug for CSKYInlineAsmRegClass {
    #[inline]
    fn fmt(&self, f: &mut ::core::fmt::Formatter) -> ::core::fmt::Result {
        ::core::fmt::Formatter::write_str(f,
            match self {
                CSKYInlineAsmRegClass::reg => "reg",
                CSKYInlineAsmRegClass::freg => "freg",
            })
    }
}
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::cmp::Eq for CSKYInlineAsmRegClass {
    #[inline]
    #[doc(hidden)]
    #[coverage(off)]
    fn assert_receiver_is_total_eq(&self) -> () {}
}
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::marker::StructuralPartialEq for CSKYInlineAsmRegClass { }
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::cmp::PartialEq for CSKYInlineAsmRegClass {
    #[inline]
    fn eq(&self, other: &CSKYInlineAsmRegClass) -> bool {
        let __self_discr = ::core::intrinsics::discriminant_value(self);
        let __arg1_discr = ::core::intrinsics::discriminant_value(other);
        __self_discr == __arg1_discr
    }
}
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::cmp::PartialOrd for CSKYInlineAsmRegClass {
    #[inline]
    fn partial_cmp(&self, other: &CSKYInlineAsmRegClass)
        -> ::core::option::Option<::core::cmp::Ordering> {
        let __self_discr = ::core::intrinsics::discriminant_value(self);
        let __arg1_discr = ::core::intrinsics::discriminant_value(other);
        ::core::cmp::PartialOrd::partial_cmp(&__self_discr, &__arg1_discr)
    }
}
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::hash::Hash for CSKYInlineAsmRegClass {
    #[inline]
    fn hash<__H: ::core::hash::Hasher>(&self, state: &mut __H) -> () {
        let __self_discr = ::core::intrinsics::discriminant_value(self);
        ::core::hash::Hash::hash(&__self_discr, state)
    }
}
const _: () =
    {
        impl<__CTX> ::rustc_data_structures::stable_hasher::HashStable<__CTX>
            for CSKYInlineAsmRegClass where __CTX: crate::HashStableContext {
            #[inline]
            fn hash_stable(&self, __hcx: &mut __CTX,
                __hasher:
                    &mut ::rustc_data_structures::stable_hasher::StableHasher) {
                ::std::mem::discriminant(self).hash_stable(__hcx, __hasher);
                match *self {
                    CSKYInlineAsmRegClass::reg => {}
                    CSKYInlineAsmRegClass::freg => {}
                }
            }
        }
    };
impl CSKYInlineAsmRegClass {
    pub fn name(self) -> rustc_span::Symbol {
        match self {
            Self::reg => rustc_span::sym::reg,
            Self::freg => rustc_span::sym::freg,
        }
    }
    pub fn parse(name: rustc_span::Symbol)
        -> Result<Self, &'static [rustc_span::Symbol]> {
        match name {
            rustc_span::sym::reg => Ok(Self::reg),
            rustc_span::sym::freg => Ok(Self::freg),
            _ => Err(&[rustc_span::sym::reg, rustc_span::sym::freg]),
        }
    }
}
pub(super) fn regclass_map()
    ->
        rustc_data_structures::fx::FxHashMap<super::InlineAsmRegClass,
        rustc_data_structures::fx::FxIndexSet<super::InlineAsmReg>> {
    use rustc_data_structures::fx::FxHashMap;
    use rustc_data_structures::fx::FxIndexSet;
    use super::InlineAsmRegClass;
    let mut map = FxHashMap::default();
    map.insert(InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::reg),
        FxIndexSet::default());
    map.insert(InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg),
        FxIndexSet::default());
    map
}def_reg_class! {
8    CSKY CSKYInlineAsmRegClass {
9        reg,
10        freg,
11    }
12}
13
14impl CSKYInlineAsmRegClass {
15    pub fn valid_modifiers(self, _arch: super::InlineAsmArch) -> &'static [char] {
16        &[]
17    }
18
19    pub fn suggest_class(self, _arch: InlineAsmArch, _ty: InlineAsmType) -> Option<Self> {
20        None
21    }
22
23    pub fn suggest_modifier(
24        self,
25        _arch: InlineAsmArch,
26        _ty: InlineAsmType,
27    ) -> Option<ModifierInfo> {
28        None
29    }
30
31    pub fn default_modifier(self, _arch: InlineAsmArch) -> Option<ModifierInfo> {
32        None
33    }
34
35    pub fn supported_types(
36        self,
37        _arch: InlineAsmArch,
38    ) -> &'static [(InlineAsmType, Option<Symbol>)] {
39        match self {
40            Self::reg => {
    use super::InlineAsmType::*;
    &[(I8, None), (I16, None), (I32, None)]
}types! { _: I8, I16, I32; },
41            Self::freg => {
    use super::InlineAsmType::*;
    &[(F32, None)]
}types! { _: F32; },
42        }
43    }
44}
45
46// The reserved registers are taken from <https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/CSKY/CSKYRegisterInfo.cpp#79>
47#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
pub enum CSKYInlineAsmReg {
    r0,
    r1,
    r2,
    r3,
    r4,
    r5,
    r6,
    r9,
    r10,
    r11,
    r12,
    r13,
    r16,
    r17,
    r18,
    r19,
    r20,
    r21,
    r22,
    r23,
    r24,
    r25,
    f0,
    f1,
    f2,
    f3,
    f4,
    f5,
    f6,
    f7,
    f8,
    f9,
    f10,
    f11,
    f12,
    f13,
    f14,
    f15,
    f16,
    f17,
    f18,
    f19,
    f20,
    f21,
    f22,
    f23,
    f24,
    f25,
    f26,
    f27,
    f28,
    f29,
    f30,
    f31,
}
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::marker::Copy for CSKYInlineAsmReg { }
#[automatically_derived]
#[doc(hidden)]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
unsafe impl ::core::clone::TrivialClone for CSKYInlineAsmReg { }
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::clone::Clone for CSKYInlineAsmReg {
    #[inline]
    fn clone(&self) -> CSKYInlineAsmReg { *self }
}
const _: () =
    {
        impl<__E: ::rustc_span::SpanEncoder> ::rustc_serialize::Encodable<__E>
            for CSKYInlineAsmReg {
            fn encode(&self, __encoder: &mut __E) {
                let disc =
                    match *self {
                        CSKYInlineAsmReg::r0 => { 0usize }
                        CSKYInlineAsmReg::r1 => { 1usize }
                        CSKYInlineAsmReg::r2 => { 2usize }
                        CSKYInlineAsmReg::r3 => { 3usize }
                        CSKYInlineAsmReg::r4 => { 4usize }
                        CSKYInlineAsmReg::r5 => { 5usize }
                        CSKYInlineAsmReg::r6 => { 6usize }
                        CSKYInlineAsmReg::r9 => { 7usize }
                        CSKYInlineAsmReg::r10 => { 8usize }
                        CSKYInlineAsmReg::r11 => { 9usize }
                        CSKYInlineAsmReg::r12 => { 10usize }
                        CSKYInlineAsmReg::r13 => { 11usize }
                        CSKYInlineAsmReg::r16 => { 12usize }
                        CSKYInlineAsmReg::r17 => { 13usize }
                        CSKYInlineAsmReg::r18 => { 14usize }
                        CSKYInlineAsmReg::r19 => { 15usize }
                        CSKYInlineAsmReg::r20 => { 16usize }
                        CSKYInlineAsmReg::r21 => { 17usize }
                        CSKYInlineAsmReg::r22 => { 18usize }
                        CSKYInlineAsmReg::r23 => { 19usize }
                        CSKYInlineAsmReg::r24 => { 20usize }
                        CSKYInlineAsmReg::r25 => { 21usize }
                        CSKYInlineAsmReg::f0 => { 22usize }
                        CSKYInlineAsmReg::f1 => { 23usize }
                        CSKYInlineAsmReg::f2 => { 24usize }
                        CSKYInlineAsmReg::f3 => { 25usize }
                        CSKYInlineAsmReg::f4 => { 26usize }
                        CSKYInlineAsmReg::f5 => { 27usize }
                        CSKYInlineAsmReg::f6 => { 28usize }
                        CSKYInlineAsmReg::f7 => { 29usize }
                        CSKYInlineAsmReg::f8 => { 30usize }
                        CSKYInlineAsmReg::f9 => { 31usize }
                        CSKYInlineAsmReg::f10 => { 32usize }
                        CSKYInlineAsmReg::f11 => { 33usize }
                        CSKYInlineAsmReg::f12 => { 34usize }
                        CSKYInlineAsmReg::f13 => { 35usize }
                        CSKYInlineAsmReg::f14 => { 36usize }
                        CSKYInlineAsmReg::f15 => { 37usize }
                        CSKYInlineAsmReg::f16 => { 38usize }
                        CSKYInlineAsmReg::f17 => { 39usize }
                        CSKYInlineAsmReg::f18 => { 40usize }
                        CSKYInlineAsmReg::f19 => { 41usize }
                        CSKYInlineAsmReg::f20 => { 42usize }
                        CSKYInlineAsmReg::f21 => { 43usize }
                        CSKYInlineAsmReg::f22 => { 44usize }
                        CSKYInlineAsmReg::f23 => { 45usize }
                        CSKYInlineAsmReg::f24 => { 46usize }
                        CSKYInlineAsmReg::f25 => { 47usize }
                        CSKYInlineAsmReg::f26 => { 48usize }
                        CSKYInlineAsmReg::f27 => { 49usize }
                        CSKYInlineAsmReg::f28 => { 50usize }
                        CSKYInlineAsmReg::f29 => { 51usize }
                        CSKYInlineAsmReg::f30 => { 52usize }
                        CSKYInlineAsmReg::f31 => { 53usize }
                    };
                ::rustc_serialize::Encoder::emit_u8(__encoder, disc as u8);
                match *self {
                    CSKYInlineAsmReg::r0 => {}
                    CSKYInlineAsmReg::r1 => {}
                    CSKYInlineAsmReg::r2 => {}
                    CSKYInlineAsmReg::r3 => {}
                    CSKYInlineAsmReg::r4 => {}
                    CSKYInlineAsmReg::r5 => {}
                    CSKYInlineAsmReg::r6 => {}
                    CSKYInlineAsmReg::r9 => {}
                    CSKYInlineAsmReg::r10 => {}
                    CSKYInlineAsmReg::r11 => {}
                    CSKYInlineAsmReg::r12 => {}
                    CSKYInlineAsmReg::r13 => {}
                    CSKYInlineAsmReg::r16 => {}
                    CSKYInlineAsmReg::r17 => {}
                    CSKYInlineAsmReg::r18 => {}
                    CSKYInlineAsmReg::r19 => {}
                    CSKYInlineAsmReg::r20 => {}
                    CSKYInlineAsmReg::r21 => {}
                    CSKYInlineAsmReg::r22 => {}
                    CSKYInlineAsmReg::r23 => {}
                    CSKYInlineAsmReg::r24 => {}
                    CSKYInlineAsmReg::r25 => {}
                    CSKYInlineAsmReg::f0 => {}
                    CSKYInlineAsmReg::f1 => {}
                    CSKYInlineAsmReg::f2 => {}
                    CSKYInlineAsmReg::f3 => {}
                    CSKYInlineAsmReg::f4 => {}
                    CSKYInlineAsmReg::f5 => {}
                    CSKYInlineAsmReg::f6 => {}
                    CSKYInlineAsmReg::f7 => {}
                    CSKYInlineAsmReg::f8 => {}
                    CSKYInlineAsmReg::f9 => {}
                    CSKYInlineAsmReg::f10 => {}
                    CSKYInlineAsmReg::f11 => {}
                    CSKYInlineAsmReg::f12 => {}
                    CSKYInlineAsmReg::f13 => {}
                    CSKYInlineAsmReg::f14 => {}
                    CSKYInlineAsmReg::f15 => {}
                    CSKYInlineAsmReg::f16 => {}
                    CSKYInlineAsmReg::f17 => {}
                    CSKYInlineAsmReg::f18 => {}
                    CSKYInlineAsmReg::f19 => {}
                    CSKYInlineAsmReg::f20 => {}
                    CSKYInlineAsmReg::f21 => {}
                    CSKYInlineAsmReg::f22 => {}
                    CSKYInlineAsmReg::f23 => {}
                    CSKYInlineAsmReg::f24 => {}
                    CSKYInlineAsmReg::f25 => {}
                    CSKYInlineAsmReg::f26 => {}
                    CSKYInlineAsmReg::f27 => {}
                    CSKYInlineAsmReg::f28 => {}
                    CSKYInlineAsmReg::f29 => {}
                    CSKYInlineAsmReg::f30 => {}
                    CSKYInlineAsmReg::f31 => {}
                }
            }
        }
    };
const _: () =
    {
        impl<__D: ::rustc_span::SpanDecoder> ::rustc_serialize::Decodable<__D>
            for CSKYInlineAsmReg {
            fn decode(__decoder: &mut __D) -> Self {
                match ::rustc_serialize::Decoder::read_u8(__decoder) as usize
                    {
                    0usize => { CSKYInlineAsmReg::r0 }
                    1usize => { CSKYInlineAsmReg::r1 }
                    2usize => { CSKYInlineAsmReg::r2 }
                    3usize => { CSKYInlineAsmReg::r3 }
                    4usize => { CSKYInlineAsmReg::r4 }
                    5usize => { CSKYInlineAsmReg::r5 }
                    6usize => { CSKYInlineAsmReg::r6 }
                    7usize => { CSKYInlineAsmReg::r9 }
                    8usize => { CSKYInlineAsmReg::r10 }
                    9usize => { CSKYInlineAsmReg::r11 }
                    10usize => { CSKYInlineAsmReg::r12 }
                    11usize => { CSKYInlineAsmReg::r13 }
                    12usize => { CSKYInlineAsmReg::r16 }
                    13usize => { CSKYInlineAsmReg::r17 }
                    14usize => { CSKYInlineAsmReg::r18 }
                    15usize => { CSKYInlineAsmReg::r19 }
                    16usize => { CSKYInlineAsmReg::r20 }
                    17usize => { CSKYInlineAsmReg::r21 }
                    18usize => { CSKYInlineAsmReg::r22 }
                    19usize => { CSKYInlineAsmReg::r23 }
                    20usize => { CSKYInlineAsmReg::r24 }
                    21usize => { CSKYInlineAsmReg::r25 }
                    22usize => { CSKYInlineAsmReg::f0 }
                    23usize => { CSKYInlineAsmReg::f1 }
                    24usize => { CSKYInlineAsmReg::f2 }
                    25usize => { CSKYInlineAsmReg::f3 }
                    26usize => { CSKYInlineAsmReg::f4 }
                    27usize => { CSKYInlineAsmReg::f5 }
                    28usize => { CSKYInlineAsmReg::f6 }
                    29usize => { CSKYInlineAsmReg::f7 }
                    30usize => { CSKYInlineAsmReg::f8 }
                    31usize => { CSKYInlineAsmReg::f9 }
                    32usize => { CSKYInlineAsmReg::f10 }
                    33usize => { CSKYInlineAsmReg::f11 }
                    34usize => { CSKYInlineAsmReg::f12 }
                    35usize => { CSKYInlineAsmReg::f13 }
                    36usize => { CSKYInlineAsmReg::f14 }
                    37usize => { CSKYInlineAsmReg::f15 }
                    38usize => { CSKYInlineAsmReg::f16 }
                    39usize => { CSKYInlineAsmReg::f17 }
                    40usize => { CSKYInlineAsmReg::f18 }
                    41usize => { CSKYInlineAsmReg::f19 }
                    42usize => { CSKYInlineAsmReg::f20 }
                    43usize => { CSKYInlineAsmReg::f21 }
                    44usize => { CSKYInlineAsmReg::f22 }
                    45usize => { CSKYInlineAsmReg::f23 }
                    46usize => { CSKYInlineAsmReg::f24 }
                    47usize => { CSKYInlineAsmReg::f25 }
                    48usize => { CSKYInlineAsmReg::f26 }
                    49usize => { CSKYInlineAsmReg::f27 }
                    50usize => { CSKYInlineAsmReg::f28 }
                    51usize => { CSKYInlineAsmReg::f29 }
                    52usize => { CSKYInlineAsmReg::f30 }
                    53usize => { CSKYInlineAsmReg::f31 }
                    n => {
                        ::core::panicking::panic_fmt(format_args!("invalid enum variant tag while decoding `CSKYInlineAsmReg`, expected 0..54, actual {0}",
                                n));
                    }
                }
            }
        }
    };
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::fmt::Debug for CSKYInlineAsmReg {
    #[inline]
    fn fmt(&self, f: &mut ::core::fmt::Formatter) -> ::core::fmt::Result {
        ::core::fmt::Formatter::write_str(f,
            match self {
                CSKYInlineAsmReg::r0 => "r0",
                CSKYInlineAsmReg::r1 => "r1",
                CSKYInlineAsmReg::r2 => "r2",
                CSKYInlineAsmReg::r3 => "r3",
                CSKYInlineAsmReg::r4 => "r4",
                CSKYInlineAsmReg::r5 => "r5",
                CSKYInlineAsmReg::r6 => "r6",
                CSKYInlineAsmReg::r9 => "r9",
                CSKYInlineAsmReg::r10 => "r10",
                CSKYInlineAsmReg::r11 => "r11",
                CSKYInlineAsmReg::r12 => "r12",
                CSKYInlineAsmReg::r13 => "r13",
                CSKYInlineAsmReg::r16 => "r16",
                CSKYInlineAsmReg::r17 => "r17",
                CSKYInlineAsmReg::r18 => "r18",
                CSKYInlineAsmReg::r19 => "r19",
                CSKYInlineAsmReg::r20 => "r20",
                CSKYInlineAsmReg::r21 => "r21",
                CSKYInlineAsmReg::r22 => "r22",
                CSKYInlineAsmReg::r23 => "r23",
                CSKYInlineAsmReg::r24 => "r24",
                CSKYInlineAsmReg::r25 => "r25",
                CSKYInlineAsmReg::f0 => "f0",
                CSKYInlineAsmReg::f1 => "f1",
                CSKYInlineAsmReg::f2 => "f2",
                CSKYInlineAsmReg::f3 => "f3",
                CSKYInlineAsmReg::f4 => "f4",
                CSKYInlineAsmReg::f5 => "f5",
                CSKYInlineAsmReg::f6 => "f6",
                CSKYInlineAsmReg::f7 => "f7",
                CSKYInlineAsmReg::f8 => "f8",
                CSKYInlineAsmReg::f9 => "f9",
                CSKYInlineAsmReg::f10 => "f10",
                CSKYInlineAsmReg::f11 => "f11",
                CSKYInlineAsmReg::f12 => "f12",
                CSKYInlineAsmReg::f13 => "f13",
                CSKYInlineAsmReg::f14 => "f14",
                CSKYInlineAsmReg::f15 => "f15",
                CSKYInlineAsmReg::f16 => "f16",
                CSKYInlineAsmReg::f17 => "f17",
                CSKYInlineAsmReg::f18 => "f18",
                CSKYInlineAsmReg::f19 => "f19",
                CSKYInlineAsmReg::f20 => "f20",
                CSKYInlineAsmReg::f21 => "f21",
                CSKYInlineAsmReg::f22 => "f22",
                CSKYInlineAsmReg::f23 => "f23",
                CSKYInlineAsmReg::f24 => "f24",
                CSKYInlineAsmReg::f25 => "f25",
                CSKYInlineAsmReg::f26 => "f26",
                CSKYInlineAsmReg::f27 => "f27",
                CSKYInlineAsmReg::f28 => "f28",
                CSKYInlineAsmReg::f29 => "f29",
                CSKYInlineAsmReg::f30 => "f30",
                CSKYInlineAsmReg::f31 => "f31",
            })
    }
}
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::cmp::Eq for CSKYInlineAsmReg {
    #[inline]
    #[doc(hidden)]
    #[coverage(off)]
    fn assert_receiver_is_total_eq(&self) -> () {}
}
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::marker::StructuralPartialEq for CSKYInlineAsmReg { }
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::cmp::PartialEq for CSKYInlineAsmReg {
    #[inline]
    fn eq(&self, other: &CSKYInlineAsmReg) -> bool {
        let __self_discr = ::core::intrinsics::discriminant_value(self);
        let __arg1_discr = ::core::intrinsics::discriminant_value(other);
        __self_discr == __arg1_discr
    }
}
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::cmp::PartialOrd for CSKYInlineAsmReg {
    #[inline]
    fn partial_cmp(&self, other: &CSKYInlineAsmReg)
        -> ::core::option::Option<::core::cmp::Ordering> {
        let __self_discr = ::core::intrinsics::discriminant_value(self);
        let __arg1_discr = ::core::intrinsics::discriminant_value(other);
        ::core::cmp::PartialOrd::partial_cmp(&__self_discr, &__arg1_discr)
    }
}
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::hash::Hash for CSKYInlineAsmReg {
    #[inline]
    fn hash<__H: ::core::hash::Hasher>(&self, state: &mut __H) -> () {
        let __self_discr = ::core::intrinsics::discriminant_value(self);
        ::core::hash::Hash::hash(&__self_discr, state)
    }
}
const _: () =
    {
        impl<__CTX> ::rustc_data_structures::stable_hasher::HashStable<__CTX>
            for CSKYInlineAsmReg where __CTX: crate::HashStableContext {
            #[inline]
            fn hash_stable(&self, __hcx: &mut __CTX,
                __hasher:
                    &mut ::rustc_data_structures::stable_hasher::StableHasher) {
                ::std::mem::discriminant(self).hash_stable(__hcx, __hasher);
                match *self {
                    CSKYInlineAsmReg::r0 => {}
                    CSKYInlineAsmReg::r1 => {}
                    CSKYInlineAsmReg::r2 => {}
                    CSKYInlineAsmReg::r3 => {}
                    CSKYInlineAsmReg::r4 => {}
                    CSKYInlineAsmReg::r5 => {}
                    CSKYInlineAsmReg::r6 => {}
                    CSKYInlineAsmReg::r9 => {}
                    CSKYInlineAsmReg::r10 => {}
                    CSKYInlineAsmReg::r11 => {}
                    CSKYInlineAsmReg::r12 => {}
                    CSKYInlineAsmReg::r13 => {}
                    CSKYInlineAsmReg::r16 => {}
                    CSKYInlineAsmReg::r17 => {}
                    CSKYInlineAsmReg::r18 => {}
                    CSKYInlineAsmReg::r19 => {}
                    CSKYInlineAsmReg::r20 => {}
                    CSKYInlineAsmReg::r21 => {}
                    CSKYInlineAsmReg::r22 => {}
                    CSKYInlineAsmReg::r23 => {}
                    CSKYInlineAsmReg::r24 => {}
                    CSKYInlineAsmReg::r25 => {}
                    CSKYInlineAsmReg::f0 => {}
                    CSKYInlineAsmReg::f1 => {}
                    CSKYInlineAsmReg::f2 => {}
                    CSKYInlineAsmReg::f3 => {}
                    CSKYInlineAsmReg::f4 => {}
                    CSKYInlineAsmReg::f5 => {}
                    CSKYInlineAsmReg::f6 => {}
                    CSKYInlineAsmReg::f7 => {}
                    CSKYInlineAsmReg::f8 => {}
                    CSKYInlineAsmReg::f9 => {}
                    CSKYInlineAsmReg::f10 => {}
                    CSKYInlineAsmReg::f11 => {}
                    CSKYInlineAsmReg::f12 => {}
                    CSKYInlineAsmReg::f13 => {}
                    CSKYInlineAsmReg::f14 => {}
                    CSKYInlineAsmReg::f15 => {}
                    CSKYInlineAsmReg::f16 => {}
                    CSKYInlineAsmReg::f17 => {}
                    CSKYInlineAsmReg::f18 => {}
                    CSKYInlineAsmReg::f19 => {}
                    CSKYInlineAsmReg::f20 => {}
                    CSKYInlineAsmReg::f21 => {}
                    CSKYInlineAsmReg::f22 => {}
                    CSKYInlineAsmReg::f23 => {}
                    CSKYInlineAsmReg::f24 => {}
                    CSKYInlineAsmReg::f25 => {}
                    CSKYInlineAsmReg::f26 => {}
                    CSKYInlineAsmReg::f27 => {}
                    CSKYInlineAsmReg::f28 => {}
                    CSKYInlineAsmReg::f29 => {}
                    CSKYInlineAsmReg::f30 => {}
                    CSKYInlineAsmReg::f31 => {}
                }
            }
        }
    };
impl CSKYInlineAsmReg {
    pub fn name(self) -> &'static str {
        match self {
            Self::r0 => "r0",
            Self::r1 => "r1",
            Self::r2 => "r2",
            Self::r3 => "r3",
            Self::r4 => "r4",
            Self::r5 => "r5",
            Self::r6 => "r6",
            Self::r9 => "r9",
            Self::r10 => "r10",
            Self::r11 => "r11",
            Self::r12 => "r12",
            Self::r13 => "r13",
            Self::r16 => "r16",
            Self::r17 => "r17",
            Self::r18 => "r18",
            Self::r19 => "r19",
            Self::r20 => "r20",
            Self::r21 => "r21",
            Self::r22 => "r22",
            Self::r23 => "r23",
            Self::r24 => "r24",
            Self::r25 => "r25",
            Self::f0 => "fr0",
            Self::f1 => "fr1",
            Self::f2 => "fr2",
            Self::f3 => "fr3",
            Self::f4 => "fr4",
            Self::f5 => "fr5",
            Self::f6 => "fr6",
            Self::f7 => "fr7",
            Self::f8 => "fr8",
            Self::f9 => "fr9",
            Self::f10 => "fr10",
            Self::f11 => "fr11",
            Self::f12 => "fr12",
            Self::f13 => "fr13",
            Self::f14 => "fr14",
            Self::f15 => "fr15",
            Self::f16 => "fr16",
            Self::f17 => "fr17",
            Self::f18 => "fr18",
            Self::f19 => "fr19",
            Self::f20 => "fr20",
            Self::f21 => "fr21",
            Self::f22 => "fr22",
            Self::f23 => "fr23",
            Self::f24 => "fr24",
            Self::f25 => "fr25",
            Self::f26 => "fr26",
            Self::f27 => "fr27",
            Self::f28 => "fr28",
            Self::f29 => "fr29",
            Self::f30 => "fr30",
            Self::f31 => "fr31",
        }
    }
    pub fn reg_class(self) -> CSKYInlineAsmRegClass {
        match self {
            Self::r0 => CSKYInlineAsmRegClass::reg,
            Self::r1 => CSKYInlineAsmRegClass::reg,
            Self::r2 => CSKYInlineAsmRegClass::reg,
            Self::r3 => CSKYInlineAsmRegClass::reg,
            Self::r4 => CSKYInlineAsmRegClass::reg,
            Self::r5 => CSKYInlineAsmRegClass::reg,
            Self::r6 => CSKYInlineAsmRegClass::reg,
            Self::r9 => CSKYInlineAsmRegClass::reg,
            Self::r10 => CSKYInlineAsmRegClass::reg,
            Self::r11 => CSKYInlineAsmRegClass::reg,
            Self::r12 => CSKYInlineAsmRegClass::reg,
            Self::r13 => CSKYInlineAsmRegClass::reg,
            Self::r16 => CSKYInlineAsmRegClass::reg,
            Self::r17 => CSKYInlineAsmRegClass::reg,
            Self::r18 => CSKYInlineAsmRegClass::reg,
            Self::r19 => CSKYInlineAsmRegClass::reg,
            Self::r20 => CSKYInlineAsmRegClass::reg,
            Self::r21 => CSKYInlineAsmRegClass::reg,
            Self::r22 => CSKYInlineAsmRegClass::reg,
            Self::r23 => CSKYInlineAsmRegClass::reg,
            Self::r24 => CSKYInlineAsmRegClass::reg,
            Self::r25 => CSKYInlineAsmRegClass::reg,
            Self::f0 => CSKYInlineAsmRegClass::freg,
            Self::f1 => CSKYInlineAsmRegClass::freg,
            Self::f2 => CSKYInlineAsmRegClass::freg,
            Self::f3 => CSKYInlineAsmRegClass::freg,
            Self::f4 => CSKYInlineAsmRegClass::freg,
            Self::f5 => CSKYInlineAsmRegClass::freg,
            Self::f6 => CSKYInlineAsmRegClass::freg,
            Self::f7 => CSKYInlineAsmRegClass::freg,
            Self::f8 => CSKYInlineAsmRegClass::freg,
            Self::f9 => CSKYInlineAsmRegClass::freg,
            Self::f10 => CSKYInlineAsmRegClass::freg,
            Self::f11 => CSKYInlineAsmRegClass::freg,
            Self::f12 => CSKYInlineAsmRegClass::freg,
            Self::f13 => CSKYInlineAsmRegClass::freg,
            Self::f14 => CSKYInlineAsmRegClass::freg,
            Self::f15 => CSKYInlineAsmRegClass::freg,
            Self::f16 => CSKYInlineAsmRegClass::freg,
            Self::f17 => CSKYInlineAsmRegClass::freg,
            Self::f18 => CSKYInlineAsmRegClass::freg,
            Self::f19 => CSKYInlineAsmRegClass::freg,
            Self::f20 => CSKYInlineAsmRegClass::freg,
            Self::f21 => CSKYInlineAsmRegClass::freg,
            Self::f22 => CSKYInlineAsmRegClass::freg,
            Self::f23 => CSKYInlineAsmRegClass::freg,
            Self::f24 => CSKYInlineAsmRegClass::freg,
            Self::f25 => CSKYInlineAsmRegClass::freg,
            Self::f26 => CSKYInlineAsmRegClass::freg,
            Self::f27 => CSKYInlineAsmRegClass::freg,
            Self::f28 => CSKYInlineAsmRegClass::freg,
            Self::f29 => CSKYInlineAsmRegClass::freg,
            Self::f30 => CSKYInlineAsmRegClass::freg,
            Self::f31 => CSKYInlineAsmRegClass::freg,
        }
    }
    pub fn parse(name: &str) -> Result<Self, &'static str> {
        match name {
            "a0" | "r0" => Ok(Self::r0),
            "a1" | "r1" => Ok(Self::r1),
            "a2" | "r2" => Ok(Self::r2),
            "a3" | "r3" => Ok(Self::r3),
            "l0" | "r4" => Ok(Self::r4),
            "l1" | "r5" => Ok(Self::r5),
            "l2" | "r6" => Ok(Self::r6),
            "l5" | "r9" => Ok(Self::r9),
            "l6" | "r10" => Ok(Self::r10),
            "l7" | "r11" => Ok(Self::r11),
            "t0" | "r12" => Ok(Self::r12),
            "t1" | "r13" => Ok(Self::r13),
            "l8" | "r16" => Ok(Self::r16),
            "l9" | "r17" => Ok(Self::r17),
            "t2" | "r18" => Ok(Self::r18),
            "t3" | "r19" => Ok(Self::r19),
            "t4" | "r20" => Ok(Self::r20),
            "t5" | "r21" => Ok(Self::r21),
            "t6" | "r22" => Ok(Self::r22),
            "t7" | "r23" => Ok(Self::r23),
            "t8" | "r24" => Ok(Self::r24),
            "t9" | "r25" => Ok(Self::r25),
            "vr0" | "fr0" => Ok(Self::f0),
            "vr1" | "fr1" => Ok(Self::f1),
            "vr2" | "fr2" => Ok(Self::f2),
            "vr3" | "fr3" => Ok(Self::f3),
            "vr4" | "fr4" => Ok(Self::f4),
            "vr5" | "fr5" => Ok(Self::f5),
            "vr6" | "fr6" => Ok(Self::f6),
            "vr7" | "fr7" => Ok(Self::f7),
            "vr8" | "fr8" => Ok(Self::f8),
            "vr9" | "fr9" => Ok(Self::f9),
            "vr10" | "fr10" => Ok(Self::f10),
            "vr11" | "fr11" => Ok(Self::f11),
            "vr12" | "fr12" => Ok(Self::f12),
            "vr13" | "fr13" => Ok(Self::f13),
            "vr14" | "fr14" => Ok(Self::f14),
            "vr15" | "fr15" => Ok(Self::f15),
            "vr16" | "fr16" => Ok(Self::f16),
            "vr17" | "fr17" => Ok(Self::f17),
            "vr18" | "fr18" => Ok(Self::f18),
            "vr19" | "fr19" => Ok(Self::f19),
            "vr20" | "fr20" => Ok(Self::f20),
            "vr21" | "fr21" => Ok(Self::f21),
            "vr22" | "fr22" => Ok(Self::f22),
            "vr23" | "fr23" => Ok(Self::f23),
            "vr24" | "fr24" => Ok(Self::f24),
            "vr25" | "fr25" => Ok(Self::f25),
            "vr26" | "fr26" => Ok(Self::f26),
            "vr27" | "fr27" => Ok(Self::f27),
            "vr28" | "fr28" => Ok(Self::f28),
            "vr29" | "fr29" => Ok(Self::f29),
            "vr30" | "fr30" => Ok(Self::f30),
            "vr31" | "fr31" => Ok(Self::f31),
            "r7" | "l3" =>
                Err("the base pointer cannot be used as an operand for inline asm"),
            "r8" | "l4" =>
                Err("the frame pointer cannot be used as an operand for inline asm"),
            "r14" | "sp" =>
                Err("the stack pointer cannot be used as an operand for inline asm"),
            "r15" | "lr" =>
                Err("the link register cannot be used as an operand for inline asm"),
            "r31" | "tls" => Err("reserver for tls"),
            "r28" | "gb" | "rgb" | "rdb" =>
                Err("the global pointer cannot be used as an operand for inline asm"),
            "r26" | "r27" | "r29" | "tb" | "rtb" | "r30" | "svbr" =>
                Err("reserved by the ABI"),
            _ => Err("unknown register"),
        }
    }
    pub fn validate(self, _arch: super::InlineAsmArch,
        _reloc_model: crate::spec::RelocModel,
        _target_features: &rustc_data_structures::fx::FxIndexSet<Symbol>,
        _target: &crate::spec::Target, _is_clobber: bool)
        -> Result<(), &'static str> {
        match self {
            Self::r0 => { Ok(()) }
            Self::r1 => { Ok(()) }
            Self::r2 => { Ok(()) }
            Self::r3 => { Ok(()) }
            Self::r4 => { Ok(()) }
            Self::r5 => { Ok(()) }
            Self::r6 => { Ok(()) }
            Self::r9 => { Ok(()) }
            Self::r10 => { Ok(()) }
            Self::r11 => { Ok(()) }
            Self::r12 => { Ok(()) }
            Self::r13 => { Ok(()) }
            Self::r16 => { Ok(()) }
            Self::r17 => { Ok(()) }
            Self::r18 => { Ok(()) }
            Self::r19 => { Ok(()) }
            Self::r20 => { Ok(()) }
            Self::r21 => { Ok(()) }
            Self::r22 => { Ok(()) }
            Self::r23 => { Ok(()) }
            Self::r24 => { Ok(()) }
            Self::r25 => { Ok(()) }
            Self::f0 => { Ok(()) }
            Self::f1 => { Ok(()) }
            Self::f2 => { Ok(()) }
            Self::f3 => { Ok(()) }
            Self::f4 => { Ok(()) }
            Self::f5 => { Ok(()) }
            Self::f6 => { Ok(()) }
            Self::f7 => { Ok(()) }
            Self::f8 => { Ok(()) }
            Self::f9 => { Ok(()) }
            Self::f10 => { Ok(()) }
            Self::f11 => { Ok(()) }
            Self::f12 => { Ok(()) }
            Self::f13 => { Ok(()) }
            Self::f14 => { Ok(()) }
            Self::f15 => { Ok(()) }
            Self::f16 => { Ok(()) }
            Self::f17 => { Ok(()) }
            Self::f18 => { Ok(()) }
            Self::f19 => { Ok(()) }
            Self::f20 => { Ok(()) }
            Self::f21 => { Ok(()) }
            Self::f22 => { Ok(()) }
            Self::f23 => { Ok(()) }
            Self::f24 => { Ok(()) }
            Self::f25 => { Ok(()) }
            Self::f26 => { Ok(()) }
            Self::f27 => { Ok(()) }
            Self::f28 => { Ok(()) }
            Self::f29 => { Ok(()) }
            Self::f30 => { Ok(()) }
            Self::f31 => { Ok(()) }
        }
    }
}
pub(super) fn fill_reg_map(_arch: super::InlineAsmArch,
    _reloc_model: crate::spec::RelocModel,
    _target_features: &rustc_data_structures::fx::FxIndexSet<Symbol>,
    _target: &crate::spec::Target,
    _map:
        &mut rustc_data_structures::fx::FxHashMap<super::InlineAsmRegClass,
        rustc_data_structures::fx::FxIndexSet<super::InlineAsmReg>>) {
    #[allow(unused_imports)]
    use super::{InlineAsmReg, InlineAsmRegClass};
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::r0));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::r1));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::r2));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::r3));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::r4));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::r5));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::r6));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::r9));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::r10));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::r11));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::r12));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::r13));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::r16));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::r17));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::r18));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::r19));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::r20));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::r21));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::r22));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::r23));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::r24));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::r25));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::f0));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::f1));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::f2));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::f3));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::f4));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::f5));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::f6));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::f7));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::f8));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::f9));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::f10));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::f11));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::f12));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::f13));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::f14));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::f15));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::f16));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::f17));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::f18));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::f19));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::f20));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::f21));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::f22));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::f23));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::f24));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::f25));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::f26));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::f27));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::f28));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::f29));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::f30));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::CSKY(CSKYInlineAsmReg::f31));
        }
    }
}def_regs! {
48    CSKY CSKYInlineAsmReg CSKYInlineAsmRegClass {
49        r0: reg = ["r0","a0"],
50        r1: reg = ["r1","a1"],
51        r2: reg = ["r2","a2"],
52        r3: reg = ["r3","a3"],
53        r4: reg = ["r4","l0"],
54        r5: reg = ["r5","l1"],
55        r6: reg = ["r6","l2"],
56        r9: reg = ["r9","l5"],// feature e2
57        r10: reg = ["r10","l6"],// feature e2
58        r11: reg = ["r11","l7"],// feature e2
59        r12: reg = ["r12","t0"],// feature e2
60        r13: reg = ["r13","t1"],// feature e2
61        r16: reg = ["r16","l8"],// feature high-register
62        r17: reg = ["r17","l9"],// feature high-register
63        r18: reg = ["r18","t2"],// feature high-register
64        r19: reg = ["r19","t3"],// feature high-register
65        r20: reg = ["r20","t4"],// feature high-register
66        r21: reg = ["r21","t5"],// feature high-register
67        r22: reg = ["r22","t6"],// feature high-register
68        r23: reg = ["r23","t7"],// feature high-register
69        r24: reg = ["r24","t8"],// feature high-register
70        r25: reg = ["r25","t9"],// feature high-register
71        f0: freg = ["fr0","vr0"],
72        f1: freg = ["fr1","vr1"],
73        f2: freg = ["fr2","vr2"],
74        f3: freg = ["fr3","vr3"],
75        f4: freg = ["fr4","vr4"],
76        f5: freg = ["fr5","vr5"],
77        f6: freg = ["fr6","vr6"],
78        f7: freg = ["fr7","vr7"],
79        f8: freg = ["fr8","vr8"],
80        f9: freg = ["fr9","vr9"],
81        f10: freg = ["fr10","vr10"],
82        f11: freg = ["fr11","vr11"],
83        f12: freg = ["fr12","vr12"],
84        f13: freg = ["fr13","vr13"],
85        f14: freg = ["fr14","vr14"],
86        f15: freg = ["fr15","vr15"],
87        f16: freg = ["fr16","vr16"],
88        f17: freg = ["fr17","vr17"],
89        f18: freg = ["fr18","vr18"],
90        f19: freg = ["fr19","vr19"],
91        f20: freg = ["fr20","vr20"],
92        f21: freg = ["fr21","vr21"],
93        f22: freg = ["fr22","vr22"],
94        f23: freg = ["fr23","vr23"],
95        f24: freg = ["fr24","vr24"],
96        f25: freg = ["fr25","vr25"],
97        f26: freg = ["fr26","vr26"],
98        f27: freg = ["fr27","vr27"],
99        f28: freg = ["fr28","vr28"],
100        f29: freg = ["fr29","vr29"],
101        f30: freg = ["fr30","vr30"],
102        f31: freg = ["fr31","vr31"],
103        #error = ["r7", "l3"] =>
104            "the base pointer cannot be used as an operand for inline asm",
105        #error = ["r8","l4"] =>
106            "the frame pointer cannot be used as an operand for inline asm",
107        #error = ["r14","sp"] =>
108            "the stack pointer cannot be used as an operand for inline asm",
109        #error = ["r15","lr"] =>
110            "the link register cannot be used as an operand for inline asm",
111        #error = ["r31","tls"] =>
112            "reserver for tls",
113        #error = ["r28", "gb", "rgb", "rdb"] =>
114            "the global pointer cannot be used as an operand for inline asm",
115        #error = ["r26","r27","r29","tb", "rtb", "r30","svbr"] =>
116            "reserved by the ABI",
117    }
118}
119
120impl CSKYInlineAsmReg {
121    pub fn emit(
122        self,
123        out: &mut dyn fmt::Write,
124        _arch: InlineAsmArch,
125        _modifier: Option<char>,
126    ) -> fmt::Result {
127        out.write_str(self.name())
128    }
129}