rustc_target/asm/
s390x.rs

1use std::fmt;
2
3use rustc_span::Symbol;
4
5use super::{InlineAsmArch, InlineAsmType, ModifierInfo};
6
7#[allow(non_camel_case_types)]
pub enum S390xInlineAsmRegClass { reg, reg_addr, freg, vreg, areg, }
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::marker::Copy for S390xInlineAsmRegClass { }
#[automatically_derived]
#[doc(hidden)]
#[allow(non_camel_case_types)]
unsafe impl ::core::clone::TrivialClone for S390xInlineAsmRegClass { }
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::clone::Clone for S390xInlineAsmRegClass {
    #[inline]
    fn clone(&self) -> S390xInlineAsmRegClass { *self }
}
const _: () =
    {
        impl<__E: ::rustc_span::SpanEncoder> ::rustc_serialize::Encodable<__E>
            for S390xInlineAsmRegClass {
            fn encode(&self, __encoder: &mut __E) {
                let disc =
                    match *self {
                        S390xInlineAsmRegClass::reg => { 0usize }
                        S390xInlineAsmRegClass::reg_addr => { 1usize }
                        S390xInlineAsmRegClass::freg => { 2usize }
                        S390xInlineAsmRegClass::vreg => { 3usize }
                        S390xInlineAsmRegClass::areg => { 4usize }
                    };
                ::rustc_serialize::Encoder::emit_u8(__encoder, disc as u8);
                match *self {
                    S390xInlineAsmRegClass::reg => {}
                    S390xInlineAsmRegClass::reg_addr => {}
                    S390xInlineAsmRegClass::freg => {}
                    S390xInlineAsmRegClass::vreg => {}
                    S390xInlineAsmRegClass::areg => {}
                }
            }
        }
    };
const _: () =
    {
        impl<__D: ::rustc_span::SpanDecoder> ::rustc_serialize::Decodable<__D>
            for S390xInlineAsmRegClass {
            fn decode(__decoder: &mut __D) -> Self {
                match ::rustc_serialize::Decoder::read_u8(__decoder) as usize
                    {
                    0usize => { S390xInlineAsmRegClass::reg }
                    1usize => { S390xInlineAsmRegClass::reg_addr }
                    2usize => { S390xInlineAsmRegClass::freg }
                    3usize => { S390xInlineAsmRegClass::vreg }
                    4usize => { S390xInlineAsmRegClass::areg }
                    n => {
                        ::core::panicking::panic_fmt(format_args!("invalid enum variant tag while decoding `S390xInlineAsmRegClass`, expected 0..5, actual {0}",
                                n));
                    }
                }
            }
        }
    };
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::fmt::Debug for S390xInlineAsmRegClass {
    #[inline]
    fn fmt(&self, f: &mut ::core::fmt::Formatter) -> ::core::fmt::Result {
        ::core::fmt::Formatter::write_str(f,
            match self {
                S390xInlineAsmRegClass::reg => "reg",
                S390xInlineAsmRegClass::reg_addr => "reg_addr",
                S390xInlineAsmRegClass::freg => "freg",
                S390xInlineAsmRegClass::vreg => "vreg",
                S390xInlineAsmRegClass::areg => "areg",
            })
    }
}
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::cmp::Eq for S390xInlineAsmRegClass {
    #[inline]
    #[doc(hidden)]
    #[coverage(off)]
    fn assert_receiver_is_total_eq(&self) -> () {}
}
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::marker::StructuralPartialEq for S390xInlineAsmRegClass { }
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::cmp::PartialEq for S390xInlineAsmRegClass {
    #[inline]
    fn eq(&self, other: &S390xInlineAsmRegClass) -> bool {
        let __self_discr = ::core::intrinsics::discriminant_value(self);
        let __arg1_discr = ::core::intrinsics::discriminant_value(other);
        __self_discr == __arg1_discr
    }
}
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::cmp::PartialOrd for S390xInlineAsmRegClass {
    #[inline]
    fn partial_cmp(&self, other: &S390xInlineAsmRegClass)
        -> ::core::option::Option<::core::cmp::Ordering> {
        let __self_discr = ::core::intrinsics::discriminant_value(self);
        let __arg1_discr = ::core::intrinsics::discriminant_value(other);
        ::core::cmp::PartialOrd::partial_cmp(&__self_discr, &__arg1_discr)
    }
}
#[automatically_derived]
#[allow(non_camel_case_types)]
impl ::core::hash::Hash for S390xInlineAsmRegClass {
    #[inline]
    fn hash<__H: ::core::hash::Hasher>(&self, state: &mut __H) -> () {
        let __self_discr = ::core::intrinsics::discriminant_value(self);
        ::core::hash::Hash::hash(&__self_discr, state)
    }
}
const _: () =
    {
        impl<__CTX> ::rustc_data_structures::stable_hasher::HashStable<__CTX>
            for S390xInlineAsmRegClass where __CTX: crate::HashStableContext {
            #[inline]
            fn hash_stable(&self, __hcx: &mut __CTX,
                __hasher:
                    &mut ::rustc_data_structures::stable_hasher::StableHasher) {
                ::std::mem::discriminant(self).hash_stable(__hcx, __hasher);
                match *self {
                    S390xInlineAsmRegClass::reg => {}
                    S390xInlineAsmRegClass::reg_addr => {}
                    S390xInlineAsmRegClass::freg => {}
                    S390xInlineAsmRegClass::vreg => {}
                    S390xInlineAsmRegClass::areg => {}
                }
            }
        }
    };
impl S390xInlineAsmRegClass {
    pub fn name(self) -> rustc_span::Symbol {
        match self {
            Self::reg => rustc_span::sym::reg,
            Self::reg_addr => rustc_span::sym::reg_addr,
            Self::freg => rustc_span::sym::freg,
            Self::vreg => rustc_span::sym::vreg,
            Self::areg => rustc_span::sym::areg,
        }
    }
    pub fn parse(name: rustc_span::Symbol)
        -> Result<Self, &'static [rustc_span::Symbol]> {
        match name {
            rustc_span::sym::reg => Ok(Self::reg),
            rustc_span::sym::reg_addr => Ok(Self::reg_addr),
            rustc_span::sym::freg => Ok(Self::freg),
            rustc_span::sym::vreg => Ok(Self::vreg),
            rustc_span::sym::areg => Ok(Self::areg),
            _ =>
                Err(&[rustc_span::sym::reg, rustc_span::sym::reg_addr,
                                rustc_span::sym::freg, rustc_span::sym::vreg,
                                rustc_span::sym::areg]),
        }
    }
}
pub(super) fn regclass_map()
    ->
        rustc_data_structures::fx::FxHashMap<super::InlineAsmRegClass,
        rustc_data_structures::fx::FxIndexSet<super::InlineAsmReg>> {
    use rustc_data_structures::fx::FxHashMap;
    use rustc_data_structures::fx::FxIndexSet;
    use super::InlineAsmRegClass;
    let mut map = FxHashMap::default();
    map.insert(InlineAsmRegClass::S390x(S390xInlineAsmRegClass::reg),
        FxIndexSet::default());
    map.insert(InlineAsmRegClass::S390x(S390xInlineAsmRegClass::reg_addr),
        FxIndexSet::default());
    map.insert(InlineAsmRegClass::S390x(S390xInlineAsmRegClass::freg),
        FxIndexSet::default());
    map.insert(InlineAsmRegClass::S390x(S390xInlineAsmRegClass::vreg),
        FxIndexSet::default());
    map.insert(InlineAsmRegClass::S390x(S390xInlineAsmRegClass::areg),
        FxIndexSet::default());
    map
}def_reg_class! {
8    S390x S390xInlineAsmRegClass {
9        reg,
10        reg_addr,
11        freg,
12        vreg,
13        areg,
14    }
15}
16
17impl S390xInlineAsmRegClass {
18    pub fn valid_modifiers(self, _arch: super::InlineAsmArch) -> &'static [char] {
19        &[]
20    }
21
22    pub fn suggest_class(self, _arch: InlineAsmArch, _ty: InlineAsmType) -> Option<Self> {
23        None
24    }
25
26    pub fn suggest_modifier(
27        self,
28        _arch: InlineAsmArch,
29        _ty: InlineAsmType,
30    ) -> Option<ModifierInfo> {
31        None
32    }
33
34    pub fn default_modifier(self, _arch: InlineAsmArch) -> Option<ModifierInfo> {
35        None
36    }
37
38    pub fn supported_types(
39        self,
40        _arch: InlineAsmArch,
41        allow_experimental_reg: bool,
42    ) -> &'static [(InlineAsmType, Option<Symbol>)] {
43        match self {
44            Self::reg | Self::reg_addr => {
    use super::InlineAsmType::*;
    &[(I8, None), (I16, None), (I32, None), (I64, None)]
}types! { _: I8, I16, I32, I64; },
45            Self::freg => {
    use super::InlineAsmType::*;
    &[(F16, None), (F32, None), (F64, None)]
}types! { _: F16, F32, F64; },
46            Self::vreg => {
47                if allow_experimental_reg {
48                    // non-clobber-only vector register support is unstable.
49                    {
    use super::InlineAsmType::*;
    &[(I32, Some(rustc_span::sym::vector)),
                (F16, Some(rustc_span::sym::vector)),
                (F32, Some(rustc_span::sym::vector)),
                (I64, Some(rustc_span::sym::vector)),
                (F64, Some(rustc_span::sym::vector)),
                (I128, Some(rustc_span::sym::vector)),
                (F128, Some(rustc_span::sym::vector)),
                (VecI8(16), Some(rustc_span::sym::vector)),
                (VecI16(8), Some(rustc_span::sym::vector)),
                (VecI32(4), Some(rustc_span::sym::vector)),
                (VecI64(2), Some(rustc_span::sym::vector)),
                (VecF16(8), Some(rustc_span::sym::vector)),
                (VecF32(4), Some(rustc_span::sym::vector)),
                (VecF64(2), Some(rustc_span::sym::vector))]
}types! {
50                        vector: I32, F16, F32, I64, F64, I128, F128,
51                            VecI8(16), VecI16(8), VecI32(4), VecI64(2), VecF16(8), VecF32(4), VecF64(2);
52                    }
53                } else {
54                    &[]
55                }
56            }
57            Self::areg => &[],
58        }
59    }
60}
61
62#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
pub enum S390xInlineAsmReg {
    r0,
    r1,
    r2,
    r3,
    r4,
    r5,
    r6,
    r7,
    r8,
    r9,
    r10,
    r12,
    r13,
    r14,
    f0,
    f1,
    f2,
    f3,
    f4,
    f5,
    f6,
    f7,
    f8,
    f9,
    f10,
    f11,
    f12,
    f13,
    f14,
    f15,
    v0,
    v1,
    v2,
    v3,
    v4,
    v5,
    v6,
    v7,
    v8,
    v9,
    v10,
    v11,
    v12,
    v13,
    v14,
    v15,
    v16,
    v17,
    v18,
    v19,
    v20,
    v21,
    v22,
    v23,
    v24,
    v25,
    v26,
    v27,
    v28,
    v29,
    v30,
    v31,
    a2,
    a3,
    a4,
    a5,
    a6,
    a7,
    a8,
    a9,
    a10,
    a11,
    a12,
    a13,
    a14,
    a15,
}
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::marker::Copy for S390xInlineAsmReg { }
#[automatically_derived]
#[doc(hidden)]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
unsafe impl ::core::clone::TrivialClone for S390xInlineAsmReg { }
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::clone::Clone for S390xInlineAsmReg {
    #[inline]
    fn clone(&self) -> S390xInlineAsmReg { *self }
}
const _: () =
    {
        impl<__E: ::rustc_span::SpanEncoder> ::rustc_serialize::Encodable<__E>
            for S390xInlineAsmReg {
            fn encode(&self, __encoder: &mut __E) {
                let disc =
                    match *self {
                        S390xInlineAsmReg::r0 => { 0usize }
                        S390xInlineAsmReg::r1 => { 1usize }
                        S390xInlineAsmReg::r2 => { 2usize }
                        S390xInlineAsmReg::r3 => { 3usize }
                        S390xInlineAsmReg::r4 => { 4usize }
                        S390xInlineAsmReg::r5 => { 5usize }
                        S390xInlineAsmReg::r6 => { 6usize }
                        S390xInlineAsmReg::r7 => { 7usize }
                        S390xInlineAsmReg::r8 => { 8usize }
                        S390xInlineAsmReg::r9 => { 9usize }
                        S390xInlineAsmReg::r10 => { 10usize }
                        S390xInlineAsmReg::r12 => { 11usize }
                        S390xInlineAsmReg::r13 => { 12usize }
                        S390xInlineAsmReg::r14 => { 13usize }
                        S390xInlineAsmReg::f0 => { 14usize }
                        S390xInlineAsmReg::f1 => { 15usize }
                        S390xInlineAsmReg::f2 => { 16usize }
                        S390xInlineAsmReg::f3 => { 17usize }
                        S390xInlineAsmReg::f4 => { 18usize }
                        S390xInlineAsmReg::f5 => { 19usize }
                        S390xInlineAsmReg::f6 => { 20usize }
                        S390xInlineAsmReg::f7 => { 21usize }
                        S390xInlineAsmReg::f8 => { 22usize }
                        S390xInlineAsmReg::f9 => { 23usize }
                        S390xInlineAsmReg::f10 => { 24usize }
                        S390xInlineAsmReg::f11 => { 25usize }
                        S390xInlineAsmReg::f12 => { 26usize }
                        S390xInlineAsmReg::f13 => { 27usize }
                        S390xInlineAsmReg::f14 => { 28usize }
                        S390xInlineAsmReg::f15 => { 29usize }
                        S390xInlineAsmReg::v0 => { 30usize }
                        S390xInlineAsmReg::v1 => { 31usize }
                        S390xInlineAsmReg::v2 => { 32usize }
                        S390xInlineAsmReg::v3 => { 33usize }
                        S390xInlineAsmReg::v4 => { 34usize }
                        S390xInlineAsmReg::v5 => { 35usize }
                        S390xInlineAsmReg::v6 => { 36usize }
                        S390xInlineAsmReg::v7 => { 37usize }
                        S390xInlineAsmReg::v8 => { 38usize }
                        S390xInlineAsmReg::v9 => { 39usize }
                        S390xInlineAsmReg::v10 => { 40usize }
                        S390xInlineAsmReg::v11 => { 41usize }
                        S390xInlineAsmReg::v12 => { 42usize }
                        S390xInlineAsmReg::v13 => { 43usize }
                        S390xInlineAsmReg::v14 => { 44usize }
                        S390xInlineAsmReg::v15 => { 45usize }
                        S390xInlineAsmReg::v16 => { 46usize }
                        S390xInlineAsmReg::v17 => { 47usize }
                        S390xInlineAsmReg::v18 => { 48usize }
                        S390xInlineAsmReg::v19 => { 49usize }
                        S390xInlineAsmReg::v20 => { 50usize }
                        S390xInlineAsmReg::v21 => { 51usize }
                        S390xInlineAsmReg::v22 => { 52usize }
                        S390xInlineAsmReg::v23 => { 53usize }
                        S390xInlineAsmReg::v24 => { 54usize }
                        S390xInlineAsmReg::v25 => { 55usize }
                        S390xInlineAsmReg::v26 => { 56usize }
                        S390xInlineAsmReg::v27 => { 57usize }
                        S390xInlineAsmReg::v28 => { 58usize }
                        S390xInlineAsmReg::v29 => { 59usize }
                        S390xInlineAsmReg::v30 => { 60usize }
                        S390xInlineAsmReg::v31 => { 61usize }
                        S390xInlineAsmReg::a2 => { 62usize }
                        S390xInlineAsmReg::a3 => { 63usize }
                        S390xInlineAsmReg::a4 => { 64usize }
                        S390xInlineAsmReg::a5 => { 65usize }
                        S390xInlineAsmReg::a6 => { 66usize }
                        S390xInlineAsmReg::a7 => { 67usize }
                        S390xInlineAsmReg::a8 => { 68usize }
                        S390xInlineAsmReg::a9 => { 69usize }
                        S390xInlineAsmReg::a10 => { 70usize }
                        S390xInlineAsmReg::a11 => { 71usize }
                        S390xInlineAsmReg::a12 => { 72usize }
                        S390xInlineAsmReg::a13 => { 73usize }
                        S390xInlineAsmReg::a14 => { 74usize }
                        S390xInlineAsmReg::a15 => { 75usize }
                    };
                ::rustc_serialize::Encoder::emit_u8(__encoder, disc as u8);
                match *self {
                    S390xInlineAsmReg::r0 => {}
                    S390xInlineAsmReg::r1 => {}
                    S390xInlineAsmReg::r2 => {}
                    S390xInlineAsmReg::r3 => {}
                    S390xInlineAsmReg::r4 => {}
                    S390xInlineAsmReg::r5 => {}
                    S390xInlineAsmReg::r6 => {}
                    S390xInlineAsmReg::r7 => {}
                    S390xInlineAsmReg::r8 => {}
                    S390xInlineAsmReg::r9 => {}
                    S390xInlineAsmReg::r10 => {}
                    S390xInlineAsmReg::r12 => {}
                    S390xInlineAsmReg::r13 => {}
                    S390xInlineAsmReg::r14 => {}
                    S390xInlineAsmReg::f0 => {}
                    S390xInlineAsmReg::f1 => {}
                    S390xInlineAsmReg::f2 => {}
                    S390xInlineAsmReg::f3 => {}
                    S390xInlineAsmReg::f4 => {}
                    S390xInlineAsmReg::f5 => {}
                    S390xInlineAsmReg::f6 => {}
                    S390xInlineAsmReg::f7 => {}
                    S390xInlineAsmReg::f8 => {}
                    S390xInlineAsmReg::f9 => {}
                    S390xInlineAsmReg::f10 => {}
                    S390xInlineAsmReg::f11 => {}
                    S390xInlineAsmReg::f12 => {}
                    S390xInlineAsmReg::f13 => {}
                    S390xInlineAsmReg::f14 => {}
                    S390xInlineAsmReg::f15 => {}
                    S390xInlineAsmReg::v0 => {}
                    S390xInlineAsmReg::v1 => {}
                    S390xInlineAsmReg::v2 => {}
                    S390xInlineAsmReg::v3 => {}
                    S390xInlineAsmReg::v4 => {}
                    S390xInlineAsmReg::v5 => {}
                    S390xInlineAsmReg::v6 => {}
                    S390xInlineAsmReg::v7 => {}
                    S390xInlineAsmReg::v8 => {}
                    S390xInlineAsmReg::v9 => {}
                    S390xInlineAsmReg::v10 => {}
                    S390xInlineAsmReg::v11 => {}
                    S390xInlineAsmReg::v12 => {}
                    S390xInlineAsmReg::v13 => {}
                    S390xInlineAsmReg::v14 => {}
                    S390xInlineAsmReg::v15 => {}
                    S390xInlineAsmReg::v16 => {}
                    S390xInlineAsmReg::v17 => {}
                    S390xInlineAsmReg::v18 => {}
                    S390xInlineAsmReg::v19 => {}
                    S390xInlineAsmReg::v20 => {}
                    S390xInlineAsmReg::v21 => {}
                    S390xInlineAsmReg::v22 => {}
                    S390xInlineAsmReg::v23 => {}
                    S390xInlineAsmReg::v24 => {}
                    S390xInlineAsmReg::v25 => {}
                    S390xInlineAsmReg::v26 => {}
                    S390xInlineAsmReg::v27 => {}
                    S390xInlineAsmReg::v28 => {}
                    S390xInlineAsmReg::v29 => {}
                    S390xInlineAsmReg::v30 => {}
                    S390xInlineAsmReg::v31 => {}
                    S390xInlineAsmReg::a2 => {}
                    S390xInlineAsmReg::a3 => {}
                    S390xInlineAsmReg::a4 => {}
                    S390xInlineAsmReg::a5 => {}
                    S390xInlineAsmReg::a6 => {}
                    S390xInlineAsmReg::a7 => {}
                    S390xInlineAsmReg::a8 => {}
                    S390xInlineAsmReg::a9 => {}
                    S390xInlineAsmReg::a10 => {}
                    S390xInlineAsmReg::a11 => {}
                    S390xInlineAsmReg::a12 => {}
                    S390xInlineAsmReg::a13 => {}
                    S390xInlineAsmReg::a14 => {}
                    S390xInlineAsmReg::a15 => {}
                }
            }
        }
    };
const _: () =
    {
        impl<__D: ::rustc_span::SpanDecoder> ::rustc_serialize::Decodable<__D>
            for S390xInlineAsmReg {
            fn decode(__decoder: &mut __D) -> Self {
                match ::rustc_serialize::Decoder::read_u8(__decoder) as usize
                    {
                    0usize => { S390xInlineAsmReg::r0 }
                    1usize => { S390xInlineAsmReg::r1 }
                    2usize => { S390xInlineAsmReg::r2 }
                    3usize => { S390xInlineAsmReg::r3 }
                    4usize => { S390xInlineAsmReg::r4 }
                    5usize => { S390xInlineAsmReg::r5 }
                    6usize => { S390xInlineAsmReg::r6 }
                    7usize => { S390xInlineAsmReg::r7 }
                    8usize => { S390xInlineAsmReg::r8 }
                    9usize => { S390xInlineAsmReg::r9 }
                    10usize => { S390xInlineAsmReg::r10 }
                    11usize => { S390xInlineAsmReg::r12 }
                    12usize => { S390xInlineAsmReg::r13 }
                    13usize => { S390xInlineAsmReg::r14 }
                    14usize => { S390xInlineAsmReg::f0 }
                    15usize => { S390xInlineAsmReg::f1 }
                    16usize => { S390xInlineAsmReg::f2 }
                    17usize => { S390xInlineAsmReg::f3 }
                    18usize => { S390xInlineAsmReg::f4 }
                    19usize => { S390xInlineAsmReg::f5 }
                    20usize => { S390xInlineAsmReg::f6 }
                    21usize => { S390xInlineAsmReg::f7 }
                    22usize => { S390xInlineAsmReg::f8 }
                    23usize => { S390xInlineAsmReg::f9 }
                    24usize => { S390xInlineAsmReg::f10 }
                    25usize => { S390xInlineAsmReg::f11 }
                    26usize => { S390xInlineAsmReg::f12 }
                    27usize => { S390xInlineAsmReg::f13 }
                    28usize => { S390xInlineAsmReg::f14 }
                    29usize => { S390xInlineAsmReg::f15 }
                    30usize => { S390xInlineAsmReg::v0 }
                    31usize => { S390xInlineAsmReg::v1 }
                    32usize => { S390xInlineAsmReg::v2 }
                    33usize => { S390xInlineAsmReg::v3 }
                    34usize => { S390xInlineAsmReg::v4 }
                    35usize => { S390xInlineAsmReg::v5 }
                    36usize => { S390xInlineAsmReg::v6 }
                    37usize => { S390xInlineAsmReg::v7 }
                    38usize => { S390xInlineAsmReg::v8 }
                    39usize => { S390xInlineAsmReg::v9 }
                    40usize => { S390xInlineAsmReg::v10 }
                    41usize => { S390xInlineAsmReg::v11 }
                    42usize => { S390xInlineAsmReg::v12 }
                    43usize => { S390xInlineAsmReg::v13 }
                    44usize => { S390xInlineAsmReg::v14 }
                    45usize => { S390xInlineAsmReg::v15 }
                    46usize => { S390xInlineAsmReg::v16 }
                    47usize => { S390xInlineAsmReg::v17 }
                    48usize => { S390xInlineAsmReg::v18 }
                    49usize => { S390xInlineAsmReg::v19 }
                    50usize => { S390xInlineAsmReg::v20 }
                    51usize => { S390xInlineAsmReg::v21 }
                    52usize => { S390xInlineAsmReg::v22 }
                    53usize => { S390xInlineAsmReg::v23 }
                    54usize => { S390xInlineAsmReg::v24 }
                    55usize => { S390xInlineAsmReg::v25 }
                    56usize => { S390xInlineAsmReg::v26 }
                    57usize => { S390xInlineAsmReg::v27 }
                    58usize => { S390xInlineAsmReg::v28 }
                    59usize => { S390xInlineAsmReg::v29 }
                    60usize => { S390xInlineAsmReg::v30 }
                    61usize => { S390xInlineAsmReg::v31 }
                    62usize => { S390xInlineAsmReg::a2 }
                    63usize => { S390xInlineAsmReg::a3 }
                    64usize => { S390xInlineAsmReg::a4 }
                    65usize => { S390xInlineAsmReg::a5 }
                    66usize => { S390xInlineAsmReg::a6 }
                    67usize => { S390xInlineAsmReg::a7 }
                    68usize => { S390xInlineAsmReg::a8 }
                    69usize => { S390xInlineAsmReg::a9 }
                    70usize => { S390xInlineAsmReg::a10 }
                    71usize => { S390xInlineAsmReg::a11 }
                    72usize => { S390xInlineAsmReg::a12 }
                    73usize => { S390xInlineAsmReg::a13 }
                    74usize => { S390xInlineAsmReg::a14 }
                    75usize => { S390xInlineAsmReg::a15 }
                    n => {
                        ::core::panicking::panic_fmt(format_args!("invalid enum variant tag while decoding `S390xInlineAsmReg`, expected 0..76, actual {0}",
                                n));
                    }
                }
            }
        }
    };
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::fmt::Debug for S390xInlineAsmReg {
    #[inline]
    fn fmt(&self, f: &mut ::core::fmt::Formatter) -> ::core::fmt::Result {
        ::core::fmt::Formatter::write_str(f,
            match self {
                S390xInlineAsmReg::r0 => "r0",
                S390xInlineAsmReg::r1 => "r1",
                S390xInlineAsmReg::r2 => "r2",
                S390xInlineAsmReg::r3 => "r3",
                S390xInlineAsmReg::r4 => "r4",
                S390xInlineAsmReg::r5 => "r5",
                S390xInlineAsmReg::r6 => "r6",
                S390xInlineAsmReg::r7 => "r7",
                S390xInlineAsmReg::r8 => "r8",
                S390xInlineAsmReg::r9 => "r9",
                S390xInlineAsmReg::r10 => "r10",
                S390xInlineAsmReg::r12 => "r12",
                S390xInlineAsmReg::r13 => "r13",
                S390xInlineAsmReg::r14 => "r14",
                S390xInlineAsmReg::f0 => "f0",
                S390xInlineAsmReg::f1 => "f1",
                S390xInlineAsmReg::f2 => "f2",
                S390xInlineAsmReg::f3 => "f3",
                S390xInlineAsmReg::f4 => "f4",
                S390xInlineAsmReg::f5 => "f5",
                S390xInlineAsmReg::f6 => "f6",
                S390xInlineAsmReg::f7 => "f7",
                S390xInlineAsmReg::f8 => "f8",
                S390xInlineAsmReg::f9 => "f9",
                S390xInlineAsmReg::f10 => "f10",
                S390xInlineAsmReg::f11 => "f11",
                S390xInlineAsmReg::f12 => "f12",
                S390xInlineAsmReg::f13 => "f13",
                S390xInlineAsmReg::f14 => "f14",
                S390xInlineAsmReg::f15 => "f15",
                S390xInlineAsmReg::v0 => "v0",
                S390xInlineAsmReg::v1 => "v1",
                S390xInlineAsmReg::v2 => "v2",
                S390xInlineAsmReg::v3 => "v3",
                S390xInlineAsmReg::v4 => "v4",
                S390xInlineAsmReg::v5 => "v5",
                S390xInlineAsmReg::v6 => "v6",
                S390xInlineAsmReg::v7 => "v7",
                S390xInlineAsmReg::v8 => "v8",
                S390xInlineAsmReg::v9 => "v9",
                S390xInlineAsmReg::v10 => "v10",
                S390xInlineAsmReg::v11 => "v11",
                S390xInlineAsmReg::v12 => "v12",
                S390xInlineAsmReg::v13 => "v13",
                S390xInlineAsmReg::v14 => "v14",
                S390xInlineAsmReg::v15 => "v15",
                S390xInlineAsmReg::v16 => "v16",
                S390xInlineAsmReg::v17 => "v17",
                S390xInlineAsmReg::v18 => "v18",
                S390xInlineAsmReg::v19 => "v19",
                S390xInlineAsmReg::v20 => "v20",
                S390xInlineAsmReg::v21 => "v21",
                S390xInlineAsmReg::v22 => "v22",
                S390xInlineAsmReg::v23 => "v23",
                S390xInlineAsmReg::v24 => "v24",
                S390xInlineAsmReg::v25 => "v25",
                S390xInlineAsmReg::v26 => "v26",
                S390xInlineAsmReg::v27 => "v27",
                S390xInlineAsmReg::v28 => "v28",
                S390xInlineAsmReg::v29 => "v29",
                S390xInlineAsmReg::v30 => "v30",
                S390xInlineAsmReg::v31 => "v31",
                S390xInlineAsmReg::a2 => "a2",
                S390xInlineAsmReg::a3 => "a3",
                S390xInlineAsmReg::a4 => "a4",
                S390xInlineAsmReg::a5 => "a5",
                S390xInlineAsmReg::a6 => "a6",
                S390xInlineAsmReg::a7 => "a7",
                S390xInlineAsmReg::a8 => "a8",
                S390xInlineAsmReg::a9 => "a9",
                S390xInlineAsmReg::a10 => "a10",
                S390xInlineAsmReg::a11 => "a11",
                S390xInlineAsmReg::a12 => "a12",
                S390xInlineAsmReg::a13 => "a13",
                S390xInlineAsmReg::a14 => "a14",
                S390xInlineAsmReg::a15 => "a15",
            })
    }
}
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::cmp::Eq for S390xInlineAsmReg {
    #[inline]
    #[doc(hidden)]
    #[coverage(off)]
    fn assert_receiver_is_total_eq(&self) -> () {}
}
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::marker::StructuralPartialEq for S390xInlineAsmReg { }
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::cmp::PartialEq for S390xInlineAsmReg {
    #[inline]
    fn eq(&self, other: &S390xInlineAsmReg) -> bool {
        let __self_discr = ::core::intrinsics::discriminant_value(self);
        let __arg1_discr = ::core::intrinsics::discriminant_value(other);
        __self_discr == __arg1_discr
    }
}
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::cmp::PartialOrd for S390xInlineAsmReg {
    #[inline]
    fn partial_cmp(&self, other: &S390xInlineAsmReg)
        -> ::core::option::Option<::core::cmp::Ordering> {
        let __self_discr = ::core::intrinsics::discriminant_value(self);
        let __arg1_discr = ::core::intrinsics::discriminant_value(other);
        ::core::cmp::PartialOrd::partial_cmp(&__self_discr, &__arg1_discr)
    }
}
#[automatically_derived]
#[allow(unreachable_code)]
#[allow(non_camel_case_types)]
impl ::core::hash::Hash for S390xInlineAsmReg {
    #[inline]
    fn hash<__H: ::core::hash::Hasher>(&self, state: &mut __H) -> () {
        let __self_discr = ::core::intrinsics::discriminant_value(self);
        ::core::hash::Hash::hash(&__self_discr, state)
    }
}
const _: () =
    {
        impl<__CTX> ::rustc_data_structures::stable_hasher::HashStable<__CTX>
            for S390xInlineAsmReg where __CTX: crate::HashStableContext {
            #[inline]
            fn hash_stable(&self, __hcx: &mut __CTX,
                __hasher:
                    &mut ::rustc_data_structures::stable_hasher::StableHasher) {
                ::std::mem::discriminant(self).hash_stable(__hcx, __hasher);
                match *self {
                    S390xInlineAsmReg::r0 => {}
                    S390xInlineAsmReg::r1 => {}
                    S390xInlineAsmReg::r2 => {}
                    S390xInlineAsmReg::r3 => {}
                    S390xInlineAsmReg::r4 => {}
                    S390xInlineAsmReg::r5 => {}
                    S390xInlineAsmReg::r6 => {}
                    S390xInlineAsmReg::r7 => {}
                    S390xInlineAsmReg::r8 => {}
                    S390xInlineAsmReg::r9 => {}
                    S390xInlineAsmReg::r10 => {}
                    S390xInlineAsmReg::r12 => {}
                    S390xInlineAsmReg::r13 => {}
                    S390xInlineAsmReg::r14 => {}
                    S390xInlineAsmReg::f0 => {}
                    S390xInlineAsmReg::f1 => {}
                    S390xInlineAsmReg::f2 => {}
                    S390xInlineAsmReg::f3 => {}
                    S390xInlineAsmReg::f4 => {}
                    S390xInlineAsmReg::f5 => {}
                    S390xInlineAsmReg::f6 => {}
                    S390xInlineAsmReg::f7 => {}
                    S390xInlineAsmReg::f8 => {}
                    S390xInlineAsmReg::f9 => {}
                    S390xInlineAsmReg::f10 => {}
                    S390xInlineAsmReg::f11 => {}
                    S390xInlineAsmReg::f12 => {}
                    S390xInlineAsmReg::f13 => {}
                    S390xInlineAsmReg::f14 => {}
                    S390xInlineAsmReg::f15 => {}
                    S390xInlineAsmReg::v0 => {}
                    S390xInlineAsmReg::v1 => {}
                    S390xInlineAsmReg::v2 => {}
                    S390xInlineAsmReg::v3 => {}
                    S390xInlineAsmReg::v4 => {}
                    S390xInlineAsmReg::v5 => {}
                    S390xInlineAsmReg::v6 => {}
                    S390xInlineAsmReg::v7 => {}
                    S390xInlineAsmReg::v8 => {}
                    S390xInlineAsmReg::v9 => {}
                    S390xInlineAsmReg::v10 => {}
                    S390xInlineAsmReg::v11 => {}
                    S390xInlineAsmReg::v12 => {}
                    S390xInlineAsmReg::v13 => {}
                    S390xInlineAsmReg::v14 => {}
                    S390xInlineAsmReg::v15 => {}
                    S390xInlineAsmReg::v16 => {}
                    S390xInlineAsmReg::v17 => {}
                    S390xInlineAsmReg::v18 => {}
                    S390xInlineAsmReg::v19 => {}
                    S390xInlineAsmReg::v20 => {}
                    S390xInlineAsmReg::v21 => {}
                    S390xInlineAsmReg::v22 => {}
                    S390xInlineAsmReg::v23 => {}
                    S390xInlineAsmReg::v24 => {}
                    S390xInlineAsmReg::v25 => {}
                    S390xInlineAsmReg::v26 => {}
                    S390xInlineAsmReg::v27 => {}
                    S390xInlineAsmReg::v28 => {}
                    S390xInlineAsmReg::v29 => {}
                    S390xInlineAsmReg::v30 => {}
                    S390xInlineAsmReg::v31 => {}
                    S390xInlineAsmReg::a2 => {}
                    S390xInlineAsmReg::a3 => {}
                    S390xInlineAsmReg::a4 => {}
                    S390xInlineAsmReg::a5 => {}
                    S390xInlineAsmReg::a6 => {}
                    S390xInlineAsmReg::a7 => {}
                    S390xInlineAsmReg::a8 => {}
                    S390xInlineAsmReg::a9 => {}
                    S390xInlineAsmReg::a10 => {}
                    S390xInlineAsmReg::a11 => {}
                    S390xInlineAsmReg::a12 => {}
                    S390xInlineAsmReg::a13 => {}
                    S390xInlineAsmReg::a14 => {}
                    S390xInlineAsmReg::a15 => {}
                }
            }
        }
    };
impl S390xInlineAsmReg {
    pub fn name(self) -> &'static str {
        match self {
            Self::r0 => "r0",
            Self::r1 => "r1",
            Self::r2 => "r2",
            Self::r3 => "r3",
            Self::r4 => "r4",
            Self::r5 => "r5",
            Self::r6 => "r6",
            Self::r7 => "r7",
            Self::r8 => "r8",
            Self::r9 => "r9",
            Self::r10 => "r10",
            Self::r12 => "r12",
            Self::r13 => "r13",
            Self::r14 => "r14",
            Self::f0 => "f0",
            Self::f1 => "f1",
            Self::f2 => "f2",
            Self::f3 => "f3",
            Self::f4 => "f4",
            Self::f5 => "f5",
            Self::f6 => "f6",
            Self::f7 => "f7",
            Self::f8 => "f8",
            Self::f9 => "f9",
            Self::f10 => "f10",
            Self::f11 => "f11",
            Self::f12 => "f12",
            Self::f13 => "f13",
            Self::f14 => "f14",
            Self::f15 => "f15",
            Self::v0 => "v0",
            Self::v1 => "v1",
            Self::v2 => "v2",
            Self::v3 => "v3",
            Self::v4 => "v4",
            Self::v5 => "v5",
            Self::v6 => "v6",
            Self::v7 => "v7",
            Self::v8 => "v8",
            Self::v9 => "v9",
            Self::v10 => "v10",
            Self::v11 => "v11",
            Self::v12 => "v12",
            Self::v13 => "v13",
            Self::v14 => "v14",
            Self::v15 => "v15",
            Self::v16 => "v16",
            Self::v17 => "v17",
            Self::v18 => "v18",
            Self::v19 => "v19",
            Self::v20 => "v20",
            Self::v21 => "v21",
            Self::v22 => "v22",
            Self::v23 => "v23",
            Self::v24 => "v24",
            Self::v25 => "v25",
            Self::v26 => "v26",
            Self::v27 => "v27",
            Self::v28 => "v28",
            Self::v29 => "v29",
            Self::v30 => "v30",
            Self::v31 => "v31",
            Self::a2 => "a2",
            Self::a3 => "a3",
            Self::a4 => "a4",
            Self::a5 => "a5",
            Self::a6 => "a6",
            Self::a7 => "a7",
            Self::a8 => "a8",
            Self::a9 => "a9",
            Self::a10 => "a10",
            Self::a11 => "a11",
            Self::a12 => "a12",
            Self::a13 => "a13",
            Self::a14 => "a14",
            Self::a15 => "a15",
        }
    }
    pub fn reg_class(self) -> S390xInlineAsmRegClass {
        match self {
            Self::r0 => S390xInlineAsmRegClass::reg,
            Self::r1 => S390xInlineAsmRegClass::reg,
            Self::r2 => S390xInlineAsmRegClass::reg,
            Self::r3 => S390xInlineAsmRegClass::reg,
            Self::r4 => S390xInlineAsmRegClass::reg,
            Self::r5 => S390xInlineAsmRegClass::reg,
            Self::r6 => S390xInlineAsmRegClass::reg,
            Self::r7 => S390xInlineAsmRegClass::reg,
            Self::r8 => S390xInlineAsmRegClass::reg,
            Self::r9 => S390xInlineAsmRegClass::reg,
            Self::r10 => S390xInlineAsmRegClass::reg,
            Self::r12 => S390xInlineAsmRegClass::reg,
            Self::r13 => S390xInlineAsmRegClass::reg,
            Self::r14 => S390xInlineAsmRegClass::reg,
            Self::f0 => S390xInlineAsmRegClass::freg,
            Self::f1 => S390xInlineAsmRegClass::freg,
            Self::f2 => S390xInlineAsmRegClass::freg,
            Self::f3 => S390xInlineAsmRegClass::freg,
            Self::f4 => S390xInlineAsmRegClass::freg,
            Self::f5 => S390xInlineAsmRegClass::freg,
            Self::f6 => S390xInlineAsmRegClass::freg,
            Self::f7 => S390xInlineAsmRegClass::freg,
            Self::f8 => S390xInlineAsmRegClass::freg,
            Self::f9 => S390xInlineAsmRegClass::freg,
            Self::f10 => S390xInlineAsmRegClass::freg,
            Self::f11 => S390xInlineAsmRegClass::freg,
            Self::f12 => S390xInlineAsmRegClass::freg,
            Self::f13 => S390xInlineAsmRegClass::freg,
            Self::f14 => S390xInlineAsmRegClass::freg,
            Self::f15 => S390xInlineAsmRegClass::freg,
            Self::v0 => S390xInlineAsmRegClass::vreg,
            Self::v1 => S390xInlineAsmRegClass::vreg,
            Self::v2 => S390xInlineAsmRegClass::vreg,
            Self::v3 => S390xInlineAsmRegClass::vreg,
            Self::v4 => S390xInlineAsmRegClass::vreg,
            Self::v5 => S390xInlineAsmRegClass::vreg,
            Self::v6 => S390xInlineAsmRegClass::vreg,
            Self::v7 => S390xInlineAsmRegClass::vreg,
            Self::v8 => S390xInlineAsmRegClass::vreg,
            Self::v9 => S390xInlineAsmRegClass::vreg,
            Self::v10 => S390xInlineAsmRegClass::vreg,
            Self::v11 => S390xInlineAsmRegClass::vreg,
            Self::v12 => S390xInlineAsmRegClass::vreg,
            Self::v13 => S390xInlineAsmRegClass::vreg,
            Self::v14 => S390xInlineAsmRegClass::vreg,
            Self::v15 => S390xInlineAsmRegClass::vreg,
            Self::v16 => S390xInlineAsmRegClass::vreg,
            Self::v17 => S390xInlineAsmRegClass::vreg,
            Self::v18 => S390xInlineAsmRegClass::vreg,
            Self::v19 => S390xInlineAsmRegClass::vreg,
            Self::v20 => S390xInlineAsmRegClass::vreg,
            Self::v21 => S390xInlineAsmRegClass::vreg,
            Self::v22 => S390xInlineAsmRegClass::vreg,
            Self::v23 => S390xInlineAsmRegClass::vreg,
            Self::v24 => S390xInlineAsmRegClass::vreg,
            Self::v25 => S390xInlineAsmRegClass::vreg,
            Self::v26 => S390xInlineAsmRegClass::vreg,
            Self::v27 => S390xInlineAsmRegClass::vreg,
            Self::v28 => S390xInlineAsmRegClass::vreg,
            Self::v29 => S390xInlineAsmRegClass::vreg,
            Self::v30 => S390xInlineAsmRegClass::vreg,
            Self::v31 => S390xInlineAsmRegClass::vreg,
            Self::a2 => S390xInlineAsmRegClass::areg,
            Self::a3 => S390xInlineAsmRegClass::areg,
            Self::a4 => S390xInlineAsmRegClass::areg,
            Self::a5 => S390xInlineAsmRegClass::areg,
            Self::a6 => S390xInlineAsmRegClass::areg,
            Self::a7 => S390xInlineAsmRegClass::areg,
            Self::a8 => S390xInlineAsmRegClass::areg,
            Self::a9 => S390xInlineAsmRegClass::areg,
            Self::a10 => S390xInlineAsmRegClass::areg,
            Self::a11 => S390xInlineAsmRegClass::areg,
            Self::a12 => S390xInlineAsmRegClass::areg,
            Self::a13 => S390xInlineAsmRegClass::areg,
            Self::a14 => S390xInlineAsmRegClass::areg,
            Self::a15 => S390xInlineAsmRegClass::areg,
        }
    }
    pub fn parse(name: &str) -> Result<Self, &'static str> {
        match name {
            "r0" => Ok(Self::r0),
            "r1" => Ok(Self::r1),
            "r2" => Ok(Self::r2),
            "r3" => Ok(Self::r3),
            "r4" => Ok(Self::r4),
            "r5" => Ok(Self::r5),
            "r6" => Ok(Self::r6),
            "r7" => Ok(Self::r7),
            "r8" => Ok(Self::r8),
            "r9" => Ok(Self::r9),
            "r10" => Ok(Self::r10),
            "r12" => Ok(Self::r12),
            "r13" => Ok(Self::r13),
            "r14" => Ok(Self::r14),
            "f0" => Ok(Self::f0),
            "f1" => Ok(Self::f1),
            "f2" => Ok(Self::f2),
            "f3" => Ok(Self::f3),
            "f4" => Ok(Self::f4),
            "f5" => Ok(Self::f5),
            "f6" => Ok(Self::f6),
            "f7" => Ok(Self::f7),
            "f8" => Ok(Self::f8),
            "f9" => Ok(Self::f9),
            "f10" => Ok(Self::f10),
            "f11" => Ok(Self::f11),
            "f12" => Ok(Self::f12),
            "f13" => Ok(Self::f13),
            "f14" => Ok(Self::f14),
            "f15" => Ok(Self::f15),
            "v0" => Ok(Self::v0),
            "v1" => Ok(Self::v1),
            "v2" => Ok(Self::v2),
            "v3" => Ok(Self::v3),
            "v4" => Ok(Self::v4),
            "v5" => Ok(Self::v5),
            "v6" => Ok(Self::v6),
            "v7" => Ok(Self::v7),
            "v8" => Ok(Self::v8),
            "v9" => Ok(Self::v9),
            "v10" => Ok(Self::v10),
            "v11" => Ok(Self::v11),
            "v12" => Ok(Self::v12),
            "v13" => Ok(Self::v13),
            "v14" => Ok(Self::v14),
            "v15" => Ok(Self::v15),
            "v16" => Ok(Self::v16),
            "v17" => Ok(Self::v17),
            "v18" => Ok(Self::v18),
            "v19" => Ok(Self::v19),
            "v20" => Ok(Self::v20),
            "v21" => Ok(Self::v21),
            "v22" => Ok(Self::v22),
            "v23" => Ok(Self::v23),
            "v24" => Ok(Self::v24),
            "v25" => Ok(Self::v25),
            "v26" => Ok(Self::v26),
            "v27" => Ok(Self::v27),
            "v28" => Ok(Self::v28),
            "v29" => Ok(Self::v29),
            "v30" => Ok(Self::v30),
            "v31" => Ok(Self::v31),
            "a2" => Ok(Self::a2),
            "a3" => Ok(Self::a3),
            "a4" => Ok(Self::a4),
            "a5" => Ok(Self::a5),
            "a6" => Ok(Self::a6),
            "a7" => Ok(Self::a7),
            "a8" => Ok(Self::a8),
            "a9" => Ok(Self::a9),
            "a10" => Ok(Self::a10),
            "a11" => Ok(Self::a11),
            "a12" => Ok(Self::a12),
            "a13" => Ok(Self::a13),
            "a14" => Ok(Self::a14),
            "a15" => Ok(Self::a15),
            "r11" =>
                Err("The frame pointer cannot be used as an operand for inline asm"),
            "r15" =>
                Err("The stack pointer cannot be used as an operand for inline asm"),
            "c0" | "c1" | "c2" | "c3" | "c4" | "c5" | "c6" | "c7" | "c8" |
                "c9" | "c10" | "c11" | "c12" | "c13" | "c14" | "c15" =>
                Err("control registers are reserved by the kernel and cannot be used as operands for inline asm"),
            "a0" | "a1" =>
                Err("a0 and a1 are reserved for system use and cannot be used as operands for inline asm"),
            _ => Err("unknown register"),
        }
    }
    pub fn validate(self, _arch: super::InlineAsmArch,
        _reloc_model: crate::spec::RelocModel,
        _target_features: &rustc_data_structures::fx::FxIndexSet<Symbol>,
        _target: &crate::spec::Target, _is_clobber: bool)
        -> Result<(), &'static str> {
        match self {
            Self::r0 => { Ok(()) }
            Self::r1 => { Ok(()) }
            Self::r2 => { Ok(()) }
            Self::r3 => { Ok(()) }
            Self::r4 => { Ok(()) }
            Self::r5 => { Ok(()) }
            Self::r6 => { Ok(()) }
            Self::r7 => { Ok(()) }
            Self::r8 => { Ok(()) }
            Self::r9 => { Ok(()) }
            Self::r10 => { Ok(()) }
            Self::r12 => { Ok(()) }
            Self::r13 => { Ok(()) }
            Self::r14 => { Ok(()) }
            Self::f0 => { Ok(()) }
            Self::f1 => { Ok(()) }
            Self::f2 => { Ok(()) }
            Self::f3 => { Ok(()) }
            Self::f4 => { Ok(()) }
            Self::f5 => { Ok(()) }
            Self::f6 => { Ok(()) }
            Self::f7 => { Ok(()) }
            Self::f8 => { Ok(()) }
            Self::f9 => { Ok(()) }
            Self::f10 => { Ok(()) }
            Self::f11 => { Ok(()) }
            Self::f12 => { Ok(()) }
            Self::f13 => { Ok(()) }
            Self::f14 => { Ok(()) }
            Self::f15 => { Ok(()) }
            Self::v0 => { Ok(()) }
            Self::v1 => { Ok(()) }
            Self::v2 => { Ok(()) }
            Self::v3 => { Ok(()) }
            Self::v4 => { Ok(()) }
            Self::v5 => { Ok(()) }
            Self::v6 => { Ok(()) }
            Self::v7 => { Ok(()) }
            Self::v8 => { Ok(()) }
            Self::v9 => { Ok(()) }
            Self::v10 => { Ok(()) }
            Self::v11 => { Ok(()) }
            Self::v12 => { Ok(()) }
            Self::v13 => { Ok(()) }
            Self::v14 => { Ok(()) }
            Self::v15 => { Ok(()) }
            Self::v16 => { Ok(()) }
            Self::v17 => { Ok(()) }
            Self::v18 => { Ok(()) }
            Self::v19 => { Ok(()) }
            Self::v20 => { Ok(()) }
            Self::v21 => { Ok(()) }
            Self::v22 => { Ok(()) }
            Self::v23 => { Ok(()) }
            Self::v24 => { Ok(()) }
            Self::v25 => { Ok(()) }
            Self::v26 => { Ok(()) }
            Self::v27 => { Ok(()) }
            Self::v28 => { Ok(()) }
            Self::v29 => { Ok(()) }
            Self::v30 => { Ok(()) }
            Self::v31 => { Ok(()) }
            Self::a2 => { Ok(()) }
            Self::a3 => { Ok(()) }
            Self::a4 => { Ok(()) }
            Self::a5 => { Ok(()) }
            Self::a6 => { Ok(()) }
            Self::a7 => { Ok(()) }
            Self::a8 => { Ok(()) }
            Self::a9 => { Ok(()) }
            Self::a10 => { Ok(()) }
            Self::a11 => { Ok(()) }
            Self::a12 => { Ok(()) }
            Self::a13 => { Ok(()) }
            Self::a14 => { Ok(()) }
            Self::a15 => { Ok(()) }
        }
    }
}
pub(super) fn fill_reg_map(_arch: super::InlineAsmArch,
    _reloc_model: crate::spec::RelocModel,
    _target_features: &rustc_data_structures::fx::FxIndexSet<Symbol>,
    _target: &crate::spec::Target,
    _map:
        &mut rustc_data_structures::fx::FxHashMap<super::InlineAsmRegClass,
        rustc_data_structures::fx::FxIndexSet<super::InlineAsmReg>>) {
    #[allow(unused_imports)]
    use super::{InlineAsmReg, InlineAsmRegClass};
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::r0));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::r1));
        }
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::reg_addr))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::r1));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::r2));
        }
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::reg_addr))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::r2));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::r3));
        }
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::reg_addr))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::r3));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::r4));
        }
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::reg_addr))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::r4));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::r5));
        }
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::reg_addr))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::r5));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::r6));
        }
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::reg_addr))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::r6));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::r7));
        }
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::reg_addr))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::r7));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::r8));
        }
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::reg_addr))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::r8));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::r9));
        }
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::reg_addr))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::r9));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::r10));
        }
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::reg_addr))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::r10));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::r12));
        }
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::reg_addr))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::r12));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::r13));
        }
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::reg_addr))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::r13));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::reg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::r14));
        }
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::reg_addr))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::r14));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::f0));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::f1));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::f2));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::f3));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::f4));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::f5));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::f6));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::f7));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::f8));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::f9));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::f10));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::f11));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::f12));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::f13));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::f14));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::freg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::f15));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::vreg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::v0));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::vreg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::v1));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::vreg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::v2));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::vreg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::v3));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::vreg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::v4));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::vreg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::v5));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::vreg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::v6));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::vreg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::v7));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::vreg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::v8));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::vreg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::v9));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::vreg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::v10));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::vreg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::v11));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::vreg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::v12));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::vreg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::v13));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::vreg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::v14));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::vreg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::v15));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::vreg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::v16));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::vreg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::v17));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::vreg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::v18));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::vreg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::v19));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::vreg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::v20));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::vreg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::v21));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::vreg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::v22));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::vreg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::v23));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::vreg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::v24));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::vreg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::v25));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::vreg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::v26));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::vreg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::v27));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::vreg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::v28));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::vreg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::v29));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::vreg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::v30));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::vreg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::v31));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::areg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::a2));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::areg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::a3));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::areg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::a4));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::areg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::a5));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::areg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::a6));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::areg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::a7));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::areg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::a8));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::areg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::a9));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::areg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::a10));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::areg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::a11));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::areg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::a12));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::areg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::a13));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::areg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::a14));
        }
    }
    if true {
        if let Some(set) =
                _map.get_mut(&InlineAsmRegClass::S390x(S390xInlineAsmRegClass::areg))
            {
            set.insert(InlineAsmReg::S390x(S390xInlineAsmReg::a15));
        }
    }
}def_regs! {
63    S390x S390xInlineAsmReg S390xInlineAsmRegClass {
64        r0: reg = ["r0"],
65        r1: reg, reg_addr = ["r1"],
66        r2: reg, reg_addr = ["r2"],
67        r3: reg, reg_addr = ["r3"],
68        r4: reg, reg_addr = ["r4"],
69        r5: reg, reg_addr = ["r5"],
70        r6: reg, reg_addr = ["r6"],
71        r7: reg, reg_addr = ["r7"],
72        r8: reg, reg_addr = ["r8"],
73        r9: reg, reg_addr = ["r9"],
74        r10: reg, reg_addr = ["r10"],
75        r12: reg, reg_addr = ["r12"],
76        r13: reg, reg_addr = ["r13"],
77        r14: reg, reg_addr = ["r14"],
78        f0: freg = ["f0"],
79        f1: freg = ["f1"],
80        f2: freg = ["f2"],
81        f3: freg = ["f3"],
82        f4: freg = ["f4"],
83        f5: freg = ["f5"],
84        f6: freg = ["f6"],
85        f7: freg = ["f7"],
86        f8: freg = ["f8"],
87        f9: freg = ["f9"],
88        f10: freg = ["f10"],
89        f11: freg = ["f11"],
90        f12: freg = ["f12"],
91        f13: freg = ["f13"],
92        f14: freg = ["f14"],
93        f15: freg = ["f15"],
94        v0: vreg = ["v0"],
95        v1: vreg = ["v1"],
96        v2: vreg = ["v2"],
97        v3: vreg = ["v3"],
98        v4: vreg = ["v4"],
99        v5: vreg = ["v5"],
100        v6: vreg = ["v6"],
101        v7: vreg = ["v7"],
102        v8: vreg = ["v8"],
103        v9: vreg = ["v9"],
104        v10: vreg = ["v10"],
105        v11: vreg = ["v11"],
106        v12: vreg = ["v12"],
107        v13: vreg = ["v13"],
108        v14: vreg = ["v14"],
109        v15: vreg = ["v15"],
110        v16: vreg = ["v16"],
111        v17: vreg = ["v17"],
112        v18: vreg = ["v18"],
113        v19: vreg = ["v19"],
114        v20: vreg = ["v20"],
115        v21: vreg = ["v21"],
116        v22: vreg = ["v22"],
117        v23: vreg = ["v23"],
118        v24: vreg = ["v24"],
119        v25: vreg = ["v25"],
120        v26: vreg = ["v26"],
121        v27: vreg = ["v27"],
122        v28: vreg = ["v28"],
123        v29: vreg = ["v29"],
124        v30: vreg = ["v30"],
125        v31: vreg = ["v31"],
126        a2: areg = ["a2"],
127        a3: areg = ["a3"],
128        a4: areg = ["a4"],
129        a5: areg = ["a5"],
130        a6: areg = ["a6"],
131        a7: areg = ["a7"],
132        a8: areg = ["a8"],
133        a9: areg = ["a9"],
134        a10: areg = ["a10"],
135        a11: areg = ["a11"],
136        a12: areg = ["a12"],
137        a13: areg = ["a13"],
138        a14: areg = ["a14"],
139        a15: areg = ["a15"],
140        #error = ["r11"] =>
141            "The frame pointer cannot be used as an operand for inline asm",
142        #error = ["r15"] =>
143            "The stack pointer cannot be used as an operand for inline asm",
144        #error = [
145            "c0", "c1", "c2", "c3",
146            "c4", "c5", "c6", "c7",
147            "c8", "c9", "c10", "c11",
148            "c12", "c13", "c14", "c15"
149        ] =>
150            "control registers are reserved by the kernel and cannot be used as operands for inline asm",
151        #error = ["a0", "a1"] =>
152            "a0 and a1 are reserved for system use and cannot be used as operands for inline asm",
153    }
154}
155
156impl S390xInlineAsmReg {
157    pub fn emit(
158        self,
159        out: &mut dyn fmt::Write,
160        _arch: InlineAsmArch,
161        _modifier: Option<char>,
162    ) -> fmt::Result {
163        out.write_fmt(format_args!("%{0}", self.name()))write!(out, "%{}", self.name())
164    }
165
166    pub fn overlapping_regs(self, mut cb: impl FnMut(S390xInlineAsmReg)) {
167        macro_rules! reg_conflicts {
168            (
169                $(
170                    $full:ident : $($field:ident)*
171                ),*;
172            ) => {
173                match self {
174                    $(
175                        Self::$full => {
176                            cb(Self::$full);
177                            $(cb(Self::$field);)*
178                        }
179                        $(Self::$field)|* => {
180                            cb(Self::$full);
181                            cb(self);
182                        }
183                    )*
184                    r => cb(r),
185                }
186            };
187        }
188
189        // The left halves of v0-v15 are aliased to f0-f15.
190        match self {
    Self::v0 => { cb(Self::v0); cb(Self::f0); }
    Self::f0 => { cb(Self::v0); cb(self); }
    Self::v1 => { cb(Self::v1); cb(Self::f1); }
    Self::f1 => { cb(Self::v1); cb(self); }
    Self::v2 => { cb(Self::v2); cb(Self::f2); }
    Self::f2 => { cb(Self::v2); cb(self); }
    Self::v3 => { cb(Self::v3); cb(Self::f3); }
    Self::f3 => { cb(Self::v3); cb(self); }
    Self::v4 => { cb(Self::v4); cb(Self::f4); }
    Self::f4 => { cb(Self::v4); cb(self); }
    Self::v5 => { cb(Self::v5); cb(Self::f5); }
    Self::f5 => { cb(Self::v5); cb(self); }
    Self::v6 => { cb(Self::v6); cb(Self::f6); }
    Self::f6 => { cb(Self::v6); cb(self); }
    Self::v7 => { cb(Self::v7); cb(Self::f7); }
    Self::f7 => { cb(Self::v7); cb(self); }
    Self::v8 => { cb(Self::v8); cb(Self::f8); }
    Self::f8 => { cb(Self::v8); cb(self); }
    Self::v9 => { cb(Self::v9); cb(Self::f9); }
    Self::f9 => { cb(Self::v9); cb(self); }
    Self::v10 => { cb(Self::v10); cb(Self::f10); }
    Self::f10 => { cb(Self::v10); cb(self); }
    Self::v11 => { cb(Self::v11); cb(Self::f11); }
    Self::f11 => { cb(Self::v11); cb(self); }
    Self::v12 => { cb(Self::v12); cb(Self::f12); }
    Self::f12 => { cb(Self::v12); cb(self); }
    Self::v13 => { cb(Self::v13); cb(Self::f13); }
    Self::f13 => { cb(Self::v13); cb(self); }
    Self::v14 => { cb(Self::v14); cb(Self::f14); }
    Self::f14 => { cb(Self::v14); cb(self); }
    Self::v15 => { cb(Self::v15); cb(Self::f15); }
    Self::f15 => { cb(Self::v15); cb(self); }
    r => cb(r),
}reg_conflicts! {
191            v0 : f0,
192            v1 : f1,
193            v2 : f2,
194            v3 : f3,
195            v4 : f4,
196            v5 : f5,
197            v6 : f6,
198            v7 : f7,
199            v8 : f8,
200            v9 : f9,
201            v10 : f10,
202            v11 : f11,
203            v12 : f12,
204            v13 : f13,
205            v14 : f14,
206            v15 : f15;
207        }
208    }
209}