Module core::arch::aarch64

1.59.0 · source · []
Available on AArch64 only.
Expand description

Platform-specific intrinsics for the aarch64 platform.

See the module documentation for more details.

Structs

APSRExperimental

Application Program Status Register

SYExperimental

Full system is the required shareability domain, reads and writes are the required access types

float32x2_tExperimental

ARM-specific 64-bit wide vector of two packed f32.

float32x2x2_tExperimental

ARM-specific type containing two float32x2_t vectors.

float32x2x3_tExperimental

ARM-specific type containing three float32x2_t vectors.

float32x2x4_tExperimental

ARM-specific type containing four float32x2_t vectors.

float32x4_tExperimental

ARM-specific 128-bit wide vector of four packed f32.

float32x4x2_tExperimental

ARM-specific type containing two float32x4_t vectors.

float32x4x3_tExperimental

ARM-specific type containing three float32x4_t vectors.

float32x4x4_tExperimental

ARM-specific type containing four float32x4_t vectors.

int8x8_tExperimental

ARM-specific 64-bit wide vector of eight packed i8.

int8x8x2_tExperimental

ARM-specific type containing two int8x8_t vectors.

int8x8x3_tExperimental

ARM-specific type containing three int8x8_t vectors.

int8x8x4_tExperimental

ARM-specific type containing four int8x8_t vectors.

int8x16_tExperimental

ARM-specific 128-bit wide vector of sixteen packed i8.

int8x16x2_tExperimental

ARM-specific type containing two int8x16_t vectors.

int8x16x3_tExperimental

ARM-specific type containing three int8x16_t vectors.

int8x16x4_tExperimental

ARM-specific type containing four int8x16_t vectors.

int16x4_tExperimental

ARM-specific 64-bit wide vector of four packed i16.

int16x4x2_tExperimental

ARM-specific type containing two int16x4_t vectors.

int16x4x3_tExperimental

ARM-specific type containing three int16x4_t vectors.

int16x4x4_tExperimental

ARM-specific type containing four int16x4_t vectors.

int16x8_tExperimental

ARM-specific 128-bit wide vector of eight packed i16.

int16x8x2_tExperimental

ARM-specific type containing two int16x8_t vectors.

int16x8x3_tExperimental

ARM-specific type containing three int16x8_t vectors.

int16x8x4_tExperimental

ARM-specific type containing four int16x8_t vectors.

int32x2_tExperimental

ARM-specific 64-bit wide vector of two packed i32.

int32x2x2_tExperimental

ARM-specific type containing two int32x2_t vectors.

int32x2x3_tExperimental

ARM-specific type containing three int32x2_t vectors.

int32x2x4_tExperimental

ARM-specific type containing four int32x2_t vectors.

int32x4_tExperimental

ARM-specific 128-bit wide vector of four packed i32.

int32x4x2_tExperimental

ARM-specific type containing two int32x4_t vectors.

int32x4x3_tExperimental

ARM-specific type containing three int32x4_t vectors.

int32x4x4_tExperimental

ARM-specific type containing four int32x4_t vectors.

int64x1_tExperimental

ARM-specific 64-bit wide vector of one packed i64.

int64x1x2_tExperimental

ARM-specific type containing four int64x1_t vectors.

int64x1x3_tExperimental

ARM-specific type containing four int64x1_t vectors.

int64x1x4_tExperimental

ARM-specific type containing four int64x1_t vectors.

int64x2_tExperimental

ARM-specific 128-bit wide vector of two packed i64.

int64x2x2_tExperimental

ARM-specific type containing four int64x2_t vectors.

int64x2x3_tExperimental

ARM-specific type containing four int64x2_t vectors.

int64x2x4_tExperimental

ARM-specific type containing four int64x2_t vectors.

poly8x8_tExperimental

ARM-specific 64-bit wide polynomial vector of eight packed p8.

poly8x8x2_tExperimental

ARM-specific type containing two poly8x8_t vectors.

poly8x8x3_tExperimental

ARM-specific type containing three poly8x8_t vectors.

poly8x8x4_tExperimental

ARM-specific type containing four poly8x8_t vectors.

poly8x16_tExperimental

ARM-specific 128-bit wide vector of sixteen packed p8.

poly8x16x2_tExperimental

ARM-specific type containing two poly8x16_t vectors.

poly8x16x3_tExperimental

ARM-specific type containing three poly8x16_t vectors.

poly8x16x4_tExperimental

ARM-specific type containing four poly8x16_t vectors.

poly16x4_tExperimental

ARM-specific 64-bit wide vector of four packed p16.

poly16x4x2_tExperimental

ARM-specific type containing two poly16x4_t vectors.

poly16x4x3_tExperimental

ARM-specific type containing three poly16x4_t vectors.

poly16x4x4_tExperimental

ARM-specific type containing four poly16x4_t vectors.

poly16x8_tExperimental

ARM-specific 128-bit wide vector of eight packed p16.

poly16x8x2_tExperimental

ARM-specific type containing two poly16x8_t vectors.

poly16x8x3_tExperimental

ARM-specific type containing three poly16x8_t vectors.

poly16x8x4_tExperimental

ARM-specific type containing four poly16x8_t vectors.

poly64x1_tExperimental

ARM-specific 64-bit wide vector of one packed p64.

poly64x1x2_tExperimental

ARM-specific type containing four poly64x1_t vectors.

poly64x1x3_tExperimental

ARM-specific type containing four poly64x1_t vectors.

poly64x1x4_tExperimental

ARM-specific type containing four poly64x1_t vectors.

poly64x2_tExperimental

ARM-specific 128-bit wide vector of two packed p64.

poly64x2x2_tExperimental

ARM-specific type containing four poly64x2_t vectors.

poly64x2x3_tExperimental

ARM-specific type containing four poly64x2_t vectors.

poly64x2x4_tExperimental

ARM-specific type containing four poly64x2_t vectors.

uint8x8_tExperimental

ARM-specific 64-bit wide vector of eight packed u8.

uint8x8x2_tExperimental

ARM-specific type containing two uint8x8_t vectors.

uint8x8x3_tExperimental

ARM-specific type containing three uint8x8_t vectors.

uint8x8x4_tExperimental

ARM-specific type containing four uint8x8_t vectors.

uint8x16_tExperimental

ARM-specific 128-bit wide vector of sixteen packed u8.

uint8x16x2_tExperimental

ARM-specific type containing two uint8x16_t vectors.

uint8x16x3_tExperimental

ARM-specific type containing three uint8x16_t vectors.

uint8x16x4_tExperimental

ARM-specific type containing four uint8x16_t vectors.

uint16x4_tExperimental

ARM-specific 64-bit wide vector of four packed u16.

uint16x4x2_tExperimental

ARM-specific type containing two uint16x4_t vectors.

uint16x4x3_tExperimental

ARM-specific type containing three uint16x4_t vectors.

uint16x4x4_tExperimental

ARM-specific type containing four uint16x4_t vectors.

uint16x8_tExperimental

ARM-specific 128-bit wide vector of eight packed u16.

uint16x8x2_tExperimental

ARM-specific type containing two uint16x8_t vectors.

uint16x8x3_tExperimental

ARM-specific type containing three uint16x8_t vectors.

uint16x8x4_tExperimental

ARM-specific type containing four uint16x8_t vectors.

uint32x2_tExperimental

ARM-specific 64-bit wide vector of two packed u32.

uint32x2x2_tExperimental

ARM-specific type containing two uint32x2_t vectors.

uint32x2x3_tExperimental

ARM-specific type containing three uint32x2_t vectors.

uint32x2x4_tExperimental

ARM-specific type containing four uint32x2_t vectors.

uint32x4_tExperimental

ARM-specific 128-bit wide vector of four packed u32.

uint32x4x2_tExperimental

ARM-specific type containing two uint32x4_t vectors.

uint32x4x3_tExperimental

ARM-specific type containing three uint32x4_t vectors.

uint32x4x4_tExperimental

ARM-specific type containing four uint32x4_t vectors.

uint64x1_tExperimental

ARM-specific 64-bit wide vector of one packed u64.

uint64x1x2_tExperimental

ARM-specific type containing four uint64x1_t vectors.

uint64x1x3_tExperimental

ARM-specific type containing four uint64x1_t vectors.

uint64x1x4_tExperimental

ARM-specific type containing four uint64x1_t vectors.

uint64x2_tExperimental

ARM-specific 128-bit wide vector of two packed u64.

uint64x2x2_tExperimental

ARM-specific type containing four uint64x2_t vectors.

uint64x2x3_tExperimental

ARM-specific type containing four uint64x2_t vectors.

uint64x2x4_tExperimental

ARM-specific type containing four uint64x2_t vectors.

ARM-specific 64-bit wide vector of one packed f64.

ARM-specific type containing two float64x1_t vectors.

ARM-specific type containing three float64x1_t vectors.

ARM-specific type containing four float64x1_t vectors.

ARM-specific 128-bit wide vector of two packed f64.

ARM-specific type containing two float64x2_t vectors.

ARM-specific type containing three float64x2_t vectors.

ARM-specific type containing four float64x2_t vectors.

Constants

See prefetch.

See prefetch.

See prefetch.

See prefetch.

_PREFETCH_READExperimental

See prefetch.

_PREFETCH_WRITEExperimental

See prefetch.

_TMFAILURE_CNCLExperimental

Transaction executed a TCANCEL instruction

_TMFAILURE_DBGExperimental

Transaction aborted due to a debug trap.

_TMFAILURE_ERRExperimental

Transaction aborted because a non-permissible operation was attempted

_TMFAILURE_IMPExperimental

Fallback error type for any other reason

_TMFAILURE_INTExperimental

Transaction failed from interrupt

_TMFAILURE_MEMExperimental

Transaction aborted because a conflict occurred

_TMFAILURE_NESTExperimental

Transaction aborted due to transactional nesting level was exceeded

_TMFAILURE_REASONExperimental

Extraction mask for failure reason

_TMFAILURE_RTRYExperimental

Transaction retry is possible.

_TMFAILURE_SIZEExperimental

Transaction aborted due to read or write set limit was exceeded

_TMFAILURE_TRIVIALExperimental

Indicates a TRIVIAL version of TM is available

_TMSTART_SUCCESSExperimental

Transaction successfully started.

Functions

__breakpointExperimental

Inserts a breakpoint instruction.

__crc32bExperimentalcrc

CRC32 single round checksum for bytes (8 bits).

__crc32cbExperimentalcrc

CRC32-C single round checksum for bytes (8 bits).

__crc32cdExperimentalcrc

CRC32-C single round checksum for quad words (64 bits).

__crc32chExperimentalcrc

CRC32-C single round checksum for half words (16 bits).

__crc32cwExperimentalcrc

CRC32-C single round checksum for words (32 bits).

__crc32dExperimentalcrc

CRC32 single round checksum for quad words (64 bits).

__crc32hExperimentalcrc

CRC32 single round checksum for half words (16 bits).

__crc32wExperimentalcrc

CRC32 single round checksum for words (32 bits).

__dmbExperimental

Generates a DMB (data memory barrier) instruction or equivalent CP15 instruction.

__dsbExperimental

Generates a DSB (data synchronization barrier) instruction or equivalent CP15 instruction.

__isbExperimental

Generates an ISB (instruction synchronization barrier) instruction or equivalent CP15 instruction.

__nopExperimental

Generates an unspecified no-op instruction.

__rsrExperimental

Reads a 32-bit system register

__rsrpExperimental

Reads a system register containing an address

__sevExperimental

Generates a SEV (send a global event) hint instruction.

__sevlExperimental

Generates a send a local event hint instruction.

__tcancelExperimentaltme

Cancels the current transaction and discards all state modifications that were performed transactionally.

__tcommitExperimentaltme

Commits the current transaction. For a nested transaction, the only effect is that the transactional nesting depth is decreased. For an outer transaction, the state modifications performed transactionally are committed to the architectural state.

__tstartExperimentaltme

Starts a new transaction. When the transaction starts successfully the return value is 0. If the transaction fails, all state modifications are discarded and a cause of the failure is encoded in the return value.

__ttestExperimentaltme

Tests if executing inside a transaction. If no transaction is currently executing, the return value is 0. Otherwise, this intrinsic returns the depth of the transaction.

__wfeExperimental

Generates a WFE (wait for event) hint instruction, or nothing.

__wfiExperimental

Generates a WFI (wait for interrupt) hint instruction, or nothing.

__wsrExperimental

Writes a 32-bit system register

__wsrpExperimental

Writes a system register containing an address

__yieldExperimental

Generates a YIELD hint instruction.

_cls_u32Experimental

Counts the leading most significant bits set.

_cls_u64Experimental

Counts the leading most significant bits set.

_clz_u64Experimental

Count Leading Zeros.

_prefetchExperimental

Fetch the cache line that contains address p using the given RW and LOCALITY.

_rbit_u64Experimental

Reverse the bit order.

_rev_u64Experimental

Reverse the order of the bytes.

brkExperimental

Generates the trap instruction BRK 1

vaba_s8Experimentalneon
vaba_s16Experimentalneon
vaba_s32Experimentalneon
vaba_u8Experimentalneon
vaba_u16Experimentalneon
vaba_u32Experimentalneon
vabal_s8Experimentalneon

Signed Absolute difference and Accumulate Long

vabal_s16Experimentalneon

Signed Absolute difference and Accumulate Long

vabal_s32Experimentalneon

Signed Absolute difference and Accumulate Long

vabal_u8Experimentalneon

Unsigned Absolute difference and Accumulate Long

vabal_u16Experimentalneon

Unsigned Absolute difference and Accumulate Long

vabal_u32Experimentalneon

Unsigned Absolute difference and Accumulate Long

vabaq_s8Experimentalneon
vabaq_s16Experimentalneon
vabaq_s32Experimentalneon
vabaq_u8Experimentalneon
vabaq_u16Experimentalneon
vabaq_u32Experimentalneon
vabd_f32Experimentalneon

Absolute difference between the arguments of Floating

vabd_s8Experimentalneon

Absolute difference between the arguments

vabd_s16Experimentalneon

Absolute difference between the arguments

vabd_s32Experimentalneon

Absolute difference between the arguments

vabd_u8Experimentalneon

Absolute difference between the arguments

vabd_u16Experimentalneon

Absolute difference between the arguments

vabd_u32Experimentalneon

Absolute difference between the arguments

vabdl_s8Experimentalneon

Signed Absolute difference Long

vabdl_s16Experimentalneon

Signed Absolute difference Long

vabdl_s32Experimentalneon

Signed Absolute difference Long

vabdl_u8Experimentalneon

Unsigned Absolute difference Long

vabdl_u16Experimentalneon

Unsigned Absolute difference Long

vabdl_u32Experimentalneon

Unsigned Absolute difference Long

vabdq_f32Experimentalneon

Absolute difference between the arguments of Floating

vabdq_s8Experimentalneon

Absolute difference between the arguments

vabdq_s16Experimentalneon

Absolute difference between the arguments

vabdq_s32Experimentalneon

Absolute difference between the arguments

vabdq_u8Experimentalneon

Absolute difference between the arguments

vabdq_u16Experimentalneon

Absolute difference between the arguments

vabdq_u32Experimentalneon

Absolute difference between the arguments

vabs_f32Experimentalneon

Floating-point absolute value

vabs_s8Experimentalneon

Absolute value (wrapping).

vabs_s16Experimentalneon

Absolute value (wrapping).

vabs_s32Experimentalneon

Absolute value (wrapping).

vabsq_f32Experimentalneon

Floating-point absolute value

vabsq_s8Experimentalneon

Absolute value (wrapping).

vabsq_s16Experimentalneon

Absolute value (wrapping).

vabsq_s32Experimentalneon

Absolute value (wrapping).

vadd_f32Experimentalneon

Vector add.

vadd_p8Experimentalneon

Bitwise exclusive OR

vadd_p16Experimentalneon

Bitwise exclusive OR

vadd_p64Experimentalneon

Bitwise exclusive OR

vadd_s8Experimentalneon

Vector add.

vadd_s16Experimentalneon

Vector add.

vadd_s32Experimentalneon

Vector add.

vadd_u8Experimentalneon

Vector add.

vadd_u16Experimentalneon

Vector add.

vadd_u32Experimentalneon

Vector add.

vaddhn_high_s16Experimentalneon

Add returning High Narrow (high half).

vaddhn_high_s32Experimentalneon

Add returning High Narrow (high half).

vaddhn_high_s64Experimentalneon

Add returning High Narrow (high half).

vaddhn_high_u16Experimentalneon

Add returning High Narrow (high half).

vaddhn_high_u32Experimentalneon

Add returning High Narrow (high half).

vaddhn_high_u64Experimentalneon

Add returning High Narrow (high half).

vaddhn_s16Experimentalneon

Add returning High Narrow.

vaddhn_s32Experimentalneon

Add returning High Narrow.

vaddhn_s64Experimentalneon

Add returning High Narrow.

vaddhn_u16Experimentalneon

Add returning High Narrow.

vaddhn_u32Experimentalneon

Add returning High Narrow.

vaddhn_u64Experimentalneon

Add returning High Narrow.

vaddl_high_s8Experimentalneon

Signed Add Long (vector, high half).

vaddl_high_s16Experimentalneon

Signed Add Long (vector, high half).

vaddl_high_s32Experimentalneon

Signed Add Long (vector, high half).

vaddl_high_u8Experimentalneon

Unsigned Add Long (vector, high half).

vaddl_high_u16Experimentalneon

Unsigned Add Long (vector, high half).

vaddl_high_u32Experimentalneon

Unsigned Add Long (vector, high half).

vaddl_s8Experimentalneon

Signed Add Long (vector).

vaddl_s16Experimentalneon

Signed Add Long (vector).

vaddl_s32Experimentalneon

Signed Add Long (vector).

vaddl_u8Experimentalneon

Unsigned Add Long (vector).

vaddl_u16Experimentalneon

Unsigned Add Long (vector).

vaddl_u32Experimentalneon

Unsigned Add Long (vector).

vaddq_f32Experimentalneon

Vector add.

vaddq_p8Experimentalneon

Bitwise exclusive OR

vaddq_p16Experimentalneon

Bitwise exclusive OR

vaddq_p64Experimentalneon

Bitwise exclusive OR

vaddq_p128Experimentalneon

Bitwise exclusive OR

vaddq_s8Experimentalneon

Vector add.

vaddq_s16Experimentalneon

Vector add.

vaddq_s32Experimentalneon

Vector add.

vaddq_s64Experimentalneon

Vector add.

vaddq_u8Experimentalneon

Vector add.

vaddq_u16Experimentalneon

Vector add.

vaddq_u32Experimentalneon

Vector add.

vaddq_u64Experimentalneon

Vector add.

vaddw_high_s8Experimentalneon

Signed Add Wide (high half).

vaddw_high_s16Experimentalneon

Signed Add Wide (high half).

vaddw_high_s32Experimentalneon

Signed Add Wide (high half).

vaddw_high_u8Experimentalneon

Unsigned Add Wide (high half).

vaddw_high_u16Experimentalneon

Unsigned Add Wide (high half).

vaddw_high_u32Experimentalneon

Unsigned Add Wide (high half).

vaddw_s8Experimentalneon

Signed Add Wide.

vaddw_s16Experimentalneon

Signed Add Wide.

vaddw_s32Experimentalneon

Signed Add Wide.

vaddw_u8Experimentalneon

Unsigned Add Wide.

vaddw_u16Experimentalneon

Unsigned Add Wide.

vaddw_u32Experimentalneon

Unsigned Add Wide.

vaesdq_u8Experimentalaes

AES single round decryption.

vaeseq_u8Experimentalaes

AES single round encryption.

vaesimcq_u8Experimentalaes

AES inverse mix columns.

vaesmcq_u8Experimentalaes

AES mix columns.

vand_s8Experimentalneon

Vector bitwise and

vand_s16Experimentalneon

Vector bitwise and

vand_s32Experimentalneon

Vector bitwise and

vand_s64Experimentalneon

Vector bitwise and

vand_u8Experimentalneon

Vector bitwise and

vand_u16Experimentalneon

Vector bitwise and

vand_u32Experimentalneon

Vector bitwise and

vand_u64Experimentalneon

Vector bitwise and

vandq_s8Experimentalneon

Vector bitwise and

vandq_s16Experimentalneon

Vector bitwise and

vandq_s32Experimentalneon

Vector bitwise and

vandq_s64Experimentalneon

Vector bitwise and

vandq_u8Experimentalneon

Vector bitwise and

vandq_u16Experimentalneon

Vector bitwise and

vandq_u32Experimentalneon

Vector bitwise and

vandq_u64Experimentalneon

Vector bitwise and

vbcaxq_s8Experimentalneon,sha3

Bit clear and exclusive OR

vbcaxq_s16Experimentalneon,sha3

Bit clear and exclusive OR

vbcaxq_s32Experimentalneon,sha3

Bit clear and exclusive OR

vbcaxq_s64Experimentalneon,sha3

Bit clear and exclusive OR

vbcaxq_u8Experimentalneon,sha3

Bit clear and exclusive OR

vbcaxq_u16Experimentalneon,sha3

Bit clear and exclusive OR

vbcaxq_u32Experimentalneon,sha3

Bit clear and exclusive OR

vbcaxq_u64Experimentalneon,sha3

Bit clear and exclusive OR

vbic_s8Experimentalneon

Vector bitwise bit clear

vbic_s16Experimentalneon

Vector bitwise bit clear

vbic_s32Experimentalneon

Vector bitwise bit clear

vbic_s64Experimentalneon

Vector bitwise bit clear

vbic_u8Experimentalneon

Vector bitwise bit clear

vbic_u16Experimentalneon

Vector bitwise bit clear

vbic_u32Experimentalneon

Vector bitwise bit clear

vbic_u64Experimentalneon

Vector bitwise bit clear

vbicq_s8Experimentalneon

Vector bitwise bit clear

vbicq_s16Experimentalneon

Vector bitwise bit clear

vbicq_s32Experimentalneon

Vector bitwise bit clear

vbicq_s64Experimentalneon

Vector bitwise bit clear

vbicq_u8Experimentalneon

Vector bitwise bit clear

vbicq_u16Experimentalneon

Vector bitwise bit clear

vbicq_u32Experimentalneon

Vector bitwise bit clear

vbicq_u64Experimentalneon

Vector bitwise bit clear

vbsl_f32Experimentalneon

Bitwise Select.

vbsl_p8Experimentalneon

Bitwise Select.

vbsl_p16Experimentalneon

Bitwise Select.

vbsl_s8Experimentalneon

Bitwise Select instructions. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register. Bitwise Select.

vbsl_s16Experimentalneon

Bitwise Select.

vbsl_s32Experimentalneon

Bitwise Select.

vbsl_s64Experimentalneon

Bitwise Select.

vbsl_u8Experimentalneon

Bitwise Select.

vbsl_u16Experimentalneon

Bitwise Select.

vbsl_u32Experimentalneon

Bitwise Select.

vbsl_u64Experimentalneon

Bitwise Select.

vbslq_f32Experimentalneon

Bitwise Select. (128-bit)

vbslq_p8Experimentalneon

Bitwise Select. (128-bit)

vbslq_p16Experimentalneon

Bitwise Select. (128-bit)

vbslq_s8Experimentalneon

Bitwise Select. (128-bit)

vbslq_s16Experimentalneon

Bitwise Select. (128-bit)

vbslq_s32Experimentalneon

Bitwise Select. (128-bit)

vbslq_s64Experimentalneon

Bitwise Select. (128-bit)

vbslq_u8Experimentalneon

Bitwise Select. (128-bit)

vbslq_u16Experimentalneon

Bitwise Select. (128-bit)

vbslq_u32Experimentalneon

Bitwise Select. (128-bit)

vbslq_u64Experimentalneon

Bitwise Select. (128-bit)

vcadd_rot90_f32Experimentalneon,fcma

Floating-point complex add

vcadd_rot270_f32Experimentalneon,fcma

Floating-point complex add

vcaddq_rot90_f32Experimentalneon,fcma

Floating-point complex add

vcaddq_rot90_f64Experimentalneon,fcma

Floating-point complex add

vcaddq_rot270_f32Experimentalneon,fcma

Floating-point complex add

vcaddq_rot270_f64Experimentalneon,fcma

Floating-point complex add

vcage_f32Experimentalneon

Floating-point absolute compare greater than or equal

vcageq_f32Experimentalneon

Floating-point absolute compare greater than or equal

vcagt_f32Experimentalneon

Floating-point absolute compare greater than

vcagtq_f32Experimentalneon

Floating-point absolute compare greater than

vcale_f32Experimentalneon

Floating-point absolute compare less than or equal

vcaleq_f32Experimentalneon

Floating-point absolute compare less than or equal

vcalt_f32Experimentalneon

Floating-point absolute compare less than

vcaltq_f32Experimentalneon

Floating-point absolute compare less than

vceq_f32Experimentalneon

Floating-point compare equal

vceq_p8Experimentalneon

Compare bitwise Equal (vector)

vceq_s8Experimentalneon

Compare bitwise Equal (vector)

vceq_s16Experimentalneon

Compare bitwise Equal (vector)

vceq_s32Experimentalneon

Compare bitwise Equal (vector)

vceq_u8Experimentalneon

Compare bitwise Equal (vector)

vceq_u16Experimentalneon

Compare bitwise Equal (vector)

vceq_u32Experimentalneon

Compare bitwise Equal (vector)

vceqq_f32Experimentalneon

Floating-point compare equal

vceqq_p8Experimentalneon

Compare bitwise Equal (vector)

vceqq_s8Experimentalneon

Compare bitwise Equal (vector)

vceqq_s16Experimentalneon

Compare bitwise Equal (vector)

vceqq_s32Experimentalneon

Compare bitwise Equal (vector)

vceqq_u8Experimentalneon

Compare bitwise Equal (vector)

vceqq_u16Experimentalneon

Compare bitwise Equal (vector)

vceqq_u32Experimentalneon

Compare bitwise Equal (vector)

vcge_f32Experimentalneon

Floating-point compare greater than or equal

vcge_s8Experimentalneon

Compare signed greater than or equal

vcge_s16Experimentalneon

Compare signed greater than or equal

vcge_s32Experimentalneon

Compare signed greater than or equal

vcge_u8Experimentalneon

Compare unsigned greater than or equal

vcge_u16Experimentalneon

Compare unsigned greater than or equal

vcge_u32Experimentalneon

Compare unsigned greater than or equal

vcgeq_f32Experimentalneon

Floating-point compare greater than or equal

vcgeq_s8Experimentalneon

Compare signed greater than or equal

vcgeq_s16Experimentalneon

Compare signed greater than or equal

vcgeq_s32Experimentalneon

Compare signed greater than or equal

vcgeq_u8Experimentalneon

Compare unsigned greater than or equal

vcgeq_u16Experimentalneon

Compare unsigned greater than or equal

vcgeq_u32Experimentalneon

Compare unsigned greater than or equal

vcgt_f32Experimentalneon

Floating-point compare greater than

vcgt_s8Experimentalneon

Compare signed greater than

vcgt_s16Experimentalneon

Compare signed greater than

vcgt_s32Experimentalneon

Compare signed greater than

vcgt_u8Experimentalneon

Compare unsigned highe

vcgt_u16Experimentalneon

Compare unsigned highe

vcgt_u32Experimentalneon

Compare unsigned highe

vcgtq_f32Experimentalneon

Floating-point compare greater than

vcgtq_s8Experimentalneon

Compare signed greater than

vcgtq_s16Experimentalneon

Compare signed greater than

vcgtq_s32Experimentalneon

Compare signed greater than

vcgtq_u8Experimentalneon

Compare unsigned highe

vcgtq_u16Experimentalneon

Compare unsigned highe

vcgtq_u32Experimentalneon

Compare unsigned highe

vcle_f32Experimentalneon

Floating-point compare less than or equal

vcle_s8Experimentalneon

Compare signed less than or equal

vcle_s16Experimentalneon

Compare signed less than or equal

vcle_s32Experimentalneon

Compare signed less than or equal

vcle_u8Experimentalneon

Compare unsigned less than or equal

vcle_u16Experimentalneon

Compare unsigned less than or equal

vcle_u32Experimentalneon

Compare unsigned less than or equal

vcleq_f32Experimentalneon

Floating-point compare less than or equal

vcleq_s8Experimentalneon

Compare signed less than or equal

vcleq_s16Experimentalneon

Compare signed less than or equal

vcleq_s32Experimentalneon

Compare signed less than or equal

vcleq_u8Experimentalneon

Compare unsigned less than or equal

vcleq_u16Experimentalneon

Compare unsigned less than or equal

vcleq_u32Experimentalneon

Compare unsigned less than or equal

vcls_s8Experimentalneon

Count leading sign bits

vcls_s16Experimentalneon

Count leading sign bits

vcls_s32Experimentalneon

Count leading sign bits

vcls_u8Experimentalneon

Count leading sign bits

vcls_u16Experimentalneon

Count leading sign bits

vcls_u32Experimentalneon

Count leading sign bits

vclsq_s8Experimentalneon

Count leading sign bits

vclsq_s16Experimentalneon

Count leading sign bits

vclsq_s32Experimentalneon

Count leading sign bits

vclsq_u8Experimentalneon

Count leading sign bits

vclsq_u16Experimentalneon

Count leading sign bits

vclsq_u32Experimentalneon

Count leading sign bits

vclt_f32Experimentalneon

Floating-point compare less than

vclt_s8Experimentalneon

Compare signed less than

vclt_s16Experimentalneon

Compare signed less than

vclt_s32Experimentalneon

Compare signed less than

vclt_u8Experimentalneon

Compare unsigned less than

vclt_u16Experimentalneon

Compare unsigned less than

vclt_u32Experimentalneon

Compare unsigned less than

vcltq_f32Experimentalneon

Floating-point compare less than

vcltq_s8Experimentalneon

Compare signed less than

vcltq_s16Experimentalneon

Compare signed less than

vcltq_s32Experimentalneon

Compare signed less than

vcltq_u8Experimentalneon

Compare unsigned less than

vcltq_u16Experimentalneon

Compare unsigned less than

vcltq_u32Experimentalneon

Compare unsigned less than

vclz_s8Experimentalneon

Count leading zero bits

vclz_s16Experimentalneon

Count leading zero bits

vclz_s32Experimentalneon

Count leading zero bits

vclz_u8Experimentalneon

Count leading zero bits

vclz_u16Experimentalneon

Count leading zero bits

vclz_u32Experimentalneon

Count leading zero bits

vclzq_s8Experimentalneon

Count leading zero bits

vclzq_s16Experimentalneon

Count leading zero bits

vclzq_s32Experimentalneon

Count leading zero bits

vclzq_u8Experimentalneon

Count leading zero bits

vclzq_u16Experimentalneon

Count leading zero bits

vclzq_u32Experimentalneon

Count leading zero bits

vcmla_f32Experimentalneon,fcma

Floating-point complex multiply accumulate

vcmla_lane_f32Experimentalneon,fcma

Floating-point complex multiply accumulate

vcmla_laneq_f32Experimentalneon,fcma

Floating-point complex multiply accumulate

vcmla_rot90_f32Experimentalneon,fcma

Floating-point complex multiply accumulate

vcmla_rot90_lane_f32Experimentalneon,fcma

Floating-point complex multiply accumulate

vcmla_rot90_laneq_f32Experimentalneon,fcma

Floating-point complex multiply accumulate

vcmla_rot180_f32Experimentalneon,fcma

Floating-point complex multiply accumulate

vcmla_rot180_lane_f32Experimentalneon,fcma

Floating-point complex multiply accumulate

vcmla_rot180_laneq_f32Experimentalneon,fcma

Floating-point complex multiply accumulate

vcmla_rot270_f32Experimentalneon,fcma

Floating-point complex multiply accumulate

vcmla_rot270_lane_f32Experimentalneon,fcma

Floating-point complex multiply accumulate

vcmla_rot270_laneq_f32Experimentalneon,fcma

Floating-point complex multiply accumulate

vcmlaq_f32Experimentalneon,fcma

Floating-point complex multiply accumulate

vcmlaq_f64Experimentalneon,fcma

Floating-point complex multiply accumulate

vcmlaq_lane_f32Experimentalneon,fcma

Floating-point complex multiply accumulate

vcmlaq_laneq_f32Experimentalneon,fcma

Floating-point complex multiply accumulate

vcmlaq_rot90_f32Experimentalneon,fcma

Floating-point complex multiply accumulate

vcmlaq_rot90_f64Experimentalneon,fcma

Floating-point complex multiply accumulate

vcmlaq_rot90_lane_f32Experimentalneon,fcma

Floating-point complex multiply accumulate

vcmlaq_rot90_laneq_f32Experimentalneon,fcma

Floating-point complex multiply accumulate

vcmlaq_rot180_f32Experimentalneon,fcma

Floating-point complex multiply accumulate

vcmlaq_rot180_f64Experimentalneon,fcma

Floating-point complex multiply accumulate

vcmlaq_rot180_lane_f32Experimentalneon,fcma

Floating-point complex multiply accumulate

vcmlaq_rot180_laneq_f32Experimentalneon,fcma

Floating-point complex multiply accumulate

vcmlaq_rot270_f32Experimentalneon,fcma

Floating-point complex multiply accumulate

vcmlaq_rot270_f64Experimentalneon,fcma

Floating-point complex multiply accumulate

vcmlaq_rot270_lane_f32Experimentalneon,fcma

Floating-point complex multiply accumulate

vcmlaq_rot270_laneq_f32Experimentalneon,fcma

Floating-point complex multiply accumulate

vcnt_p8Experimentalneon

Population count per byte.

vcnt_s8Experimentalneon

Population count per byte.

vcnt_u8Experimentalneon

Population count per byte.

vcntq_p8Experimentalneon

Population count per byte.

vcntq_s8Experimentalneon

Population count per byte.

vcntq_u8Experimentalneon

Population count per byte.

vcreate_f32Experimentalneon

Insert vector element from another vector element

vcreate_p8Experimentalneon

Insert vector element from another vector element

vcreate_p16Experimentalneon

Insert vector element from another vector element

vcreate_p64Experimentalneon,aes

Insert vector element from another vector element

vcreate_s8Experimentalneon

Insert vector element from another vector element

vcreate_s16Experimentalneon

Insert vector element from another vector element

vcreate_s32Experimentalneon

Insert vector element from another vector element

vcreate_s64Experimentalneon

Insert vector element from another vector element

vcreate_u8Experimentalneon

Insert vector element from another vector element

vcreate_u16Experimentalneon

Insert vector element from another vector element

vcreate_u32Experimentalneon

Insert vector element from another vector element

vcreate_u64Experimentalneon

Insert vector element from another vector element

vcvt_f32_s32Experimentalneon

Fixed-point convert to floating-point

vcvt_f32_u32Experimentalneon

Fixed-point convert to floating-point

vcvt_s32_f32Experimentalneon

Floating-point convert to signed fixed-point, rounding toward zero

vcvt_u32_f32Experimentalneon

Floating-point convert to unsigned fixed-point, rounding toward zero

vcvtq_f32_s32Experimentalneon

Fixed-point convert to floating-point

vcvtq_f32_u32Experimentalneon

Fixed-point convert to floating-point

vcvtq_s32_f32Experimentalneon

Floating-point convert to signed fixed-point, rounding toward zero

vcvtq_u32_f32Experimentalneon

Floating-point convert to unsigned fixed-point, rounding toward zero

vdot_lane_s32Experimentalneon,dotprod

Dot product arithmetic

vdot_lane_u32Experimentalneon,dotprod

Dot product arithmetic

vdot_laneq_s32Experimentalneon,dotprod

Dot product arithmetic

vdot_laneq_u32Experimentalneon,dotprod

Dot product arithmetic

vdot_s32Experimentalneon,dotprod

Dot product arithmetic

vdot_u32Experimentalneon,dotprod

Dot product arithmetic

vdotq_lane_s32Experimentalneon,dotprod

Dot product arithmetic

vdotq_lane_u32Experimentalneon,dotprod

Dot product arithmetic

vdotq_laneq_s32Experimentalneon,dotprod

Dot product arithmetic

vdotq_laneq_u32Experimentalneon,dotprod

Dot product arithmetic

vdotq_s32Experimentalneon,dotprod

Dot product arithmetic

vdotq_u32Experimentalneon,dotprod

Dot product arithmetic

vdup_lane_f32Experimentalneon

Set all vector lanes to the same value

vdup_lane_p8Experimentalneon

Set all vector lanes to the same value

vdup_lane_p16Experimentalneon

Set all vector lanes to the same value

vdup_lane_s8Experimentalneon

Set all vector lanes to the same value

vdup_lane_s16Experimentalneon

Set all vector lanes to the same value

vdup_lane_s32Experimentalneon

Set all vector lanes to the same value

vdup_lane_s64Experimentalneon

Set all vector lanes to the same value

vdup_lane_u8Experimentalneon

Set all vector lanes to the same value

vdup_lane_u16Experimentalneon

Set all vector lanes to the same value

vdup_lane_u32Experimentalneon

Set all vector lanes to the same value

vdup_lane_u64Experimentalneon

Set all vector lanes to the same value

vdup_laneq_f32Experimentalneon

Set all vector lanes to the same value

vdup_laneq_p8Experimentalneon

Set all vector lanes to the same value

vdup_laneq_p16Experimentalneon

Set all vector lanes to the same value

vdup_laneq_s8Experimentalneon

Set all vector lanes to the same value

vdup_laneq_s16Experimentalneon

Set all vector lanes to the same value

vdup_laneq_s32Experimentalneon

Set all vector lanes to the same value

vdup_laneq_s64Experimentalneon

Set all vector lanes to the same value

vdup_laneq_u8Experimentalneon

Set all vector lanes to the same value

vdup_laneq_u16Experimentalneon

Set all vector lanes to the same value

vdup_laneq_u32Experimentalneon

Set all vector lanes to the same value

vdup_laneq_u64Experimentalneon

Set all vector lanes to the same value

vdup_n_f32Experimentalneon

Duplicate vector element to vector or scalar

vdup_n_p8Experimentalneon

Duplicate vector element to vector or scalar

vdup_n_p16Experimentalneon

Duplicate vector element to vector or scalar

vdup_n_s8Experimentalneon

Duplicate vector element to vector or scalar

vdup_n_s16Experimentalneon

Duplicate vector element to vector or scalar

vdup_n_s32Experimentalneon

Duplicate vector element to vector or scalar

vdup_n_s64Experimentalneon

Duplicate vector element to vector or scalar

vdup_n_u8Experimentalneon

Duplicate vector element to vector or scalar

vdup_n_u16Experimentalneon

Duplicate vector element to vector or scalar

vdup_n_u32Experimentalneon

Duplicate vector element to vector or scalar

vdup_n_u64Experimentalneon

Duplicate vector element to vector or scalar

vdupq_lane_f32Experimentalneon

Set all vector lanes to the same value

vdupq_lane_p8Experimentalneon

Set all vector lanes to the same value

vdupq_lane_p16Experimentalneon

Set all vector lanes to the same value

vdupq_lane_s8Experimentalneon

Set all vector lanes to the same value

vdupq_lane_s16Experimentalneon

Set all vector lanes to the same value

vdupq_lane_s32Experimentalneon

Set all vector lanes to the same value

vdupq_lane_s64Experimentalneon

Set all vector lanes to the same value

vdupq_lane_u8Experimentalneon

Set all vector lanes to the same value

vdupq_lane_u16Experimentalneon

Set all vector lanes to the same value

vdupq_lane_u32Experimentalneon

Set all vector lanes to the same value

vdupq_lane_u64Experimentalneon

Set all vector lanes to the same value

vdupq_laneq_f32Experimentalneon

Set all vector lanes to the same value

vdupq_laneq_p8Experimentalneon

Set all vector lanes to the same value

vdupq_laneq_p16Experimentalneon

Set all vector lanes to the same value

vdupq_laneq_s8Experimentalneon

Set all vector lanes to the same value

vdupq_laneq_s16Experimentalneon

Set all vector lanes to the same value

vdupq_laneq_s32Experimentalneon

Set all vector lanes to the same value

vdupq_laneq_s64Experimentalneon

Set all vector lanes to the same value

vdupq_laneq_u8Experimentalneon

Set all vector lanes to the same value

vdupq_laneq_u16Experimentalneon

Set all vector lanes to the same value

vdupq_laneq_u32Experimentalneon

Set all vector lanes to the same value

vdupq_laneq_u64Experimentalneon

Set all vector lanes to the same value

vdupq_n_f32Experimentalneon

Duplicate vector element to vector or scalar

vdupq_n_p8Experimentalneon

Duplicate vector element to vector or scalar

vdupq_n_p16Experimentalneon

Duplicate vector element to vector or scalar

vdupq_n_s8Experimentalneon

Duplicate vector element to vector or scalar

vdupq_n_s16Experimentalneon

Duplicate vector element to vector or scalar

vdupq_n_s32Experimentalneon

Duplicate vector element to vector or scalar

vdupq_n_s64Experimentalneon

Duplicate vector element to vector or scalar

vdupq_n_u8Experimentalneon

Duplicate vector element to vector or scalar

vdupq_n_u16Experimentalneon

Duplicate vector element to vector or scalar

vdupq_n_u32Experimentalneon

Duplicate vector element to vector or scalar

vdupq_n_u64Experimentalneon

Duplicate vector element to vector or scalar

veor3q_s8Experimentalneon,sha3

Three-way exclusive OR

veor3q_s16Experimentalneon,sha3

Three-way exclusive OR

veor3q_s32Experimentalneon,sha3

Three-way exclusive OR

veor3q_s64Experimentalneon,sha3

Three-way exclusive OR

veor3q_u8Experimentalneon,sha3

Three-way exclusive OR

veor3q_u16Experimentalneon,sha3

Three-way exclusive OR

veor3q_u32Experimentalneon,sha3

Three-way exclusive OR

veor3q_u64Experimentalneon,sha3

Three-way exclusive OR

veor_s8Experimentalneon

Vector bitwise exclusive or (vector)

veor_s16Experimentalneon

Vector bitwise exclusive or (vector)

veor_s32Experimentalneon

Vector bitwise exclusive or (vector)

veor_s64Experimentalneon

Vector bitwise exclusive or (vector)

veor_u8Experimentalneon

Vector bitwise exclusive or (vector)

veor_u16Experimentalneon

Vector bitwise exclusive or (vector)

veor_u32Experimentalneon

Vector bitwise exclusive or (vector)

veor_u64Experimentalneon

Vector bitwise exclusive or (vector)

veorq_s8Experimentalneon

Vector bitwise exclusive or (vector)

veorq_s16Experimentalneon

Vector bitwise exclusive or (vector)

veorq_s32Experimentalneon

Vector bitwise exclusive or (vector)

veorq_s64Experimentalneon

Vector bitwise exclusive or (vector)

veorq_u8Experimentalneon

Vector bitwise exclusive or (vector)

veorq_u16Experimentalneon

Vector bitwise exclusive or (vector)

veorq_u32Experimentalneon

Vector bitwise exclusive or (vector)

veorq_u64Experimentalneon

Vector bitwise exclusive or (vector)

vext_f32Experimentalneon

Extract vector from pair of vectors

vext_p8Experimentalneon

Extract vector from pair of vectors

vext_p16Experimentalneon

Extract vector from pair of vectors

vext_s8Experimentalneon

Extract vector from pair of vectors

vext_s16Experimentalneon

Extract vector from pair of vectors

vext_s32Experimentalneon

Extract vector from pair of vectors

vext_s64Experimentalneon

Extract vector from pair of vectors

vext_u8Experimentalneon

Extract vector from pair of vectors

vext_u16Experimentalneon

Extract vector from pair of vectors

vext_u32Experimentalneon

Extract vector from pair of vectors

vext_u64Experimentalneon

Extract vector from pair of vectors

vextq_f32Experimentalneon

Extract vector from pair of vectors

vextq_p8Experimentalneon

Extract vector from pair of vectors

vextq_p16Experimentalneon

Extract vector from pair of vectors

vextq_s8Experimentalneon

Extract vector from pair of vectors

vextq_s16Experimentalneon

Extract vector from pair of vectors

vextq_s32Experimentalneon

Extract vector from pair of vectors

vextq_s64Experimentalneon

Extract vector from pair of vectors

vextq_u8Experimentalneon

Extract vector from pair of vectors

vextq_u16Experimentalneon

Extract vector from pair of vectors

vextq_u32Experimentalneon

Extract vector from pair of vectors

vextq_u64Experimentalneon

Extract vector from pair of vectors

vfma_f32Experimentalneon

Floating-point fused Multiply-Add to accumulator(vector)

vfma_n_f32Experimentalneon

Floating-point fused Multiply-Add to accumulator(vector)

vfmaq_f32Experimentalneon

Floating-point fused Multiply-Add to accumulator(vector)

vfmaq_n_f32Experimentalneon

Floating-point fused Multiply-Add to accumulator(vector)

vfms_f32Experimentalneon

Floating-point fused multiply-subtract from accumulator

vfms_n_f32Experimentalneon

Floating-point fused Multiply-subtract to accumulator(vector)

vfmsq_f32Experimentalneon

Floating-point fused multiply-subtract from accumulator

vfmsq_n_f32Experimentalneon

Floating-point fused Multiply-subtract to accumulator(vector)

vget_high_f32Experimentalneon

Duplicate vector element to vector or scalar

vget_high_p8Experimentalneon

Duplicate vector element to vector or scalar

vget_high_p16Experimentalneon

Duplicate vector element to vector or scalar

vget_high_s8Experimentalneon

Duplicate vector element to vector or scalar

vget_high_s16Experimentalneon

Duplicate vector element to vector or scalar

vget_high_s32Experimentalneon

Duplicate vector element to vector or scalar

vget_high_s64Experimentalneon

Duplicate vector element to vector or scalar

vget_high_u8Experimentalneon

Duplicate vector element to vector or scalar

vget_high_u16Experimentalneon

Duplicate vector element to vector or scalar

vget_high_u32Experimentalneon

Duplicate vector element to vector or scalar

vget_high_u64Experimentalneon

Duplicate vector element to vector or scalar

vget_lane_f32Experimentalneon

Duplicate vector element to vector or scalar

vget_lane_p8Experimentalneon

Move vector element to general-purpose register

vget_lane_p16Experimentalneon

Move vector element to general-purpose register

vget_lane_p64Experimentalneon

Move vector element to general-purpose register

vget_lane_s8Experimentalneon

Move vector element to general-purpose register

vget_lane_s16Experimentalneon

Move vector element to general-purpose register

vget_lane_s32Experimentalneon

Move vector element to general-purpose register

vget_lane_s64Experimentalneon

Move vector element to general-purpose register

vget_lane_u8Experimentalneon

Move vector element to general-purpose register

vget_lane_u16Experimentalneon

Move vector element to general-purpose register

vget_lane_u32Experimentalneon

Move vector element to general-purpose register

vget_lane_u64Experimentalneon

Move vector element to general-purpose register

vget_low_f32Experimentalneon

Duplicate vector element to vector or scalar

vget_low_p8Experimentalneon

Duplicate vector element to vector or scalar

vget_low_p16Experimentalneon

Duplicate vector element to vector or scalar

vget_low_s8Experimentalneon

Duplicate vector element to vector or scalar

vget_low_s16Experimentalneon

Duplicate vector element to vector or scalar

vget_low_s32Experimentalneon

Duplicate vector element to vector or scalar

vget_low_s64Experimentalneon

Duplicate vector element to vector or scalar

vget_low_u8Experimentalneon

Duplicate vector element to vector or scalar

vget_low_u16Experimentalneon

Duplicate vector element to vector or scalar

vget_low_u32Experimentalneon

Duplicate vector element to vector or scalar

vget_low_u64Experimentalneon

Duplicate vector element to vector or scalar

vgetq_lane_f32Experimentalneon

Duplicate vector element to vector or scalar

vgetq_lane_p8Experimentalneon

Move vector element to general-purpose register

vgetq_lane_p16Experimentalneon

Move vector element to general-purpose register

vgetq_lane_p64Experimentalneon

Move vector element to general-purpose register

vgetq_lane_s8Experimentalneon

Move vector element to general-purpose register

vgetq_lane_s16Experimentalneon

Move vector element to general-purpose register

vgetq_lane_s32Experimentalneon

Move vector element to general-purpose register

vgetq_lane_s64Experimentalneon

Move vector element to general-purpose register

vgetq_lane_u8Experimentalneon

Move vector element to general-purpose register

vgetq_lane_u16Experimentalneon

Move vector element to general-purpose register

vgetq_lane_u32Experimentalneon

Move vector element to general-purpose register

vgetq_lane_u64Experimentalneon

Move vector element to general-purpose register

vhadd_s8Experimentalneon

Halving add

vhadd_s16Experimentalneon

Halving add

vhadd_s32Experimentalneon

Halving add

vhadd_u8Experimentalneon

Halving add

vhadd_u16Experimentalneon

Halving add

vhadd_u32Experimentalneon

Halving add

vhaddq_s8Experimentalneon

Halving add

vhaddq_s16Experimentalneon

Halving add

vhaddq_s32Experimentalneon

Halving add

vhaddq_u8Experimentalneon

Halving add

vhaddq_u16Experimentalneon

Halving add

vhaddq_u32Experimentalneon

Halving add

vhsub_s8Experimentalneon

Signed halving subtract

vhsub_s16Experimentalneon

Signed halving subtract

vhsub_s32Experimentalneon

Signed halving subtract

vhsub_u8Experimentalneon

Signed halving subtract

vhsub_u16Experimentalneon

Signed halving subtract

vhsub_u32Experimentalneon

Signed halving subtract

vhsubq_s8Experimentalneon

Signed halving subtract

vhsubq_s16Experimentalneon

Signed halving subtract

vhsubq_s32Experimentalneon

Signed halving subtract

vhsubq_u8Experimentalneon

Signed halving subtract

vhsubq_u16Experimentalneon

Signed halving subtract

vhsubq_u32Experimentalneon

Signed halving subtract

vld1_dup_f32Experimentalneon

Load one single-element structure and Replicate to all lanes (of one register).

vld1_dup_p8Experimentalneon

Load one single-element structure and Replicate to all lanes (of one register).

vld1_dup_p16Experimentalneon

Load one single-element structure and Replicate to all lanes (of one register).

vld1_dup_p64Experimentalneon,aes

Load one single-element structure and Replicate to all lanes (of one register).

vld1_dup_s8Experimentalneon

Load one single-element structure and Replicate to all lanes (of one register).

vld1_dup_s16Experimentalneon

Load one single-element structure and Replicate to all lanes (of one register).

vld1_dup_s32Experimentalneon

Load one single-element structure and Replicate to all lanes (of one register).

vld1_dup_s64Experimentalneon

Load one single-element structure and Replicate to all lanes (of one register).

vld1_dup_u8Experimentalneon

Load one single-element structure and Replicate to all lanes (of one register).

vld1_dup_u16Experimentalneon

Load one single-element structure and Replicate to all lanes (of one register).

vld1_dup_u32Experimentalneon

Load one single-element structure and Replicate to all lanes (of one register).

vld1_dup_u64Experimentalneon

Load one single-element structure and Replicate to all lanes (of one register).

vld1_f32_x2Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1_f32_x3Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1_f32_x4Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1_lane_f32Experimentalneon

Load one single-element structure to one lane of one register.

vld1_lane_p8Experimentalneon

Load one single-element structure to one lane of one register.

vld1_lane_p16Experimentalneon

Load one single-element structure to one lane of one register.

vld1_lane_p64Experimentalneon,aes

Load one single-element structure to one lane of one register.

vld1_lane_s8Experimentalneon

Load one single-element structure to one lane of one register.

vld1_lane_s16Experimentalneon

Load one single-element structure to one lane of one register.

vld1_lane_s32Experimentalneon

Load one single-element structure to one lane of one register.

vld1_lane_s64Experimentalneon

Load one single-element structure to one lane of one register.

vld1_lane_u8Experimentalneon

Load one single-element structure to one lane of one register.

vld1_lane_u16Experimentalneon

Load one single-element structure to one lane of one register.

vld1_lane_u32Experimentalneon

Load one single-element structure to one lane of one register.

vld1_lane_u64Experimentalneon

Load one single-element structure to one lane of one register.

vld1_p8_x2Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1_p8_x3Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1_p8_x4Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1_p16_x2Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1_p16_x3Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1_p16_x4Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1_p64_x2Experimentalneon,aes

Load multiple single-element structures to one, two, three, or four registers

vld1_p64_x3Experimentalneon,aes

Load multiple single-element structures to one, two, three, or four registers

vld1_p64_x4Experimentalneon,aes

Load multiple single-element structures to one, two, three, or four registers

vld1_s8_x2Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1_s8_x3Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1_s8_x4Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1_s16_x2Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1_s16_x3Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1_s16_x4Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1_s32_x2Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1_s32_x3Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1_s32_x4Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1_s64_x2Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1_s64_x3Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1_s64_x4Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1_u8_x2Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1_u8_x3Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1_u8_x4Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1_u16_x2Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1_u16_x3Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1_u16_x4Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1_u32_x2Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1_u32_x3Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1_u32_x4Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1_u64_x2Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1_u64_x3Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1_u64_x4Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1q_dup_f32Experimentalneon

Load one single-element structure and Replicate to all lanes (of one register).

vld1q_dup_p8Experimentalneon

Load one single-element structure and Replicate to all lanes (of one register).

vld1q_dup_p16Experimentalneon

Load one single-element structure and Replicate to all lanes (of one register).

vld1q_dup_p64Experimentalneon,aes

Load one single-element structure and Replicate to all lanes (of one register).

vld1q_dup_s8Experimentalneon

Load one single-element structure and Replicate to all lanes (of one register).

vld1q_dup_s16Experimentalneon

Load one single-element structure and Replicate to all lanes (of one register).

vld1q_dup_s32Experimentalneon

Load one single-element structure and Replicate to all lanes (of one register).

vld1q_dup_s64Experimentalneon

Load one single-element structure and Replicate to all lanes (of one register).

vld1q_dup_u8Experimentalneon

Load one single-element structure and Replicate to all lanes (of one register).

vld1q_dup_u16Experimentalneon

Load one single-element structure and Replicate to all lanes (of one register).

vld1q_dup_u32Experimentalneon

Load one single-element structure and Replicate to all lanes (of one register).

vld1q_dup_u64Experimentalneon

Load one single-element structure and Replicate to all lanes (of one register).

vld1q_f32_x2Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1q_f32_x3Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1q_f32_x4Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1q_lane_f32Experimentalneon

Load one single-element structure to one lane of one register.

vld1q_lane_p8Experimentalneon

Load one single-element structure to one lane of one register.

vld1q_lane_p16Experimentalneon

Load one single-element structure to one lane of one register.

vld1q_lane_p64Experimentalneon,aes

Load one single-element structure to one lane of one register.

vld1q_lane_s8Experimentalneon

Load one single-element structure to one lane of one register.

vld1q_lane_s16Experimentalneon

Load one single-element structure to one lane of one register.

vld1q_lane_s32Experimentalneon

Load one single-element structure to one lane of one register.

vld1q_lane_s64Experimentalneon

Load one single-element structure to one lane of one register.

vld1q_lane_u8Experimentalneon

Load one single-element structure to one lane of one register.

vld1q_lane_u16Experimentalneon

Load one single-element structure to one lane of one register.

vld1q_lane_u32Experimentalneon

Load one single-element structure to one lane of one register.

vld1q_lane_u64Experimentalneon

Load one single-element structure to one lane of one register.

vld1q_p8_x2Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1q_p8_x3Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1q_p8_x4Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1q_p16_x2Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1q_p16_x3Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1q_p16_x4Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1q_p64_x2Experimentalneon,aes

Load multiple single-element structures to one, two, three, or four registers

vld1q_p64_x3Experimentalneon,aes

Load multiple single-element structures to one, two, three, or four registers

vld1q_p64_x4Experimentalneon,aes

Load multiple single-element structures to one, two, three, or four registers

vld1q_s8_x2Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1q_s8_x3Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1q_s8_x4Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1q_s16_x2Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1q_s16_x3Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1q_s16_x4Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1q_s32_x2Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1q_s32_x3Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1q_s32_x4Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1q_s64_x2Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1q_s64_x3Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1q_s64_x4Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1q_u8_x2Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1q_u8_x3Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1q_u8_x4Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1q_u16_x2Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1q_u16_x3Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1q_u16_x4Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1q_u32_x2Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1q_u32_x3Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1q_u32_x4Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1q_u64_x2Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1q_u64_x3Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld1q_u64_x4Experimentalneon

Load multiple single-element structures to one, two, three, or four registers

vld2_dup_p8Experimentalneon

Load single 2-element structure and replicate to all lanes of two registers

vld2_dup_p16Experimentalneon

Load single 2-element structure and replicate to all lanes of two registers

vld2_dup_p64Experimentalneon,aes

Load single 2-element structure and replicate to all lanes of two registers

vld2_dup_u8Experimentalneon

Load single 2-element structure and replicate to all lanes of two registers

vld2_dup_u16Experimentalneon

Load single 2-element structure and replicate to all lanes of two registers

vld2_dup_u32Experimentalneon

Load single 2-element structure and replicate to all lanes of two registers

vld2_dup_u64Experimentalneon

Load single 2-element structure and replicate to all lanes of two registers

vld2_lane_p8Experimentalneon

Load multiple 2-element structures to two registers

vld2_lane_p16Experimentalneon

Load multiple 2-element structures to two registers

vld2_lane_u8Experimentalneon

Load multiple 2-element structures to two registers

vld2_lane_u16Experimentalneon

Load multiple 2-element structures to two registers

vld2_lane_u32Experimentalneon

Load multiple 2-element structures to two registers

vld2_p8Experimentalneon

Load multiple 2-element structures to two registers

vld2_p16Experimentalneon

Load multiple 2-element structures to two registers

vld2_p64Experimentalneon,aes

Load multiple 2-element structures to two registers

vld2_u8Experimentalneon

Load multiple 2-element structures to two registers

vld2_u16Experimentalneon

Load multiple 2-element structures to two registers

vld2_u32Experimentalneon

Load multiple 2-element structures to two registers

vld2_u64Experimentalneon

Load multiple 2-element structures to two registers

vld2q_dup_p8Experimentalneon

Load single 2-element structure and replicate to all lanes of two registers

vld2q_dup_p16Experimentalneon

Load single 2-element structure and replicate to all lanes of two registers

vld2q_dup_u8Experimentalneon

Load single 2-element structure and replicate to all lanes of two registers

vld2q_dup_u16Experimentalneon

Load single 2-element structure and replicate to all lanes of two registers

vld2q_dup_u32Experimentalneon

Load single 2-element structure and replicate to all lanes of two registers

vld2q_lane_p16Experimentalneon

Load multiple 2-element structures to two registers

vld2q_lane_u16Experimentalneon

Load multiple 2-element structures to two registers

vld2q_lane_u32Experimentalneon

Load multiple 2-element structures to two registers

vld2q_p8Experimentalneon

Load multiple 2-element structures to two registers

vld2q_p16Experimentalneon

Load multiple 2-element structures to two registers

vld2q_u8Experimentalneon

Load multiple 2-element structures to two registers

vld2q_u16Experimentalneon

Load multiple 2-element structures to two registers

vld2q_u32Experimentalneon

Load multiple 2-element structures to two registers

vld3_dup_p8Experimentalneon

Load single 3-element structure and replicate to all lanes of three registers

vld3_dup_p16Experimentalneon

Load single 3-element structure and replicate to all lanes of three registers

vld3_dup_p64Experimentalneon,aes

Load single 3-element structure and replicate to all lanes of three registers

vld3_dup_u8Experimentalneon

Load single 3-element structure and replicate to all lanes of three registers

vld3_dup_u16Experimentalneon

Load single 3-element structure and replicate to all lanes of three registers

vld3_dup_u32Experimentalneon

Load single 3-element structure and replicate to all lanes of three registers

vld3_dup_u64Experimentalneon

Load single 3-element structure and replicate to all lanes of three registers

vld3_lane_p8Experimentalneon

Load multiple 3-element structures to three registers

vld3_lane_p16Experimentalneon

Load multiple 3-element structures to three registers

vld3_lane_u8Experimentalneon

Load multiple 3-element structures to three registers

vld3_lane_u16Experimentalneon

Load multiple 3-element structures to three registers

vld3_lane_u32Experimentalneon

Load multiple 3-element structures to three registers

vld3_p8Experimentalneon

Load multiple 3-element structures to three registers

vld3_p16Experimentalneon

Load multiple 3-element structures to three registers

vld3_p64Experimentalneon,aes

Load multiple 3-element structures to three registers

vld3_u8Experimentalneon

Load multiple 3-element structures to three registers

vld3_u16Experimentalneon

Load multiple 3-element structures to three registers

vld3_u32Experimentalneon

Load multiple 3-element structures to three registers

vld3_u64Experimentalneon

Load multiple 3-element structures to three registers

vld3q_dup_p8Experimentalneon

Load single 3-element structure and replicate to all lanes of three registers

vld3q_dup_p16Experimentalneon

Load single 3-element structure and replicate to all lanes of three registers

vld3q_dup_u8Experimentalneon

Load single 3-element structure and replicate to all lanes of three registers

vld3q_dup_u16Experimentalneon

Load single 3-element structure and replicate to all lanes of three registers

vld3q_dup_u32Experimentalneon

Load single 3-element structure and replicate to all lanes of three registers

vld3q_lane_p16Experimentalneon

Load multiple 3-element structures to three registers

vld3q_lane_u16Experimentalneon

Load multiple 3-element structures to three registers

vld3q_lane_u32Experimentalneon

Load multiple 3-element structures to three registers

vld3q_p8Experimentalneon

Load multiple 3-element structures to three registers

vld3q_p16Experimentalneon

Load multiple 3-element structures to three registers

vld3q_u8Experimentalneon

Load multiple 3-element structures to three registers

vld3q_u16Experimentalneon

Load multiple 3-element structures to three registers

vld3q_u32Experimentalneon

Load multiple 3-element structures to three registers

vld4_dup_p8Experimentalneon

Load single 4-element structure and replicate to all lanes of four registers

vld4_dup_p16Experimentalneon

Load single 4-element structure and replicate to all lanes of four registers

vld4_dup_p64Experimentalneon,aes

Load single 4-element structure and replicate to all lanes of four registers

vld4_dup_u8Experimentalneon

Load single 4-element structure and replicate to all lanes of four registers

vld4_dup_u16Experimentalneon

Load single 4-element structure and replicate to all lanes of four registers

vld4_dup_u32Experimentalneon

Load single 4-element structure and replicate to all lanes of four registers

vld4_dup_u64Experimentalneon

Load single 4-element structure and replicate to all lanes of four registers

vld4_lane_p8Experimentalneon

Load multiple 4-element structures to four registers

vld4_lane_p16Experimentalneon

Load multiple 4-element structures to four registers

vld4_lane_u8Experimentalneon

Load multiple 4-element structures to four registers

vld4_lane_u16Experimentalneon

Load multiple 4-element structures to four registers

vld4_lane_u32Experimentalneon

Load multiple 4-element structures to four registers

vld4_p8Experimentalneon

Load multiple 4-element structures to four registers

vld4_p16Experimentalneon

Load multiple 4-element structures to four registers

vld4_p64Experimentalneon,aes

Load multiple 4-element structures to four registers

vld4_u8Experimentalneon

Load multiple 4-element structures to four registers

vld4_u16Experimentalneon

Load multiple 4-element structures to four registers

vld4_u32Experimentalneon

Load multiple 4-element structures to four registers

vld4_u64Experimentalneon

Load multiple 4-element structures to four registers

vld4q_dup_p8Experimentalneon

Load single 4-element structure and replicate to all lanes of four registers

vld4q_dup_p16Experimentalneon

Load single 4-element structure and replicate to all lanes of four registers

vld4q_dup_u8Experimentalneon

Load single 4-element structure and replicate to all lanes of four registers

vld4q_dup_u16Experimentalneon

Load single 4-element structure and replicate to all lanes of four registers

vld4q_dup_u32Experimentalneon

Load single 4-element structure and replicate to all lanes of four registers

vld4q_lane_p16Experimentalneon

Load multiple 4-element structures to four registers

vld4q_lane_u16Experimentalneon

Load multiple 4-element structures to four registers

vld4q_lane_u32Experimentalneon

Load multiple 4-element structures to four registers

vld4q_p8Experimentalneon

Load multiple 4-element structures to four registers

vld4q_p16Experimentalneon

Load multiple 4-element structures to four registers

vld4q_u8Experimentalneon

Load multiple 4-element structures to four registers

vld4q_u16Experimentalneon

Load multiple 4-element structures to four registers

vld4q_u32Experimentalneon

Load multiple 4-element structures to four registers

vldrq_p128Experimentalneon

Load SIMD&FP register (immediate offset)

vmax_f32Experimentalneon

Maximum (vector)

vmax_s8Experimentalneon

Maximum (vector)

vmax_s16Experimentalneon

Maximum (vector)

vmax_s32Experimentalneon

Maximum (vector)

vmax_u8Experimentalneon

Maximum (vector)

vmax_u16Experimentalneon

Maximum (vector)

vmax_u32Experimentalneon

Maximum (vector)

vmaxnm_f32Experimentalneon

Floating-point Maximum Number (vector)

vmaxnmq_f32Experimentalneon

Floating-point Maximum Number (vector)

vmaxq_f32Experimentalneon

Maximum (vector)

vmaxq_s8Experimentalneon

Maximum (vector)

vmaxq_s16Experimentalneon

Maximum (vector)

vmaxq_s32Experimentalneon

Maximum (vector)

vmaxq_u8Experimentalneon

Maximum (vector)

vmaxq_u16Experimentalneon

Maximum (vector)

vmaxq_u32Experimentalneon

Maximum (vector)

vmin_f32Experimentalneon

Minimum (vector)

vmin_s8Experimentalneon

Minimum (vector)

vmin_s16Experimentalneon

Minimum (vector)

vmin_s32Experimentalneon

Minimum (vector)

vmin_u8Experimentalneon

Minimum (vector)

vmin_u16Experimentalneon

Minimum (vector)

vmin_u32Experimentalneon

Minimum (vector)

vminnm_f32Experimentalneon

Floating-point Minimum Number (vector)

vminnmq_f32Experimentalneon

Floating-point Minimum Number (vector)

vminq_f32Experimentalneon

Minimum (vector)

vminq_s8Experimentalneon

Minimum (vector)

vminq_s16Experimentalneon

Minimum (vector)

vminq_s32Experimentalneon

Minimum (vector)

vminq_u8Experimentalneon

Minimum (vector)

vminq_u16Experimentalneon

Minimum (vector)

vminq_u32Experimentalneon

Minimum (vector)

vmla_f32Experimentalneon

Floating-point multiply-add to accumulator

vmla_lane_f32Experimentalneon

Vector multiply accumulate with scalar

vmla_lane_s16Experimentalneon

Vector multiply accumulate with scalar

vmla_lane_s32Experimentalneon

Vector multiply accumulate with scalar

vmla_lane_u16Experimentalneon

Vector multiply accumulate with scalar

vmla_lane_u32Experimentalneon

Vector multiply accumulate with scalar

vmla_laneq_f32Experimentalneon

Vector multiply accumulate with scalar

vmla_laneq_s16Experimentalneon

Vector multiply accumulate with scalar

vmla_laneq_s32Experimentalneon

Vector multiply accumulate with scalar

vmla_laneq_u16Experimentalneon

Vector multiply accumulate with scalar

vmla_laneq_u32Experimentalneon

Vector multiply accumulate with scalar

vmla_n_f32Experimentalneon

Vector multiply accumulate with scalar

vmla_n_s16Experimentalneon

Vector multiply accumulate with scalar

vmla_n_s32Experimentalneon

Vector multiply accumulate with scalar

vmla_n_u16Experimentalneon

Vector multiply accumulate with scalar

vmla_n_u32Experimentalneon

Vector multiply accumulate with scalar

vmla_s8Experimentalneon

Multiply-add to accumulator

vmla_s16Experimentalneon

Multiply-add to accumulator

vmla_s32Experimentalneon

Multiply-add to accumulator

vmla_u8Experimentalneon

Multiply-add to accumulator

vmla_u16Experimentalneon

Multiply-add to accumulator

vmla_u32Experimentalneon

Multiply-add to accumulator

vmlal_lane_s16Experimentalneon

Vector widening multiply accumulate with scalar

vmlal_lane_s32Experimentalneon

Vector widening multiply accumulate with scalar

vmlal_lane_u16Experimentalneon

Vector widening multiply accumulate with scalar

vmlal_lane_u32Experimentalneon

Vector widening multiply accumulate with scalar

vmlal_laneq_s16Experimentalneon

Vector widening multiply accumulate with scalar

vmlal_laneq_s32Experimentalneon

Vector widening multiply accumulate with scalar

vmlal_laneq_u16Experimentalneon

Vector widening multiply accumulate with scalar

vmlal_laneq_u32Experimentalneon

Vector widening multiply accumulate with scalar

vmlal_n_s16Experimentalneon

Vector widening multiply accumulate with scalar

vmlal_n_s32Experimentalneon

Vector widening multiply accumulate with scalar

vmlal_n_u16Experimentalneon

Vector widening multiply accumulate with scalar

vmlal_n_u32Experimentalneon

Vector widening multiply accumulate with scalar

vmlal_s8Experimentalneon

Signed multiply-add long

vmlal_s16Experimentalneon

Signed multiply-add long

vmlal_s32Experimentalneon

Signed multiply-add long

vmlal_u8Experimentalneon

Unsigned multiply-add long

vmlal_u16Experimentalneon

Unsigned multiply-add long

vmlal_u32Experimentalneon

Unsigned multiply-add long

vmlaq_f32Experimentalneon

Floating-point multiply-add to accumulator

vmlaq_lane_f32Experimentalneon

Vector multiply accumulate with scalar

vmlaq_lane_s16Experimentalneon

Vector multiply accumulate with scalar

vmlaq_lane_s32Experimentalneon

Vector multiply accumulate with scalar

vmlaq_lane_u16Experimentalneon

Vector multiply accumulate with scalar

vmlaq_lane_u32Experimentalneon

Vector multiply accumulate with scalar

vmlaq_laneq_f32Experimentalneon

Vector multiply accumulate with scalar

vmlaq_laneq_s16Experimentalneon

Vector multiply accumulate with scalar

vmlaq_laneq_s32Experimentalneon

Vector multiply accumulate with scalar

vmlaq_laneq_u16Experimentalneon

Vector multiply accumulate with scalar

vmlaq_laneq_u32Experimentalneon

Vector multiply accumulate with scalar

vmlaq_n_f32Experimentalneon

Vector multiply accumulate with scalar

vmlaq_n_s16Experimentalneon

Vector multiply accumulate with scalar

vmlaq_n_s32Experimentalneon

Vector multiply accumulate with scalar

vmlaq_n_u16Experimentalneon

Vector multiply accumulate with scalar

vmlaq_n_u32Experimentalneon

Vector multiply accumulate with scalar

vmlaq_s8Experimentalneon

Multiply-add to accumulator

vmlaq_s16Experimentalneon

Multiply-add to accumulator

vmlaq_s32Experimentalneon

Multiply-add to accumulator

vmlaq_u8Experimentalneon

Multiply-add to accumulator

vmlaq_u16Experimentalneon

Multiply-add to accumulator

vmlaq_u32Experimentalneon

Multiply-add to accumulator

vmls_f32Experimentalneon

Floating-point multiply-subtract from accumulator

vmls_lane_f32Experimentalneon

Vector multiply subtract with scalar

vmls_lane_s16Experimentalneon

Vector multiply subtract with scalar

vmls_lane_s32Experimentalneon

Vector multiply subtract with scalar

vmls_lane_u16Experimentalneon

Vector multiply subtract with scalar

vmls_lane_u32Experimentalneon

Vector multiply subtract with scalar

vmls_laneq_f32Experimentalneon

Vector multiply subtract with scalar

vmls_laneq_s16Experimentalneon

Vector multiply subtract with scalar

vmls_laneq_s32Experimentalneon

Vector multiply subtract with scalar

vmls_laneq_u16Experimentalneon

Vector multiply subtract with scalar

vmls_laneq_u32Experimentalneon

Vector multiply subtract with scalar

vmls_n_f32Experimentalneon

Vector multiply subtract with scalar

vmls_n_s16Experimentalneon

Vector multiply subtract with scalar

vmls_n_s32Experimentalneon

Vector multiply subtract with scalar

vmls_n_u16Experimentalneon

Vector multiply subtract with scalar

vmls_n_u32Experimentalneon

Vector multiply subtract with scalar

vmls_s8Experimentalneon

Multiply-subtract from accumulator

vmls_s16Experimentalneon

Multiply-subtract from accumulator

vmls_s32Experimentalneon

Multiply-subtract from accumulator

vmls_u8Experimentalneon

Multiply-subtract from accumulator

vmls_u16Experimentalneon

Multiply-subtract from accumulator

vmls_u32Experimentalneon

Multiply-subtract from accumulator

vmlsl_lane_s16Experimentalneon

Vector widening multiply subtract with scalar

vmlsl_lane_s32Experimentalneon

Vector widening multiply subtract with scalar

vmlsl_lane_u16Experimentalneon

Vector widening multiply subtract with scalar

vmlsl_lane_u32Experimentalneon

Vector widening multiply subtract with scalar

vmlsl_laneq_s16Experimentalneon

Vector widening multiply subtract with scalar

vmlsl_laneq_s32Experimentalneon

Vector widening multiply subtract with scalar

vmlsl_laneq_u16Experimentalneon

Vector widening multiply subtract with scalar

vmlsl_laneq_u32Experimentalneon

Vector widening multiply subtract with scalar

vmlsl_n_s16Experimentalneon

Vector widening multiply subtract with scalar

vmlsl_n_s32Experimentalneon

Vector widening multiply subtract with scalar

vmlsl_n_u16Experimentalneon

Vector widening multiply subtract with scalar

vmlsl_n_u32Experimentalneon

Vector widening multiply subtract with scalar

vmlsl_s8Experimentalneon

Signed multiply-subtract long

vmlsl_s16Experimentalneon

Signed multiply-subtract long

vmlsl_s32Experimentalneon

Signed multiply-subtract long

vmlsl_u8Experimentalneon

Unsigned multiply-subtract long

vmlsl_u16Experimentalneon

Unsigned multiply-subtract long

vmlsl_u32Experimentalneon

Unsigned multiply-subtract long

vmlsq_f32Experimentalneon

Floating-point multiply-subtract from accumulator

vmlsq_lane_f32Experimentalneon

Vector multiply subtract with scalar

vmlsq_lane_s16Experimentalneon

Vector multiply subtract with scalar

vmlsq_lane_s32Experimentalneon

Vector multiply subtract with scalar

vmlsq_lane_u16Experimentalneon

Vector multiply subtract with scalar

vmlsq_lane_u32Experimentalneon

Vector multiply subtract with scalar

vmlsq_laneq_f32Experimentalneon

Vector multiply subtract with scalar

vmlsq_laneq_s16Experimentalneon

Vector multiply subtract with scalar

vmlsq_laneq_s32Experimentalneon

Vector multiply subtract with scalar

vmlsq_laneq_u16Experimentalneon

Vector multiply subtract with scalar

vmlsq_laneq_u32Experimentalneon

Vector multiply subtract with scalar

vmlsq_n_f32Experimentalneon

Vector multiply subtract with scalar

vmlsq_n_s16Experimentalneon

Vector multiply subtract with scalar

vmlsq_n_s32Experimentalneon

Vector multiply subtract with scalar

vmlsq_n_u16Experimentalneon

Vector multiply subtract with scalar

vmlsq_n_u32Experimentalneon

Vector multiply subtract with scalar

vmlsq_s8Experimentalneon

Multiply-subtract from accumulator

vmlsq_s16Experimentalneon

Multiply-subtract from accumulator

vmlsq_s32Experimentalneon

Multiply-subtract from accumulator

vmlsq_u8Experimentalneon

Multiply-subtract from accumulator

vmlsq_u16Experimentalneon

Multiply-subtract from accumulator

vmlsq_u32Experimentalneon

Multiply-subtract from accumulator

vmmlaq_s32Experimentali8mm and neon

8-bit integer matrix multiply-accumulate

vmmlaq_u32Experimentali8mm and neon

8-bit integer matrix multiply-accumulate

vmov_n_f32Experimentalneon

Duplicate vector element to vector or scalar

vmov_n_p8Experimentalneon

Duplicate vector element to vector or scalar

vmov_n_p16Experimentalneon

Duplicate vector element to vector or scalar

vmov_n_s8Experimentalneon

Duplicate vector element to vector or scalar

vmov_n_s16Experimentalneon

Duplicate vector element to vector or scalar

vmov_n_s32Experimentalneon

Duplicate vector element to vector or scalar

vmov_n_s64Experimentalneon

Duplicate vector element to vector or scalar

vmov_n_u8Experimentalneon

Duplicate vector element to vector or scalar

vmov_n_u16Experimentalneon

Duplicate vector element to vector or scalar

vmov_n_u32Experimentalneon

Duplicate vector element to vector or scalar

vmov_n_u64Experimentalneon

Duplicate vector element to vector or scalar

vmovl_s8Experimentalneon

Vector long move.

vmovl_s16Experimentalneon

Vector long move.

vmovl_s32Experimentalneon

Vector long move.

vmovl_u8Experimentalneon

Vector long move.

vmovl_u16Experimentalneon

Vector long move.

vmovl_u32Experimentalneon

Vector long move.

vmovn_s16Experimentalneon

Vector narrow integer.

vmovn_s32Experimentalneon

Vector narrow integer.

vmovn_s64Experimentalneon

Vector narrow integer.

vmovn_u16Experimentalneon

Vector narrow integer.

vmovn_u32Experimentalneon

Vector narrow integer.

vmovn_u64Experimentalneon

Vector narrow integer.

vmovq_n_f32Experimentalneon

Duplicate vector element to vector or scalar

vmovq_n_p8Experimentalneon

Duplicate vector element to vector or scalar

vmovq_n_p16Experimentalneon

Duplicate vector element to vector or scalar

vmovq_n_s8Experimentalneon

Duplicate vector element to vector or scalar

vmovq_n_s16Experimentalneon

Duplicate vector element to vector or scalar

vmovq_n_s32Experimentalneon

Duplicate vector element to vector or scalar

vmovq_n_s64Experimentalneon

Duplicate vector element to vector or scalar

vmovq_n_u8Experimentalneon

Duplicate vector element to vector or scalar

vmovq_n_u16Experimentalneon

Duplicate vector element to vector or scalar

vmovq_n_u32Experimentalneon

Duplicate vector element to vector or scalar

vmovq_n_u64Experimentalneon

Duplicate vector element to vector or scalar

vmul_f32Experimentalneon

Multiply

vmul_lane_f32Experimentalneon

Floating-point multiply

vmul_lane_s16Experimentalneon

Multiply

vmul_lane_s32Experimentalneon

Multiply

vmul_lane_u16Experimentalneon

Multiply

vmul_lane_u32Experimentalneon

Multiply

vmul_laneq_f32Experimentalneon

Floating-point multiply

vmul_laneq_s16Experimentalneon

Multiply

vmul_laneq_s32Experimentalneon

Multiply

vmul_laneq_u16Experimentalneon

Multiply

vmul_laneq_u32Experimentalneon

Multiply

vmul_n_f32Experimentalneon

Vector multiply by scalar

vmul_n_s16Experimentalneon

Vector multiply by scalar

vmul_n_s32Experimentalneon

Vector multiply by scalar

vmul_n_u16Experimentalneon

Vector multiply by scalar

vmul_n_u32Experimentalneon

Vector multiply by scalar

vmul_p8Experimentalneon

Polynomial multiply

vmul_s8Experimentalneon

Multiply

vmul_s16Experimentalneon

Multiply

vmul_s32Experimentalneon

Multiply

vmul_u8Experimentalneon

Multiply

vmul_u16Experimentalneon

Multiply

vmul_u32Experimentalneon

Multiply

vmull_lane_s16Experimentalneon

Vector long multiply by scalar

vmull_lane_s32Experimentalneon

Vector long multiply by scalar

vmull_lane_u16Experimentalneon

Vector long multiply by scalar

vmull_lane_u32Experimentalneon

Vector long multiply by scalar

vmull_laneq_s16Experimentalneon

Vector long multiply by scalar

vmull_laneq_s32Experimentalneon

Vector long multiply by scalar

vmull_laneq_u16Experimentalneon

Vector long multiply by scalar

vmull_laneq_u32Experimentalneon

Vector long multiply by scalar

vmull_n_s16Experimentalneon

Vector long multiply with scalar

vmull_n_s32Experimentalneon

Vector long multiply with scalar

vmull_n_u16Experimentalneon

Vector long multiply with scalar

vmull_n_u32Experimentalneon

Vector long multiply with scalar

vmull_p8Experimentalneon

Polynomial multiply long

vmull_s8Experimentalneon

Signed multiply long

vmull_s16Experimentalneon

Signed multiply long

vmull_s32Experimentalneon

Signed multiply long

vmull_u8Experimentalneon

Unsigned multiply long

vmull_u16Experimentalneon

Unsigned multiply long

vmull_u32Experimentalneon

Unsigned multiply long

vmulq_f32Experimentalneon

Multiply

vmulq_lane_f32Experimentalneon

Floating-point multiply

vmulq_lane_s16Experimentalneon

Multiply

vmulq_lane_s32Experimentalneon

Multiply

vmulq_lane_u16Experimentalneon

Multiply

vmulq_lane_u32Experimentalneon

Multiply

vmulq_laneq_f32Experimentalneon

Floating-point multiply

vmulq_laneq_s16Experimentalneon

Multiply

vmulq_laneq_s32Experimentalneon

Multiply

vmulq_laneq_u16Experimentalneon

Multiply

vmulq_laneq_u32Experimentalneon

Multiply

vmulq_n_f32Experimentalneon

Vector multiply by scalar

vmulq_n_s16Experimentalneon

Vector multiply by scalar

vmulq_n_s32Experimentalneon

Vector multiply by scalar

vmulq_n_u16Experimentalneon

Vector multiply by scalar

vmulq_n_u32Experimentalneon

Vector multiply by scalar

vmulq_p8Experimentalneon

Polynomial multiply

vmulq_s8Experimentalneon

Multiply

vmulq_s16Experimentalneon

Multiply

vmulq_s32Experimentalneon

Multiply

vmulq_u8Experimentalneon

Multiply

vmulq_u16Experimentalneon

Multiply

vmulq_u32Experimentalneon

Multiply

vmvn_p8Experimentalneon

Vector bitwise not.

vmvn_s8Experimentalneon

Vector bitwise not.

vmvn_s16Experimentalneon

Vector bitwise not.

vmvn_s32Experimentalneon

Vector bitwise not.

vmvn_u8Experimentalneon

Vector bitwise not.

vmvn_u16Experimentalneon

Vector bitwise not.

vmvn_u32Experimentalneon

Vector bitwise not.

vmvnq_p8Experimentalneon

Vector bitwise not.

vmvnq_s8Experimentalneon

Vector bitwise not.

vmvnq_s16Experimentalneon

Vector bitwise not.

vmvnq_s32Experimentalneon

Vector bitwise not.

vmvnq_u8Experimentalneon

Vector bitwise not.

vmvnq_u16Experimentalneon

Vector bitwise not.

vmvnq_u32Experimentalneon

Vector bitwise not.

vneg_f32Experimentalneon

Negate

vneg_s8Experimentalneon

Negate

vneg_s16Experimentalneon

Negate

vneg_s32Experimentalneon

Negate

vnegq_f32Experimentalneon

Negate

vnegq_s8Experimentalneon

Negate

vnegq_s16Experimentalneon

Negate

vnegq_s32Experimentalneon

Negate

vorn_s8Experimentalneon

Vector bitwise inclusive OR NOT

vorn_s16Experimentalneon

Vector bitwise inclusive OR NOT

vorn_s32Experimentalneon

Vector bitwise inclusive OR NOT

vorn_s64Experimentalneon

Vector bitwise inclusive OR NOT

vorn_u8Experimentalneon

Vector bitwise inclusive OR NOT

vorn_u16Experimentalneon

Vector bitwise inclusive OR NOT

vorn_u32Experimentalneon

Vector bitwise inclusive OR NOT

vorn_u64Experimentalneon

Vector bitwise inclusive OR NOT

vornq_s8Experimentalneon

Vector bitwise inclusive OR NOT

vornq_s16Experimentalneon

Vector bitwise inclusive OR NOT

vornq_s32Experimentalneon

Vector bitwise inclusive OR NOT

vornq_s64Experimentalneon

Vector bitwise inclusive OR NOT

vornq_u8Experimentalneon

Vector bitwise inclusive OR NOT

vornq_u16Experimentalneon

Vector bitwise inclusive OR NOT

vornq_u32Experimentalneon

Vector bitwise inclusive OR NOT

vornq_u64Experimentalneon

Vector bitwise inclusive OR NOT

vorr_s8Experimentalneon

Vector bitwise or (immediate, inclusive)

vorr_s16Experimentalneon

Vector bitwise or (immediate, inclusive)

vorr_s32Experimentalneon

Vector bitwise or (immediate, inclusive)

vorr_s64Experimentalneon

Vector bitwise or (immediate, inclusive)

vorr_u8Experimentalneon

Vector bitwise or (immediate, inclusive)

vorr_u16Experimentalneon

Vector bitwise or (immediate, inclusive)

vorr_u32Experimentalneon

Vector bitwise or (immediate, inclusive)

vorr_u64Experimentalneon

Vector bitwise or (immediate, inclusive)

vorrq_s8Experimentalneon

Vector bitwise or (immediate, inclusive)

vorrq_s16Experimentalneon

Vector bitwise or (immediate, inclusive)

vorrq_s32Experimentalneon

Vector bitwise or (immediate, inclusive)

vorrq_s64Experimentalneon

Vector bitwise or (immediate, inclusive)

vorrq_u8Experimentalneon

Vector bitwise or (immediate, inclusive)

vorrq_u16Experimentalneon

Vector bitwise or (immediate, inclusive)

vorrq_u32Experimentalneon

Vector bitwise or (immediate, inclusive)

vorrq_u64Experimentalneon

Vector bitwise or (immediate, inclusive)

vpadal_s8Experimentalneon

Signed Add and Accumulate Long Pairwise.

vpadal_s16Experimentalneon

Signed Add and Accumulate Long Pairwise.

vpadal_s32Experimentalneon

Signed Add and Accumulate Long Pairwise.

vpadal_u8Experimentalneon

Unsigned Add and Accumulate Long Pairwise.

vpadal_u16Experimentalneon

Unsigned Add and Accumulate Long Pairwise.

vpadal_u32Experimentalneon

Unsigned Add and Accumulate Long Pairwise.

vpadalq_s8Experimentalneon

Signed Add and Accumulate Long Pairwise.

vpadalq_s16Experimentalneon

Signed Add and Accumulate Long Pairwise.

vpadalq_s32Experimentalneon

Signed Add and Accumulate Long Pairwise.

vpadalq_u8Experimentalneon

Unsigned Add and Accumulate Long Pairwise.

vpadalq_u16Experimentalneon

Unsigned Add and Accumulate Long Pairwise.

vpadalq_u32Experimentalneon

Unsigned Add and Accumulate Long Pairwise.

vpadd_f32Experimentalneon

Floating-point add pairwise

vpadd_s8Experimentalneon

Add pairwise.

vpadd_s16Experimentalneon

Add pairwise.

vpadd_s32Experimentalneon

Add pairwise.

vpadd_u8Experimentalneon

Add pairwise.

vpadd_u16Experimentalneon

Add pairwise.

vpadd_u32Experimentalneon

Add pairwise.

vpaddl_s8Experimentalneon

Signed Add Long Pairwise.

vpaddl_s16Experimentalneon

Signed Add Long Pairwise.

vpaddl_s32Experimentalneon

Signed Add Long Pairwise.

vpaddl_u8Experimentalneon

Unsigned Add Long Pairwise.

vpaddl_u16Experimentalneon

Unsigned Add Long Pairwise.

vpaddl_u32Experimentalneon

Unsigned Add Long Pairwise.

vpaddlq_s8Experimentalneon

Signed Add Long Pairwise.

vpaddlq_s16Experimentalneon

Signed Add Long Pairwise.

vpaddlq_s32Experimentalneon

Signed Add Long Pairwise.

vpaddlq_u8Experimentalneon

Unsigned Add Long Pairwise.

vpaddlq_u16Experimentalneon

Unsigned Add Long Pairwise.

vpaddlq_u32Experimentalneon

Unsigned Add Long Pairwise.

vpmax_f32Experimentalneon

Folding maximum of adjacent pairs

vpmax_s8Experimentalneon

Folding maximum of adjacent pairs

vpmax_s16Experimentalneon

Folding maximum of adjacent pairs

vpmax_s32Experimentalneon

Folding maximum of adjacent pairs

vpmax_u8Experimentalneon

Folding maximum of adjacent pairs

vpmax_u16Experimentalneon

Folding maximum of adjacent pairs

vpmax_u32Experimentalneon

Folding maximum of adjacent pairs

vpmin_f32Experimentalneon

Folding minimum of adjacent pairs

vpmin_s8Experimentalneon

Folding minimum of adjacent pairs

vpmin_s16Experimentalneon

Folding minimum of adjacent pairs

vpmin_s32Experimentalneon

Folding minimum of adjacent pairs

vpmin_u8Experimentalneon

Folding minimum of adjacent pairs

vpmin_u16Experimentalneon

Folding minimum of adjacent pairs

vpmin_u32Experimentalneon

Folding minimum of adjacent pairs

vqabs_s8Experimentalneon

Singned saturating Absolute value

vqabs_s16Experimentalneon

Singned saturating Absolute value

vqabs_s32Experimentalneon

Singned saturating Absolute value

vqabsq_s8Experimentalneon

Singned saturating Absolute value

vqabsq_s16Experimentalneon

Singned saturating Absolute value

vqabsq_s32Experimentalneon

Singned saturating Absolute value

vqadd_s8Experimentalneon

Saturating add

vqadd_s16Experimentalneon

Saturating add

vqadd_s32Experimentalneon

Saturating add

vqadd_s64Experimentalneon

Saturating add

vqadd_u8Experimentalneon

Saturating add

vqadd_u16Experimentalneon

Saturating add

vqadd_u32Experimentalneon

Saturating add

vqadd_u64Experimentalneon

Saturating add

vqaddq_s8Experimentalneon

Saturating add

vqaddq_s16Experimentalneon

Saturating add

vqaddq_s32Experimentalneon

Saturating add

vqaddq_s64Experimentalneon

Saturating add

vqaddq_u8Experimentalneon

Saturating add

vqaddq_u16Experimentalneon

Saturating add

vqaddq_u32Experimentalneon

Saturating add

vqaddq_u64Experimentalneon

Saturating add

vqdmlal_lane_s16Experimentalneon

Vector widening saturating doubling multiply accumulate with scalar

vqdmlal_lane_s32Experimentalneon

Vector widening saturating doubling multiply accumulate with scalar

vqdmlal_n_s16Experimentalneon

Vector widening saturating doubling multiply accumulate with scalar

vqdmlal_n_s32Experimentalneon

Vector widening saturating doubling multiply accumulate with scalar

vqdmlal_s16Experimentalneon

Signed saturating doubling multiply-add long

vqdmlal_s32Experimentalneon

Signed saturating doubling multiply-add long

vqdmlsl_lane_s16Experimentalneon

Vector widening saturating doubling multiply subtract with scalar

vqdmlsl_lane_s32Experimentalneon

Vector widening saturating doubling multiply subtract with scalar

vqdmlsl_n_s16Experimentalneon

Vector widening saturating doubling multiply subtract with scalar

vqdmlsl_n_s32Experimentalneon

Vector widening saturating doubling multiply subtract with scalar

vqdmlsl_s16Experimentalneon

Signed saturating doubling multiply-subtract long

vqdmlsl_s32Experimentalneon

Signed saturating doubling multiply-subtract long

vqdmulh_laneq_s16Experimentalneon

Vector saturating doubling multiply high by scalar

vqdmulh_laneq_s32Experimentalneon

Vector saturating doubling multiply high by scalar

vqdmulh_n_s16Experimentalneon

Vector saturating doubling multiply high with scalar

vqdmulh_n_s32Experimentalneon

Vector saturating doubling multiply high with scalar

vqdmulh_s16Experimentalneon

Signed saturating doubling multiply returning high half

vqdmulh_s32Experimentalneon

Signed saturating doubling multiply returning high half

vqdmulhq_laneq_s16Experimentalneon

Vector saturating doubling multiply high by scalar

vqdmulhq_laneq_s32Experimentalneon

Vector saturating doubling multiply high by scalar

vqdmulhq_n_s16Experimentalneon

Vector saturating doubling multiply high with scalar

vqdmulhq_n_s32Experimentalneon

Vector saturating doubling multiply high with scalar

vqdmulhq_s16Experimentalneon

Signed saturating doubling multiply returning high half

vqdmulhq_s32Experimentalneon

Signed saturating doubling multiply returning high half

vqdmull_lane_s16Experimentalneon

Vector saturating doubling long multiply by scalar

vqdmull_lane_s32Experimentalneon

Vector saturating doubling long multiply by scalar

vqdmull_n_s16Experimentalneon

Vector saturating doubling long multiply with scalar

vqdmull_n_s32Experimentalneon

Vector saturating doubling long multiply with scalar

vqdmull_s16Experimentalneon

Signed saturating doubling multiply long

vqdmull_s32Experimentalneon

Signed saturating doubling multiply long

vqmovn_s16Experimentalneon

Signed saturating extract narrow

vqmovn_s32Experimentalneon

Signed saturating extract narrow

vqmovn_s64Experimentalneon

Signed saturating extract narrow

vqmovn_u16Experimentalneon

Unsigned saturating extract narrow

vqmovn_u32Experimentalneon

Unsigned saturating extract narrow

vqmovn_u64Experimentalneon

Unsigned saturating extract narrow

vqmovun_s16Experimentalneon

Signed saturating extract unsigned narrow

vqmovun_s32Experimentalneon

Signed saturating extract unsigned narrow

vqmovun_s64Experimentalneon

Signed saturating extract unsigned narrow

vqneg_s8Experimentalneon

Signed saturating negate

vqneg_s16Experimentalneon

Signed saturating negate

vqneg_s32Experimentalneon

Signed saturating negate

vqnegq_s8Experimentalneon

Signed saturating negate

vqnegq_s16Experimentalneon

Signed saturating negate

vqnegq_s32Experimentalneon

Signed saturating negate

vqrdmulh_lane_s16Experimentalneon

Vector rounding saturating doubling multiply high by scalar

vqrdmulh_lane_s32Experimentalneon

Vector rounding saturating doubling multiply high by scalar

vqrdmulh_laneq_s16Experimentalneon

Vector rounding saturating doubling multiply high by scalar

vqrdmulh_laneq_s32Experimentalneon

Vector rounding saturating doubling multiply high by scalar

vqrdmulh_n_s16Experimentalneon

Vector saturating rounding doubling multiply high with scalar

vqrdmulh_n_s32Experimentalneon

Vector saturating rounding doubling multiply high with scalar

vqrdmulh_s16Experimentalneon

Signed saturating rounding doubling multiply returning high half

vqrdmulh_s32Experimentalneon

Signed saturating rounding doubling multiply returning high half

vqrdmulhq_lane_s16Experimentalneon

Vector rounding saturating doubling multiply high by scalar

vqrdmulhq_lane_s32Experimentalneon

Vector rounding saturating doubling multiply high by scalar

vqrdmulhq_laneq_s16Experimentalneon

Vector rounding saturating doubling multiply high by scalar

vqrdmulhq_laneq_s32Experimentalneon

Vector rounding saturating doubling multiply high by scalar

vqrdmulhq_n_s16Experimentalneon

Vector saturating rounding doubling multiply high with scalar

vqrdmulhq_n_s32Experimentalneon

Vector saturating rounding doubling multiply high with scalar

vqrdmulhq_s16Experimentalneon

Signed saturating rounding doubling multiply returning high half

vqrdmulhq_s32Experimentalneon

Signed saturating rounding doubling multiply returning high half

vqrshl_s8Experimentalneon

Signed saturating rounding shift left

vqrshl_s16Experimentalneon

Signed saturating rounding shift left

vqrshl_s32Experimentalneon

Signed saturating rounding shift left

vqrshl_s64Experimentalneon

Signed saturating rounding shift left

vqrshl_u8Experimentalneon

Unsigned signed saturating rounding shift left

vqrshl_u16Experimentalneon

Unsigned signed saturating rounding shift left

vqrshl_u32Experimentalneon

Unsigned signed saturating rounding shift left

vqrshl_u64Experimentalneon

Unsigned signed saturating rounding shift left

vqrshlq_s8Experimentalneon

Signed saturating rounding shift left

vqrshlq_s16Experimentalneon

Signed saturating rounding shift left

vqrshlq_s32Experimentalneon

Signed saturating rounding shift left

vqrshlq_s64Experimentalneon

Signed saturating rounding shift left

vqrshlq_u8Experimentalneon

Unsigned signed saturating rounding shift left

vqrshlq_u16Experimentalneon

Unsigned signed saturating rounding shift left

vqrshlq_u32Experimentalneon

Unsigned signed saturating rounding shift left

vqrshlq_u64Experimentalneon

Unsigned signed saturating rounding shift left

vqshl_n_s8Experimentalneon

Signed saturating shift left

vqshl_n_s16Experimentalneon

Signed saturating shift left

vqshl_n_s32Experimentalneon

Signed saturating shift left

vqshl_n_s64Experimentalneon

Signed saturating shift left

vqshl_n_u8Experimentalneon

Unsigned saturating shift left

vqshl_n_u16Experimentalneon

Unsigned saturating shift left

vqshl_n_u32Experimentalneon

Unsigned saturating shift left

vqshl_n_u64Experimentalneon

Unsigned saturating shift left

vqshl_s8Experimentalneon

Signed saturating shift left

vqshl_s16Experimentalneon

Signed saturating shift left

vqshl_s32Experimentalneon

Signed saturating shift left

vqshl_s64Experimentalneon

Signed saturating shift left

vqshl_u8Experimentalneon

Unsigned saturating shift left

vqshl_u16Experimentalneon

Unsigned saturating shift left

vqshl_u32Experimentalneon

Unsigned saturating shift left

vqshl_u64Experimentalneon

Unsigned saturating shift left

vqshlq_n_s8Experimentalneon

Signed saturating shift left

vqshlq_n_s16Experimentalneon

Signed saturating shift left

vqshlq_n_s32Experimentalneon

Signed saturating shift left

vqshlq_n_s64Experimentalneon

Signed saturating shift left

vqshlq_n_u8Experimentalneon

Unsigned saturating shift left

vqshlq_n_u16Experimentalneon

Unsigned saturating shift left

vqshlq_n_u32Experimentalneon

Unsigned saturating shift left

vqshlq_n_u64Experimentalneon

Unsigned saturating shift left

vqshlq_s8Experimentalneon

Signed saturating shift left

vqshlq_s16Experimentalneon

Signed saturating shift left

vqshlq_s32Experimentalneon

Signed saturating shift left

vqshlq_s64Experimentalneon

Signed saturating shift left

vqshlq_u8Experimentalneon

Unsigned saturating shift left

vqshlq_u16Experimentalneon

Unsigned saturating shift left

vqshlq_u32Experimentalneon

Unsigned saturating shift left

vqshlq_u64Experimentalneon

Unsigned saturating shift left

vqsub_s8Experimentalneon

Saturating subtract

vqsub_s16Experimentalneon

Saturating subtract

vqsub_s32Experimentalneon

Saturating subtract

vqsub_s64Experimentalneon

Saturating subtract

vqsub_u8Experimentalneon

Saturating subtract

vqsub_u16Experimentalneon

Saturating subtract

vqsub_u32Experimentalneon

Saturating subtract

vqsub_u64Experimentalneon

Saturating subtract

vqsubq_s8Experimentalneon

Saturating subtract

vqsubq_s16Experimentalneon

Saturating subtract

vqsubq_s32Experimentalneon

Saturating subtract

vqsubq_s64Experimentalneon

Saturating subtract

vqsubq_u8Experimentalneon

Saturating subtract

vqsubq_u16Experimentalneon

Saturating subtract

vqsubq_u32Experimentalneon

Saturating subtract

vqsubq_u64Experimentalneon

Saturating subtract

vraddhn_high_s16Experimentalneon

Rounding Add returning High Narrow (high half).

vraddhn_high_s32Experimentalneon

Rounding Add returning High Narrow (high half).

vraddhn_high_s64Experimentalneon

Rounding Add returning High Narrow (high half).

vraddhn_high_u16Experimentalneon

Rounding Add returning High Narrow (high half).

vraddhn_high_u32Experimentalneon

Rounding Add returning High Narrow (high half).

vraddhn_high_u64Experimentalneon

Rounding Add returning High Narrow (high half).

vraddhn_s16Experimentalneon

Rounding Add returning High Narrow.

vraddhn_s32Experimentalneon

Rounding Add returning High Narrow.

vraddhn_s64Experimentalneon

Rounding Add returning High Narrow.

vraddhn_u16Experimentalneon

Rounding Add returning High Narrow.

vraddhn_u32Experimentalneon

Rounding Add returning High Narrow.

vraddhn_u64Experimentalneon

Rounding Add returning High Narrow.

vrax1q_u64Experimentalneon,sha3

Rotate and exclusive OR

vrecpe_f32Experimentalneon

Reciprocal estimate.

vrecpe_u32Experimentalneon

Unsigned reciprocal estimate

vrecpeq_f32Experimentalneon

Reciprocal estimate.

vrecpeq_u32Experimentalneon

Unsigned reciprocal estimate

vrecps_f32Experimentalneon

Floating-point reciprocal step

vrecpsq_f32Experimentalneon

Floating-point reciprocal step

vreinterpret_f32_p8Experimentalneon

Vector reinterpret cast operation

vreinterpret_f32_p16Experimentalneon

Vector reinterpret cast operation

vreinterpret_f32_s8Experimentalneon

Vector reinterpret cast operation

vreinterpret_f32_s16Experimentalneon

Vector reinterpret cast operation

vreinterpret_f32_s32Experimentalneon

Vector reinterpret cast operation

vreinterpret_f32_s64Experimentalneon

Vector reinterpret cast operation

vreinterpret_f32_u8Experimentalneon

Vector reinterpret cast operation

vreinterpret_f32_u16Experimentalneon

Vector reinterpret cast operation

vreinterpret_f32_u32Experimentalneon

Vector reinterpret cast operation

vreinterpret_f32_u64Experimentalneon

Vector reinterpret cast operation

vreinterpret_p8_f32Experimentalneon

Vector reinterpret cast operation

vreinterpret_p8_p16Experimentalneon

Vector reinterpret cast operation

vreinterpret_p8_p64Experimentalneon,aes

Vector reinterpret cast operation

vreinterpret_p8_s8Experimentalneon

Vector reinterpret cast operation

vreinterpret_p8_s16Experimentalneon

Vector reinterpret cast operation

vreinterpret_p8_s32Experimentalneon

Vector reinterpret cast operation

vreinterpret_p8_s64Experimentalneon

Vector reinterpret cast operation

vreinterpret_p8_u8Experimentalneon

Vector reinterpret cast operation

vreinterpret_p8_u16Experimentalneon

Vector reinterpret cast operation

vreinterpret_p8_u32Experimentalneon

Vector reinterpret cast operation

vreinterpret_p8_u64Experimentalneon

Vector reinterpret cast operation

vreinterpret_p16_f32Experimentalneon

Vector reinterpret cast operation

vreinterpret_p16_p8Experimentalneon

Vector reinterpret cast operation

vreinterpret_p16_p64Experimentalneon,aes

Vector reinterpret cast operation

vreinterpret_p16_s8Experimentalneon

Vector reinterpret cast operation

vreinterpret_p16_s16Experimentalneon

Vector reinterpret cast operation

vreinterpret_p16_s32Experimentalneon

Vector reinterpret cast operation

vreinterpret_p16_s64Experimentalneon

Vector reinterpret cast operation

vreinterpret_p16_u8Experimentalneon

Vector reinterpret cast operation

vreinterpret_p16_u16Experimentalneon

Vector reinterpret cast operation

vreinterpret_p16_u32Experimentalneon

Vector reinterpret cast operation

vreinterpret_p16_u64Experimentalneon

Vector reinterpret cast operation

vreinterpret_p64_p8Experimentalneon,aes

Vector reinterpret cast operation

vreinterpret_p64_p16Experimentalneon,aes

Vector reinterpret cast operation

vreinterpret_p64_s8Experimentalneon,aes

Vector reinterpret cast operation

vreinterpret_p64_s16Experimentalneon,aes

Vector reinterpret cast operation

vreinterpret_p64_s32Experimentalneon,aes

Vector reinterpret cast operation

vreinterpret_p64_u8Experimentalneon,aes

Vector reinterpret cast operation

vreinterpret_p64_u16Experimentalneon,aes

Vector reinterpret cast operation

vreinterpret_p64_u32Experimentalneon,aes

Vector reinterpret cast operation

vreinterpret_s8_f32Experimentalneon

Vector reinterpret cast operation

vreinterpret_s8_p8Experimentalneon

Vector reinterpret cast operation

vreinterpret_s8_p16Experimentalneon

Vector reinterpret cast operation

vreinterpret_s8_p64Experimentalneon,aes

Vector reinterpret cast operation

vreinterpret_s8_s16Experimentalneon

Vector reinterpret cast operation

vreinterpret_s8_s32Experimentalneon

Vector reinterpret cast operation

vreinterpret_s8_s64Experimentalneon

Vector reinterpret cast operation

vreinterpret_s8_u8Experimentalneon

Vector reinterpret cast operation

vreinterpret_s8_u16Experimentalneon

Vector reinterpret cast operation

vreinterpret_s8_u32Experimentalneon

Vector reinterpret cast operation

vreinterpret_s8_u64Experimentalneon

Vector reinterpret cast operation

vreinterpret_s16_f32Experimentalneon

Vector reinterpret cast operation

vreinterpret_s16_p8Experimentalneon

Vector reinterpret cast operation

vreinterpret_s16_p16Experimentalneon

Vector reinterpret cast operation

vreinterpret_s16_p64Experimentalneon,aes

Vector reinterpret cast operation

vreinterpret_s16_s8Experimentalneon

Vector reinterpret cast operation

vreinterpret_s16_s32Experimentalneon

Vector reinterpret cast operation

vreinterpret_s16_s64Experimentalneon

Vector reinterpret cast operation

vreinterpret_s16_u8Experimentalneon

Vector reinterpret cast operation

vreinterpret_s16_u16Experimentalneon

Vector reinterpret cast operation

vreinterpret_s16_u32Experimentalneon

Vector reinterpret cast operation

vreinterpret_s16_u64Experimentalneon

Vector reinterpret cast operation

vreinterpret_s32_f32Experimentalneon

Vector reinterpret cast operation

vreinterpret_s32_p8Experimentalneon

Vector reinterpret cast operation

vreinterpret_s32_p16Experimentalneon

Vector reinterpret cast operation

vreinterpret_s32_p64Experimentalneon,aes

Vector reinterpret cast operation

vreinterpret_s32_s8Experimentalneon

Vector reinterpret cast operation

vreinterpret_s32_s16Experimentalneon

Vector reinterpret cast operation

vreinterpret_s32_s64Experimentalneon

Vector reinterpret cast operation

vreinterpret_s32_u8Experimentalneon

Vector reinterpret cast operation

vreinterpret_s32_u16Experimentalneon

Vector reinterpret cast operation

vreinterpret_s32_u32Experimentalneon

Vector reinterpret cast operation

vreinterpret_s32_u64Experimentalneon

Vector reinterpret cast operation

vreinterpret_s64_f32Experimentalneon

Vector reinterpret cast operation

vreinterpret_s64_p8Experimentalneon

Vector reinterpret cast operation

vreinterpret_s64_p16Experimentalneon

Vector reinterpret cast operation

vreinterpret_s64_s8Experimentalneon

Vector reinterpret cast operation

vreinterpret_s64_s16Experimentalneon

Vector reinterpret cast operation

vreinterpret_s64_s32Experimentalneon

Vector reinterpret cast operation

vreinterpret_s64_u8Experimentalneon

Vector reinterpret cast operation

vreinterpret_s64_u16Experimentalneon

Vector reinterpret cast operation

vreinterpret_s64_u32Experimentalneon

Vector reinterpret cast operation

vreinterpret_s64_u64Experimentalneon

Vector reinterpret cast operation

vreinterpret_u8_f32Experimentalneon

Vector reinterpret cast operation

vreinterpret_u8_p8Experimentalneon

Vector reinterpret cast operation

vreinterpret_u8_p16Experimentalneon

Vector reinterpret cast operation

vreinterpret_u8_p64Experimentalneon,aes

Vector reinterpret cast operation

vreinterpret_u8_s8Experimentalneon

Vector reinterpret cast operation

vreinterpret_u8_s16Experimentalneon

Vector reinterpret cast operation

vreinterpret_u8_s32Experimentalneon

Vector reinterpret cast operation

vreinterpret_u8_s64Experimentalneon

Vector reinterpret cast operation

vreinterpret_u8_u16Experimentalneon

Vector reinterpret cast operation

vreinterpret_u8_u32Experimentalneon

Vector reinterpret cast operation

vreinterpret_u8_u64Experimentalneon

Vector reinterpret cast operation

vreinterpret_u16_f32Experimentalneon

Vector reinterpret cast operation

vreinterpret_u16_p8Experimentalneon

Vector reinterpret cast operation

vreinterpret_u16_p16Experimentalneon

Vector reinterpret cast operation

vreinterpret_u16_p64Experimentalneon,aes

Vector reinterpret cast operation

vreinterpret_u16_s8Experimentalneon

Vector reinterpret cast operation

vreinterpret_u16_s16Experimentalneon

Vector reinterpret cast operation

vreinterpret_u16_s32Experimentalneon

Vector reinterpret cast operation

vreinterpret_u16_s64Experimentalneon

Vector reinterpret cast operation

vreinterpret_u16_u8Experimentalneon

Vector reinterpret cast operation

vreinterpret_u16_u32Experimentalneon

Vector reinterpret cast operation

vreinterpret_u16_u64Experimentalneon

Vector reinterpret cast operation

vreinterpret_u32_f32Experimentalneon

Vector reinterpret cast operation

vreinterpret_u32_p8Experimentalneon

Vector reinterpret cast operation

vreinterpret_u32_p16Experimentalneon

Vector reinterpret cast operation

vreinterpret_u32_p64Experimentalneon,aes

Vector reinterpret cast operation

vreinterpret_u32_s8Experimentalneon

Vector reinterpret cast operation

vreinterpret_u32_s16Experimentalneon

Vector reinterpret cast operation

vreinterpret_u32_s32Experimentalneon

Vector reinterpret cast operation

vreinterpret_u32_s64Experimentalneon

Vector reinterpret cast operation

vreinterpret_u32_u8Experimentalneon

Vector reinterpret cast operation

vreinterpret_u32_u16Experimentalneon

Vector reinterpret cast operation

vreinterpret_u32_u64Experimentalneon

Vector reinterpret cast operation

vreinterpret_u64_f32Experimentalneon

Vector reinterpret cast operation

vreinterpret_u64_p8Experimentalneon

Vector reinterpret cast operation

vreinterpret_u64_p16Experimentalneon

Vector reinterpret cast operation

vreinterpret_u64_s8Experimentalneon

Vector reinterpret cast operation

vreinterpret_u64_s16Experimentalneon

Vector reinterpret cast operation

vreinterpret_u64_s32Experimentalneon

Vector reinterpret cast operation

vreinterpret_u64_s64Experimentalneon

Vector reinterpret cast operation

vreinterpret_u64_u8Experimentalneon

Vector reinterpret cast operation

vreinterpret_u64_u16Experimentalneon

Vector reinterpret cast operation

vreinterpret_u64_u32Experimentalneon

Vector reinterpret cast operation

vreinterpretq_f32_p8Experimentalneon

Vector reinterpret cast operation

vreinterpretq_f32_p16Experimentalneon

Vector reinterpret cast operation

Vector reinterpret cast operation

vreinterpretq_f32_s8Experimentalneon

Vector reinterpret cast operation

vreinterpretq_f32_s16Experimentalneon

Vector reinterpret cast operation

vreinterpretq_f32_s32Experimentalneon

Vector reinterpret cast operation

vreinterpretq_f32_s64Experimentalneon

Vector reinterpret cast operation

vreinterpretq_f32_u8Experimentalneon

Vector reinterpret cast operation

vreinterpretq_f32_u16Experimentalneon

Vector reinterpret cast operation

vreinterpretq_f32_u32Experimentalneon

Vector reinterpret cast operation

vreinterpretq_f32_u64Experimentalneon

Vector reinterpret cast operation

vreinterpretq_p8_f32Experimentalneon

Vector reinterpret cast operation

vreinterpretq_p8_p16Experimentalneon

Vector reinterpret cast operation

vreinterpretq_p8_p64Experimentalneon,aes

Vector reinterpret cast operation

vreinterpretq_p8_p128Experimentalneon,aes

Vector reinterpret cast operation

vreinterpretq_p8_s8Experimentalneon

Vector reinterpret cast operation

vreinterpretq_p8_s16Experimentalneon

Vector reinterpret cast operation

vreinterpretq_p8_s32Experimentalneon

Vector reinterpret cast operation

vreinterpretq_p8_s64Experimentalneon

Vector reinterpret cast operation

vreinterpretq_p8_u8Experimentalneon

Vector reinterpret cast operation

vreinterpretq_p8_u16Experimentalneon

Vector reinterpret cast operation

vreinterpretq_p8_u32Experimentalneon

Vector reinterpret cast operation

vreinterpretq_p8_u64Experimentalneon

Vector reinterpret cast operation

vreinterpretq_p16_f32Experimentalneon

Vector reinterpret cast operation

vreinterpretq_p16_p8Experimentalneon

Vector reinterpret cast operation

vreinterpretq_p16_p64Experimentalneon,aes

Vector reinterpret cast operation

vreinterpretq_p16_p128Experimentalneon,aes

Vector reinterpret cast operation

vreinterpretq_p16_s8Experimentalneon

Vector reinterpret cast operation

vreinterpretq_p16_s16Experimentalneon

Vector reinterpret cast operation

vreinterpretq_p16_s32Experimentalneon

Vector reinterpret cast operation

vreinterpretq_p16_s64Experimentalneon

Vector reinterpret cast operation

vreinterpretq_p16_u8Experimentalneon

Vector reinterpret cast operation

vreinterpretq_p16_u16Experimentalneon

Vector reinterpret cast operation

vreinterpretq_p16_u32Experimentalneon

Vector reinterpret cast operation

vreinterpretq_p16_u64Experimentalneon

Vector reinterpret cast operation

vreinterpretq_p64_p8Experimentalneon,aes

Vector reinterpret cast operation

vreinterpretq_p64_p16Experimentalneon,aes

Vector reinterpret cast operation

vreinterpretq_p64_p128Experimentalneon,aes

Vector reinterpret cast operation

vreinterpretq_p64_s8Experimentalneon,aes

Vector reinterpret cast operation

vreinterpretq_p64_s16Experimentalneon,aes

Vector reinterpret cast operation

vreinterpretq_p64_s32Experimentalneon,aes

Vector reinterpret cast operation

vreinterpretq_p64_u8Experimentalneon,aes

Vector reinterpret cast operation

vreinterpretq_p64_u16Experimentalneon,aes

Vector reinterpret cast operation

vreinterpretq_p64_u32Experimentalneon,aes

Vector reinterpret cast operation

Vector reinterpret cast operation

vreinterpretq_p128_p8Experimentalneon,aes

Vector reinterpret cast operation

vreinterpretq_p128_p16Experimentalneon,aes

Vector reinterpret cast operation

vreinterpretq_p128_p64Experimentalneon,aes

Vector reinterpret cast operation

vreinterpretq_p128_s8Experimentalneon,aes

Vector reinterpret cast operation

vreinterpretq_p128_s16Experimentalneon,aes

Vector reinterpret cast operation

vreinterpretq_p128_s32Experimentalneon,aes

Vector reinterpret cast operation

vreinterpretq_p128_s64Experimentalneon,aes

Vector reinterpret cast operation

vreinterpretq_p128_u8Experimentalneon,aes

Vector reinterpret cast operation

vreinterpretq_p128_u16Experimentalneon,aes

Vector reinterpret cast operation

vreinterpretq_p128_u32Experimentalneon,aes

Vector reinterpret cast operation

vreinterpretq_p128_u64Experimentalneon,aes

Vector reinterpret cast operation

vreinterpretq_s8_f32Experimentalneon

Vector reinterpret cast operation

vreinterpretq_s8_p8Experimentalneon

Vector reinterpret cast operation

vreinterpretq_s8_p16Experimentalneon

Vector reinterpret cast operation

vreinterpretq_s8_p64Experimentalneon,aes

Vector reinterpret cast operation

vreinterpretq_s8_p128Experimentalneon,aes

Vector reinterpret cast operation

vreinterpretq_s8_s16Experimentalneon

Vector reinterpret cast operation

vreinterpretq_s8_s32Experimentalneon

Vector reinterpret cast operation

vreinterpretq_s8_s64Experimentalneon

Vector reinterpret cast operation

vreinterpretq_s8_u8Experimentalneon

Vector reinterpret cast operation

vreinterpretq_s8_u16Experimentalneon

Vector reinterpret cast operation

vreinterpretq_s8_u32Experimentalneon

Vector reinterpret cast operation

vreinterpretq_s8_u64Experimentalneon

Vector reinterpret cast operation

vreinterpretq_s16_f32Experimentalneon

Vector reinterpret cast operation

vreinterpretq_s16_p8Experimentalneon

Vector reinterpret cast operation

vreinterpretq_s16_p16Experimentalneon

Vector reinterpret cast operation

vreinterpretq_s16_p64Experimentalneon,aes

Vector reinterpret cast operation

vreinterpretq_s16_p128Experimentalneon,aes

Vector reinterpret cast operation

vreinterpretq_s16_s8Experimentalneon

Vector reinterpret cast operation

vreinterpretq_s16_s32Experimentalneon

Vector reinterpret cast operation

vreinterpretq_s16_s64Experimentalneon

Vector reinterpret cast operation

vreinterpretq_s16_u8Experimentalneon

Vector reinterpret cast operation

vreinterpretq_s16_u16Experimentalneon

Vector reinterpret cast operation

vreinterpretq_s16_u32Experimentalneon

Vector reinterpret cast operation

vreinterpretq_s16_u64Experimentalneon

Vector reinterpret cast operation

vreinterpretq_s32_f32Experimentalneon

Vector reinterpret cast operation

vreinterpretq_s32_p8Experimentalneon

Vector reinterpret cast operation

vreinterpretq_s32_p16Experimentalneon

Vector reinterpret cast operation

vreinterpretq_s32_p64Experimentalneon,aes

Vector reinterpret cast operation

vreinterpretq_s32_p128Experimentalneon,aes

Vector reinterpret cast operation

vreinterpretq_s32_s8Experimentalneon

Vector reinterpret cast operation

vreinterpretq_s32_s16Experimentalneon

Vector reinterpret cast operation

vreinterpretq_s32_s64Experimentalneon

Vector reinterpret cast operation

vreinterpretq_s32_u8Experimentalneon

Vector reinterpret cast operation

vreinterpretq_s32_u16Experimentalneon

Vector reinterpret cast operation

vreinterpretq_s32_u32Experimentalneon

Vector reinterpret cast operation

vreinterpretq_s32_u64Experimentalneon

Vector reinterpret cast operation

vreinterpretq_s64_f32Experimentalneon

Vector reinterpret cast operation

vreinterpretq_s64_p8Experimentalneon

Vector reinterpret cast operation

vreinterpretq_s64_p16Experimentalneon

Vector reinterpret cast operation

vreinterpretq_s64_p128Experimentalneon,aes

Vector reinterpret cast operation

vreinterpretq_s64_s8Experimentalneon

Vector reinterpret cast operation

vreinterpretq_s64_s16Experimentalneon

Vector reinterpret cast operation

vreinterpretq_s64_s32Experimentalneon

Vector reinterpret cast operation

vreinterpretq_s64_u8Experimentalneon

Vector reinterpret cast operation

vreinterpretq_s64_u16Experimentalneon

Vector reinterpret cast operation

vreinterpretq_s64_u32Experimentalneon

Vector reinterpret cast operation

vreinterpretq_s64_u64Experimentalneon

Vector reinterpret cast operation

vreinterpretq_u8_f32Experimentalneon

Vector reinterpret cast operation

vreinterpretq_u8_p8Experimentalneon

Vector reinterpret cast operation

vreinterpretq_u8_p16Experimentalneon

Vector reinterpret cast operation

vreinterpretq_u8_p64Experimentalneon,aes

Vector reinterpret cast operation

vreinterpretq_u8_p128Experimentalneon,aes

Vector reinterpret cast operation

vreinterpretq_u8_s8Experimentalneon

Vector reinterpret cast operation

vreinterpretq_u8_s16Experimentalneon

Vector reinterpret cast operation

vreinterpretq_u8_s32Experimentalneon

Vector reinterpret cast operation

vreinterpretq_u8_s64Experimentalneon

Vector reinterpret cast operation

vreinterpretq_u8_u16Experimentalneon

Vector reinterpret cast operation

vreinterpretq_u8_u32Experimentalneon

Vector reinterpret cast operation

vreinterpretq_u8_u64Experimentalneon

Vector reinterpret cast operation

vreinterpretq_u16_f32Experimentalneon

Vector reinterpret cast operation

vreinterpretq_u16_p8Experimentalneon

Vector reinterpret cast operation

vreinterpretq_u16_p16Experimentalneon

Vector reinterpret cast operation

vreinterpretq_u16_p64Experimentalneon,aes

Vector reinterpret cast operation

vreinterpretq_u16_p128Experimentalneon,aes

Vector reinterpret cast operation

vreinterpretq_u16_s8Experimentalneon

Vector reinterpret cast operation

vreinterpretq_u16_s16Experimentalneon

Vector reinterpret cast operation

vreinterpretq_u16_s32Experimentalneon

Vector reinterpret cast operation

vreinterpretq_u16_s64Experimentalneon

Vector reinterpret cast operation

vreinterpretq_u16_u8Experimentalneon

Vector reinterpret cast operation

vreinterpretq_u16_u32Experimentalneon

Vector reinterpret cast operation

vreinterpretq_u16_u64Experimentalneon

Vector reinterpret cast operation

vreinterpretq_u32_f32Experimentalneon

Vector reinterpret cast operation

vreinterpretq_u32_p8Experimentalneon

Vector reinterpret cast operation

vreinterpretq_u32_p16Experimentalneon

Vector reinterpret cast operation

vreinterpretq_u32_p64Experimentalneon,aes

Vector reinterpret cast operation

vreinterpretq_u32_p128Experimentalneon,aes

Vector reinterpret cast operation

vreinterpretq_u32_s8Experimentalneon

Vector reinterpret cast operation

vreinterpretq_u32_s16Experimentalneon

Vector reinterpret cast operation

vreinterpretq_u32_s32Experimentalneon

Vector reinterpret cast operation

vreinterpretq_u32_s64Experimentalneon

Vector reinterpret cast operation

vreinterpretq_u32_u8Experimentalneon

Vector reinterpret cast operation

vreinterpretq_u32_u16Experimentalneon

Vector reinterpret cast operation

vreinterpretq_u32_u64Experimentalneon

Vector reinterpret cast operation

vreinterpretq_u64_f32Experimentalneon

Vector reinterpret cast operation

vreinterpretq_u64_p8Experimentalneon

Vector reinterpret cast operation

vreinterpretq_u64_p16Experimentalneon

Vector reinterpret cast operation

vreinterpretq_u64_p128Experimentalneon,aes

Vector reinterpret cast operation

vreinterpretq_u64_s8Experimentalneon

Vector reinterpret cast operation

vreinterpretq_u64_s16Experimentalneon

Vector reinterpret cast operation

vreinterpretq_u64_s32Experimentalneon

Vector reinterpret cast operation

vreinterpretq_u64_s64Experimentalneon

Vector reinterpret cast operation

vreinterpretq_u64_u8Experimentalneon

Vector reinterpret cast operation

vreinterpretq_u64_u16Experimentalneon

Vector reinterpret cast operation

vreinterpretq_u64_u32Experimentalneon

Vector reinterpret cast operation

vrev16_p8Experimentalneon

Reversing vector elements (swap endianness)

vrev16_s8Experimentalneon

Reversing vector elements (swap endianness)

vrev16_u8Experimentalneon

Reversing vector elements (swap endianness)

vrev16q_p8Experimentalneon

Reversing vector elements (swap endianness)

vrev16q_s8Experimentalneon

Reversing vector elements (swap endianness)

vrev16q_u8Experimentalneon

Reversing vector elements (swap endianness)

vrev32_p8Experimentalneon

Reversing vector elements (swap endianness)

vrev32_p16Experimentalneon

Reversing vector elements (swap endianness)

vrev32_s8Experimentalneon

Reversing vector elements (swap endianness)

vrev32_s16Experimentalneon

Reversing vector elements (swap endianness)

vrev32_u8Experimentalneon

Reversing vector elements (swap endianness)

vrev32_u16Experimentalneon

Reversing vector elements (swap endianness)

vrev32q_p8Experimentalneon

Reversing vector elements (swap endianness)

vrev32q_p16Experimentalneon

Reversing vector elements (swap endianness)

vrev32q_s8Experimentalneon

Reversing vector elements (swap endianness)

vrev32q_s16Experimentalneon

Reversing vector elements (swap endianness)

vrev32q_u8Experimentalneon

Reversing vector elements (swap endianness)

vrev32q_u16Experimentalneon

Reversing vector elements (swap endianness)

vrev64_f32Experimentalneon

Reversing vector elements (swap endianness)

vrev64_p8Experimentalneon

Reversing vector elements (swap endianness)

vrev64_p16Experimentalneon

Reversing vector elements (swap endianness)

vrev64_s8Experimentalneon

Reversing vector elements (swap endianness)

vrev64_s16Experimentalneon

Reversing vector elements (swap endianness)

vrev64_s32Experimentalneon

Reversing vector elements (swap endianness)

vrev64_u8Experimentalneon

Reversing vector elements (swap endianness)

vrev64_u16Experimentalneon

Reversing vector elements (swap endianness)

vrev64_u32Experimentalneon

Reversing vector elements (swap endianness)

vrev64q_f32Experimentalneon

Reversing vector elements (swap endianness)

vrev64q_p8Experimentalneon

Reversing vector elements (swap endianness)

vrev64q_p16Experimentalneon

Reversing vector elements (swap endianness)

vrev64q_s8Experimentalneon

Reversing vector elements (swap endianness)

vrev64q_s16Experimentalneon

Reversing vector elements (swap endianness)

vrev64q_s32Experimentalneon

Reversing vector elements (swap endianness)

vrev64q_u8Experimentalneon

Reversing vector elements (swap endianness)

vrev64q_u16Experimentalneon

Reversing vector elements (swap endianness)

vrev64q_u32Experimentalneon

Reversing vector elements (swap endianness)

vrhadd_s8Experimentalneon

Rounding halving add

vrhadd_s16Experimentalneon

Rounding halving add

vrhadd_s32Experimentalneon

Rounding halving add

vrhadd_u8Experimentalneon

Rounding halving add

vrhadd_u16Experimentalneon

Rounding halving add

vrhadd_u32Experimentalneon

Rounding halving add

vrhaddq_s8Experimentalneon

Rounding halving add

vrhaddq_s16Experimentalneon

Rounding halving add

vrhaddq_s32Experimentalneon

Rounding halving add

vrhaddq_u8Experimentalneon

Rounding halving add

vrhaddq_u16Experimentalneon

Rounding halving add

vrhaddq_u32Experimentalneon

Rounding halving add

vrnd32x_f32Experimentalneon,frintts

Floating-point round to 32-bit integer, using current rounding mode

vrnd32xq_f32Experimentalneon,frintts

Floating-point round to 32-bit integer, using current rounding mode

vrnd32z_f32Experimentalneon,frintts

Floating-point round to 32-bit integer toward zero

vrnd32zq_f32Experimentalneon,frintts

Floating-point round to 32-bit integer toward zero

vrnd64x_f32Experimentalneon,frintts

Floating-point round to 64-bit integer, using current rounding mode

vrnd64xq_f32Experimentalneon,frintts

Floating-point round to 64-bit integer, using current rounding mode

vrnd64z_f32Experimentalneon,frintts

Floating-point round to 64-bit integer toward zero

vrnd64zq_f32Experimentalneon,frintts

Floating-point round to 64-bit integer toward zero

vrndn_f32Experimentalneon

Floating-point round to integral, to nearest with ties to even

vrndnq_f32Experimentalneon

Floating-point round to integral, to nearest with ties to even

vrshl_s8Experimentalneon

Signed rounding shift left

vrshl_s16Experimentalneon

Signed rounding shift left

vrshl_s32Experimentalneon

Signed rounding shift left

vrshl_s64Experimentalneon

Signed rounding shift left

vrshl_u8Experimentalneon

Unsigned rounding shift left

vrshl_u16Experimentalneon

Unsigned rounding shift left

vrshl_u32Experimentalneon

Unsigned rounding shift left

vrshl_u64Experimentalneon

Unsigned rounding shift left

vrshlq_s8Experimentalneon

Signed rounding shift left

vrshlq_s16Experimentalneon

Signed rounding shift left

vrshlq_s32Experimentalneon

Signed rounding shift left

vrshlq_s64Experimentalneon

Signed rounding shift left

vrshlq_u8Experimentalneon

Unsigned rounding shift left

vrshlq_u16Experimentalneon

Unsigned rounding shift left

vrshlq_u32Experimentalneon

Unsigned rounding shift left

vrshlq_u64Experimentalneon

Unsigned rounding shift left

vrshr_n_s8Experimentalneon

Signed rounding shift right

vrshr_n_s16Experimentalneon

Signed rounding shift right

vrshr_n_s32Experimentalneon

Signed rounding shift right

vrshr_n_s64Experimentalneon

Signed rounding shift right

vrshr_n_u8Experimentalneon

Unsigned rounding shift right

vrshr_n_u16Experimentalneon

Unsigned rounding shift right

vrshr_n_u32Experimentalneon

Unsigned rounding shift right

vrshr_n_u64Experimentalneon

Unsigned rounding shift right

vrshrn_n_u16Experimentalneon

Rounding shift right narrow

vrshrn_n_u32Experimentalneon

Rounding shift right narrow

vrshrn_n_u64Experimentalneon

Rounding shift right narrow

vrshrq_n_s8Experimentalneon

Signed rounding shift right

vrshrq_n_s16Experimentalneon

Signed rounding shift right

vrshrq_n_s32Experimentalneon

Signed rounding shift right

vrshrq_n_s64Experimentalneon

Signed rounding shift right

vrshrq_n_u8Experimentalneon

Unsigned rounding shift right

vrshrq_n_u16Experimentalneon

Unsigned rounding shift right

vrshrq_n_u32Experimentalneon

Unsigned rounding shift right

vrshrq_n_u64Experimentalneon

Unsigned rounding shift right

vrsqrte_f32Experimentalneon

Reciprocal square-root estimate.

vrsqrte_u32Experimentalneon

Unsigned reciprocal square root estimate

vrsqrteq_f32Experimentalneon

Reciprocal square-root estimate.

vrsqrteq_u32Experimentalneon

Unsigned reciprocal square root estimate

vrsqrts_f32Experimentalneon

Floating-point reciprocal square root step

vrsqrtsq_f32Experimentalneon

Floating-point reciprocal square root step

vrsra_n_s8Experimentalneon

Signed rounding shift right and accumulate

vrsra_n_s16Experimentalneon

Signed rounding shift right and accumulate

vrsra_n_s32Experimentalneon

Signed rounding shift right and accumulate

vrsra_n_s64Experimentalneon

Signed rounding shift right and accumulate

vrsra_n_u8Experimentalneon

Unsigned rounding shift right and accumulate

vrsra_n_u16Experimentalneon

Unsigned rounding shift right and accumulate

vrsra_n_u32Experimentalneon

Unsigned rounding shift right and accumulate

vrsra_n_u64Experimentalneon

Unsigned rounding shift right and accumulate

vrsraq_n_s8Experimentalneon

Signed rounding shift right and accumulate

vrsraq_n_s16Experimentalneon

Signed rounding shift right and accumulate

vrsraq_n_s32Experimentalneon

Signed rounding shift right and accumulate

vrsraq_n_s64Experimentalneon

Signed rounding shift right and accumulate

vrsraq_n_u8Experimentalneon

Unsigned rounding shift right and accumulate

vrsraq_n_u16Experimentalneon

Unsigned rounding shift right and accumulate

vrsraq_n_u32Experimentalneon

Unsigned rounding shift right and accumulate

vrsraq_n_u64Experimentalneon

Unsigned rounding shift right and accumulate

vrsubhn_s16Experimentalneon

Rounding subtract returning high narrow

vrsubhn_s32Experimentalneon

Rounding subtract returning high narrow

vrsubhn_s64Experimentalneon

Rounding subtract returning high narrow

vrsubhn_u16Experimentalneon

Rounding subtract returning high narrow

vrsubhn_u32Experimentalneon

Rounding subtract returning high narrow

vrsubhn_u64Experimentalneon

Rounding subtract returning high narrow

vset_lane_f32Experimentalneon

Insert vector element from another vector element

vset_lane_p8Experimentalneon

Insert vector element from another vector element

vset_lane_p16Experimentalneon

Insert vector element from another vector element

vset_lane_p64Experimentalneon,aes

Insert vector element from another vector element

vset_lane_s8Experimentalneon

Insert vector element from another vector element

vset_lane_s16Experimentalneon

Insert vector element from another vector element

vset_lane_s32Experimentalneon

Insert vector element from another vector element

vset_lane_s64Experimentalneon

Insert vector element from another vector element

vset_lane_u8Experimentalneon

Insert vector element from another vector element

vset_lane_u16Experimentalneon

Insert vector element from another vector element

vset_lane_u32Experimentalneon

Insert vector element from another vector element

vset_lane_u64Experimentalneon

Insert vector element from another vector element

vsetq_lane_f32Experimentalneon

Insert vector element from another vector element

vsetq_lane_p8Experimentalneon

Insert vector element from another vector element

vsetq_lane_p16Experimentalneon

Insert vector element from another vector element

vsetq_lane_p64Experimentalneon,aes

Insert vector element from another vector element

vsetq_lane_s8Experimentalneon

Insert vector element from another vector element

vsetq_lane_s16Experimentalneon

Insert vector element from another vector element

vsetq_lane_s32Experimentalneon

Insert vector element from another vector element

vsetq_lane_s64Experimentalneon

Insert vector element from another vector element

vsetq_lane_u8Experimentalneon

Insert vector element from another vector element

vsetq_lane_u16Experimentalneon

Insert vector element from another vector element

vsetq_lane_u32Experimentalneon

Insert vector element from another vector element

vsetq_lane_u64Experimentalneon

Insert vector element from another vector element

vsha1cq_u32Experimentalsha2

SHA1 hash update accelerator, choose.

vsha1h_u32Experimentalsha2

SHA1 fixed rotate.

vsha1mq_u32Experimentalsha2

SHA1 hash update accelerator, majority.

vsha1pq_u32Experimentalsha2

SHA1 hash update accelerator, parity.

vsha1su0q_u32Experimentalsha2

SHA1 schedule update accelerator, first part.

vsha1su1q_u32Experimentalsha2

SHA1 schedule update accelerator, second part.

vsha256h2q_u32Experimentalsha2

SHA256 hash update accelerator, upper part.

vsha256hq_u32Experimentalsha2

SHA256 hash update accelerator.

vsha256su0q_u32Experimentalsha2

SHA256 schedule update accelerator, first part.

vsha256su1q_u32Experimentalsha2

SHA256 schedule update accelerator, second part.

vsha512h2q_u64Experimentalneon,sha3

SHA512 hash update part 2

vsha512hq_u64Experimentalneon,sha3

SHA512 hash update part 1

vsha512su0q_u64Experimentalneon,sha3

SHA512 schedule update 0

vsha512su1q_u64Experimentalneon,sha3

SHA512 schedule update 1

vshl_n_s8Experimentalneon

Shift left

vshl_n_s16Experimentalneon

Shift left

vshl_n_s32Experimentalneon

Shift left

vshl_n_s64Experimentalneon

Shift left

vshl_n_u8Experimentalneon

Shift left

vshl_n_u16Experimentalneon

Shift left

vshl_n_u32Experimentalneon

Shift left

vshl_n_u64Experimentalneon

Shift left

vshl_s8Experimentalneon

Signed Shift left

vshl_s16Experimentalneon

Signed Shift left

vshl_s32Experimentalneon

Signed Shift left

vshl_s64Experimentalneon

Signed Shift left

vshl_u8Experimentalneon

Unsigned Shift left

vshl_u16Experimentalneon

Unsigned Shift left

vshl_u32Experimentalneon

Unsigned Shift left

vshl_u64Experimentalneon

Unsigned Shift left

vshll_n_s8Experimentalneon

Signed shift left long

vshll_n_s16Experimentalneon

Signed shift left long

vshll_n_s32Experimentalneon

Signed shift left long

vshll_n_u8Experimentalneon

Signed shift left long

vshll_n_u16Experimentalneon

Signed shift left long

vshll_n_u32Experimentalneon

Signed shift left long

vshlq_n_s8Experimentalneon

Shift left

vshlq_n_s16Experimentalneon

Shift left

vshlq_n_s32Experimentalneon

Shift left

vshlq_n_s64Experimentalneon

Shift left

vshlq_n_u8Experimentalneon

Shift left

vshlq_n_u16Experimentalneon

Shift left

vshlq_n_u32Experimentalneon

Shift left

vshlq_n_u64Experimentalneon

Shift left

vshlq_s8Experimentalneon

Signed Shift left

vshlq_s16Experimentalneon

Signed Shift left

vshlq_s32Experimentalneon

Signed Shift left

vshlq_s64Experimentalneon

Signed Shift left

vshlq_u8Experimentalneon

Unsigned Shift left

vshlq_u16Experimentalneon

Unsigned Shift left

vshlq_u32Experimentalneon

Unsigned Shift left

vshlq_u64Experimentalneon

Unsigned Shift left

vshr_n_s8Experimentalneon

Shift right

vshr_n_s16Experimentalneon

Shift right

vshr_n_s32Experimentalneon

Shift right

vshr_n_s64Experimentalneon

Shift right

vshr_n_u8Experimentalneon

Shift right

vshr_n_u16Experimentalneon

Shift right

vshr_n_u32Experimentalneon

Shift right

vshr_n_u64Experimentalneon

Shift right

vshrn_n_s16Experimentalneon

Shift right narrow

vshrn_n_s32Experimentalneon

Shift right narrow

vshrn_n_s64Experimentalneon

Shift right narrow

vshrn_n_u16Experimentalneon

Shift right narrow

vshrn_n_u32Experimentalneon

Shift right narrow

vshrn_n_u64Experimentalneon

Shift right narrow

vshrq_n_s8Experimentalneon

Shift right

vshrq_n_s16Experimentalneon

Shift right

vshrq_n_s32Experimentalneon

Shift right

vshrq_n_s64Experimentalneon

Shift right

vshrq_n_u8Experimentalneon

Shift right

vshrq_n_u16Experimentalneon

Shift right

vshrq_n_u32Experimentalneon

Shift right

vshrq_n_u64Experimentalneon

Shift right

vsm3partw1q_u32Experimentalneon,sm4

SM3PARTW1

vsm3partw2q_u32Experimentalneon,sm4

SM3PARTW2

vsm3ss1q_u32Experimentalneon,sm4

SM3SS1

vsm3tt1aq_u32Experimentalneon,sm4

SM3TT1A

vsm3tt1bq_u32Experimentalneon,sm4

SM3TT1B

vsm3tt2aq_u32Experimentalneon,sm4

SM3TT2A

vsm3tt2bq_u32Experimentalneon,sm4

SM3TT2B

vsm4ekeyq_u32Experimentalneon,sm4

SM4 key

vsm4eq_u32Experimentalneon,sm4

SM4 encode

vsra_n_s8Experimentalneon

Signed shift right and accumulate

vsra_n_s16Experimentalneon

Signed shift right and accumulate

vsra_n_s32Experimentalneon

Signed shift right and accumulate

vsra_n_s64Experimentalneon

Signed shift right and accumulate

vsra_n_u8Experimentalneon

Unsigned shift right and accumulate

vsra_n_u16Experimentalneon

Unsigned shift right and accumulate

vsra_n_u32Experimentalneon

Unsigned shift right and accumulate

vsra_n_u64Experimentalneon

Unsigned shift right and accumulate

vsraq_n_s8Experimentalneon

Signed shift right and accumulate

vsraq_n_s16Experimentalneon

Signed shift right and accumulate

vsraq_n_s32Experimentalneon

Signed shift right and accumulate

vsraq_n_s64Experimentalneon

Signed shift right and accumulate

vsraq_n_u8Experimentalneon

Unsigned shift right and accumulate

vsraq_n_u16Experimentalneon

Unsigned shift right and accumulate

vsraq_n_u32Experimentalneon

Unsigned shift right and accumulate

vsraq_n_u64Experimentalneon

Unsigned shift right and accumulate

vst1_lane_f32Experimentalneon

Store multiple single-element structures from one, two, three, or four registers

vst1_lane_p8Experimentalneon

Store multiple single-element structures from one, two, three, or four registers

vst1_lane_p16Experimentalneon

Store multiple single-element structures from one, two, three, or four registers

vst1_lane_p64Experimentalneon,aes

Store multiple single-element structures from one, two, three, or four registers

vst1_lane_s8Experimentalneon

Store multiple single-element structures from one, two, three, or four registers

vst1_lane_s16Experimentalneon

Store multiple single-element structures from one, two, three, or four registers

vst1_lane_s32Experimentalneon

Store multiple single-element structures from one, two, three, or four registers

vst1_lane_s64Experimentalneon

Store multiple single-element structures from one, two, three, or four registers

vst1_lane_u8Experimentalneon

Store multiple single-element structures from one, two, three, or four registers

vst1_lane_u16Experimentalneon

Store multiple single-element structures from one, two, three, or four registers

vst1_lane_u32Experimentalneon

Store multiple single-element structures from one, two, three, or four registers

vst1_lane_u64Experimentalneon

Store multiple single-element structures from one, two, three, or four registers

vst1_p8_x2Experimentalneon

Store multiple single-element structures to one, two, three, or four registers

vst1_p8_x3Experimentalneon

Store multiple single-element structures to one, two, three, or four registers

vst1_p8_x4Experimentalneon

Store multiple single-element structures to one, two, three, or four registers

vst1_p16_x2Experimentalneon

Store multiple single-element structures to one, two, three, or four registers

vst1_p16_x3Experimentalneon

Store multiple single-element structures to one, two, three, or four registers

vst1_p16_x4Experimentalneon

Store multiple single-element structures to one, two, three, or four registers

vst1_p64_x2Experimentalneon,aes

Store multiple single-element structures to one, two, three, or four registers

vst1_p64_x3Experimentalneon,aes

Store multiple single-element structures to one, two, three, or four registers

vst1_p64_x4Experimentalneon,aes

Store multiple single-element structures to one, two, three, or four registers

vst1_u8_x2Experimentalneon

Store multiple single-element structures to one, two, three, or four registers

vst1_u8_x3Experimentalneon

Store multiple single-element structures to one, two, three, or four registers

vst1_u8_x4Experimentalneon

Store multiple single-element structures to one, two, three, or four registers

vst1_u16_x2Experimentalneon

Store multiple single-element structures to one, two, three, or four registers

vst1_u16_x3Experimentalneon

Store multiple single-element structures to one, two, three, or four registers

vst1_u16_x4Experimentalneon

Store multiple single-element structures to one, two, three, or four registers

vst1_u32_x2Experimentalneon

Store multiple single-element structures to one, two, three, or four registers

vst1_u32_x3Experimentalneon

Store multiple single-element structures to one, two, three, or four registers

vst1_u32_x4Experimentalneon

Store multiple single-element structures to one, two, three, or four registers

vst1_u64_x2Experimentalneon

Store multiple single-element structures to one, two, three, or four registers

vst1_u64_x3Experimentalneon

Store multiple single-element structures to one, two, three, or four registers

vst1_u64_x4Experimentalneon

Store multiple single-element structures to one, two, three, or four registers

vst1q_lane_f32Experimentalneon

Store multiple single-element structures from one, two, three, or four registers

vst1q_lane_p8Experimentalneon

Store multiple single-element structures from one, two, three, or four registers

vst1q_lane_p16Experimentalneon

Store multiple single-element structures from one, two, three, or four registers

vst1q_lane_p64Experimentalneon,aes

Store multiple single-element structures from one, two, three, or four registers

vst1q_lane_s8Experimentalneon

Store multiple single-element structures from one, two, three, or four registers

vst1q_lane_s16Experimentalneon

Store multiple single-element structures from one, two, three, or four registers

vst1q_lane_s32Experimentalneon

Store multiple single-element structures from one, two, three, or four registers

vst1q_lane_s64Experimentalneon

Store multiple single-element structures from one, two, three, or four registers

vst1q_lane_u8Experimentalneon

Store multiple single-element structures from one, two, three, or four registers

vst1q_lane_u16Experimentalneon

Store multiple single-element structures from one, two, three, or four registers

vst1q_lane_u32Experimentalneon

Store multiple single-element structures from one, two, three, or four registers

vst1q_lane_u64Experimentalneon

Store multiple single-element structures from one, two, three, or four registers

vst1q_p8_x2Experimentalneon

Store multiple single-element structures to one, two, three, or four registers

vst1q_p8_x3Experimentalneon

Store multiple single-element structures to one, two, three, or four registers

vst1q_p8_x4Experimentalneon

Store multiple single-element structures to one, two, three, or four registers

vst1q_p16_x2Experimentalneon

Store multiple single-element structures to one, two, three, or four registers

vst1q_p16_x3Experimentalneon

Store multiple single-element structures to one, two, three, or four registers

vst1q_p16_x4Experimentalneon

Store multiple single-element structures to one, two, three, or four registers

vst1q_p64_x2Experimentalneon,aes

Store multiple single-element structures to one, two, three, or four registers

vst1q_p64_x3Experimentalneon,aes

Store multiple single-element structures to one, two, three, or four registers

vst1q_p64_x4Experimentalneon,aes

Store multiple single-element structures to one, two, three, or four registers

vst1q_u8_x2Experimentalneon

Store multiple single-element structures to one, two, three, or four registers

vst1q_u8_x3Experimentalneon

Store multiple single-element structures to one, two, three, or four registers

vst1q_u8_x4Experimentalneon

Store multiple single-element structures to one, two, three, or four registers

vst1q_u16_x2Experimentalneon

Store multiple single-element structures to one, two, three, or four registers

vst1q_u16_x3Experimentalneon

Store multiple single-element structures to one, two, three, or four registers

vst1q_u16_x4Experimentalneon

Store multiple single-element structures to one, two, three, or four registers

vst1q_u32_x2Experimentalneon

Store multiple single-element structures to one, two, three, or four registers

vst1q_u32_x3Experimentalneon

Store multiple single-element structures to one, two, three, or four registers

vst1q_u32_x4Experimentalneon

Store multiple single-element structures to one, two, three, or four registers

vst1q_u64_x2Experimentalneon

Store multiple single-element structures to one, two, three, or four registers

vst1q_u64_x3Experimentalneon

Store multiple single-element structures to one, two, three, or four registers

vst1q_u64_x4Experimentalneon

Store multiple single-element structures to one, two, three, or four registers

vst2_lane_p8Experimentalneon

Store multiple 2-element structures from two registers

vst2_lane_p16Experimentalneon

Store multiple 2-element structures from two registers

vst2_lane_u8Experimentalneon

Store multiple 2-element structures from two registers

vst2_lane_u16Experimentalneon

Store multiple 2-element structures from two registers

vst2_lane_u32Experimentalneon

Store multiple 2-element structures from two registers

vst2_p8Experimentalneon

Store multiple 2-element structures from two registers

vst2_p16Experimentalneon

Store multiple 2-element structures from two registers

vst2_p64Experimentalneon,aes

Store multiple 2-element structures from two registers

vst2_u8Experimentalneon

Store multiple 2-element structures from two registers

vst2_u16Experimentalneon

Store multiple 2-element structures from two registers

vst2_u32Experimentalneon

Store multiple 2-element structures from two registers

vst2_u64Experimentalneon

Store multiple 2-element structures from two registers

vst2q_lane_p16Experimentalneon

Store multiple 2-element structures from two registers

vst2q_lane_u16Experimentalneon

Store multiple 2-element structures from two registers

vst2q_lane_u32Experimentalneon

Store multiple 2-element structures from two registers

vst2q_p8Experimentalneon

Store multiple 2-element structures from two registers

vst2q_p16Experimentalneon

Store multiple 2-element structures from two registers

vst2q_u8Experimentalneon

Store multiple 2-element structures from two registers

vst2q_u16Experimentalneon

Store multiple 2-element structures from two registers

vst2q_u32Experimentalneon

Store multiple 2-element structures from two registers

vst3_lane_p8Experimentalneon

Store multiple 3-element structures from three registers

vst3_lane_p16Experimentalneon

Store multiple 3-element structures from three registers

vst3_lane_u8Experimentalneon

Store multiple 3-element structures from three registers

vst3_lane_u16Experimentalneon

Store multiple 3-element structures from three registers

vst3_lane_u32Experimentalneon

Store multiple 3-element structures from three registers

vst3_p8Experimentalneon

Store multiple 3-element structures from three registers

vst3_p16Experimentalneon

Store multiple 3-element structures from three registers

vst3_p64Experimentalneon,aes

Store multiple 3-element structures from three registers

vst3_u8Experimentalneon

Store multiple 3-element structures from three registers

vst3_u16Experimentalneon

Store multiple 3-element structures from three registers

vst3_u32Experimentalneon

Store multiple 3-element structures from three registers

vst3_u64Experimentalneon

Store multiple 3-element structures from three registers

vst3q_lane_p16Experimentalneon

Store multiple 3-element structures from three registers

vst3q_lane_u16Experimentalneon

Store multiple 3-element structures from three registers

vst3q_lane_u32Experimentalneon

Store multiple 3-element structures from three registers

vst3q_p8Experimentalneon

Store multiple 3-element structures from three registers

vst3q_p16Experimentalneon

Store multiple 3-element structures from three registers

vst3q_u8Experimentalneon

Store multiple 3-element structures from three registers

vst3q_u16Experimentalneon

Store multiple 3-element structures from three registers

vst3q_u32Experimentalneon

Store multiple 3-element structures from three registers

vst4_lane_p8Experimentalneon

Store multiple 4-element structures from four registers

vst4_lane_p16Experimentalneon

Store multiple 4-element structures from four registers

vst4_lane_u8Experimentalneon

Store multiple 4-element structures from four registers

vst4_lane_u16Experimentalneon

Store multiple 4-element structures from four registers

vst4_lane_u32Experimentalneon

Store multiple 4-element structures from four registers

vst4_p8Experimentalneon

Store multiple 4-element structures from four registers

vst4_p16Experimentalneon

Store multiple 4-element structures from four registers

vst4_p64Experimentalneon,aes

Store multiple 4-element structures from four registers

vst4_u8Experimentalneon

Store multiple 4-element structures from four registers

vst4_u16Experimentalneon

Store multiple 4-element structures from four registers

vst4_u32Experimentalneon

Store multiple 4-element structures from four registers

vst4_u64Experimentalneon

Store multiple 4-element structures from four registers

vst4q_lane_p16Experimentalneon

Store multiple 4-element structures from four registers

vst4q_lane_u16Experimentalneon

Store multiple 4-element structures from four registers

vst4q_lane_u32Experimentalneon

Store multiple 4-element structures from four registers

vst4q_p8Experimentalneon

Store multiple 4-element structures from four registers

vst4q_p16Experimentalneon

Store multiple 4-element structures from four registers

vst4q_u8Experimentalneon

Store multiple 4-element structures from four registers

vst4q_u16Experimentalneon

Store multiple 4-element structures from four registers

vst4q_u32Experimentalneon

Store multiple 4-element structures from four registers

vstrq_p128Experimentalneon

Store SIMD&FP register (immediate offset)

vsub_f32Experimentalneon

Subtract

vsub_s8Experimentalneon

Subtract

vsub_s16Experimentalneon

Subtract

vsub_s32Experimentalneon

Subtract

vsub_s64Experimentalneon

Subtract

vsub_u8Experimentalneon

Subtract

vsub_u16Experimentalneon

Subtract

vsub_u32Experimentalneon

Subtract

vsub_u64Experimentalneon

Subtract

vsubhn_high_s16Experimentalneon

Subtract returning high narrow

vsubhn_high_s32Experimentalneon

Subtract returning high narrow

vsubhn_high_s64Experimentalneon

Subtract returning high narrow

vsubhn_high_u16Experimentalneon

Subtract returning high narrow

vsubhn_high_u32Experimentalneon

Subtract returning high narrow

vsubhn_high_u64Experimentalneon

Subtract returning high narrow

vsubhn_s16Experimentalneon

Subtract returning high narrow

vsubhn_s32Experimentalneon

Subtract returning high narrow

vsubhn_s64Experimentalneon

Subtract returning high narrow

vsubhn_u16Experimentalneon

Subtract returning high narrow

vsubhn_u32Experimentalneon

Subtract returning high narrow

vsubhn_u64Experimentalneon

Subtract returning high narrow

vsubl_s8Experimentalneon

Signed Subtract Long

vsubl_s16Experimentalneon

Signed Subtract Long

vsubl_s32Experimentalneon

Signed Subtract Long

vsubl_u8Experimentalneon

Unsigned Subtract Long

vsubl_u16Experimentalneon

Unsigned Subtract Long

vsubl_u32Experimentalneon

Unsigned Subtract Long

vsubq_f32Experimentalneon

Subtract

vsubq_s8Experimentalneon

Subtract

vsubq_s16Experimentalneon

Subtract

vsubq_s32Experimentalneon

Subtract

vsubq_s64Experimentalneon

Subtract

vsubq_u8Experimentalneon

Subtract

vsubq_u16Experimentalneon

Subtract

vsubq_u32Experimentalneon

Subtract

vsubq_u64Experimentalneon

Subtract

vsubw_s8Experimentalneon

Signed Subtract Wide

vsubw_s16Experimentalneon

Signed Subtract Wide

vsubw_s32Experimentalneon

Signed Subtract Wide

vsubw_u8Experimentalneon

Unsigned Subtract Wide

vsubw_u16Experimentalneon

Unsigned Subtract Wide

vsubw_u32Experimentalneon

Unsigned Subtract Wide

vtrn_f32Experimentalneon

Transpose elements

vtrn_p8Experimentalneon

Transpose elements

vtrn_p16Experimentalneon

Transpose elements

vtrn_s8Experimentalneon

Transpose elements

vtrn_s16Experimentalneon

Transpose elements

vtrn_s32Experimentalneon

Transpose elements

vtrn_u8Experimentalneon

Transpose elements

vtrn_u16Experimentalneon

Transpose elements

vtrn_u32Experimentalneon

Transpose elements

vtrnq_f32Experimentalneon

Transpose elements

vtrnq_p8Experimentalneon

Transpose elements

vtrnq_p16Experimentalneon

Transpose elements

vtrnq_s8Experimentalneon

Transpose elements

vtrnq_s16Experimentalneon

Transpose elements

vtrnq_s32Experimentalneon

Transpose elements

vtrnq_u8Experimentalneon

Transpose elements

vtrnq_u16Experimentalneon

Transpose elements

vtrnq_u32Experimentalneon

Transpose elements

vtst_p8Experimentalneon

Signed compare bitwise Test bits nonzero

vtst_p16Experimentalneon

Signed compare bitwise Test bits nonzero

vtst_s8Experimentalneon

Signed compare bitwise Test bits nonzero

vtst_s16Experimentalneon

Signed compare bitwise Test bits nonzero

vtst_s32Experimentalneon

Signed compare bitwise Test bits nonzero

vtst_u8Experimentalneon

Unsigned compare bitwise Test bits nonzero

vtst_u16Experimentalneon

Unsigned compare bitwise Test bits nonzero

vtst_u32Experimentalneon

Unsigned compare bitwise Test bits nonzero

vtstq_p8Experimentalneon

Signed compare bitwise Test bits nonzero

vtstq_p16Experimentalneon

Signed compare bitwise Test bits nonzero

vtstq_s8Experimentalneon

Signed compare bitwise Test bits nonzero

vtstq_s16Experimentalneon

Signed compare bitwise Test bits nonzero

vtstq_s32Experimentalneon

Signed compare bitwise Test bits nonzero

vtstq_u8Experimentalneon

Unsigned compare bitwise Test bits nonzero

vtstq_u16Experimentalneon

Unsigned compare bitwise Test bits nonzero

vtstq_u32Experimentalneon

Unsigned compare bitwise Test bits nonzero

vusmmlaq_s32Experimentali8mm and neon

Unsigned and signed 8-bit integer matrix multiply-accumulate

vuzp_f32Experimentalneon

Unzip vectors

vuzp_p8Experimentalneon

Unzip vectors

vuzp_p16Experimentalneon

Unzip vectors

vuzp_s8Experimentalneon

Unzip vectors

vuzp_s16Experimentalneon

Unzip vectors

vuzp_s32Experimentalneon

Unzip vectors

vuzp_u8Experimentalneon

Unzip vectors

vuzp_u16Experimentalneon

Unzip vectors

vuzp_u32Experimentalneon

Unzip vectors

vuzpq_f32Experimentalneon

Unzip vectors

vuzpq_p8Experimentalneon

Unzip vectors

vuzpq_p16Experimentalneon

Unzip vectors

vuzpq_s8Experimentalneon

Unzip vectors

vuzpq_s16Experimentalneon

Unzip vectors

vuzpq_s32Experimentalneon

Unzip vectors

vuzpq_u8Experimentalneon

Unzip vectors

vuzpq_u16Experimentalneon

Unzip vectors

vuzpq_u32Experimentalneon

Unzip vectors

vxarq_u64Experimentalneon,sha3

Exclusive OR and rotate

vzip_f32Experimentalneon

Zip vectors