1.33.0[][src]Module core::arch::wasm32

This is supported on WebAssembly only.

Platform-specific intrinsics for the wasm32 platform.

This module provides intrinsics specific to the WebAssembly architecture. Here you'll find intrinsics necessary for leveraging WebAssembly proposals such as atomics and simd. These proposals are evolving over time and as such the support here is unstable and requires the nightly channel. As WebAssembly proposals stabilize these functions will also become stable.

See the module documentation for general information about the arch module and platform intrinsics.

Atomics

The threads proposal for WebAssembly adds a number of instructions for dealing with multithreaded programs. Atomic instructions can all be generated through std::sync::atomic types, but some instructions have no equivalent in Rust such as memory.atomic.notify so this module will provide these intrinsics.

At this time, however, these intrinsics are only available when the standard library itself is compiled with atomics. Compiling with atomics is not enabled by default and requires passing -Ctarget-feature=+atomics to rustc. The standard library shipped via rustup is not compiled with atomics. To get access to these intrinsics you'll need to compile the standard library from source with the requisite compiler flags.

SIMD

The simd proposal for WebAssembly adds a new v128 type for a 128-bit SIMD register. It also adds a large array of instructions to operate on the v128 type to perform data processing. The SIMD proposal has been in progress for quite some time and many instructions have come and gone. This module attempts to keep up with the proposal, but if you notice anything awry please feel free to open an issue.

It's important to be aware that the current state of development of SIMD in WebAssembly is still somewhat early days. There's lots of pieces to demo and prototype with, but discussions and support are still in progress. There's a number of pitfalls and gotchas in various places, which will attempt to be documented here, but there may be others lurking!

Using SIMD is intended to be similar to as you would on x86_64, for example. You'd write a function such as:

This example is not tested
#[cfg(target_arch = "wasm32")]
#[target_feature(enable = "simd128")]
unsafe fn uses_simd() {
    use std::arch::wasm32::*;
    // ...
}
Run

Unlike x86_64, however, WebAssembly does not currently have dynamic detection at runtime as to whether SIMD is supported (this is one of the motivators for the conditional sections proposal, but that is still pretty early days). This means that your binary will either have SIMD and can only run on engines which support SIMD, or it will not have SIMD at all. For compatibility the standard library itself does not use any SIMD internally. Determining how best to ship your WebAssembly binary with SIMD is largely left up to you as it can can be pretty nuanced depending on your situation.

To enable SIMD support at compile time you need to do one of two things:

If you enable SIMD via either of these routes then you'll have a WebAssembly binary that uses SIMD instructions, and you'll need to ship that accordingly. Also note that if you call SIMD intrinsics but don't enable SIMD via either of these mechanisms, you'll still have SIMD generated in your program. This means to generate a binary without SIMD you'll need to avoid both options above plus calling into any intrinsics in this module.

Note: Due to rust-lang/rust#74320 it's recommended to compile your entire program with SIMD support (using RUSTFLAGS) or otherwise functions may not be inlined correctly.

Note: LLVM's SIMD support is actually split into two features: simd128 and unimplemented-simd128. Rust code can enable simd128 with #[target_feature] (and test for it with #[cfg(target_feature = "simd128")], but it cannot enable unimplemented-simd128. The only way to enable this feature is to compile with -Ctarget-feature=+simd128,+unimplemented-simd128. This second feature enables more recent instructions implemented in LLVM which haven't always had enough time to make their way to runtimes.

Structs

v128ExperimentalWebAssembly

WASM-specific 128-bit wide SIMD vector type.

Functions

memory_growWebAssembly

Corresponding intrinsic to wasm's memory.grow instruction

memory_sizeWebAssembly

Corresponding intrinsic to wasm's memory.size instruction

unreachableWebAssembly

Generates the trap instruction UNREACHABLE

f32x4_absExperimentalWebAssembly and simd128

Calculates the absolute value of each lane of a 128-bit vector interpreted as four 32-bit floating point numbers.

f32x4_addExperimentalWebAssembly and simd128

Adds pairwise lanes of two 128-bit vectors interpreted as four 32-bit floating point numbers.

f32x4_constExperimentalWebAssembly and simd128

Materializes a constant SIMD value from the immediate operands.

f32x4_convert_i32x4_sExperimentalWebAssembly and simd128

Converts a 128-bit vector interpreted as four 32-bit signed integers into a 128-bit vector of four 32-bit floating point numbers.

f32x4_convert_i32x4_uExperimentalWebAssembly and simd128

Converts a 128-bit vector interpreted as four 32-bit unsigned integers into a 128-bit vector of four 32-bit floating point numbers.

f32x4_divExperimentalWebAssembly and simd128

Divides pairwise lanes of two 128-bit vectors interpreted as four 32-bit floating point numbers.

f32x4_eqExperimentalWebAssembly and simd128

Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit floating point numbers.

f32x4_extract_laneExperimentalWebAssembly and simd128

Extracts a lane from a 128-bit vector interpreted as 4 packed f32 numbers.

f32x4_geExperimentalWebAssembly and simd128

Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit floating point numbers.

f32x4_gtExperimentalWebAssembly and simd128

Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit floating point numbers.

f32x4_leExperimentalWebAssembly and simd128

Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit floating point numbers.

f32x4_ltExperimentalWebAssembly and simd128

Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit floating point numbers.

f32x4_maxExperimentalWebAssembly and simd128

Calculates the maximum of pairwise lanes of two 128-bit vectors interpreted as four 32-bit floating point numbers.

f32x4_minExperimentalWebAssembly and simd128

Calculates the minimum of pairwise lanes of two 128-bit vectors interpreted as four 32-bit floating point numbers.

f32x4_mulExperimentalWebAssembly and simd128

Multiplies pairwise lanes of two 128-bit vectors interpreted as four 32-bit floating point numbers.

f32x4_neExperimentalWebAssembly and simd128

Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit floating point numbers.

f32x4_negExperimentalWebAssembly and simd128

Negates each lane of a 128-bit vector interpreted as four 32-bit floating point numbers.

f32x4_replace_laneExperimentalWebAssembly and simd128

Replaces a lane from a 128-bit vector interpreted as 4 packed f32 numbers.

f32x4_splatExperimentalWebAssembly and simd128

Creates a vector with identical lanes.

f32x4_sqrtExperimentalWebAssembly and simd128

Calculates the square root of each lane of a 128-bit vector interpreted as four 32-bit floating point numbers.

f32x4_subExperimentalWebAssembly and simd128

Subtracts pairwise lanes of two 128-bit vectors interpreted as four 32-bit floating point numbers.

f64x2_absExperimentalWebAssembly and simd128

Calculates the absolute value of each lane of a 128-bit vector interpreted as two 64-bit floating point numbers.

f64x2_addExperimentalWebAssembly and simd128

Adds pairwise lanes of two 128-bit vectors interpreted as two 64-bit floating point numbers.

f64x2_constExperimentalWebAssembly and simd128

Materializes a constant SIMD value from the immediate operands.

f64x2_divExperimentalWebAssembly and simd128

Divides pairwise lanes of two 128-bit vectors interpreted as two 64-bit floating point numbers.

f64x2_eqExperimentalWebAssembly and simd128

Compares two 128-bit vectors as if they were two vectors of 2 sixty-four-bit floating point numbers.

f64x2_extract_laneExperimentalWebAssembly and simd128

Extracts a lane from a 128-bit vector interpreted as 2 packed f64 numbers.

f64x2_geExperimentalWebAssembly and simd128

Compares two 128-bit vectors as if they were two vectors of 2 sixty-four-bit floating point numbers.

f64x2_gtExperimentalWebAssembly and simd128

Compares two 128-bit vectors as if they were two vectors of 2 sixty-four-bit floating point numbers.

f64x2_leExperimentalWebAssembly and simd128

Compares two 128-bit vectors as if they were two vectors of 2 sixty-four-bit floating point numbers.

f64x2_ltExperimentalWebAssembly and simd128

Compares two 128-bit vectors as if they were two vectors of 2 sixty-four-bit floating point numbers.

f64x2_maxExperimentalWebAssembly and simd128

Calculates the maximum of pairwise lanes of two 128-bit vectors interpreted as two 64-bit floating point numbers.

f64x2_minExperimentalWebAssembly and simd128

Calculates the minimum of pairwise lanes of two 128-bit vectors interpreted as two 64-bit floating point numbers.

f64x2_mulExperimentalWebAssembly and simd128

Multiplies pairwise lanes of two 128-bit vectors interpreted as two 64-bit floating point numbers.

f64x2_neExperimentalWebAssembly and simd128

Compares two 128-bit vectors as if they were two vectors of 2 sixty-four-bit floating point numbers.

f64x2_negExperimentalWebAssembly and simd128

Negates each lane of a 128-bit vector interpreted as two 64-bit floating point numbers.

f64x2_replace_laneExperimentalWebAssembly and simd128

Replaces a lane from a 128-bit vector interpreted as 2 packed f64 numbers.

f64x2_splatExperimentalWebAssembly and simd128

Creates a vector with identical lanes.

f64x2_sqrtExperimentalWebAssembly and simd128

Calculates the square root of each lane of a 128-bit vector interpreted as two 64-bit floating point numbers.

f64x2_subExperimentalWebAssembly and simd128

Subtracts pairwise lanes of two 128-bit vectors interpreted as two 64-bit floating point numbers.

i8x16_absExperimentalWebAssembly and simd128

Lane-wise wrapping absolute value.

i8x16_addExperimentalWebAssembly and simd128

Adds two 128-bit vectors as if they were two packed sixteen 8-bit integers.

i8x16_add_saturate_sExperimentalWebAssembly and simd128

Adds two 128-bit vectors as if they were two packed sixteen 8-bit signed integers, saturating on overflow to i8::MAX.

i8x16_add_saturate_uExperimentalWebAssembly and simd128

Adds two 128-bit vectors as if they were two packed sixteen 8-bit unsigned integers, saturating on overflow to u8::MAX.

i8x16_all_trueExperimentalWebAssembly and simd128

Returns 1 if all lanes are nonzero or 0 if any lane is nonzero.

i8x16_any_trueExperimentalWebAssembly and simd128

Returns 1 if any lane is nonzero or 0 if all lanes are zero.

i8x16_avgr_uExperimentalWebAssembly and simd128

Lane-wise rounding average.

i8x16_constExperimentalWebAssembly and simd128

Materializes a constant SIMD value from the immediate operands.

i8x16_eqExperimentalWebAssembly and simd128

Compares two 128-bit vectors as if they were two vectors of 16 eight-bit integers.

i8x16_extract_laneExperimentalWebAssembly and simd128

Extracts a lane from a 128-bit vector interpreted as 16 packed i8 numbers.

i8x16_ge_sExperimentalWebAssembly and simd128

Compares two 128-bit vectors as if they were two vectors of 16 eight-bit signed integers.

i8x16_ge_uExperimentalWebAssembly and simd128

Compares two 128-bit vectors as if they were two vectors of 16 eight-bit unsigned integers.

i8x16_gt_sExperimentalWebAssembly and simd128

Compares two 128-bit vectors as if they were two vectors of 16 eight-bit signed integers.

i8x16_gt_uExperimentalWebAssembly and simd128

Compares two 128-bit vectors as if they were two vectors of 16 eight-bit unsigned integers.

i8x16_le_sExperimentalWebAssembly and simd128

Compares two 128-bit vectors as if they were two vectors of 16 eight-bit signed integers.

i8x16_le_uExperimentalWebAssembly and simd128

Compares two 128-bit vectors as if they were two vectors of 16 eight-bit unsigned integers.

i8x16_lt_sExperimentalWebAssembly and simd128

Compares two 128-bit vectors as if they were two vectors of 16 eight-bit signed integers.

i8x16_lt_uExperimentalWebAssembly and simd128

Compares two 128-bit vectors as if they were two vectors of 16 eight-bit unsigned integers.

i8x16_max_sExperimentalWebAssembly and simd128

Compares lane-wise signed integers, and returns the maximum of each pair.

i8x16_max_uExperimentalWebAssembly and simd128

Compares lane-wise unsigned integers, and returns the maximum of each pair.

i8x16_min_sExperimentalWebAssembly and simd128

Compares lane-wise signed integers, and returns the minimum of each pair.

i8x16_min_uExperimentalWebAssembly and simd128

Compares lane-wise unsigned integers, and returns the minimum of each pair.

i8x16_narrow_i16x8_sExperimentalWebAssembly and simd128

Converts two input vectors into a smaller lane vector by narrowing each lane.

i8x16_narrow_i16x8_uExperimentalWebAssembly and simd128

Converts two input vectors into a smaller lane vector by narrowing each lane.

i8x16_neExperimentalWebAssembly and simd128

Compares two 128-bit vectors as if they were two vectors of 16 eight-bit integers.

i8x16_negExperimentalWebAssembly and simd128

Negates a 128-bit vectors intepreted as sixteen 8-bit signed integers

i8x16_replace_laneExperimentalWebAssembly and simd128

Replaces a lane from a 128-bit vector interpreted as 16 packed i8 numbers.

i8x16_shlExperimentalWebAssembly and simd128

Shifts each lane to the left by the specified number of bits.

i8x16_shr_sExperimentalWebAssembly and simd128

Shifts each lane to the right by the specified number of bits, sign extending.

i8x16_shr_uExperimentalWebAssembly and simd128

Shifts each lane to the right by the specified number of bits, shifting in zeros.

i8x16_splatExperimentalWebAssembly and simd128

Creates a vector with identical lanes.

i8x16_subExperimentalWebAssembly and simd128

Subtracts two 128-bit vectors as if they were two packed sixteen 8-bit integers.

i8x16_sub_saturate_sExperimentalWebAssembly and simd128

Subtracts two 128-bit vectors as if they were two packed sixteen 8-bit signed integers, saturating on overflow to i8::MIN.

i8x16_sub_saturate_uExperimentalWebAssembly and simd128

Subtracts two 128-bit vectors as if they were two packed sixteen 8-bit unsigned integers, saturating on overflow to 0.

i16x8_absExperimentalWebAssembly and simd128

Lane-wise wrapping absolute value.

i16x8_addExperimentalWebAssembly and simd128

Adds two 128-bit vectors as if they were two packed eight 16-bit integers.

i16x8_add_saturate_sExperimentalWebAssembly and simd128

Adds two 128-bit vectors as if they were two packed eight 16-bit signed integers, saturating on overflow to i16::MAX.

i16x8_add_saturate_uExperimentalWebAssembly and simd128

Adds two 128-bit vectors as if they were two packed eight 16-bit unsigned integers, saturating on overflow to u16::MAX.

i16x8_all_trueExperimentalWebAssembly and simd128

Returns 1 if all lanes are nonzero or 0 if any lane is nonzero.

i16x8_any_trueExperimentalWebAssembly and simd128

Returns 1 if any lane is nonzero or 0 if all lanes are zero.

i16x8_avgr_uExperimentalWebAssembly and simd128

Lane-wise rounding average.

i16x8_constExperimentalWebAssembly and simd128

Materializes a constant SIMD value from the immediate operands.

i16x8_eqExperimentalWebAssembly and simd128

Compares two 128-bit vectors as if they were two vectors of 8 sixteen-bit integers.

i16x8_extract_laneExperimentalWebAssembly and simd128

Extracts a lane from a 128-bit vector interpreted as 8 packed i16 numbers.

i16x8_ge_sExperimentalWebAssembly and simd128

Compares two 128-bit vectors as if they were two vectors of 8 sixteen-bit signed integers.

i16x8_ge_uExperimentalWebAssembly and simd128

Compares two 128-bit vectors as if they were two vectors of 8 sixteen-bit unsigned integers.

i16x8_gt_sExperimentalWebAssembly and simd128

Compares two 128-bit vectors as if they were two vectors of 8 sixteen-bit signed integers.

i16x8_gt_uExperimentalWebAssembly and simd128

Compares two 128-bit vectors as if they were two vectors of 8 sixteen-bit unsigned integers.

i16x8_le_sExperimentalWebAssembly and simd128

Compares two 128-bit vectors as if they were two vectors of 8 sixteen-bit signed integers.

i16x8_le_uExperimentalWebAssembly and simd128

Compares two 128-bit vectors as if they were two vectors of 8 sixteen-bit unsigned integers.

i16x8_load8x8_sExperimentalWebAssembly and simd128

Load eight 8-bit integers and sign extend each one to a 16-bit lane

i16x8_load8x8_uExperimentalWebAssembly and simd128

Load eight 8-bit integers and zero extend each one to a 16-bit lane

i16x8_lt_sExperimentalWebAssembly and simd128

Compares two 128-bit vectors as if they were two vectors of 8 sixteen-bit signed integers.

i16x8_lt_uExperimentalWebAssembly and simd128

Compares two 128-bit vectors as if they were two vectors of 8 sixteen-bit unsigned integers.

i16x8_max_sExperimentalWebAssembly and simd128

Compares lane-wise signed integers, and returns the maximum of each pair.

i16x8_max_uExperimentalWebAssembly and simd128

Compares lane-wise unsigned integers, and returns the maximum of each pair.

i16x8_min_sExperimentalWebAssembly and simd128

Compares lane-wise signed integers, and returns the minimum of each pair.

i16x8_min_uExperimentalWebAssembly and simd128

Compares lane-wise unsigned integers, and returns the minimum of each pair.

i16x8_mulExperimentalWebAssembly and simd128

Multiplies two 128-bit vectors as if they were two packed eight 16-bit signed integers.

i16x8_narrow_i32x4_sExperimentalWebAssembly and simd128

Converts two input vectors into a smaller lane vector by narrowing each lane.

i16x8_narrow_i32x4_uExperimentalWebAssembly and simd128

Converts two input vectors into a smaller lane vector by narrowing each lane.

i16x8_neExperimentalWebAssembly and simd128

Compares two 128-bit vectors as if they were two vectors of 8 sixteen-bit integers.

i16x8_negExperimentalWebAssembly and simd128

Negates a 128-bit vectors intepreted as eight 16-bit signed integers

i16x8_replace_laneExperimentalWebAssembly and simd128

Replaces a lane from a 128-bit vector interpreted as 8 packed i16 numbers.

i16x8_shlExperimentalWebAssembly and simd128

Shifts each lane to the left by the specified number of bits.

i16x8_shr_sExperimentalWebAssembly and simd128

Shifts each lane to the right by the specified number of bits, sign extending.

i16x8_shr_uExperimentalWebAssembly and simd128

Shifts each lane to the right by the specified number of bits, shifting in zeros.

i16x8_splatExperimentalWebAssembly and simd128

Creates a vector with identical lanes.

i16x8_subExperimentalWebAssembly and simd128

Subtracts two 128-bit vectors as if they were two packed eight 16-bit integers.

i16x8_sub_saturate_sExperimentalWebAssembly and simd128

Subtracts two 128-bit vectors as if they were two packed eight 16-bit signed integers, saturating on overflow to i16::MIN.

i16x8_sub_saturate_uExperimentalWebAssembly and simd128

Subtracts two 128-bit vectors as if they were two packed eight 16-bit unsigned integers, saturating on overflow to 0.

i16x8_widen_high_i8x16_sExperimentalWebAssembly

Converts high half of the smaller lane vector to a larger lane vector, sign extended.

i16x8_widen_high_i8x16_uExperimentalWebAssembly

Converts high half of the smaller lane vector to a larger lane vector, zero extended.

i16x8_widen_low_i8x16_sExperimentalWebAssembly

Converts low half of the smaller lane vector to a larger lane vector, sign extended.

i16x8_widen_low_i8x16_uExperimentalWebAssembly

Converts low half of the smaller lane vector to a larger lane vector, zero extended.

i32x4_absExperimentalWebAssembly and simd128

Lane-wise wrapping absolute value.

i32x4_addExperimentalWebAssembly and simd128

Adds two 128-bit vectors as if they were two packed four 32-bit integers.

i32x4_all_trueExperimentalWebAssembly and simd128

Returns 1 if all lanes are nonzero or 0 if any lane is nonzero.

i32x4_any_trueExperimentalWebAssembly and simd128

Returns 1 if any lane is nonzero or 0 if all lanes are zero.

i32x4_constExperimentalWebAssembly and simd128

Materializes a constant SIMD value from the immediate operands.

i32x4_eqExperimentalWebAssembly and simd128

Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit integers.

i32x4_extract_laneExperimentalWebAssembly and simd128

Extracts a lane from a 128-bit vector interpreted as 4 packed i32 numbers.

i32x4_ge_sExperimentalWebAssembly and simd128

Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit signed integers.

i32x4_ge_uExperimentalWebAssembly and simd128

Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit unsigned integers.

i32x4_gt_sExperimentalWebAssembly and simd128

Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit signed integers.

i32x4_gt_uExperimentalWebAssembly and simd128

Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit unsigned integers.

i32x4_le_sExperimentalWebAssembly and simd128

Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit signed integers.

i32x4_le_uExperimentalWebAssembly and simd128

Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit unsigned integers.

i32x4_load16x4_sExperimentalWebAssembly and simd128

Load four 16-bit integers and sign extend each one to a 32-bit lane

i32x4_load16x4_uExperimentalWebAssembly and simd128

Load four 16-bit integers and zero extend each one to a 32-bit lane

i32x4_lt_sExperimentalWebAssembly and simd128

Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit signed integers.

i32x4_lt_uExperimentalWebAssembly and simd128

Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit unsigned integers.

i32x4_max_sExperimentalWebAssembly and simd128

Compares lane-wise signed integers, and returns the maximum of each pair.

i32x4_max_uExperimentalWebAssembly and simd128

Compares lane-wise unsigned integers, and returns the maximum of each pair.

i32x4_min_sExperimentalWebAssembly and simd128

Compares lane-wise signed integers, and returns the minimum of each pair.

i32x4_min_uExperimentalWebAssembly and simd128

Compares lane-wise unsigned integers, and returns the minimum of each pair.

i32x4_mulExperimentalWebAssembly and simd128

Multiplies two 128-bit vectors as if they were two packed four 32-bit signed integers.

i32x4_neExperimentalWebAssembly and simd128

Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit integers.

i32x4_negExperimentalWebAssembly and simd128

Negates a 128-bit vectors intepreted as four 32-bit signed integers

i32x4_replace_laneExperimentalWebAssembly and simd128

Replaces a lane from a 128-bit vector interpreted as 4 packed i32 numbers.

i32x4_shlExperimentalWebAssembly and simd128

Shifts each lane to the left by the specified number of bits.

i32x4_shr_sExperimentalWebAssembly and simd128

Shifts each lane to the right by the specified number of bits, sign extending.

i32x4_shr_uExperimentalWebAssembly and simd128

Shifts each lane to the right by the specified number of bits, shifting in zeros.

i32x4_splatExperimentalWebAssembly and simd128

Creates a vector with identical lanes.

i32x4_subExperimentalWebAssembly and simd128

Subtracts two 128-bit vectors as if they were two packed four 32-bit integers.

i32x4_trunc_sat_f32x4_sExperimentalWebAssembly and simd128

Converts a 128-bit vector interpreted as four 32-bit floating point numbers into a 128-bit vector of four 32-bit signed integers.

i32x4_trunc_sat_f32x4_uExperimentalWebAssembly and simd128

Converts a 128-bit vector interpreted as four 32-bit floating point numbers into a 128-bit vector of four 32-bit unsigned integers.

i32x4_widen_high_i16x8_sExperimentalWebAssembly

Converts high half of the smaller lane vector to a larger lane vector, sign extended.

i32x4_widen_high_i16x8_uExperimentalWebAssembly

Converts high half of the smaller lane vector to a larger lane vector, zero extended.

i32x4_widen_low_i16x8_sExperimentalWebAssembly

Converts low half of the smaller lane vector to a larger lane vector, sign extended.

i32x4_widen_low_i16x8_uExperimentalWebAssembly

Converts low half of the smaller lane vector to a larger lane vector, zero extended.

i64x2_addExperimentalWebAssembly and simd128

Adds two 128-bit vectors as if they were two packed two 64-bit integers.

i64x2_constExperimentalWebAssembly and simd128

Materializes a constant SIMD value from the immediate operands.

i64x2_extract_laneExperimentalWebAssembly and simd128

Extracts a lane from a 128-bit vector interpreted as 2 packed i64 numbers.

i64x2_load32x2_sExperimentalWebAssembly and simd128

Load two 32-bit integers and sign extend each one to a 64-bit lane

i64x2_load32x2_uExperimentalWebAssembly and simd128

Load two 32-bit integers and zero extend each one to a 64-bit lane

i64x2_mulExperimentalWebAssembly and simd128

Multiplies two 128-bit vectors as if they were two packed two 64-bit integers.

i64x2_negExperimentalWebAssembly and simd128

Negates a 128-bit vectors intepreted as two 64-bit signed integers

i64x2_replace_laneExperimentalWebAssembly and simd128

Replaces a lane from a 128-bit vector interpreted as 2 packed i64 numbers.

i64x2_shlExperimentalWebAssembly and simd128

Shifts each lane to the left by the specified number of bits.

i64x2_shr_sExperimentalWebAssembly and simd128

Shifts each lane to the right by the specified number of bits, sign extending.

i64x2_shr_uExperimentalWebAssembly and simd128

Shifts each lane to the right by the specified number of bits, shifting in zeros.

i64x2_splatExperimentalWebAssembly and simd128

Creates a vector with identical lanes.

i64x2_subExperimentalWebAssembly and simd128

Subtracts two 128-bit vectors as if they were two packed two 64-bit integers.

memory_atomic_notifyExperimentalWebAssembly

Corresponding intrinsic to wasm's memory.atomic.notify instruction

memory_atomic_wait32ExperimentalWebAssembly

Corresponding intrinsic to wasm's memory.atomic.wait32 instruction

memory_atomic_wait64ExperimentalWebAssembly

Corresponding intrinsic to wasm's memory.atomic.wait64 instruction

v8x16_load_splatExperimentalWebAssembly and simd128

Load a single element and splat to all lanes of a v128 vector.

v8x16_shuffleExperimentalWebAssembly and simd128

Returns a new vector with lanes selected from the lanes of the two input vectors $a and $b specified in the 16 immediate operands.

v8x16_swizzleExperimentalWebAssembly and simd128

Returns a new vector with lanes selected from the lanes of the first input vector a specified in the second input vector s.

v16x8_load_splatExperimentalWebAssembly and simd128

Load a single element and splat to all lanes of a v128 vector.

v16x8_shuffleExperimentalWebAssembly and simd128

Same as v8x16_shuffle, except operates as if the inputs were eight 16-bit integers, only taking 8 indices to shuffle.

v32x4_load_splatExperimentalWebAssembly and simd128

Load a single element and splat to all lanes of a v128 vector.

v32x4_shuffleExperimentalWebAssembly and simd128

Same as v8x16_shuffle, except operates as if the inputs were four 32-bit integers, only taking 4 indices to shuffle.

v64x2_load_splatExperimentalWebAssembly and simd128

Load a single element and splat to all lanes of a v128 vector.

v64x2_shuffleExperimentalWebAssembly and simd128

Same as v8x16_shuffle, except operates as if the inputs were two 64-bit integers, only taking 2 indices to shuffle.

v128_andExperimentalWebAssembly and simd128

Performs a bitwise and of the two input 128-bit vectors, returning the resulting vector.

v128_andnotExperimentalWebAssembly and simd128

Bitwise AND of bits of a and the logical inverse of bits of b.

v128_bitselectExperimentalWebAssembly and simd128

Use the bitmask in c to select bits from v1 when 1 and v2 when 0.

v128_loadExperimentalWebAssembly and simd128

Loads a v128 vector from the given heap address.

v128_notExperimentalWebAssembly and simd128

Flips each bit of the 128-bit input vector.

v128_orExperimentalWebAssembly and simd128

Performs a bitwise or of the two input 128-bit vectors, returning the resulting vector.

v128_storeExperimentalWebAssembly and simd128

Stores a v128 vector to the given heap address.

v128_xorExperimentalWebAssembly and simd128

Performs a bitwise xor of the two input 128-bit vectors, returning the resulting vector.