1.33.0[−][src]Module core::arch::wasm32
Platformspecific intrinsics for the wasm32
platform.
This module provides intrinsics specific to the WebAssembly architecture. Here you'll find intrinsics necessary for leveraging WebAssembly proposals such as atomics and simd. These proposals are evolving over time and as such the support here is unstable and requires the nightly channel. As WebAssembly proposals stabilize these functions will also become stable.
See the module documentation for general information
about the arch
module and platform intrinsics.
Atomics
The threads proposal for WebAssembly adds a number of
instructions for dealing with multithreaded programs. Atomic
instructions can all be generated through std::sync::atomic
types, but
some instructions have no equivalent in Rust such as
memory.atomic.notify
so this module will provide these intrinsics.
At this time, however, these intrinsics are only available when the
standard library itself is compiled with atomics. Compiling with
atomics is not enabled by default and requires passing
Ctargetfeature=+atomics
to rustc. The standard library shipped via
rustup
is not compiled with atomics. To get access to these intrinsics
you'll need to compile the standard library from source with the
requisite compiler flags.
SIMD
The simd proposal for WebAssembly adds a new v128
type for a
128bit SIMD register. It also adds a large array of instructions to
operate on the v128
type to perform data processing. The SIMD proposal
has been in progress for quite some time and many instructions have come
and gone. This module attempts to keep up with the proposal, but if you
notice anything awry please feel free to open an
issue.
It's important to be aware that the current state of development of SIMD in WebAssembly is still somewhat early days. There's lots of pieces to demo and prototype with, but discussions and support are still in progress. There's a number of pitfalls and gotchas in various places, which will attempt to be documented here, but there may be others lurking!
Using SIMD is intended to be similar to as you would on x86_64
, for
example. You'd write a function such as:
#[cfg(target_arch = "wasm32")] #[target_feature(enable = "simd128")] unsafe fn uses_simd() { use std::arch::wasm32::*; // ... }Run
Unlike x86_64
, however, WebAssembly does not currently have dynamic
detection at runtime as to whether SIMD is supported (this is one of the
motivators for the conditional sections proposal, but
that is still pretty early days). This means that your binary will
either have SIMD and can only run on engines which support SIMD, or it
will not have SIMD at all. For compatibility the standard library itself
does not use any SIMD internally. Determining how best to ship your
WebAssembly binary with SIMD is largely left up to you as it can can be
pretty nuanced depending on your situation.
To enable SIMD support at compile time you need to do one of two things:

First you can annotate functions with
#[target_feature(enable = "simd128")]
. This causes just that one function to have SIMD support available to it, and intrinsics will get inlined as usual in this situation. 
Second you can compile your program with
Ctargetfeature=+simd128
. This compilation flag blanket enables SIMD support for your entire compilation. Note that this does not include the standard library unless you recompile the standard library.
If you enable SIMD via either of these routes then you'll have a WebAssembly binary that uses SIMD instructions, and you'll need to ship that accordingly. Also note that if you call SIMD intrinsics but don't enable SIMD via either of these mechanisms, you'll still have SIMD generated in your program. This means to generate a binary without SIMD you'll need to avoid both options above plus calling into any intrinsics in this module.
Note: Due to rustlang/rust#74320 it's recommended to compile your entire program with SIMD support (using
RUSTFLAGS
) or otherwise functions may not be inlined correctly.
Note: LLVM's SIMD support is actually split into two features:
simd128
andunimplementedsimd128
. Rust code can enablesimd128
with#[target_feature]
(and test for it with#[cfg(target_feature = "simd128")]
, but it cannot enableunimplementedsimd128
. The only way to enable this feature is to compile withCtargetfeature=+simd128,+unimplementedsimd128
. This second feature enables more recent instructions implemented in LLVM which haven't always had enough time to make their way to runtimes.
Structs
v128  ExperimentalWebAssembly WASMspecific 128bit wide SIMD vector type. 
Functions
memory_grow  WebAssembly Corresponding intrinsic to wasm's 
memory_size  WebAssembly Corresponding intrinsic to wasm's 
unreachable^{⚠}  WebAssembly Generates the trap instruction 
f32x4_abs^{⚠}  ExperimentalWebAssembly and simd128 Calculates the absolute value of each lane of a 128bit vector interpreted as four 32bit floating point numbers. 
f32x4_add^{⚠}  ExperimentalWebAssembly and simd128 Adds pairwise lanes of two 128bit vectors interpreted as four 32bit floating point numbers. 
f32x4_const^{⚠}  ExperimentalWebAssembly and simd128 Materializes a constant SIMD value from the immediate operands. 
f32x4_convert_i32x4_s^{⚠}  ExperimentalWebAssembly and simd128 Converts a 128bit vector interpreted as four 32bit signed integers into a 128bit vector of four 32bit floating point numbers. 
f32x4_convert_i32x4_u^{⚠}  ExperimentalWebAssembly and simd128 Converts a 128bit vector interpreted as four 32bit unsigned integers into a 128bit vector of four 32bit floating point numbers. 
f32x4_div^{⚠}  ExperimentalWebAssembly and simd128 Divides pairwise lanes of two 128bit vectors interpreted as four 32bit floating point numbers. 
f32x4_eq^{⚠}  ExperimentalWebAssembly and simd128 Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit floating point numbers. 
f32x4_extract_lane^{⚠}  ExperimentalWebAssembly and simd128 Extracts a lane from a 128bit vector interpreted as 4 packed f32 numbers. 
f32x4_ge^{⚠}  ExperimentalWebAssembly and simd128 Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit floating point numbers. 
f32x4_gt^{⚠}  ExperimentalWebAssembly and simd128 Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit floating point numbers. 
f32x4_le^{⚠}  ExperimentalWebAssembly and simd128 Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit floating point numbers. 
f32x4_lt^{⚠}  ExperimentalWebAssembly and simd128 Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit floating point numbers. 
f32x4_max^{⚠}  ExperimentalWebAssembly and simd128 Calculates the maximum of pairwise lanes of two 128bit vectors interpreted as four 32bit floating point numbers. 
f32x4_min^{⚠}  ExperimentalWebAssembly and simd128 Calculates the minimum of pairwise lanes of two 128bit vectors interpreted as four 32bit floating point numbers. 
f32x4_mul^{⚠}  ExperimentalWebAssembly and simd128 Multiplies pairwise lanes of two 128bit vectors interpreted as four 32bit floating point numbers. 
f32x4_ne^{⚠}  ExperimentalWebAssembly and simd128 Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit floating point numbers. 
f32x4_neg^{⚠}  ExperimentalWebAssembly and simd128 Negates each lane of a 128bit vector interpreted as four 32bit floating point numbers. 
f32x4_replace_lane^{⚠}  ExperimentalWebAssembly and simd128 Replaces a lane from a 128bit vector interpreted as 4 packed f32 numbers. 
f32x4_splat^{⚠}  ExperimentalWebAssembly and simd128 Creates a vector with identical lanes. 
f32x4_sqrt^{⚠}  ExperimentalWebAssembly and simd128 Calculates the square root of each lane of a 128bit vector interpreted as four 32bit floating point numbers. 
f32x4_sub^{⚠}  ExperimentalWebAssembly and simd128 Subtracts pairwise lanes of two 128bit vectors interpreted as four 32bit floating point numbers. 
f64x2_abs^{⚠}  ExperimentalWebAssembly and simd128 Calculates the absolute value of each lane of a 128bit vector interpreted as two 64bit floating point numbers. 
f64x2_add^{⚠}  ExperimentalWebAssembly and simd128 Adds pairwise lanes of two 128bit vectors interpreted as two 64bit floating point numbers. 
f64x2_const^{⚠}  ExperimentalWebAssembly and simd128 Materializes a constant SIMD value from the immediate operands. 
f64x2_div^{⚠}  ExperimentalWebAssembly and simd128 Divides pairwise lanes of two 128bit vectors interpreted as two 64bit floating point numbers. 
f64x2_eq^{⚠}  ExperimentalWebAssembly and simd128 Compares two 128bit vectors as if they were two vectors of 2 sixtyfourbit floating point numbers. 
f64x2_extract_lane^{⚠}  ExperimentalWebAssembly and simd128 Extracts a lane from a 128bit vector interpreted as 2 packed f64 numbers. 
f64x2_ge^{⚠}  ExperimentalWebAssembly and simd128 Compares two 128bit vectors as if they were two vectors of 2 sixtyfourbit floating point numbers. 
f64x2_gt^{⚠}  ExperimentalWebAssembly and simd128 Compares two 128bit vectors as if they were two vectors of 2 sixtyfourbit floating point numbers. 
f64x2_le^{⚠}  ExperimentalWebAssembly and simd128 Compares two 128bit vectors as if they were two vectors of 2 sixtyfourbit floating point numbers. 
f64x2_lt^{⚠}  ExperimentalWebAssembly and simd128 Compares two 128bit vectors as if they were two vectors of 2 sixtyfourbit floating point numbers. 
f64x2_max^{⚠}  ExperimentalWebAssembly and simd128 Calculates the maximum of pairwise lanes of two 128bit vectors interpreted as two 64bit floating point numbers. 
f64x2_min^{⚠}  ExperimentalWebAssembly and simd128 Calculates the minimum of pairwise lanes of two 128bit vectors interpreted as two 64bit floating point numbers. 
f64x2_mul^{⚠}  ExperimentalWebAssembly and simd128 Multiplies pairwise lanes of two 128bit vectors interpreted as two 64bit floating point numbers. 
f64x2_ne^{⚠}  ExperimentalWebAssembly and simd128 Compares two 128bit vectors as if they were two vectors of 2 sixtyfourbit floating point numbers. 
f64x2_neg^{⚠}  ExperimentalWebAssembly and simd128 Negates each lane of a 128bit vector interpreted as two 64bit floating point numbers. 
f64x2_replace_lane^{⚠}  ExperimentalWebAssembly and simd128 Replaces a lane from a 128bit vector interpreted as 2 packed f64 numbers. 
f64x2_splat^{⚠}  ExperimentalWebAssembly and simd128 Creates a vector with identical lanes. 
f64x2_sqrt^{⚠}  ExperimentalWebAssembly and simd128 Calculates the square root of each lane of a 128bit vector interpreted as two 64bit floating point numbers. 
f64x2_sub^{⚠}  ExperimentalWebAssembly and simd128 Subtracts pairwise lanes of two 128bit vectors interpreted as two 64bit floating point numbers. 
i8x16_abs^{⚠}  ExperimentalWebAssembly and simd128 Lanewise wrapping absolute value. 
i8x16_add^{⚠}  ExperimentalWebAssembly and simd128 Adds two 128bit vectors as if they were two packed sixteen 8bit integers. 
i8x16_add_saturate_s^{⚠}  ExperimentalWebAssembly and simd128 Adds two 128bit vectors as if they were two packed sixteen 8bit signed
integers, saturating on overflow to 
i8x16_add_saturate_u^{⚠}  ExperimentalWebAssembly and simd128 Adds two 128bit vectors as if they were two packed sixteen 8bit unsigned
integers, saturating on overflow to 
i8x16_all_true^{⚠}  ExperimentalWebAssembly and simd128 Returns 1 if all lanes are nonzero or 0 if any lane is nonzero. 
i8x16_any_true^{⚠}  ExperimentalWebAssembly and simd128 Returns 1 if any lane is nonzero or 0 if all lanes are zero. 
i8x16_avgr_u^{⚠}  ExperimentalWebAssembly and simd128 Lanewise rounding average. 
i8x16_const^{⚠}  ExperimentalWebAssembly and simd128 Materializes a constant SIMD value from the immediate operands. 
i8x16_eq^{⚠}  ExperimentalWebAssembly and simd128 Compares two 128bit vectors as if they were two vectors of 16 eightbit integers. 
i8x16_extract_lane^{⚠}  ExperimentalWebAssembly and simd128 Extracts a lane from a 128bit vector interpreted as 16 packed i8 numbers. 
i8x16_ge_s^{⚠}  ExperimentalWebAssembly and simd128 Compares two 128bit vectors as if they were two vectors of 16 eightbit signed integers. 
i8x16_ge_u^{⚠}  ExperimentalWebAssembly and simd128 Compares two 128bit vectors as if they were two vectors of 16 eightbit unsigned integers. 
i8x16_gt_s^{⚠}  ExperimentalWebAssembly and simd128 Compares two 128bit vectors as if they were two vectors of 16 eightbit signed integers. 
i8x16_gt_u^{⚠}  ExperimentalWebAssembly and simd128 Compares two 128bit vectors as if they were two vectors of 16 eightbit unsigned integers. 
i8x16_le_s^{⚠}  ExperimentalWebAssembly and simd128 Compares two 128bit vectors as if they were two vectors of 16 eightbit signed integers. 
i8x16_le_u^{⚠}  ExperimentalWebAssembly and simd128 Compares two 128bit vectors as if they were two vectors of 16 eightbit unsigned integers. 
i8x16_lt_s^{⚠}  ExperimentalWebAssembly and simd128 Compares two 128bit vectors as if they were two vectors of 16 eightbit signed integers. 
i8x16_lt_u^{⚠}  ExperimentalWebAssembly and simd128 Compares two 128bit vectors as if they were two vectors of 16 eightbit unsigned integers. 
i8x16_max_s^{⚠}  ExperimentalWebAssembly and simd128 Compares lanewise signed integers, and returns the maximum of each pair. 
i8x16_max_u^{⚠}  ExperimentalWebAssembly and simd128 Compares lanewise unsigned integers, and returns the maximum of each pair. 
i8x16_min_s^{⚠}  ExperimentalWebAssembly and simd128 Compares lanewise signed integers, and returns the minimum of each pair. 
i8x16_min_u^{⚠}  ExperimentalWebAssembly and simd128 Compares lanewise unsigned integers, and returns the minimum of each pair. 
i8x16_narrow_i16x8_s^{⚠}  ExperimentalWebAssembly and simd128 Converts two input vectors into a smaller lane vector by narrowing each lane. 
i8x16_narrow_i16x8_u^{⚠}  ExperimentalWebAssembly and simd128 Converts two input vectors into a smaller lane vector by narrowing each lane. 
i8x16_ne^{⚠}  ExperimentalWebAssembly and simd128 Compares two 128bit vectors as if they were two vectors of 16 eightbit integers. 
i8x16_neg^{⚠}  ExperimentalWebAssembly and simd128 Negates a 128bit vectors intepreted as sixteen 8bit signed integers 
i8x16_replace_lane^{⚠}  ExperimentalWebAssembly and simd128 Replaces a lane from a 128bit vector interpreted as 16 packed i8 numbers. 
i8x16_shl^{⚠}  ExperimentalWebAssembly and simd128 Shifts each lane to the left by the specified number of bits. 
i8x16_shr_s^{⚠}  ExperimentalWebAssembly and simd128 Shifts each lane to the right by the specified number of bits, sign extending. 
i8x16_shr_u^{⚠}  ExperimentalWebAssembly and simd128 Shifts each lane to the right by the specified number of bits, shifting in zeros. 
i8x16_splat^{⚠}  ExperimentalWebAssembly and simd128 Creates a vector with identical lanes. 
i8x16_sub^{⚠}  ExperimentalWebAssembly and simd128 Subtracts two 128bit vectors as if they were two packed sixteen 8bit integers. 
i8x16_sub_saturate_s^{⚠}  ExperimentalWebAssembly and simd128 Subtracts two 128bit vectors as if they were two packed sixteen 8bit
signed integers, saturating on overflow to 
i8x16_sub_saturate_u^{⚠}  ExperimentalWebAssembly and simd128 Subtracts two 128bit vectors as if they were two packed sixteen 8bit unsigned integers, saturating on overflow to 0. 
i16x8_abs^{⚠}  ExperimentalWebAssembly and simd128 Lanewise wrapping absolute value. 
i16x8_add^{⚠}  ExperimentalWebAssembly and simd128 Adds two 128bit vectors as if they were two packed eight 16bit integers. 
i16x8_add_saturate_s^{⚠}  ExperimentalWebAssembly and simd128 Adds two 128bit vectors as if they were two packed eight 16bit signed
integers, saturating on overflow to 
i16x8_add_saturate_u^{⚠}  ExperimentalWebAssembly and simd128 Adds two 128bit vectors as if they were two packed eight 16bit unsigned
integers, saturating on overflow to 
i16x8_all_true^{⚠}  ExperimentalWebAssembly and simd128 Returns 1 if all lanes are nonzero or 0 if any lane is nonzero. 
i16x8_any_true^{⚠}  ExperimentalWebAssembly and simd128 Returns 1 if any lane is nonzero or 0 if all lanes are zero. 
i16x8_avgr_u^{⚠}  ExperimentalWebAssembly and simd128 Lanewise rounding average. 
i16x8_const^{⚠}  ExperimentalWebAssembly and simd128 Materializes a constant SIMD value from the immediate operands. 
i16x8_eq^{⚠}  ExperimentalWebAssembly and simd128 Compares two 128bit vectors as if they were two vectors of 8 sixteenbit integers. 
i16x8_extract_lane^{⚠}  ExperimentalWebAssembly and simd128 Extracts a lane from a 128bit vector interpreted as 8 packed i16 numbers. 
i16x8_ge_s^{⚠}  ExperimentalWebAssembly and simd128 Compares two 128bit vectors as if they were two vectors of 8 sixteenbit signed integers. 
i16x8_ge_u^{⚠}  ExperimentalWebAssembly and simd128 Compares two 128bit vectors as if they were two vectors of 8 sixteenbit unsigned integers. 
i16x8_gt_s^{⚠}  ExperimentalWebAssembly and simd128 Compares two 128bit vectors as if they were two vectors of 8 sixteenbit signed integers. 
i16x8_gt_u^{⚠}  ExperimentalWebAssembly and simd128 Compares two 128bit vectors as if they were two vectors of 8 sixteenbit unsigned integers. 
i16x8_le_s^{⚠}  ExperimentalWebAssembly and simd128 Compares two 128bit vectors as if they were two vectors of 8 sixteenbit signed integers. 
i16x8_le_u^{⚠}  ExperimentalWebAssembly and simd128 Compares two 128bit vectors as if they were two vectors of 8 sixteenbit unsigned integers. 
i16x8_load8x8_s^{⚠}  ExperimentalWebAssembly and simd128 Load eight 8bit integers and sign extend each one to a 16bit lane 
i16x8_load8x8_u^{⚠}  ExperimentalWebAssembly and simd128 Load eight 8bit integers and zero extend each one to a 16bit lane 
i16x8_lt_s^{⚠}  ExperimentalWebAssembly and simd128 Compares two 128bit vectors as if they were two vectors of 8 sixteenbit signed integers. 
i16x8_lt_u^{⚠}  ExperimentalWebAssembly and simd128 Compares two 128bit vectors as if they were two vectors of 8 sixteenbit unsigned integers. 
i16x8_max_s^{⚠}  ExperimentalWebAssembly and simd128 Compares lanewise signed integers, and returns the maximum of each pair. 
i16x8_max_u^{⚠}  ExperimentalWebAssembly and simd128 Compares lanewise unsigned integers, and returns the maximum of each pair. 
i16x8_min_s^{⚠}  ExperimentalWebAssembly and simd128 Compares lanewise signed integers, and returns the minimum of each pair. 
i16x8_min_u^{⚠}  ExperimentalWebAssembly and simd128 Compares lanewise unsigned integers, and returns the minimum of each pair. 
i16x8_mul^{⚠}  ExperimentalWebAssembly and simd128 Multiplies two 128bit vectors as if they were two packed eight 16bit signed integers. 
i16x8_narrow_i32x4_s^{⚠}  ExperimentalWebAssembly and simd128 Converts two input vectors into a smaller lane vector by narrowing each lane. 
i16x8_narrow_i32x4_u^{⚠}  ExperimentalWebAssembly and simd128 Converts two input vectors into a smaller lane vector by narrowing each lane. 
i16x8_ne^{⚠}  ExperimentalWebAssembly and simd128 Compares two 128bit vectors as if they were two vectors of 8 sixteenbit integers. 
i16x8_neg^{⚠}  ExperimentalWebAssembly and simd128 Negates a 128bit vectors intepreted as eight 16bit signed integers 
i16x8_replace_lane^{⚠}  ExperimentalWebAssembly and simd128 Replaces a lane from a 128bit vector interpreted as 8 packed i16 numbers. 
i16x8_shl^{⚠}  ExperimentalWebAssembly and simd128 Shifts each lane to the left by the specified number of bits. 
i16x8_shr_s^{⚠}  ExperimentalWebAssembly and simd128 Shifts each lane to the right by the specified number of bits, sign extending. 
i16x8_shr_u^{⚠}  ExperimentalWebAssembly and simd128 Shifts each lane to the right by the specified number of bits, shifting in zeros. 
i16x8_splat^{⚠}  ExperimentalWebAssembly and simd128 Creates a vector with identical lanes. 
i16x8_sub^{⚠}  ExperimentalWebAssembly and simd128 Subtracts two 128bit vectors as if they were two packed eight 16bit integers. 
i16x8_sub_saturate_s^{⚠}  ExperimentalWebAssembly and simd128 Subtracts two 128bit vectors as if they were two packed eight 16bit
signed integers, saturating on overflow to 
i16x8_sub_saturate_u^{⚠}  ExperimentalWebAssembly and simd128 Subtracts two 128bit vectors as if they were two packed eight 16bit unsigned integers, saturating on overflow to 0. 
i16x8_widen_high_i8x16_s^{⚠}  ExperimentalWebAssembly Converts high half of the smaller lane vector to a larger lane vector, sign extended. 
i16x8_widen_high_i8x16_u^{⚠}  ExperimentalWebAssembly Converts high half of the smaller lane vector to a larger lane vector, zero extended. 
i16x8_widen_low_i8x16_s^{⚠}  ExperimentalWebAssembly Converts low half of the smaller lane vector to a larger lane vector, sign extended. 
i16x8_widen_low_i8x16_u^{⚠}  ExperimentalWebAssembly Converts low half of the smaller lane vector to a larger lane vector, zero extended. 
i32x4_abs^{⚠}  ExperimentalWebAssembly and simd128 Lanewise wrapping absolute value. 
i32x4_add^{⚠}  ExperimentalWebAssembly and simd128 Adds two 128bit vectors as if they were two packed four 32bit integers. 
i32x4_all_true^{⚠}  ExperimentalWebAssembly and simd128 Returns 1 if all lanes are nonzero or 0 if any lane is nonzero. 
i32x4_any_true^{⚠}  ExperimentalWebAssembly and simd128 Returns 1 if any lane is nonzero or 0 if all lanes are zero. 
i32x4_const^{⚠}  ExperimentalWebAssembly and simd128 Materializes a constant SIMD value from the immediate operands. 
i32x4_eq^{⚠}  ExperimentalWebAssembly and simd128 Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit integers. 
i32x4_extract_lane^{⚠}  ExperimentalWebAssembly and simd128 Extracts a lane from a 128bit vector interpreted as 4 packed i32 numbers. 
i32x4_ge_s^{⚠}  ExperimentalWebAssembly and simd128 Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit signed integers. 
i32x4_ge_u^{⚠}  ExperimentalWebAssembly and simd128 Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit unsigned integers. 
i32x4_gt_s^{⚠}  ExperimentalWebAssembly and simd128 Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit signed integers. 
i32x4_gt_u^{⚠}  ExperimentalWebAssembly and simd128 Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit unsigned integers. 
i32x4_le_s^{⚠}  ExperimentalWebAssembly and simd128 Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit signed integers. 
i32x4_le_u^{⚠}  ExperimentalWebAssembly and simd128 Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit unsigned integers. 
i32x4_load16x4_s^{⚠}  ExperimentalWebAssembly and simd128 Load four 16bit integers and sign extend each one to a 32bit lane 
i32x4_load16x4_u^{⚠}  ExperimentalWebAssembly and simd128 Load four 16bit integers and zero extend each one to a 32bit lane 
i32x4_lt_s^{⚠}  ExperimentalWebAssembly and simd128 Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit signed integers. 
i32x4_lt_u^{⚠}  ExperimentalWebAssembly and simd128 Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit unsigned integers. 
i32x4_max_s^{⚠}  ExperimentalWebAssembly and simd128 Compares lanewise signed integers, and returns the maximum of each pair. 
i32x4_max_u^{⚠}  ExperimentalWebAssembly and simd128 Compares lanewise unsigned integers, and returns the maximum of each pair. 
i32x4_min_s^{⚠}  ExperimentalWebAssembly and simd128 Compares lanewise signed integers, and returns the minimum of each pair. 
i32x4_min_u^{⚠}  ExperimentalWebAssembly and simd128 Compares lanewise unsigned integers, and returns the minimum of each pair. 
i32x4_mul^{⚠}  ExperimentalWebAssembly and simd128 Multiplies two 128bit vectors as if they were two packed four 32bit signed integers. 
i32x4_ne^{⚠}  ExperimentalWebAssembly and simd128 Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit integers. 
i32x4_neg^{⚠}  ExperimentalWebAssembly and simd128 Negates a 128bit vectors intepreted as four 32bit signed integers 
i32x4_replace_lane^{⚠}  ExperimentalWebAssembly and simd128 Replaces a lane from a 128bit vector interpreted as 4 packed i32 numbers. 
i32x4_shl^{⚠}  ExperimentalWebAssembly and simd128 Shifts each lane to the left by the specified number of bits. 
i32x4_shr_s^{⚠}  ExperimentalWebAssembly and simd128 Shifts each lane to the right by the specified number of bits, sign extending. 
i32x4_shr_u^{⚠}  ExperimentalWebAssembly and simd128 Shifts each lane to the right by the specified number of bits, shifting in zeros. 
i32x4_splat^{⚠}  ExperimentalWebAssembly and simd128 Creates a vector with identical lanes. 
i32x4_sub^{⚠}  ExperimentalWebAssembly and simd128 Subtracts two 128bit vectors as if they were two packed four 32bit integers. 
i32x4_trunc_sat_f32x4_s^{⚠}  ExperimentalWebAssembly and simd128 Converts a 128bit vector interpreted as four 32bit floating point numbers into a 128bit vector of four 32bit signed integers. 
i32x4_trunc_sat_f32x4_u^{⚠}  ExperimentalWebAssembly and simd128 Converts a 128bit vector interpreted as four 32bit floating point numbers into a 128bit vector of four 32bit unsigned integers. 
i32x4_widen_high_i16x8_s^{⚠}  ExperimentalWebAssembly Converts high half of the smaller lane vector to a larger lane vector, sign extended. 
i32x4_widen_high_i16x8_u^{⚠}  ExperimentalWebAssembly Converts high half of the smaller lane vector to a larger lane vector, zero extended. 
i32x4_widen_low_i16x8_s^{⚠}  ExperimentalWebAssembly Converts low half of the smaller lane vector to a larger lane vector, sign extended. 
i32x4_widen_low_i16x8_u^{⚠}  ExperimentalWebAssembly Converts low half of the smaller lane vector to a larger lane vector, zero extended. 
i64x2_add^{⚠}  ExperimentalWebAssembly and simd128 Adds two 128bit vectors as if they were two packed two 64bit integers. 
i64x2_const^{⚠}  ExperimentalWebAssembly and simd128 Materializes a constant SIMD value from the immediate operands. 
i64x2_extract_lane^{⚠}  ExperimentalWebAssembly and simd128 Extracts a lane from a 128bit vector interpreted as 2 packed i64 numbers. 
i64x2_load32x2_s^{⚠}  ExperimentalWebAssembly and simd128 Load two 32bit integers and sign extend each one to a 64bit lane 
i64x2_load32x2_u^{⚠}  ExperimentalWebAssembly and simd128 Load two 32bit integers and zero extend each one to a 64bit lane 
i64x2_mul^{⚠}  ExperimentalWebAssembly and simd128 Multiplies two 128bit vectors as if they were two packed two 64bit integers. 
i64x2_neg^{⚠}  ExperimentalWebAssembly and simd128 Negates a 128bit vectors intepreted as two 64bit signed integers 
i64x2_replace_lane^{⚠}  ExperimentalWebAssembly and simd128 Replaces a lane from a 128bit vector interpreted as 2 packed i64 numbers. 
i64x2_shl^{⚠}  ExperimentalWebAssembly and simd128 Shifts each lane to the left by the specified number of bits. 
i64x2_shr_s^{⚠}  ExperimentalWebAssembly and simd128 Shifts each lane to the right by the specified number of bits, sign extending. 
i64x2_shr_u^{⚠}  ExperimentalWebAssembly and simd128 Shifts each lane to the right by the specified number of bits, shifting in zeros. 
i64x2_splat^{⚠}  ExperimentalWebAssembly and simd128 Creates a vector with identical lanes. 
i64x2_sub^{⚠}  ExperimentalWebAssembly and simd128 Subtracts two 128bit vectors as if they were two packed two 64bit integers. 
memory_atomic_notify^{⚠}  ExperimentalWebAssembly Corresponding intrinsic to wasm's 
memory_atomic_wait32^{⚠}  ExperimentalWebAssembly Corresponding intrinsic to wasm's 
memory_atomic_wait64^{⚠}  ExperimentalWebAssembly Corresponding intrinsic to wasm's 
v8x16_load_splat^{⚠}  ExperimentalWebAssembly and simd128 Load a single element and splat to all lanes of a v128 vector. 
v8x16_shuffle^{⚠}  ExperimentalWebAssembly and simd128 Returns a new vector with lanes selected from the lanes of the two input
vectors 
v8x16_swizzle^{⚠}  ExperimentalWebAssembly and simd128 Returns a new vector with lanes selected from the lanes of the first input
vector 
v16x8_load_splat^{⚠}  ExperimentalWebAssembly and simd128 Load a single element and splat to all lanes of a v128 vector. 
v16x8_shuffle^{⚠}  ExperimentalWebAssembly and simd128 Same as 
v32x4_load_splat^{⚠}  ExperimentalWebAssembly and simd128 Load a single element and splat to all lanes of a v128 vector. 
v32x4_shuffle^{⚠}  ExperimentalWebAssembly and simd128 Same as 
v64x2_load_splat^{⚠}  ExperimentalWebAssembly and simd128 Load a single element and splat to all lanes of a v128 vector. 
v64x2_shuffle^{⚠}  ExperimentalWebAssembly and simd128 Same as 
v128_and^{⚠}  ExperimentalWebAssembly and simd128 Performs a bitwise and of the two input 128bit vectors, returning the resulting vector. 
v128_andnot^{⚠}  ExperimentalWebAssembly and simd128 Bitwise AND of bits of 
v128_bitselect^{⚠}  ExperimentalWebAssembly and simd128 Use the bitmask in 
v128_load^{⚠}  ExperimentalWebAssembly and simd128 Loads a 
v128_not^{⚠}  ExperimentalWebAssembly and simd128 Flips each bit of the 128bit input vector. 
v128_or^{⚠}  ExperimentalWebAssembly and simd128 Performs a bitwise or of the two input 128bit vectors, returning the resulting vector. 
v128_store^{⚠}  ExperimentalWebAssembly and simd128 Stores a 
v128_xor^{⚠}  ExperimentalWebAssembly and simd128 Performs a bitwise xor of the two input 128bit vectors, returning the resulting vector. 