rustc_hir_typeck/
inline_asm.rs

1use rustc_abi::FieldIdx;
2use rustc_ast::InlineAsmTemplatePiece;
3use rustc_data_structures::fx::FxIndexSet;
4use rustc_hir::def_id::DefId;
5use rustc_hir::{self as hir, LangItem};
6use rustc_middle::bug;
7use rustc_middle::ty::{self, Article, FloatTy, IntTy, Ty, TyCtxt, TypeVisitableExt, UintTy};
8use rustc_session::lint;
9use rustc_span::def_id::LocalDefId;
10use rustc_span::{ErrorGuaranteed, Span, Symbol, sym};
11use rustc_target::asm::{
12    InlineAsmReg, InlineAsmRegClass, InlineAsmRegOrRegClass, InlineAsmType, ModifierInfo,
13};
14use rustc_trait_selection::infer::InferCtxtExt;
15
16use crate::FnCtxt;
17use crate::errors::RegisterTypeUnstable;
18
19pub(crate) struct InlineAsmCtxt<'a, 'tcx> {
20    target_features: &'tcx FxIndexSet<Symbol>,
21    fcx: &'a FnCtxt<'a, 'tcx>,
22}
23
24enum NonAsmTypeReason<'tcx> {
25    UnevaluatedSIMDArrayLength(DefId, ty::Const<'tcx>),
26    Invalid(Ty<'tcx>),
27    InvalidElement(DefId, Ty<'tcx>),
28    NotSizedPtr(Ty<'tcx>),
29    EmptySIMDArray(Ty<'tcx>),
30    Tainted(ErrorGuaranteed),
31}
32
33impl<'a, 'tcx> InlineAsmCtxt<'a, 'tcx> {
34    pub(crate) fn new(fcx: &'a FnCtxt<'a, 'tcx>, def_id: LocalDefId) -> Self {
35        InlineAsmCtxt { target_features: fcx.tcx.asm_target_features(def_id), fcx }
36    }
37
38    fn tcx(&self) -> TyCtxt<'tcx> {
39        self.fcx.tcx
40    }
41
42    fn expr_ty(&self, expr: &hir::Expr<'tcx>) -> Ty<'tcx> {
43        let ty = self.fcx.typeck_results.borrow().expr_ty_adjusted(expr);
44        let ty = self.fcx.try_structurally_resolve_type(expr.span, ty);
45        if ty.has_non_region_infer() {
46            Ty::new_misc_error(self.tcx())
47        } else {
48            self.tcx().erase_and_anonymize_regions(ty)
49        }
50    }
51
52    // FIXME(compiler-errors): This could use `<$ty as Pointee>::Metadata == ()`
53    fn is_thin_ptr_ty(&self, span: Span, ty: Ty<'tcx>) -> bool {
54        // Type still may have region variables, but `Sized` does not depend
55        // on those, so just erase them before querying.
56        if self.fcx.type_is_sized_modulo_regions(self.fcx.param_env, ty) {
57            return true;
58        }
59        if let ty::Foreign(..) = self.fcx.try_structurally_resolve_type(span, ty).kind() {
60            return true;
61        }
62        false
63    }
64
65    fn get_asm_ty(
66        &self,
67        span: Span,
68        ty: Ty<'tcx>,
69    ) -> Result<InlineAsmType, NonAsmTypeReason<'tcx>> {
70        let asm_ty_isize = match self.tcx().sess.target.pointer_width {
71            16 => InlineAsmType::I16,
72            32 => InlineAsmType::I32,
73            64 => InlineAsmType::I64,
74            width => bug!("unsupported pointer width: {width}"),
75        };
76
77        match *ty.kind() {
78            ty::Int(IntTy::I8) | ty::Uint(UintTy::U8) => Ok(InlineAsmType::I8),
79            ty::Int(IntTy::I16) | ty::Uint(UintTy::U16) => Ok(InlineAsmType::I16),
80            ty::Int(IntTy::I32) | ty::Uint(UintTy::U32) => Ok(InlineAsmType::I32),
81            ty::Int(IntTy::I64) | ty::Uint(UintTy::U64) => Ok(InlineAsmType::I64),
82            ty::Int(IntTy::I128) | ty::Uint(UintTy::U128) => Ok(InlineAsmType::I128),
83            ty::Int(IntTy::Isize) | ty::Uint(UintTy::Usize) => Ok(asm_ty_isize),
84            ty::Float(FloatTy::F16) => Ok(InlineAsmType::F16),
85            ty::Float(FloatTy::F32) => Ok(InlineAsmType::F32),
86            ty::Float(FloatTy::F64) => Ok(InlineAsmType::F64),
87            ty::Float(FloatTy::F128) => Ok(InlineAsmType::F128),
88            ty::FnPtr(..) => Ok(asm_ty_isize),
89            ty::RawPtr(elem_ty, _) => {
90                if self.is_thin_ptr_ty(span, elem_ty) {
91                    Ok(asm_ty_isize)
92                } else {
93                    Err(NonAsmTypeReason::NotSizedPtr(ty))
94                }
95            }
96            ty::Adt(adt, args) if adt.repr().simd() => {
97                if !adt.is_struct() {
98                    let guar = self.fcx.dcx().span_delayed_bug(
99                        span,
100                        format!("repr(simd) should only be used on structs, got {}", adt.descr()),
101                    );
102                    return Err(NonAsmTypeReason::Tainted(guar));
103                }
104
105                let fields = &adt.non_enum_variant().fields;
106                if fields.is_empty() {
107                    return Err(NonAsmTypeReason::EmptySIMDArray(ty));
108                }
109                let field = &fields[FieldIdx::ZERO];
110                let elem_ty = field.ty(self.tcx(), args);
111
112                let (size, ty) = match *elem_ty.kind() {
113                    ty::Array(ty, len) => {
114                        // FIXME: `try_structurally_resolve_const` doesn't eval consts
115                        // in the old solver.
116                        let len = if self.fcx.next_trait_solver() {
117                            self.fcx.try_structurally_resolve_const(span, len)
118                        } else {
119                            self.fcx.tcx.normalize_erasing_regions(
120                                self.fcx.typing_env(self.fcx.param_env),
121                                len,
122                            )
123                        };
124                        let Some(len) = len.try_to_target_usize(self.tcx()) else {
125                            return Err(NonAsmTypeReason::UnevaluatedSIMDArrayLength(
126                                field.did, len,
127                            ));
128                        };
129                        (len, ty)
130                    }
131                    _ => (fields.len() as u64, elem_ty),
132                };
133
134                match ty.kind() {
135                    ty::Int(IntTy::I8) | ty::Uint(UintTy::U8) => Ok(InlineAsmType::VecI8(size)),
136                    ty::Int(IntTy::I16) | ty::Uint(UintTy::U16) => Ok(InlineAsmType::VecI16(size)),
137                    ty::Int(IntTy::I32) | ty::Uint(UintTy::U32) => Ok(InlineAsmType::VecI32(size)),
138                    ty::Int(IntTy::I64) | ty::Uint(UintTy::U64) => Ok(InlineAsmType::VecI64(size)),
139                    ty::Int(IntTy::I128) | ty::Uint(UintTy::U128) => {
140                        Ok(InlineAsmType::VecI128(size))
141                    }
142                    ty::Int(IntTy::Isize) | ty::Uint(UintTy::Usize) => {
143                        Ok(match self.tcx().sess.target.pointer_width {
144                            16 => InlineAsmType::VecI16(size),
145                            32 => InlineAsmType::VecI32(size),
146                            64 => InlineAsmType::VecI64(size),
147                            width => bug!("unsupported pointer width: {width}"),
148                        })
149                    }
150                    ty::Float(FloatTy::F16) => Ok(InlineAsmType::VecF16(size)),
151                    ty::Float(FloatTy::F32) => Ok(InlineAsmType::VecF32(size)),
152                    ty::Float(FloatTy::F64) => Ok(InlineAsmType::VecF64(size)),
153                    ty::Float(FloatTy::F128) => Ok(InlineAsmType::VecF128(size)),
154                    _ => Err(NonAsmTypeReason::InvalidElement(field.did, ty)),
155                }
156            }
157            ty::Infer(_) => bug!("unexpected infer ty in asm operand"),
158            _ => Err(NonAsmTypeReason::Invalid(ty)),
159        }
160    }
161
162    fn check_asm_operand_type(
163        &self,
164        idx: usize,
165        reg: InlineAsmRegOrRegClass,
166        expr: &'tcx hir::Expr<'tcx>,
167        template: &[InlineAsmTemplatePiece],
168        is_input: bool,
169        tied_input: Option<(&'tcx hir::Expr<'tcx>, Option<InlineAsmType>)>,
170    ) -> Option<InlineAsmType> {
171        let ty = self.expr_ty(expr);
172        if ty.has_non_region_infer() {
173            bug!("inference variable in asm operand ty: {:?} {:?}", expr, ty);
174        }
175
176        let asm_ty = match *ty.kind() {
177            // `!` is allowed for input but not for output (issue #87802)
178            ty::Never if is_input => return None,
179            _ if ty.references_error() => return None,
180            ty::Adt(adt, args) if self.tcx().is_lang_item(adt.did(), LangItem::MaybeUninit) => {
181                let ty = args.type_at(0);
182                self.get_asm_ty(expr.span, ty)
183            }
184            _ => self.get_asm_ty(expr.span, ty),
185        };
186        let asm_ty = match asm_ty {
187            Ok(asm_ty) => asm_ty,
188            Err(reason) => {
189                match reason {
190                    NonAsmTypeReason::UnevaluatedSIMDArrayLength(did, len) => {
191                        let msg = format!("cannot evaluate SIMD vector length `{len}`");
192                        self.fcx
193                            .dcx()
194                            .struct_span_err(self.tcx().def_span(did), msg)
195                            .with_span_note(
196                                expr.span,
197                                "SIMD vector length needs to be known statically for use in `asm!`",
198                            )
199                            .emit();
200                    }
201                    NonAsmTypeReason::Invalid(ty) => {
202                        let msg = format!("cannot use value of type `{ty}` for inline assembly");
203                        self.fcx.dcx().struct_span_err(expr.span, msg).with_note(
204                            "only integers, floats, SIMD vectors, pointers and function pointers \
205                            can be used as arguments for inline assembly",
206                        ).emit();
207                    }
208                    NonAsmTypeReason::NotSizedPtr(ty) => {
209                        let msg = format!(
210                            "cannot use value of unsized pointer type `{ty}` for inline assembly"
211                        );
212                        self.fcx
213                            .dcx()
214                            .struct_span_err(expr.span, msg)
215                            .with_note("only sized pointers can be used in inline assembly")
216                            .emit();
217                    }
218                    NonAsmTypeReason::InvalidElement(did, ty) => {
219                        let msg = format!(
220                            "cannot use SIMD vector with element type `{ty}` for inline assembly"
221                        );
222                        self.fcx.dcx()
223                        .struct_span_err(self.tcx().def_span(did), msg).with_span_note(
224                            expr.span,
225                            "only integers, floats, SIMD vectors, pointers and function pointers \
226                            can be used as arguments for inline assembly",
227                        ).emit();
228                    }
229                    NonAsmTypeReason::EmptySIMDArray(ty) => {
230                        let msg = format!("use of empty SIMD vector `{ty}`");
231                        self.fcx.dcx().struct_span_err(expr.span, msg).emit();
232                    }
233                    NonAsmTypeReason::Tainted(_error_guard) => {
234                        // An error has already been reported.
235                    }
236                }
237                return None;
238            }
239        };
240
241        // Check that the type implements Copy. The only case where this can
242        // possibly fail is for SIMD types which don't #[derive(Copy)].
243        if !self.fcx.type_is_copy_modulo_regions(self.fcx.param_env, ty) {
244            let msg = "arguments for inline assembly must be copyable";
245            self.fcx
246                .dcx()
247                .struct_span_err(expr.span, msg)
248                .with_note(format!("`{ty}` does not implement the Copy trait"))
249                .emit();
250        }
251
252        // Ideally we wouldn't need to do this, but LLVM's register allocator
253        // really doesn't like it when tied operands have different types.
254        //
255        // This is purely an LLVM limitation, but we have to live with it since
256        // there is no way to hide this with implicit conversions.
257        //
258        // For the purposes of this check we only look at the `InlineAsmType`,
259        // which means that pointers and integers are treated as identical (modulo
260        // size).
261        if let Some((in_expr, Some(in_asm_ty))) = tied_input {
262            if in_asm_ty != asm_ty {
263                let msg = "incompatible types for asm inout argument";
264                let in_expr_ty = self.expr_ty(in_expr);
265                self.fcx
266                    .dcx()
267                    .struct_span_err(vec![in_expr.span, expr.span], msg)
268                    .with_span_label(in_expr.span, format!("type `{in_expr_ty}`"))
269                    .with_span_label(expr.span, format!("type `{ty}`"))
270                    .with_note(
271                        "asm inout arguments must have the same type, \
272                        unless they are both pointers or integers of the same size",
273                    )
274                    .emit();
275            }
276
277            // All of the later checks have already been done on the input, so
278            // let's not emit errors and warnings twice.
279            return Some(asm_ty);
280        }
281
282        // Check the type against the list of types supported by the selected
283        // register class.
284        let asm_arch = self.tcx().sess.asm_arch.unwrap();
285        let allow_experimental_reg = self.tcx().features().asm_experimental_reg();
286        let reg_class = reg.reg_class();
287        let supported_tys = reg_class.supported_types(asm_arch, allow_experimental_reg);
288        let Some((_, feature)) = supported_tys.iter().find(|&&(t, _)| t == asm_ty) else {
289            let mut err = if !allow_experimental_reg
290                && reg_class.supported_types(asm_arch, true).iter().any(|&(t, _)| t == asm_ty)
291            {
292                self.tcx().sess.create_feature_err(
293                    RegisterTypeUnstable { span: expr.span, ty },
294                    sym::asm_experimental_reg,
295                )
296            } else {
297                let msg = format!("type `{ty}` cannot be used with this register class");
298                let mut err = self.fcx.dcx().struct_span_err(expr.span, msg);
299                let supported_tys: Vec<_> =
300                    supported_tys.iter().map(|(t, _)| t.to_string()).collect();
301                err.note(format!(
302                    "register class `{}` supports these types: {}",
303                    reg_class.name(),
304                    supported_tys.join(", "),
305                ));
306                err
307            };
308            if let Some(suggest) = reg_class.suggest_class(asm_arch, asm_ty) {
309                err.help(format!("consider using the `{}` register class instead", suggest.name()));
310            }
311            err.emit();
312            return Some(asm_ty);
313        };
314
315        // Check whether the selected type requires a target feature. Note that
316        // this is different from the feature check we did earlier. While the
317        // previous check checked that this register class is usable at all
318        // with the currently enabled features, some types may only be usable
319        // with a register class when a certain feature is enabled. We check
320        // this here since it depends on the results of typeck.
321        //
322        // Also note that this check isn't run when the operand type is never
323        // (!). In that case we still need the earlier check to verify that the
324        // register class is usable at all.
325        if let Some(feature) = feature {
326            if !self.target_features.contains(feature) {
327                let msg = format!("`{feature}` target feature is not enabled");
328                self.fcx
329                    .dcx()
330                    .struct_span_err(expr.span, msg)
331                    .with_note(format!(
332                        "this is required to use type `{}` with register class `{}`",
333                        ty,
334                        reg_class.name(),
335                    ))
336                    .emit();
337                return Some(asm_ty);
338            }
339        }
340
341        // Check whether a modifier is suggested for using this type.
342        if let Some(ModifierInfo {
343            modifier: suggested_modifier,
344            result: suggested_result,
345            size: suggested_size,
346        }) = reg_class.suggest_modifier(asm_arch, asm_ty)
347        {
348            // Search for any use of this operand without a modifier and emit
349            // the suggestion for them.
350            let mut spans = vec![];
351            for piece in template {
352                if let &InlineAsmTemplatePiece::Placeholder { operand_idx, modifier, span } = piece
353                {
354                    if operand_idx == idx && modifier.is_none() {
355                        spans.push(span);
356                    }
357                }
358            }
359            if !spans.is_empty() {
360                let ModifierInfo {
361                    modifier: default_modifier,
362                    result: default_result,
363                    size: default_size,
364                } = reg_class.default_modifier(asm_arch).unwrap();
365                self.tcx().node_span_lint(
366                    lint::builtin::ASM_SUB_REGISTER,
367                    expr.hir_id,
368                    spans,
369                    |lint| {
370                        lint.primary_message("formatting may not be suitable for sub-register argument");
371                        lint.span_label(expr.span, "for this argument");
372                        lint.help(format!(
373                            "use `{{{idx}:{suggested_modifier}}}` to have the register formatted as `{suggested_result}` (for {suggested_size}-bit values)",
374                        ));
375                        lint.help(format!(
376                            "or use `{{{idx}:{default_modifier}}}` to keep the default formatting of `{default_result}` (for {default_size}-bit values)",
377                        ));
378                    },
379                );
380            }
381        }
382
383        Some(asm_ty)
384    }
385
386    pub(crate) fn check_asm(&self, asm: &hir::InlineAsm<'tcx>) {
387        let Some(asm_arch) = self.tcx().sess.asm_arch else {
388            self.fcx.dcx().delayed_bug("target architecture does not support asm");
389            return;
390        };
391        let allow_experimental_reg = self.tcx().features().asm_experimental_reg();
392        for (idx, &(op, op_sp)) in asm.operands.iter().enumerate() {
393            // Validate register classes against currently enabled target
394            // features. We check that at least one type is available for
395            // the enabled features.
396            //
397            // We ignore target feature requirements for clobbers: if the
398            // feature is disabled then the compiler doesn't care what we
399            // do with the registers.
400            //
401            // Note that this is only possible for explicit register
402            // operands, which cannot be used in the asm string.
403            if let Some(reg) = op.reg() {
404                // Some explicit registers cannot be used depending on the
405                // target. Reject those here.
406                if let InlineAsmRegOrRegClass::Reg(reg) = reg {
407                    if let InlineAsmReg::Err = reg {
408                        // `validate` will panic on `Err`, as an error must
409                        // already have been reported.
410                        continue;
411                    }
412                    if let Err(msg) = reg.validate(
413                        asm_arch,
414                        self.tcx().sess.relocation_model(),
415                        self.target_features,
416                        &self.tcx().sess.target,
417                        op.is_clobber(),
418                    ) {
419                        let msg = format!("cannot use register `{}`: {}", reg.name(), msg);
420                        self.fcx.dcx().span_err(op_sp, msg);
421                        continue;
422                    }
423                }
424
425                if !op.is_clobber() {
426                    let mut missing_required_features = vec![];
427                    let reg_class = reg.reg_class();
428                    if let InlineAsmRegClass::Err = reg_class {
429                        continue;
430                    }
431                    for &(_, feature) in reg_class.supported_types(asm_arch, allow_experimental_reg)
432                    {
433                        match feature {
434                            Some(feature) => {
435                                if self.target_features.contains(&feature) {
436                                    missing_required_features.clear();
437                                    break;
438                                } else {
439                                    missing_required_features.push(feature);
440                                }
441                            }
442                            None => {
443                                missing_required_features.clear();
444                                break;
445                            }
446                        }
447                    }
448
449                    // We are sorting primitive strs here and can use unstable sort here
450                    missing_required_features.sort_unstable();
451                    missing_required_features.dedup();
452                    match &missing_required_features[..] {
453                        [] => {}
454                        [feature] => {
455                            let msg = format!(
456                                "register class `{}` requires the `{}` target feature",
457                                reg_class.name(),
458                                feature
459                            );
460                            self.fcx.dcx().span_err(op_sp, msg);
461                            // register isn't enabled, don't do more checks
462                            continue;
463                        }
464                        features => {
465                            let msg = format!(
466                                "register class `{}` requires at least one of the following target features: {}",
467                                reg_class.name(),
468                                features
469                                    .iter()
470                                    .map(|f| f.as_str())
471                                    .intersperse(", ")
472                                    .collect::<String>(),
473                            );
474                            self.fcx.dcx().span_err(op_sp, msg);
475                            // register isn't enabled, don't do more checks
476                            continue;
477                        }
478                    }
479                }
480            }
481
482            match op {
483                hir::InlineAsmOperand::In { reg, expr } => {
484                    self.check_asm_operand_type(idx, reg, expr, asm.template, true, None);
485                }
486                hir::InlineAsmOperand::Out { reg, late: _, expr } => {
487                    if let Some(expr) = expr {
488                        self.check_asm_operand_type(idx, reg, expr, asm.template, false, None);
489                    }
490                }
491                hir::InlineAsmOperand::InOut { reg, late: _, expr } => {
492                    self.check_asm_operand_type(idx, reg, expr, asm.template, false, None);
493                }
494                hir::InlineAsmOperand::SplitInOut { reg, late: _, in_expr, out_expr } => {
495                    let in_ty =
496                        self.check_asm_operand_type(idx, reg, in_expr, asm.template, true, None);
497                    if let Some(out_expr) = out_expr {
498                        self.check_asm_operand_type(
499                            idx,
500                            reg,
501                            out_expr,
502                            asm.template,
503                            false,
504                            Some((in_expr, in_ty)),
505                        );
506                    }
507                }
508                hir::InlineAsmOperand::Const { anon_const } => {
509                    let ty = self.expr_ty(self.tcx().hir_body(anon_const.body).value);
510                    match ty.kind() {
511                        ty::Error(_) => {}
512                        _ if ty.is_integral() => {}
513                        _ => {
514                            self.fcx
515                                .dcx()
516                                .struct_span_err(op_sp, "invalid type for `const` operand")
517                                .with_span_label(
518                                    self.tcx().def_span(anon_const.def_id),
519                                    format!("is {} `{}`", ty.kind().article(), ty),
520                                )
521                                .with_help("`const` operands must be of an integer type")
522                                .emit();
523                        }
524                    }
525                }
526                // Typeck has checked that SymFn refers to a function.
527                hir::InlineAsmOperand::SymFn { expr } => {
528                    let ty = self.expr_ty(expr);
529                    match ty.kind() {
530                        ty::FnDef(..) => {}
531                        ty::Error(_) => {}
532                        _ => {
533                            self.fcx
534                                .dcx()
535                                .struct_span_err(op_sp, "invalid `sym` operand")
536                                .with_span_label(
537                                    expr.span,
538                                    format!("is {} `{}`", ty.kind().article(), ty),
539                                )
540                                .with_help(
541                                    "`sym` operands must refer to either a function or a static",
542                                )
543                                .emit();
544                        }
545                    }
546                }
547                // AST lowering guarantees that SymStatic points to a static.
548                hir::InlineAsmOperand::SymStatic { .. } => {}
549                // No special checking is needed for labels.
550                hir::InlineAsmOperand::Label { .. } => {}
551            }
552        }
553    }
554}
rustc_hir_typeck/inline_asm.rs

rustc_hir_typeck/
inline_asm.rs
