Function core::arch::arm::__isb

source ·
pub unsafe fn __isb<A>(arg: A)
where A: Isb,
🔬This is a nightly-only experimental API. (stdarch_arm_barrier #117219)
Available on ARM only.
Expand description

Generates an ISB (instruction synchronization barrier) instruction or equivalent CP15 instruction.

This instruction flushes the processor pipeline fetch buffers, so that following instructions are fetched from cache or memory.

An ISB is needed after some system maintenance operations. An ISB is also needed before transferring control to code that has been loaded or modified in memory, for example by an overlay mechanism or just-in-time code generator. (Note that if instruction and data caches are separate, privileged cache maintenance operations would be needed in order to unify the caches.)

The only supported argument for the __isb() intrinsic is 15, corresponding to the SY (full system) scope of the ISB instruction.