Enum AmdgpuInlineAsmRegClass 

pub enum AmdgpuInlineAsmRegClass {
    Sgpr(u16),
    Vgpr(u16),
}

Amdgpu register classes

The number is the size of the register class in bits.

Variants

Sgpr(u16)

Vgpr(u16)

Implementations

impl AmdgpuInlineAsmRegClass

fn prefix(self) -> &'static str

Prefix when printed and register constraint in LLVM

fn bits(self) -> u16

Return size of the register class in bits

fn bytes(self) -> u16

Return size of the register class in bytes

fn try_get_name(self) -> Option<Symbol>

Returns the name or None if this is not a valid register class

pub fn name(self) -> Symbol

pub fn parse(name: Symbol) -> Result<Self, &'static [Symbol]>

pub fn valid_modifiers(self, _arch: InlineAsmArch) -> &'static [char]

pub fn suggest_class( self, _arch: InlineAsmArch, ty: InlineAsmType, ) -> Option<Self>

pub fn suggest_modifier( self, _arch: InlineAsmArch, _ty: InlineAsmType, ) -> Option<ModifierInfo>

pub fn default_modifier(self, _arch: InlineAsmArch) -> Option<ModifierInfo>

pub fn supported_types( self, _arch: InlineAsmArch, ) -> Vec<(InlineAsmType, Option<Symbol>)>

fn max_num(self) -> u16

The number of supported registers in this class. The returned number is the length, so supported register indices are 0 to max_num()-1.

fn parse_with_prefix(prefix: char, bits: u16) -> Result<Self, &'static str>

Get register class from prefix and size.

Trait Implementations

impl Clone for AmdgpuInlineAsmRegClass

fn clone(&self) -> AmdgpuInlineAsmRegClass

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for AmdgpuInlineAsmRegClass

impl Debug for AmdgpuInlineAsmRegClass

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<__D: SpanDecoder> Decodable<__D> for AmdgpuInlineAsmRegClass

fn decode(__decoder: &mut __D) -> Self

impl<__E: SpanEncoder> Encodable<__E> for AmdgpuInlineAsmRegClass

fn encode(&self, __encoder: &mut __E)

impl Eq for AmdgpuInlineAsmRegClass

impl Hash for AmdgpuInlineAsmRegClass

fn hash<__H: Hasher>(&self, state: &mut __H)

Feeds this value into the given Hasher.

fn hash_slice<H>(data: &[Self], state: &mut H)

where H: Hasher, Self: Sized,

Feeds a slice of this type into the given Hasher.

impl PartialEq for AmdgpuInlineAsmRegClass

fn eq(&self, other: &AmdgpuInlineAsmRegClass) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl PartialOrd for AmdgpuInlineAsmRegClass

fn partial_cmp(&self, other: &AmdgpuInlineAsmRegClass) -> Option<Ordering>

This method returns an ordering between self and other values if one exists.

fn lt(&self, other: &Rhs) -> bool

Tests less than (for self and other) and is used by the < operator.

fn le(&self, other: &Rhs) -> bool

Tests less than or equal to (for self and other) and is used by the <= operator.

fn gt(&self, other: &Rhs) -> bool

Tests greater than (for self and other) and is used by the > operator.

fn ge(&self, other: &Rhs) -> bool

Tests greater than or equal to (for self and other) and is used by the >= operator.

impl StableHash for AmdgpuInlineAsmRegClass

fn stable_hash<__Hcx: StableHashCtxt>( &self, __hcx: &mut __Hcx, __hasher: &mut StableHasher, )

impl StructuralPartialEq for AmdgpuInlineAsmRegClass

Layout

Note: Most layout information is completely unstable and may even differ between compilations. The only exception is types with certain repr(...) attributes. Please see the Rust Reference's “Type Layout” chapter for details on type layout guarantees.

Size: 4 bytes

Size for each variant:

• Sgpr: 2 bytes
• Vgpr: 2 bytes