If the register is a Hexagon register pair then return its LLVM double register index.
LLVM uses d0, d1, β¦ for Hexagon double registers in inline asm constraints,
not the assembly-printed r1:0, r3:2, β¦ format.
If the register is a Hexagon HVX vector pair then return its LLVM W-register index.
LLVM uses w0, w1, β¦ for Hexagon vector pair registers in inline asm constraints.