Module core::arch::wasm32 1.33.0[−][src]
Expand description
Platformspecific intrinsics for the wasm32
platform.
This module provides intrinsics specific to the WebAssembly
architecture. Here you’ll find intrinsics specific to WebAssembly that
aren’t otherwise surfaced somewhere in a crossplatform abstraction of
std
, and you’ll also find functions for leveraging WebAssembly
proposals such as atomics and simd.
Intrinsics in the wasm32
module are modeled after the WebAssembly
instructions that they represent. Most functions are named after the
instruction they intend to correspond to, and the arguments/results
correspond to the type signature of the instruction itself. Stable
WebAssembly instructions are documented online.
If a proposal is not yet stable in WebAssembly itself then the functions within this function may be unstable and require the nightly channel of Rust to use. As the proposal itself stabilizes the intrinsics in this module should stabilize as well.
See the module documentation for general information
about the arch
module and platform intrinsics.
Atomics
The threads proposal for WebAssembly adds a number of
instructions for dealing with multithreaded programs. Most instructions
added in the atomics proposal are exposed in Rust through the
std::sync::atomic
module. Some instructions, however, don’t have
direct equivalents in Rust so they’re exposed here instead.
Note that the instructions added in the atomics proposal can work in
either a context with a shared wasm memory and without. These intrinsics
are always available in the standard library, but you likely won’t be
able to use them too productively unless you recompile the standard
library (and all your code) with Ctargetfeature=+atomics
.
It’s also worth pointing out that multithreaded WebAssembly and its
story in Rust is still in a somewhat “early days” phase as of the time
of this writing. Pieces should mostly work but it generally requires a
good deal of manual setup. At this time it’s not as simple as “just call
std::thread::spawn
”, but it will hopefully get there one day!
SIMD
The simd proposal for WebAssembly added a new v128
type for a
128bit SIMD register. It also added a large array of instructions to
operate on the v128
type to perform data processing. Using SIMD on
wasm is intended to be similar to as you would on x86_64
, for example.
You’d write a function such as:
#[cfg(target_arch = "wasm32")]
#[target_feature(enable = "simd128")]
unsafe fn uses_simd() {
use std::arch::wasm32::*;
// ...
}
RunUnlike x86_64
, however, WebAssembly does not currently have dynamic
detection at runtime as to whether SIMD is supported (this is one of the
motivators for the conditional sections and feature
detection proposals, but that is still pretty early days). This means
that your binary will either have SIMD and can only run on engines
which support SIMD, or it will not have SIMD at all. For compatibility
the standard library itself does not use any SIMD internally.
Determining how best to ship your WebAssembly binary with SIMD is
largely left up to you as it can can be pretty nuanced depending on
your situation.
To enable SIMD support at compile time you need to do one of two things:

First you can annotate functions with
#[target_feature(enable = "simd128")]
. This causes just that one function to have SIMD support available to it, and intrinsics will get inlined as usual in this situation. 
Second you can compile your program with
Ctargetfeature=+simd128
. This compilation flag blanket enables SIMD support for your entire compilation. Note that this does not include the standard library unless you recompile the standard library.
If you enable SIMD via either of these routes then you’ll have a WebAssembly binary that uses SIMD instructions, and you’ll need to ship that accordingly. Also note that if you call SIMD intrinsics but don’t enable SIMD via either of these mechanisms, you’ll still have SIMD generated in your program. This means to generate a binary without SIMD you’ll need to avoid both options above plus calling into any intrinsics in this module.
Structs
WASMspecific 128bit wide SIMD vector type.
Functions
Corresponding intrinsic to wasm’s memory.atomic.notify
instruction
Corresponding intrinsic to wasm’s memory.atomic.wait32
instruction
Corresponding intrinsic to wasm’s memory.atomic.wait64
instruction
simd128
Materializes a SIMD value from the provided operands.
simd128
Calculates the absolute value of each lane of a 128bit vector interpreted as four 32bit floating point numbers.
simd128
Adds pairwise lanes of two 128bit vectors interpreted as four 32bit floating point numbers.
simd128
Lanewise rounding to the nearest integral value not smaller than the input.
simd128
Converts a 128bit vector interpreted as four 32bit signed integers into a 128bit vector of four 32bit floating point numbers.
simd128
Converts a 128bit vector interpreted as four 32bit unsigned integers into a 128bit vector of four 32bit floating point numbers.
simd128
Conversion of the two doubleprecision floating point lanes to two lower singleprecision lanes of the result. The two higher lanes of the result are initialized to zero. If the conversion result is not representable as a singleprecision floating point number, it is rounded to the nearesteven representable number.
simd128
Divides pairwise lanes of two 128bit vectors interpreted as four 32bit floating point numbers.
simd128
Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit floating point numbers.
simd128
Extracts a lane from a 128bit vector interpreted as 4 packed f32 numbers.
simd128
Lanewise rounding to the nearest integral value not greater than the input.
simd128
Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit floating point numbers.
simd128
Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit floating point numbers.
simd128
Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit floating point numbers.
simd128
Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit floating point numbers.
simd128
Calculates the maximum of pairwise lanes of two 128bit vectors interpreted as four 32bit floating point numbers.
simd128
Calculates the minimum of pairwise lanes of two 128bit vectors interpreted as four 32bit floating point numbers.
simd128
Multiplies pairwise lanes of two 128bit vectors interpreted as four 32bit floating point numbers.
simd128
Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit floating point numbers.
simd128
Lanewise rounding to the nearest integral value; if two values are equally near, rounds to the even one.
simd128
Negates each lane of a 128bit vector interpreted as four 32bit floating point numbers.
simd128
Lanewise maximum value, defined as a < b ? b : a
simd128
Lanewise minimum value, defined as b < a ? b : a
simd128
Replaces a lane from a 128bit vector interpreted as 4 packed f32 numbers.
simd128
Creates a vector with identical lanes.
simd128
Calculates the square root of each lane of a 128bit vector interpreted as four 32bit floating point numbers.
simd128
Subtracts pairwise lanes of two 128bit vectors interpreted as four 32bit floating point numbers.
simd128
Lanewise rounding to the nearest integral value with the magnitude not larger than the input.
simd128
Materializes a SIMD value from the provided operands.
simd128
Calculates the absolute value of each lane of a 128bit vector interpreted as two 64bit floating point numbers.
simd128
Adds pairwise lanes of two 128bit vectors interpreted as two 64bit floating point numbers.
simd128
Lanewise rounding to the nearest integral value not smaller than the input.
simd128
Lanewise conversion from integer to floating point.
simd128
Lanewise conversion from integer to floating point.
simd128
Divides pairwise lanes of two 128bit vectors interpreted as two 64bit floating point numbers.
simd128
Compares two 128bit vectors as if they were two vectors of 2 sixtyfourbit floating point numbers.
simd128
Extracts a lane from a 128bit vector interpreted as 2 packed f64 numbers.
simd128
Lanewise rounding to the nearest integral value not greater than the input.
simd128
Compares two 128bit vectors as if they were two vectors of 2 sixtyfourbit floating point numbers.
simd128
Compares two 128bit vectors as if they were two vectors of 2 sixtyfourbit floating point numbers.
simd128
Compares two 128bit vectors as if they were two vectors of 2 sixtyfourbit floating point numbers.
simd128
Compares two 128bit vectors as if they were two vectors of 2 sixtyfourbit floating point numbers.
simd128
Calculates the maximum of pairwise lanes of two 128bit vectors interpreted as two 64bit floating point numbers.
simd128
Calculates the minimum of pairwise lanes of two 128bit vectors interpreted as two 64bit floating point numbers.
simd128
Multiplies pairwise lanes of two 128bit vectors interpreted as two 64bit floating point numbers.
simd128
Compares two 128bit vectors as if they were two vectors of 2 sixtyfourbit floating point numbers.
simd128
Lanewise rounding to the nearest integral value; if two values are equally near, rounds to the even one.
simd128
Negates each lane of a 128bit vector interpreted as two 64bit floating point numbers.
simd128
Lanewise maximum value, defined as a < b ? b : a
simd128
Lanewise minimum value, defined as b < a ? b : a
simd128
Conversion of the two lower singleprecision floating point lanes to the two doubleprecision lanes of the result.
simd128
Replaces a lane from a 128bit vector interpreted as 2 packed f64 numbers.
simd128
Creates a vector with identical lanes.
simd128
Calculates the square root of each lane of a 128bit vector interpreted as two 64bit floating point numbers.
simd128
Subtracts pairwise lanes of two 128bit vectors interpreted as two 64bit floating point numbers.
simd128
Lanewise rounding to the nearest integral value with the magnitude not larger than the input.
simd128
Materializes a SIMD value from the provided operands.
simd128
Lanewise wrapping absolute value.
simd128
Adds two 128bit vectors as if they were two packed sixteen 8bit integers.
simd128
Adds two 128bit vectors as if they were two packed sixteen 8bit signed
integers, saturating on overflow to i8::MAX
.
simd128
Returns true if all lanes are nonzero, false otherwise.
simd128
Extracts the high bit for each lane in a
and produce a scalar mask with
all bits concatenated.
simd128
Compares two 128bit vectors as if they were two vectors of 16 eightbit integers.
simd128
Extracts a lane from a 128bit vector interpreted as 16 packed i8 numbers.
simd128
Compares two 128bit vectors as if they were two vectors of 16 eightbit signed integers.
simd128
Compares two 128bit vectors as if they were two vectors of 16 eightbit signed integers.
simd128
Compares two 128bit vectors as if they were two vectors of 16 eightbit signed integers.
simd128
Compares two 128bit vectors as if they were two vectors of 16 eightbit signed integers.
simd128
Compares lanewise signed integers, and returns the maximum of each pair.
simd128
Compares lanewise signed integers, and returns the minimum of each pair.
simd128
Converts two input vectors into a smaller lane vector by narrowing each lane.
simd128
Compares two 128bit vectors as if they were two vectors of 16 eightbit integers.
simd128
Negates a 128bit vectors intepreted as sixteen 8bit signed integers
simd128
Count the number of bits set to one within each lane.
simd128
Replaces a lane from a 128bit vector interpreted as 16 packed i8 numbers.
simd128
Shifts each lane to the left by the specified number of bits.
simd128
Shifts each lane to the right by the specified number of bits, sign extending.
simd128
Returns a new vector with lanes selected from the lanes of the two input
vectors $a
and $b
specified in the 16 immediate operands.
simd128
Creates a vector with identical lanes.
simd128
Subtracts two 128bit vectors as if they were two packed sixteen 8bit integers.
simd128
Subtracts two 128bit vectors as if they were two packed sixteen 8bit
signed integers, saturating on overflow to i8::MIN
.
simd128
Returns a new vector with lanes selected from the lanes of the first input
vector a
specified in the second input vector s
.
simd128
Materializes a SIMD value from the provided operands.
simd128
Lanewise wrapping absolute value.
simd128
Adds two 128bit vectors as if they were two packed eight 16bit integers.
simd128
Adds two 128bit vectors as if they were two packed eight 16bit signed
integers, saturating on overflow to i16::MAX
.
simd128
Returns true if all lanes are nonzero, false otherwise.
simd128
Extracts the high bit for each lane in a
and produce a scalar mask with
all bits concatenated.
simd128
Compares two 128bit vectors as if they were two vectors of 8 sixteenbit integers.
simd128
Lanewise integer extended pairwise addition producing extended results (twice wider results than the inputs).
simd128
Lanewise integer extended pairwise addition producing extended results (twice wider results than the inputs).
simd128
Converts high half of the smaller lane vector to a larger lane vector, sign extended.
simd128
Converts high half of the smaller lane vector to a larger lane vector, zero extended.
simd128
Converts low half of the smaller lane vector to a larger lane vector, sign extended.
simd128
Converts low half of the smaller lane vector to a larger lane vector, zero extended.
simd128
Lanewise integer extended multiplication producing twice wider result than the inputs.
simd128
Lanewise integer extended multiplication producing twice wider result than the inputs.
simd128
Lanewise integer extended multiplication producing twice wider result than the inputs.
simd128
Lanewise integer extended multiplication producing twice wider result than the inputs.
simd128
Extracts a lane from a 128bit vector interpreted as 8 packed i16 numbers.
simd128
Compares two 128bit vectors as if they were two vectors of 8 sixteenbit signed integers.
simd128
Compares two 128bit vectors as if they were two vectors of 8 sixteenbit signed integers.
simd128
Compares two 128bit vectors as if they were two vectors of 8 sixteenbit signed integers.
Load eight 8bit integers and sign extend each one to a 16bit lane
Load eight 8bit integers and zero extend each one to a 16bit lane
simd128
Compares two 128bit vectors as if they were two vectors of 8 sixteenbit signed integers.
simd128
Compares lanewise signed integers, and returns the maximum of each pair.
simd128
Compares lanewise signed integers, and returns the minimum of each pair.
simd128
Multiplies two 128bit vectors as if they were two packed eight 16bit signed integers.
simd128
Converts two input vectors into a smaller lane vector by narrowing each lane.
simd128
Compares two 128bit vectors as if they were two vectors of 8 sixteenbit integers.
simd128
Negates a 128bit vectors intepreted as eight 16bit signed integers
simd128
Lanewise saturating rounding multiplication in Q15 format.
simd128
Replaces a lane from a 128bit vector interpreted as 8 packed i16 numbers.
simd128
Shifts each lane to the left by the specified number of bits.
simd128
Shifts each lane to the right by the specified number of bits, sign extending.
simd128
Same as i8x16_shuffle
, except operates as if the inputs were eight
16bit integers, only taking 8 indices to shuffle.
simd128
Creates a vector with identical lanes.
simd128
Subtracts two 128bit vectors as if they were two packed eight 16bit integers.
simd128
Subtracts two 128bit vectors as if they were two packed eight 16bit
signed integers, saturating on overflow to i16::MIN
.
simd128
Materializes a SIMD value from the provided operands.
simd128
Lanewise wrapping absolute value.
simd128
Adds two 128bit vectors as if they were two packed four 32bit integers.
simd128
Returns true if all lanes are nonzero, false otherwise.
simd128
Extracts the high bit for each lane in a
and produce a scalar mask with
all bits concatenated.
simd128
Lanewise multiply signed 16bit integers in the two input vectors and add adjacent pairs of the full 32bit results.
simd128
Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit integers.
simd128
Lanewise integer extended pairwise addition producing extended results (twice wider results than the inputs).
simd128
Lanewise integer extended pairwise addition producing extended results (twice wider results than the inputs).
simd128
Converts high half of the smaller lane vector to a larger lane vector, sign extended.
simd128
Converts high half of the smaller lane vector to a larger lane vector, zero extended.
simd128
Converts low half of the smaller lane vector to a larger lane vector, sign extended.
simd128
Converts low half of the smaller lane vector to a larger lane vector, zero extended.
simd128
Lanewise integer extended multiplication producing twice wider result than the inputs.
simd128
Lanewise integer extended multiplication producing twice wider result than the inputs.
simd128
Lanewise integer extended multiplication producing twice wider result than the inputs.
simd128
Lanewise integer extended multiplication producing twice wider result than the inputs.
simd128
Extracts a lane from a 128bit vector interpreted as 4 packed i32 numbers.
simd128
Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit signed integers.
simd128
Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit signed integers.
simd128
Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit signed integers.
Load four 16bit integers and sign extend each one to a 32bit lane
Load four 16bit integers and zero extend each one to a 32bit lane
simd128
Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit signed integers.
simd128
Compares lanewise signed integers, and returns the maximum of each pair.
simd128
Compares lanewise signed integers, and returns the minimum of each pair.
simd128
Multiplies two 128bit vectors as if they were two packed four 32bit signed integers.
simd128
Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit integers.
simd128
Negates a 128bit vectors intepreted as four 32bit signed integers
simd128
Replaces a lane from a 128bit vector interpreted as 4 packed i32 numbers.
simd128
Shifts each lane to the left by the specified number of bits.
simd128
Shifts each lane to the right by the specified number of bits, sign extending.
simd128
Same as i8x16_shuffle
, except operates as if the inputs were four
32bit integers, only taking 4 indices to shuffle.
simd128
Creates a vector with identical lanes.
simd128
Subtracts two 128bit vectors as if they were two packed four 32bit integers.
simd128
Converts a 128bit vector interpreted as four 32bit floating point numbers into a 128bit vector of four 32bit signed integers.
simd128
Saturating conversion of the two doubleprecision floating point lanes to
two lower integer lanes using the IEEE convertToIntegerTowardZero
function.
simd128
Materializes a SIMD value from the provided operands.
simd128
Lanewise wrapping absolute value.
simd128
Adds two 128bit vectors as if they were two packed two 64bit integers.
simd128
Returns true if all lanes are nonzero, false otherwise.
simd128
Extracts the high bit for each lane in a
and produce a scalar mask with
all bits concatenated.
simd128
Compares two 128bit vectors as if they were two vectors of 2 sixtyfourbit integers.
simd128
Converts high half of the smaller lane vector to a larger lane vector, sign extended.
simd128
Converts high half of the smaller lane vector to a larger lane vector, zero extended.
simd128
Converts low half of the smaller lane vector to a larger lane vector, sign extended.
simd128
Converts low half of the smaller lane vector to a larger lane vector, zero extended.
simd128
Lanewise integer extended multiplication producing twice wider result than the inputs.
simd128
Lanewise integer extended multiplication producing twice wider result than the inputs.
simd128
Lanewise integer extended multiplication producing twice wider result than the inputs.
simd128
Lanewise integer extended multiplication producing twice wider result than the inputs.
simd128
Extracts a lane from a 128bit vector interpreted as 2 packed i64 numbers.
simd128
Compares two 128bit vectors as if they were two vectors of 2 sixtyfourbit signed integers.
simd128
Compares two 128bit vectors as if they were two vectors of 2 sixtyfourbit signed integers.
simd128
Compares two 128bit vectors as if they were two vectors of 2 sixtyfourbit signed integers.
Load two 32bit integers and sign extend each one to a 64bit lane
Load two 32bit integers and zero extend each one to a 64bit lane
simd128
Compares two 128bit vectors as if they were two vectors of 2 sixtyfourbit signed integers.
simd128
Multiplies two 128bit vectors as if they were two packed two 64bit integers.
simd128
Compares two 128bit vectors as if they were two vectors of 2 sixtyfourbit integers.
simd128
Negates a 128bit vectors intepreted as two 64bit signed integers
simd128
Replaces a lane from a 128bit vector interpreted as 2 packed i64 numbers.
simd128
Shifts each lane to the left by the specified number of bits.
simd128
Shifts each lane to the right by the specified number of bits, sign extending.
simd128
Same as i8x16_shuffle
, except operates as if the inputs were two
64bit integers, only taking 2 indices to shuffle.
simd128
Creates a vector with identical lanes.
simd128
Subtracts two 128bit vectors as if they were two packed two 64bit integers.
Corresponding intrinsic to wasm’s memory.grow
instruction
Corresponding intrinsic to wasm’s memory.size
instruction
simd128
Materializes a SIMD value from the provided operands.
simd128
Adds two 128bit vectors as if they were two packed sixteen 8bit integers.
simd128
Adds two 128bit vectors as if they were two packed sixteen 8bit unsigned
integers, saturating on overflow to u8::MAX
.
simd128
Returns true if all lanes are nonzero, false otherwise.
simd128
Lanewise rounding average.
simd128
Extracts the high bit for each lane in a
and produce a scalar mask with
all bits concatenated.
simd128
Compares two 128bit vectors as if they were two vectors of 16 eightbit integers.
simd128
Extracts a lane from a 128bit vector interpreted as 16 packed u8 numbers.
simd128
Compares two 128bit vectors as if they were two vectors of 16 eightbit unsigned integers.
simd128
Compares two 128bit vectors as if they were two vectors of 16 eightbit unsigned integers.
simd128
Compares two 128bit vectors as if they were two vectors of 16 eightbit unsigned integers.
simd128
Compares two 128bit vectors as if they were two vectors of 16 eightbit unsigned integers.
simd128
Compares lanewise unsigned integers, and returns the maximum of each pair.
simd128
Compares lanewise unsigned integers, and returns the minimum of each pair.
simd128
Converts two input vectors into a smaller lane vector by narrowing each lane.
simd128
Compares two 128bit vectors as if they were two vectors of 16 eightbit integers.
simd128
Count the number of bits set to one within each lane.
simd128
Replaces a lane from a 128bit vector interpreted as 16 packed u8 numbers.
simd128
Shifts each lane to the left by the specified number of bits.
simd128
Shifts each lane to the right by the specified number of bits, shifting in zeros.
simd128
Returns a new vector with lanes selected from the lanes of the two input
vectors $a
and $b
specified in the 16 immediate operands.
simd128
Creates a vector with identical lanes.
simd128
Subtracts two 128bit vectors as if they were two packed sixteen 8bit integers.
simd128
Subtracts two 128bit vectors as if they were two packed sixteen 8bit unsigned integers, saturating on overflow to 0.
simd128
Returns a new vector with lanes selected from the lanes of the first input
vector a
specified in the second input vector s
.
simd128
Materializes a SIMD value from the provided operands.
simd128
Adds two 128bit vectors as if they were two packed eight 16bit integers.
simd128
Adds two 128bit vectors as if they were two packed eight 16bit unsigned
integers, saturating on overflow to u16::MAX
.
simd128
Returns true if all lanes are nonzero, false otherwise.
simd128
Lanewise rounding average.
simd128
Extracts the high bit for each lane in a
and produce a scalar mask with
all bits concatenated.
simd128
Compares two 128bit vectors as if they were two vectors of 8 sixteenbit integers.
simd128
Lanewise integer extended pairwise addition producing extended results (twice wider results than the inputs).
simd128
Converts high half of the smaller lane vector to a larger lane vector, zero extended.
simd128
Converts low half of the smaller lane vector to a larger lane vector, zero extended.
simd128
Lanewise integer extended multiplication producing twice wider result than the inputs.
simd128
Lanewise integer extended multiplication producing twice wider result than the inputs.
simd128
Extracts a lane from a 128bit vector interpreted as 8 packed u16 numbers.
simd128
Compares two 128bit vectors as if they were two vectors of 8 sixteenbit unsigned integers.
simd128
Compares two 128bit vectors as if they were two vectors of 8 sixteenbit unsigned integers.
simd128
Compares two 128bit vectors as if they were two vectors of 8 sixteenbit unsigned integers.
Load eight 8bit integers and zero extend each one to a 16bit lane
simd128
Compares two 128bit vectors as if they were two vectors of 8 sixteenbit unsigned integers.
simd128
Compares lanewise unsigned integers, and returns the maximum of each pair.
simd128
Compares lanewise unsigned integers, and returns the minimum of each pair.
simd128
Multiplies two 128bit vectors as if they were two packed eight 16bit signed integers.
simd128
Converts two input vectors into a smaller lane vector by narrowing each lane.
simd128
Compares two 128bit vectors as if they were two vectors of 8 sixteenbit integers.
simd128
Replaces a lane from a 128bit vector interpreted as 8 packed u16 numbers.
simd128
Shifts each lane to the left by the specified number of bits.
simd128
Shifts each lane to the right by the specified number of bits, shifting in zeros.
simd128
Same as i8x16_shuffle
, except operates as if the inputs were eight
16bit integers, only taking 8 indices to shuffle.
simd128
Creates a vector with identical lanes.
simd128
Subtracts two 128bit vectors as if they were two packed eight 16bit integers.
simd128
Subtracts two 128bit vectors as if they were two packed eight 16bit unsigned integers, saturating on overflow to 0.
simd128
Materializes a SIMD value from the provided operands.
simd128
Adds two 128bit vectors as if they were two packed four 32bit integers.
simd128
Returns true if all lanes are nonzero, false otherwise.
simd128
Extracts the high bit for each lane in a
and produce a scalar mask with
all bits concatenated.
simd128
Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit integers.
simd128
Lanewise integer extended pairwise addition producing extended results (twice wider results than the inputs).
simd128
Converts high half of the smaller lane vector to a larger lane vector, zero extended.
simd128
Converts low half of the smaller lane vector to a larger lane vector, zero extended.
simd128
Lanewise integer extended multiplication producing twice wider result than the inputs.
simd128
Lanewise integer extended multiplication producing twice wider result than the inputs.
simd128
Extracts a lane from a 128bit vector interpreted as 4 packed u32 numbers.
simd128
Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit unsigned integers.
simd128
Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit unsigned integers.
simd128
Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit unsigned integers.
Load four 16bit integers and zero extend each one to a 32bit lane
simd128
Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit unsigned integers.
simd128
Compares lanewise unsigned integers, and returns the maximum of each pair.
simd128
Compares lanewise unsigned integers, and returns the minimum of each pair.
simd128
Multiplies two 128bit vectors as if they were two packed four 32bit signed integers.
simd128
Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit integers.
simd128
Replaces a lane from a 128bit vector interpreted as 4 packed u32 numbers.
simd128
Shifts each lane to the left by the specified number of bits.
simd128
Shifts each lane to the right by the specified number of bits, shifting in zeros.
simd128
Same as i8x16_shuffle
, except operates as if the inputs were four
32bit integers, only taking 4 indices to shuffle.
simd128
Creates a vector with identical lanes.
simd128
Subtracts two 128bit vectors as if they were two packed four 32bit integers.
simd128
Converts a 128bit vector interpreted as four 32bit floating point numbers into a 128bit vector of four 32bit unsigned integers.
simd128
Saturating conversion of the two doubleprecision floating point lanes to
two lower integer lanes using the IEEE convertToIntegerTowardZero
function.
simd128
Materializes a SIMD value from the provided operands.
simd128
Adds two 128bit vectors as if they were two packed two 64bit integers.
simd128
Returns true if all lanes are nonzero, false otherwise.
simd128
Extracts the high bit for each lane in a
and produce a scalar mask with
all bits concatenated.
simd128
Compares two 128bit vectors as if they were two vectors of 2 sixtyfourbit integers.
simd128
Converts high half of the smaller lane vector to a larger lane vector, zero extended.
simd128
Converts low half of the smaller lane vector to a larger lane vector, zero extended.
simd128
Lanewise integer extended multiplication producing twice wider result than the inputs.
simd128
Lanewise integer extended multiplication producing twice wider result than the inputs.
simd128
Extracts a lane from a 128bit vector interpreted as 2 packed u64 numbers.
Load two 32bit integers and zero extend each one to a 64bit lane
simd128
Multiplies two 128bit vectors as if they were two packed two 64bit integers.
simd128
Compares two 128bit vectors as if they were two vectors of 2 sixtyfourbit integers.
simd128
Replaces a lane from a 128bit vector interpreted as 2 packed u64 numbers.
simd128
Shifts each lane to the left by the specified number of bits.
simd128
Shifts each lane to the right by the specified number of bits, shifting in zeros.
simd128
Same as i8x16_shuffle
, except operates as if the inputs were two
64bit integers, only taking 2 indices to shuffle.
simd128
Creates a vector with identical lanes.
simd128
Subtracts two 128bit vectors as if they were two packed two 64bit integers.
Generates the unreachable
instruction, which causes an unconditional trap.
simd128
Performs a bitwise and of the two input 128bit vectors, returning the resulting vector.
simd128
Bitwise AND of bits of a
and the logical inverse of bits of b
.
simd128
Returns true
if any bit in a
is set, or false
otherwise.
simd128
Use the bitmask in c
to select bits from v1
when 1 and v2
when 0.
Loads an 8bit value from m
and sets lane L
of v
to that value.
Load a single element and splat to all lanes of a v128 vector.
Loads a 16bit value from m
and sets lane L
of v
to that value.
Load a single element and splat to all lanes of a v128 vector.
Loads a 32bit value from m
and sets lane L
of v
to that value.
Load a single element and splat to all lanes of a v128 vector.
Load a 32bit element into the low bits of the vector and sets all other bits to zero.
Loads a 64bit value from m
and sets lane L
of v
to that value.
Load a single element and splat to all lanes of a v128 vector.
Load a 64bit element into the low bits of the vector and sets all other bits to zero.
simd128
Flips each bit of the 128bit input vector.
simd128
Performs a bitwise or of the two input 128bit vectors, returning the resulting vector.
Stores a v128
vector to the given heap address.
Stores the 8bit value from lane L
of v
into m
Stores the 16bit value from lane L
of v
into m
Stores the 32bit value from lane L
of v
into m
Stores the 64bit value from lane L
of v
into m
simd128
Performs a bitwise xor of the two input 128bit vectors, returning the resulting vector.