1.0.0[][src]Enum core::sync::atomic::Ordering

#[non_exhaustive]
pub enum Ordering { Relaxed, Release, Acquire, AcqRel, SeqCst, }

Atomic memory orderings

Memory orderings limit the ways that both the compiler and CPU may reorder instructions around atomic operations. At its most restrictive, "sequentially consistent" atomics allow neither reads nor writes to be moved either before or after the atomic operation; on the other end "relaxed" atomics allow all reorderings.

Rust's memory orderings are the same as LLVM's.

For more information see the nomicon.

Variants (Non-exhaustive)

Non-exhaustive enums could have additional variants added in future. Therefore, when matching against variants of non-exhaustive enums, an extra wildcard arm must be added to account for any future variants.

No ordering constraints, only atomic operations.

Corresponds to LLVM's Monotonic ordering.

When coupled with a store, all previous operations become ordered before any load of this value with Acquire (or stronger) ordering. In particular, all previous writes become visible to all threads that perform an Acquire (or stronger) load of this value.

Notice that using this ordering for an operation that combines loads and stores leads to a Relaxed load operation!

This ordering is only applicable for operations that can perform a store.

Corresponds to LLVM's Release ordering.

When coupled with a load, if the loaded value was written by a store operation with Release (or stronger) ordering, then all subsequent operations become ordered after that store. In particular, all subsequent loads will see data written before the store.

Notice that using this ordering for an operation that combines loads and stores leads to a Relaxed store operation!

This ordering is only applicable for operations that can perform a load.

Corresponds to LLVM's Acquire ordering.

Has the effects of both Acquire and Release together: For loads it uses Acquire ordering. For stores it uses the Release ordering.

Notice that in the case of compare_and_swap, it is possible that the operation ends up not performing any store and hence it has just Acquire ordering. However, AcqRel will never perform Relaxed accesses.

This ordering is only applicable for operations that combine both loads and stores.

Corresponds to LLVM's AcquireRelease ordering.

Like Acquire/Release/AcqRel (for load, store, and load-with-store operations, respectively) with the additional guarantee that all threads see all sequentially consistent operations in the same order.

Corresponds to LLVM's SequentiallyConsistent ordering.

Trait Implementations

impl Copy for Ordering
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impl Clone for Ordering
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Performs copy-assignment from source. Read more

impl Debug for Ordering
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Auto Trait Implementations

impl Send for Ordering

impl Sync for Ordering

Blanket Implementations

impl<T, U> Into for T where
    U: From<T>, 
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impl<T> From for T
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impl<T, U> TryInto for T where
    U: TryFrom<T>, 
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🔬 This is a nightly-only experimental API. (try_from #33417)

The type returned in the event of a conversion error.

impl<T, U> TryFrom for T where
    T: From<U>, 
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🔬 This is a nightly-only experimental API. (try_from #33417)

The type returned in the event of a conversion error.

impl<T> Borrow for T where
    T: ?Sized
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impl<T> BorrowMut for T where
    T: ?Sized
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impl<T> Any for T where
    T: 'static + ?Sized
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