Function core::arch::riscv32::sha256sum1

source ·
pub unsafe fn sha256sum1(rs1: u32) -> u32
🔬This is a nightly-only experimental API. (riscv_ext_intrinsics #114544)
Available on RISC-V RV32 and target feature zknh only.
Expand description

Implements the Sum1 transformation function as used in the SHA2-256 hash function [49] (Section 4.1.2).

This instruction is supported for both RV32 and RV64 base architectures. For RV32, the entire XLEN source register is operated on. For RV64, the low 32 bits of the source register are operated on, and the result sign extended to XLEN bits. Though named for SHA2-256, the instruction works for both the SHA2-224 and SHA2-256 parameterisations as described in [49]. This instruction must always be implemented such that its execution latency does not depend on the data being operated on.

Source: RISC-V Cryptography Extensions Volume I: Scalar & Entropy Source Instructions

Version: v1.0.1

Section: 3.30


This function is safe to use if the zknh target feature is present.