Expand description
Platformspecific intrinsics for the wasm32
platform.
This module provides intrinsics specific to the WebAssembly
architecture. Here you’ll find intrinsics specific to WebAssembly that
aren’t otherwise surfaced somewhere in a crossplatform abstraction of
std
, and you’ll also find functions for leveraging WebAssembly
proposals such as atomics and simd.
Intrinsics in the wasm32
module are modeled after the WebAssembly
instructions that they represent. Most functions are named after the
instruction they intend to correspond to, and the arguments/results
correspond to the type signature of the instruction itself. Stable
WebAssembly instructions are documented online.
If a proposal is not yet stable in WebAssembly itself then the functions within this function may be unstable and require the nightly channel of Rust to use. As the proposal itself stabilizes the intrinsics in this module should stabilize as well.
See the module documentation for general information
about the arch
module and platform intrinsics.
§Atomics
The threads proposal for WebAssembly adds a number of
instructions for dealing with multithreaded programs. Most instructions
added in the atomics proposal are exposed in Rust through the
std::sync::atomic
module. Some instructions, however, don’t have
direct equivalents in Rust so they’re exposed here instead.
Note that the instructions added in the atomics proposal can work in
either a context with a shared wasm memory and without. These intrinsics
are always available in the standard library, but you likely won’t be
able to use them too productively unless you recompile the standard
library (and all your code) with Ctargetfeature=+atomics
.
It’s also worth pointing out that multithreaded WebAssembly and its
story in Rust is still in a somewhat “early days” phase as of the time
of this writing. Pieces should mostly work but it generally requires a
good deal of manual setup. At this time it’s not as simple as “just call
std::thread::spawn
”, but it will hopefully get there one day!
§SIMD
The simd proposal for WebAssembly added a new v128
type for a
128bit SIMD register. It also added a large array of instructions to
operate on the v128
type to perform data processing. Using SIMD on
wasm is intended to be similar to as you would on x86_64
, for example.
You’d write a function such as:
#[cfg(target_arch = "wasm32")]
#[target_feature(enable = "simd128")]
unsafe fn uses_simd() {
use std::arch::wasm32::*;
// ...
}
Unlike x86_64
, however, WebAssembly does not currently have dynamic
detection at runtime as to whether SIMD is supported (this is one of the
motivators for the conditional sections and feature
detection proposals, but that is still pretty early days). This means
that your binary will either have SIMD and can only run on engines
which support SIMD, or it will not have SIMD at all. For compatibility
the standard library itself does not use any SIMD internally.
Determining how best to ship your WebAssembly binary with SIMD is
largely left up to you as it can be pretty nuanced depending on
your situation.
To enable SIMD support at compile time you need to do one of two things:

First you can annotate functions with
#[target_feature(enable = "simd128")]
. This causes just that one function to have SIMD support available to it, and intrinsics will get inlined as usual in this situation. 
Second you can compile your program with
Ctargetfeature=+simd128
. This compilation flag blanket enables SIMD support for your entire compilation. Note that this does not include the standard library unless you recompile the standard library.
If you enable SIMD via either of these routes then you’ll have a WebAssembly binary that uses SIMD instructions, and you’ll need to ship that accordingly. Also note that if you call SIMD intrinsics but don’t enable SIMD via either of these mechanisms, you’ll still have SIMD generated in your program. This means to generate a binary without SIMD you’ll need to avoid both options above plus calling into any intrinsics in this module.
Structs§
 v128
target_family="wasm"
WASMspecific 128bit wide SIMD vector type.
Functions§
 f32x4
target_family="wasm"
Materializes a SIMD value from the provided operands.  f32x4_
abs target_family="wasm"
andsimd128
Calculates the absolute value of each lane of a 128bit vector interpreted as four 32bit floating point numbers.  f32x4_
add target_family="wasm"
andsimd128
Lanewise addition of two 128bit vectors interpreted as four 32bit floating point numbers.  f32x4_
ceil target_family="wasm"
andsimd128
Lanewise rounding to the nearest integral value not smaller than the input.  f32x4_
convert_ i32x4 target_family="wasm"
andsimd128
Converts a 128bit vector interpreted as four 32bit signed integers into a 128bit vector of four 32bit floating point numbers.  f32x4_
convert_ u32x4 target_family="wasm"
andsimd128
Converts a 128bit vector interpreted as four 32bit unsigned integers into a 128bit vector of four 32bit floating point numbers.  f32x4_
demote_ f64x2_ zero target_family="wasm"
andsimd128
Conversion of the two doubleprecision floating point lanes to two lower singleprecision lanes of the result. The two higher lanes of the result are initialized to zero. If the conversion result is not representable as a singleprecision floating point number, it is rounded to the nearesteven representable number.  f32x4_
div target_family="wasm"
andsimd128
Lanewise division of two 128bit vectors interpreted as four 32bit floating point numbers.  f32x4_
eq target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit floating point numbers.  f32x4_
extract_ lane target_family="wasm"
andsimd128
Extracts a lane from a 128bit vector interpreted as 4 packed f32 numbers.  f32x4_
floor target_family="wasm"
andsimd128
Lanewise rounding to the nearest integral value not greater than the input.  f32x4_
ge target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit floating point numbers.  f32x4_
gt target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit floating point numbers.  f32x4_
le target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit floating point numbers.  f32x4_
lt target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit floating point numbers.  f32x4_
max target_family="wasm"
andsimd128
Calculates the lanewise minimum of two 128bit vectors interpreted as four 32bit floating point numbers.  f32x4_
min target_family="wasm"
andsimd128
Calculates the lanewise minimum of two 128bit vectors interpreted as four 32bit floating point numbers.  f32x4_
mul target_family="wasm"
andsimd128
Lanewise multiplication of two 128bit vectors interpreted as four 32bit floating point numbers.  f32x4_
ne target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit floating point numbers.  f32x4_
nearest target_family="wasm"
andsimd128
Lanewise rounding to the nearest integral value; if two values are equally near, rounds to the even one.  f32x4_
neg target_family="wasm"
andsimd128
Negates each lane of a 128bit vector interpreted as four 32bit floating point numbers.  f32x4_
pmax target_family="wasm"
andsimd128
Lanewise maximum value, defined asa < b ? b : a
 f32x4_
pmin target_family="wasm"
andsimd128
Lanewise minimum value, defined asb < a ? b : a
 f32x4_
relaxed_ madd target_family="wasm"
andrelaxedsimd
Computesa * b + c
with either one rounding or two roundings.  f32x4_
relaxed_ max target_family="wasm"
andrelaxedsimd
A relaxed version off32x4_max
which is eitherf32x4_max
orf32x4_pmax
.  f32x4_
relaxed_ min target_family="wasm"
andrelaxedsimd
A relaxed version off32x4_min
which is eitherf32x4_min
orf32x4_pmin
.  f32x4_
relaxed_ nmadd target_family="wasm"
andrelaxedsimd
Computesa * b + c
with either one rounding or two roundings.  f32x4_
replace_ lane target_family="wasm"
andsimd128
Replaces a lane from a 128bit vector interpreted as 4 packed f32 numbers.  f32x4_
splat target_family="wasm"
andsimd128
Creates a vector with identical lanes.  f32x4_
sqrt target_family="wasm"
andsimd128
Calculates the square root of each lane of a 128bit vector interpreted as four 32bit floating point numbers.  f32x4_
sub target_family="wasm"
andsimd128
Lanewise subtraction of two 128bit vectors interpreted as four 32bit floating point numbers.  f32x4_
trunc target_family="wasm"
andsimd128
Lanewise rounding to the nearest integral value with the magnitude not larger than the input.  f64x2
target_family="wasm"
Materializes a SIMD value from the provided operands.  f64x2_
abs target_family="wasm"
andsimd128
Calculates the absolute value of each lane of a 128bit vector interpreted as two 64bit floating point numbers.  f64x2_
add target_family="wasm"
andsimd128
Lanewise add of two 128bit vectors interpreted as two 64bit floating point numbers.  f64x2_
ceil target_family="wasm"
andsimd128
Lanewise rounding to the nearest integral value not smaller than the input.  f64x2_
convert_ low_ i32x4 target_family="wasm"
andsimd128
Lanewise conversion from integer to floating point.  f64x2_
convert_ low_ u32x4 target_family="wasm"
andsimd128
Lanewise conversion from integer to floating point.  f64x2_
div target_family="wasm"
andsimd128
Lanewise divide of two 128bit vectors interpreted as two 64bit floating point numbers.  f64x2_
eq target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 2 sixtyfourbit floating point numbers.  f64x2_
extract_ lane target_family="wasm"
andsimd128
Extracts a lane from a 128bit vector interpreted as 2 packed f64 numbers.  f64x2_
floor target_family="wasm"
andsimd128
Lanewise rounding to the nearest integral value not greater than the input.  f64x2_
ge target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 2 sixtyfourbit floating point numbers.  f64x2_
gt target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 2 sixtyfourbit floating point numbers.  f64x2_
le target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 2 sixtyfourbit floating point numbers.  f64x2_
lt target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 2 sixtyfourbit floating point numbers.  f64x2_
max target_family="wasm"
andsimd128
Calculates the lanewise maximum of two 128bit vectors interpreted as two 64bit floating point numbers.  f64x2_
min target_family="wasm"
andsimd128
Calculates the lanewise minimum of two 128bit vectors interpreted as two 64bit floating point numbers.  f64x2_
mul target_family="wasm"
andsimd128
Lanewise multiply of two 128bit vectors interpreted as two 64bit floating point numbers.  f64x2_
ne target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 2 sixtyfourbit floating point numbers.  f64x2_
nearest target_family="wasm"
andsimd128
Lanewise rounding to the nearest integral value; if two values are equally near, rounds to the even one.  f64x2_
neg target_family="wasm"
andsimd128
Negates each lane of a 128bit vector interpreted as two 64bit floating point numbers.  f64x2_
pmax target_family="wasm"
andsimd128
Lanewise maximum value, defined asa < b ? b : a
 f64x2_
pmin target_family="wasm"
andsimd128
Lanewise minimum value, defined asb < a ? b : a
 f64x2_
promote_ low_ f32x4 target_family="wasm"
andsimd128
Conversion of the two lower singleprecision floating point lanes to the two doubleprecision lanes of the result.  f64x2_
relaxed_ madd target_family="wasm"
andrelaxedsimd
Computesa * b + c
with either one rounding or two roundings.  f64x2_
relaxed_ max target_family="wasm"
andrelaxedsimd
A relaxed version off64x2_max
which is eitherf64x2_max
orf64x2_pmax
.  f64x2_
relaxed_ min target_family="wasm"
andrelaxedsimd
A relaxed version off64x2_min
which is eitherf64x2_min
orf64x2_pmin
.  f64x2_
relaxed_ nmadd target_family="wasm"
andrelaxedsimd
Computesa * b + c
with either one rounding or two roundings.  f64x2_
replace_ lane target_family="wasm"
andsimd128
Replaces a lane from a 128bit vector interpreted as 2 packed f64 numbers.  f64x2_
splat target_family="wasm"
andsimd128
Creates a vector with identical lanes.  f64x2_
sqrt target_family="wasm"
andsimd128
Calculates the square root of each lane of a 128bit vector interpreted as two 64bit floating point numbers.  f64x2_
sub target_family="wasm"
andsimd128
Lanewise subtract of two 128bit vectors interpreted as two 64bit floating point numbers.  f64x2_
trunc target_family="wasm"
andsimd128
Lanewise rounding to the nearest integral value with the magnitude not larger than the input.  i8x16
target_family="wasm"
Materializes a SIMD value from the provided operands.  i8x16_
abs target_family="wasm"
andsimd128
Lanewise wrapping absolute value.  i8x16_
add target_family="wasm"
andsimd128
Adds two 128bit vectors as if they were two packed sixteen 8bit integers.  i8x16_
add_ sat target_family="wasm"
andsimd128
Adds two 128bit vectors as if they were two packed sixteen 8bit signed integers, saturating on overflow toi8::MAX
.  i8x16_
all_ true target_family="wasm"
andsimd128
Returns true if all lanes are nonzero, false otherwise.  i8x16_
bitmask target_family="wasm"
andsimd128
Extracts the high bit for each lane ina
and produce a scalar mask with all bits concatenated.  i8x16_
eq target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 16 eightbit integers.  i8x16_
extract_ lane target_family="wasm"
andsimd128
Extracts a lane from a 128bit vector interpreted as 16 packed i8 numbers.  i8x16_
ge target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 16 eightbit signed integers.  i8x16_
gt target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 16 eightbit signed integers.  i8x16_
le target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 16 eightbit signed integers.  i8x16_
lt target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 16 eightbit signed integers.  i8x16_
max target_family="wasm"
andsimd128
Compares lanewise signed integers, and returns the maximum of each pair.  i8x16_
min target_family="wasm"
andsimd128
Compares lanewise signed integers, and returns the minimum of each pair.  i8x16_
narrow_ i16x8 target_family="wasm"
andsimd128
Converts two input vectors into a smaller lane vector by narrowing each lane.  i8x16_
ne target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 16 eightbit integers.  i8x16_
neg target_family="wasm"
andsimd128
Negates a 128bit vectors interpreted as sixteen 8bit signed integers  i8x16_
popcnt target_family="wasm"
andsimd128
Count the number of bits set to one within each lane.  i8x16_
relaxed_ laneselect target_family="wasm"
andrelaxedsimd
A relaxed version ofv128_bitselect
where this either behaves the same asv128_bitselect
or the high bit of each lanem
is inspected and the corresponding lane ofa
is chosen if the bit is 1 or the lane ofb
is chosen if it’s zero.  i8x16_
relaxed_ swizzle target_family="wasm"
andrelaxedsimd
A relaxed version ofi8x16_swizzle(a, s)
which selects lanes froma
using indices ins
.  i8x16_
replace_ lane target_family="wasm"
andsimd128
Replaces a lane from a 128bit vector interpreted as 16 packed i8 numbers.  i8x16_
shl target_family="wasm"
andsimd128
Shifts each lane to the left by the specified number of bits.  i8x16_
shr target_family="wasm"
andsimd128
Shifts each lane to the right by the specified number of bits, sign extending.  i8x16_
shuffle target_family="wasm"
andsimd128
Returns a new vector with lanes selected from the lanes of the two input vectors$a
and$b
specified in the 16 immediate operands.  i8x16_
splat target_family="wasm"
andsimd128
Creates a vector with identical lanes.  i8x16_
sub target_family="wasm"
andsimd128
Subtracts two 128bit vectors as if they were two packed sixteen 8bit integers.  i8x16_
sub_ sat target_family="wasm"
andsimd128
Subtracts two 128bit vectors as if they were two packed sixteen 8bit signed integers, saturating on overflow toi8::MIN
.  i8x16_
swizzle target_family="wasm"
andsimd128
Returns a new vector with lanes selected from the lanes of the first input vectora
specified in the second input vectors
.  i16x8
target_family="wasm"
Materializes a SIMD value from the provided operands.  i16x8_
abs target_family="wasm"
andsimd128
Lanewise wrapping absolute value.  i16x8_
add target_family="wasm"
andsimd128
Adds two 128bit vectors as if they were two packed eight 16bit integers.  i16x8_
add_ sat target_family="wasm"
andsimd128
Adds two 128bit vectors as if they were two packed eight 16bit signed integers, saturating on overflow toi16::MAX
.  i16x8_
all_ true target_family="wasm"
andsimd128
Returns true if all lanes are nonzero, false otherwise.  i16x8_
bitmask target_family="wasm"
andsimd128
Extracts the high bit for each lane ina
and produce a scalar mask with all bits concatenated.  i16x8_
eq target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 8 sixteenbit integers.  i16x8_
extadd_ pairwise_ i8x16 target_family="wasm"
andsimd128
Integer extended pairwise addition producing extended results (twice wider results than the inputs).  i16x8_
extadd_ pairwise_ u8x16 target_family="wasm"
andsimd128
Integer extended pairwise addition producing extended results (twice wider results than the inputs).  i16x8_
extend_ high_ i8x16 target_family="wasm"
andsimd128
Converts high half of the smaller lane vector to a larger lane vector, sign extended.  i16x8_
extend_ high_ u8x16 target_family="wasm"
andsimd128
Converts high half of the smaller lane vector to a larger lane vector, zero extended.  i16x8_
extend_ low_ i8x16 target_family="wasm"
andsimd128
Converts low half of the smaller lane vector to a larger lane vector, sign extended.  i16x8_
extend_ low_ u8x16 target_family="wasm"
andsimd128
Converts low half of the smaller lane vector to a larger lane vector, zero extended.  i16x8_
extmul_ high_ i8x16 target_family="wasm"
andsimd128
Lanewise integer extended multiplication producing twice wider result than the inputs.  i16x8_
extmul_ high_ u8x16 target_family="wasm"
andsimd128
Lanewise integer extended multiplication producing twice wider result than the inputs.  i16x8_
extmul_ low_ i8x16 target_family="wasm"
andsimd128
Lanewise integer extended multiplication producing twice wider result than the inputs.  i16x8_
extmul_ low_ u8x16 target_family="wasm"
andsimd128
Lanewise integer extended multiplication producing twice wider result than the inputs.  i16x8_
extract_ lane target_family="wasm"
andsimd128
Extracts a lane from a 128bit vector interpreted as 8 packed i16 numbers.  i16x8_
ge target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 8 sixteenbit signed integers.  i16x8_
gt target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 8 sixteenbit signed integers.  i16x8_
le target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 8 sixteenbit signed integers.  i16x8_
load_ ^{⚠}extend_ i8x8 target_family="wasm"
andsimd128
Load eight 8bit integers and sign extend each one to a 16bit lane  i16x8_
load_ ^{⚠}extend_ u8x8 target_family="wasm"
andsimd128
Load eight 8bit integers and zero extend each one to a 16bit lane  i16x8_
lt target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 8 sixteenbit signed integers.  i16x8_
max target_family="wasm"
andsimd128
Compares lanewise signed integers, and returns the maximum of each pair.  i16x8_
min target_family="wasm"
andsimd128
Compares lanewise signed integers, and returns the minimum of each pair.  i16x8_
mul target_family="wasm"
andsimd128
Multiplies two 128bit vectors as if they were two packed eight 16bit signed integers.  i16x8_
narrow_ i32x4 target_family="wasm"
andsimd128
Converts two input vectors into a smaller lane vector by narrowing each lane.  i16x8_
ne target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 8 sixteenbit integers.  i16x8_
neg target_family="wasm"
andsimd128
Negates a 128bit vectors interpreted as eight 16bit signed integers  i16x8_
q15mulr_ sat target_family="wasm"
andsimd128
Lanewise saturating rounding multiplication in Q15 format.  i16x8_
relaxed_ dot_ i8x16_ i7x16 target_family="wasm"
andrelaxedsimd
A relaxed dotproduct instruction.  i16x8_
relaxed_ laneselect target_family="wasm"
andrelaxedsimd
A relaxed version ofv128_bitselect
where this either behaves the same asv128_bitselect
or the high bit of each lanem
is inspected and the corresponding lane ofa
is chosen if the bit is 1 or the lane ofb
is chosen if it’s zero.  i16x8_
relaxed_ q15mulr target_family="wasm"
andrelaxedsimd
A relaxed version ofi16x8_relaxed_q15mulr
where if both lanes arei16::MIN
then the result is eitheri16::MIN
ori16::MAX
.  i16x8_
replace_ lane target_family="wasm"
andsimd128
Replaces a lane from a 128bit vector interpreted as 8 packed i16 numbers.  i16x8_
shl target_family="wasm"
andsimd128
Shifts each lane to the left by the specified number of bits.  i16x8_
shr target_family="wasm"
andsimd128
Shifts each lane to the right by the specified number of bits, sign extending.  i16x8_
shuffle target_family="wasm"
andsimd128
Same asi8x16_shuffle
, except operates as if the inputs were eight 16bit integers, only taking 8 indices to shuffle.  i16x8_
splat target_family="wasm"
andsimd128
Creates a vector with identical lanes.  i16x8_
sub target_family="wasm"
andsimd128
Subtracts two 128bit vectors as if they were two packed eight 16bit integers.  i16x8_
sub_ sat target_family="wasm"
andsimd128
Subtracts two 128bit vectors as if they were two packed eight 16bit signed integers, saturating on overflow toi16::MIN
.  i32x4
target_family="wasm"
Materializes a SIMD value from the provided operands.  i32x4_
abs target_family="wasm"
andsimd128
Lanewise wrapping absolute value.  i32x4_
add target_family="wasm"
andsimd128
Adds two 128bit vectors as if they were two packed four 32bit integers.  i32x4_
all_ true target_family="wasm"
andsimd128
Returns true if all lanes are nonzero, false otherwise.  i32x4_
bitmask target_family="wasm"
andsimd128
Extracts the high bit for each lane ina
and produce a scalar mask with all bits concatenated.  i32x4_
dot_ i16x8 target_family="wasm"
andsimd128
Lanewise multiply signed 16bit integers in the two input vectors and add adjacent pairs of the full 32bit results.  i32x4_
eq target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit integers.  i32x4_
extadd_ pairwise_ i16x8 target_family="wasm"
andsimd128
Integer extended pairwise addition producing extended results (twice wider results than the inputs).  i32x4_
extadd_ pairwise_ u16x8 target_family="wasm"
andsimd128
Integer extended pairwise addition producing extended results (twice wider results than the inputs).  i32x4_
extend_ high_ i16x8 target_family="wasm"
andsimd128
Converts high half of the smaller lane vector to a larger lane vector, sign extended.  i32x4_
extend_ high_ u16x8 target_family="wasm"
andsimd128
Converts high half of the smaller lane vector to a larger lane vector, zero extended.  i32x4_
extend_ low_ i16x8 target_family="wasm"
andsimd128
Converts low half of the smaller lane vector to a larger lane vector, sign extended.  i32x4_
extend_ low_ u16x8 target_family="wasm"
andsimd128
Converts low half of the smaller lane vector to a larger lane vector, zero extended.  i32x4_
extmul_ high_ i16x8 target_family="wasm"
andsimd128
Lanewise integer extended multiplication producing twice wider result than the inputs.  i32x4_
extmul_ high_ u16x8 target_family="wasm"
andsimd128
Lanewise integer extended multiplication producing twice wider result than the inputs.  i32x4_
extmul_ low_ i16x8 target_family="wasm"
andsimd128
Lanewise integer extended multiplication producing twice wider result than the inputs.  i32x4_
extmul_ low_ u16x8 target_family="wasm"
andsimd128
Lanewise integer extended multiplication producing twice wider result than the inputs.  i32x4_
extract_ lane target_family="wasm"
andsimd128
Extracts a lane from a 128bit vector interpreted as 4 packed i32 numbers.  i32x4_
ge target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit signed integers.  i32x4_
gt target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit signed integers.  i32x4_
le target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit signed integers.  i32x4_
load_ ^{⚠}extend_ i16x4 target_family="wasm"
andsimd128
Load four 16bit integers and sign extend each one to a 32bit lane  i32x4_
load_ ^{⚠}extend_ u16x4 target_family="wasm"
andsimd128
Load four 16bit integers and zero extend each one to a 32bit lane  i32x4_
lt target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit signed integers.  i32x4_
max target_family="wasm"
andsimd128
Compares lanewise signed integers, and returns the maximum of each pair.  i32x4_
min target_family="wasm"
andsimd128
Compares lanewise signed integers, and returns the minimum of each pair.  i32x4_
mul target_family="wasm"
andsimd128
Multiplies two 128bit vectors as if they were two packed four 32bit signed integers.  i32x4_
ne target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit integers.  i32x4_
neg target_family="wasm"
andsimd128
Negates a 128bit vectors interpreted as four 32bit signed integers  i32x4_
relaxed_ dot_ i8x16_ i7x16_ add target_family="wasm"
andrelaxedsimd
Similar toi16x8_relaxed_dot_i8x16_i7x16
except that the intermediatei16x8
result is fed intoi32x4_extadd_pairwise_i16x8
followed byi32x4_add
to add the valuec
to the result.  i32x4_
relaxed_ laneselect target_family="wasm"
andrelaxedsimd
A relaxed version ofv128_bitselect
where this either behaves the same asv128_bitselect
or the high bit of each lanem
is inspected and the corresponding lane ofa
is chosen if the bit is 1 or the lane ofb
is chosen if it’s zero.  i32x4_
relaxed_ trunc_ f32x4 target_family="wasm"
andrelaxedsimd
A relaxed version ofi32x4_trunc_sat_f32x4(a)
converts thef32
lanes ofa
to signed 32bit integers.  i32x4_
relaxed_ trunc_ f64x2_ zero target_family="wasm"
andrelaxedsimd
A relaxed version ofi32x4_trunc_sat_f64x2_zero(a)
converts thef64
lanes ofa
to signed 32bit integers and the upper two lanes are zero.  i32x4_
replace_ lane target_family="wasm"
andsimd128
Replaces a lane from a 128bit vector interpreted as 4 packed i32 numbers.  i32x4_
shl target_family="wasm"
andsimd128
Shifts each lane to the left by the specified number of bits.  i32x4_
shr target_family="wasm"
andsimd128
Shifts each lane to the right by the specified number of bits, sign extending.  i32x4_
shuffle target_family="wasm"
andsimd128
Same asi8x16_shuffle
, except operates as if the inputs were four 32bit integers, only taking 4 indices to shuffle.  i32x4_
splat target_family="wasm"
andsimd128
Creates a vector with identical lanes.  i32x4_
sub target_family="wasm"
andsimd128
Subtracts two 128bit vectors as if they were two packed four 32bit integers.  i32x4_
trunc_ sat_ f32x4 target_family="wasm"
andsimd128
Converts a 128bit vector interpreted as four 32bit floating point numbers into a 128bit vector of four 32bit signed integers.  i32x4_
trunc_ sat_ f64x2_ zero target_family="wasm"
andsimd128
Saturating conversion of the two doubleprecision floating point lanes to two lower integer lanes using the IEEEconvertToIntegerTowardZero
function.  i64x2
target_family="wasm"
Materializes a SIMD value from the provided operands.  i64x2_
abs target_family="wasm"
andsimd128
Lanewise wrapping absolute value.  i64x2_
add target_family="wasm"
andsimd128
Adds two 128bit vectors as if they were two packed two 64bit integers.  i64x2_
all_ true target_family="wasm"
andsimd128
Returns true if all lanes are nonzero, false otherwise.  i64x2_
bitmask target_family="wasm"
andsimd128
Extracts the high bit for each lane ina
and produce a scalar mask with all bits concatenated.  i64x2_
eq target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 2 sixtyfourbit integers.  i64x2_
extend_ high_ i32x4 target_family="wasm"
andsimd128
Converts high half of the smaller lane vector to a larger lane vector, sign extended.  i64x2_
extend_ high_ u32x4 target_family="wasm"
andsimd128
Converts high half of the smaller lane vector to a larger lane vector, zero extended.  i64x2_
extend_ low_ i32x4 target_family="wasm"
andsimd128
Converts low half of the smaller lane vector to a larger lane vector, sign extended.  i64x2_
extend_ low_ u32x4 target_family="wasm"
andsimd128
Converts low half of the smaller lane vector to a larger lane vector, zero extended.  i64x2_
extmul_ high_ i32x4 target_family="wasm"
andsimd128
Lanewise integer extended multiplication producing twice wider result than the inputs.  i64x2_
extmul_ high_ u32x4 target_family="wasm"
andsimd128
Lanewise integer extended multiplication producing twice wider result than the inputs.  i64x2_
extmul_ low_ i32x4 target_family="wasm"
andsimd128
Lanewise integer extended multiplication producing twice wider result than the inputs.  i64x2_
extmul_ low_ u32x4 target_family="wasm"
andsimd128
Lanewise integer extended multiplication producing twice wider result than the inputs.  i64x2_
extract_ lane target_family="wasm"
andsimd128
Extracts a lane from a 128bit vector interpreted as 2 packed i64 numbers.  i64x2_
ge target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 2 sixtyfourbit signed integers.  i64x2_
gt target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 2 sixtyfourbit signed integers.  i64x2_
le target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 2 sixtyfourbit signed integers.  i64x2_
load_ ^{⚠}extend_ i32x2 target_family="wasm"
andsimd128
Load two 32bit integers and sign extend each one to a 64bit lane  i64x2_
load_ ^{⚠}extend_ u32x2 target_family="wasm"
andsimd128
Load two 32bit integers and zero extend each one to a 64bit lane  i64x2_
lt target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 2 sixtyfourbit signed integers.  i64x2_
mul target_family="wasm"
andsimd128
Multiplies two 128bit vectors as if they were two packed two 64bit integers.  i64x2_
ne target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 2 sixtyfourbit integers.  i64x2_
neg target_family="wasm"
andsimd128
Negates a 128bit vectors interpreted as two 64bit signed integers  i64x2_
relaxed_ laneselect target_family="wasm"
andrelaxedsimd
A relaxed version ofv128_bitselect
where this either behaves the same asv128_bitselect
or the high bit of each lanem
is inspected and the corresponding lane ofa
is chosen if the bit is 1 or the lane ofb
is chosen if it’s zero.  i64x2_
replace_ lane target_family="wasm"
andsimd128
Replaces a lane from a 128bit vector interpreted as 2 packed i64 numbers.  i64x2_
shl target_family="wasm"
andsimd128
Shifts each lane to the left by the specified number of bits.  i64x2_
shr target_family="wasm"
andsimd128
Shifts each lane to the right by the specified number of bits, sign extending.  i64x2_
shuffle target_family="wasm"
andsimd128
Same asi8x16_shuffle
, except operates as if the inputs were two 64bit integers, only taking 2 indices to shuffle.  i64x2_
splat target_family="wasm"
andsimd128
Creates a vector with identical lanes.  i64x2_
sub target_family="wasm"
andsimd128
Subtracts two 128bit vectors as if they were two packed two 64bit integers.  memory_
grow target_family="wasm"
Corresponding intrinsic to wasm’smemory.grow
instruction  memory_
size target_family="wasm"
Corresponding intrinsic to wasm’smemory.size
instruction  u8x16
target_family="wasm"
Materializes a SIMD value from the provided operands.  u8x16_
add target_family="wasm"
andsimd128
Adds two 128bit vectors as if they were two packed sixteen 8bit integers.  u8x16_
add_ sat target_family="wasm"
andsimd128
Adds two 128bit vectors as if they were two packed sixteen 8bit unsigned integers, saturating on overflow tou8::MAX
.  u8x16_
all_ true target_family="wasm"
andsimd128
Returns true if all lanes are nonzero, false otherwise.  u8x16_
avgr target_family="wasm"
andsimd128
Lanewise rounding average.  u8x16_
bitmask target_family="wasm"
andsimd128
Extracts the high bit for each lane ina
and produce a scalar mask with all bits concatenated.  u8x16_
eq target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 16 eightbit integers.  u8x16_
extract_ lane target_family="wasm"
andsimd128
Extracts a lane from a 128bit vector interpreted as 16 packed u8 numbers.  u8x16_
ge target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 16 eightbit unsigned integers.  u8x16_
gt target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 16 eightbit unsigned integers.  u8x16_
le target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 16 eightbit unsigned integers.  u8x16_
lt target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 16 eightbit unsigned integers.  u8x16_
max target_family="wasm"
andsimd128
Compares lanewise unsigned integers, and returns the maximum of each pair.  u8x16_
min target_family="wasm"
andsimd128
Compares lanewise unsigned integers, and returns the minimum of each pair.  u8x16_
narrow_ i16x8 target_family="wasm"
andsimd128
Converts two input vectors into a smaller lane vector by narrowing each lane.  u8x16_
ne target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 16 eightbit integers.  u8x16_
popcnt target_family="wasm"
andsimd128
Count the number of bits set to one within each lane.  u8x16_
relaxed_ laneselect target_family="wasm"
andrelaxedsimd
A relaxed version ofv128_bitselect
where this either behaves the same asv128_bitselect
or the high bit of each lanem
is inspected and the corresponding lane ofa
is chosen if the bit is 1 or the lane ofb
is chosen if it’s zero.  u8x16_
relaxed_ swizzle target_family="wasm"
andrelaxedsimd
A relaxed version ofi8x16_swizzle(a, s)
which selects lanes froma
using indices ins
.  u8x16_
replace_ lane target_family="wasm"
andsimd128
Replaces a lane from a 128bit vector interpreted as 16 packed u8 numbers.  u8x16_
shl target_family="wasm"
andsimd128
Shifts each lane to the left by the specified number of bits.  u8x16_
shr target_family="wasm"
andsimd128
Shifts each lane to the right by the specified number of bits, shifting in zeros.  u8x16_
shuffle target_family="wasm"
andsimd128
Returns a new vector with lanes selected from the lanes of the two input vectors$a
and$b
specified in the 16 immediate operands.  u8x16_
splat target_family="wasm"
andsimd128
Creates a vector with identical lanes.  u8x16_
sub target_family="wasm"
andsimd128
Subtracts two 128bit vectors as if they were two packed sixteen 8bit integers.  u8x16_
sub_ sat target_family="wasm"
andsimd128
Subtracts two 128bit vectors as if they were two packed sixteen 8bit unsigned integers, saturating on overflow to 0.  u8x16_
swizzle target_family="wasm"
andsimd128
Returns a new vector with lanes selected from the lanes of the first input vectora
specified in the second input vectors
.  u16x8
target_family="wasm"
Materializes a SIMD value from the provided operands.  u16x8_
add target_family="wasm"
andsimd128
Adds two 128bit vectors as if they were two packed eight 16bit integers.  u16x8_
add_ sat target_family="wasm"
andsimd128
Adds two 128bit vectors as if they were two packed eight 16bit unsigned integers, saturating on overflow tou16::MAX
.  u16x8_
all_ true target_family="wasm"
andsimd128
Returns true if all lanes are nonzero, false otherwise.  u16x8_
avgr target_family="wasm"
andsimd128
Lanewise rounding average.  u16x8_
bitmask target_family="wasm"
andsimd128
Extracts the high bit for each lane ina
and produce a scalar mask with all bits concatenated.  u16x8_
eq target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 8 sixteenbit integers.  u16x8_
extadd_ pairwise_ u8x16 target_family="wasm"
andsimd128
Integer extended pairwise addition producing extended results (twice wider results than the inputs).  u16x8_
extend_ high_ u8x16 target_family="wasm"
andsimd128
Converts high half of the smaller lane vector to a larger lane vector, zero extended.  u16x8_
extend_ low_ u8x16 target_family="wasm"
andsimd128
Converts low half of the smaller lane vector to a larger lane vector, zero extended.  u16x8_
extmul_ high_ u8x16 target_family="wasm"
andsimd128
Lanewise integer extended multiplication producing twice wider result than the inputs.  u16x8_
extmul_ low_ u8x16 target_family="wasm"
andsimd128
Lanewise integer extended multiplication producing twice wider result than the inputs.  u16x8_
extract_ lane target_family="wasm"
andsimd128
Extracts a lane from a 128bit vector interpreted as 8 packed u16 numbers.  u16x8_
ge target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 8 sixteenbit unsigned integers.  u16x8_
gt target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 8 sixteenbit unsigned integers.  u16x8_
le target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 8 sixteenbit unsigned integers.  u16x8_
load_ ^{⚠}extend_ u8x8 target_family="wasm"
andsimd128
Load eight 8bit integers and zero extend each one to a 16bit lane  u16x8_
lt target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 8 sixteenbit unsigned integers.  u16x8_
max target_family="wasm"
andsimd128
Compares lanewise unsigned integers, and returns the maximum of each pair.  u16x8_
min target_family="wasm"
andsimd128
Compares lanewise unsigned integers, and returns the minimum of each pair.  u16x8_
mul target_family="wasm"
andsimd128
Multiplies two 128bit vectors as if they were two packed eight 16bit signed integers.  u16x8_
narrow_ i32x4 target_family="wasm"
andsimd128
Converts two input vectors into a smaller lane vector by narrowing each lane.  u16x8_
ne target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 8 sixteenbit integers.  u16x8_
relaxed_ dot_ i8x16_ i7x16 target_family="wasm"
andrelaxedsimd
A relaxed dotproduct instruction.  u16x8_
relaxed_ laneselect target_family="wasm"
andrelaxedsimd
A relaxed version ofv128_bitselect
where this either behaves the same asv128_bitselect
or the high bit of each lanem
is inspected and the corresponding lane ofa
is chosen if the bit is 1 or the lane ofb
is chosen if it’s zero.  u16x8_
relaxed_ q15mulr target_family="wasm"
andrelaxedsimd
A relaxed version ofi16x8_relaxed_q15mulr
where if both lanes arei16::MIN
then the result is eitheri16::MIN
ori16::MAX
.  u16x8_
replace_ lane target_family="wasm"
andsimd128
Replaces a lane from a 128bit vector interpreted as 8 packed u16 numbers.  u16x8_
shl target_family="wasm"
andsimd128
Shifts each lane to the left by the specified number of bits.  u16x8_
shr target_family="wasm"
andsimd128
Shifts each lane to the right by the specified number of bits, shifting in zeros.  u16x8_
shuffle target_family="wasm"
andsimd128
Same asi8x16_shuffle
, except operates as if the inputs were eight 16bit integers, only taking 8 indices to shuffle.  u16x8_
splat target_family="wasm"
andsimd128
Creates a vector with identical lanes.  u16x8_
sub target_family="wasm"
andsimd128
Subtracts two 128bit vectors as if they were two packed eight 16bit integers.  u16x8_
sub_ sat target_family="wasm"
andsimd128
Subtracts two 128bit vectors as if they were two packed eight 16bit unsigned integers, saturating on overflow to 0.  u32x4
target_family="wasm"
Materializes a SIMD value from the provided operands.  u32x4_
add target_family="wasm"
andsimd128
Adds two 128bit vectors as if they were two packed four 32bit integers.  u32x4_
all_ true target_family="wasm"
andsimd128
Returns true if all lanes are nonzero, false otherwise.  u32x4_
bitmask target_family="wasm"
andsimd128
Extracts the high bit for each lane ina
and produce a scalar mask with all bits concatenated.  u32x4_
eq target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit integers.  u32x4_
extadd_ pairwise_ u16x8 target_family="wasm"
andsimd128
Integer extended pairwise addition producing extended results (twice wider results than the inputs).  u32x4_
extend_ high_ u16x8 target_family="wasm"
andsimd128
Converts high half of the smaller lane vector to a larger lane vector, zero extended.  u32x4_
extend_ low_ u16x8 target_family="wasm"
andsimd128
Converts low half of the smaller lane vector to a larger lane vector, zero extended.  u32x4_
extmul_ high_ u16x8 target_family="wasm"
andsimd128
Lanewise integer extended multiplication producing twice wider result than the inputs.  u32x4_
extmul_ low_ u16x8 target_family="wasm"
andsimd128
Lanewise integer extended multiplication producing twice wider result than the inputs.  u32x4_
extract_ lane target_family="wasm"
andsimd128
Extracts a lane from a 128bit vector interpreted as 4 packed u32 numbers.  u32x4_
ge target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit unsigned integers.  u32x4_
gt target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit unsigned integers.  u32x4_
le target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit unsigned integers.  u32x4_
load_ ^{⚠}extend_ u16x4 target_family="wasm"
andsimd128
Load four 16bit integers and zero extend each one to a 32bit lane  u32x4_
lt target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit unsigned integers.  u32x4_
max target_family="wasm"
andsimd128
Compares lanewise unsigned integers, and returns the maximum of each pair.  u32x4_
min target_family="wasm"
andsimd128
Compares lanewise unsigned integers, and returns the minimum of each pair.  u32x4_
mul target_family="wasm"
andsimd128
Multiplies two 128bit vectors as if they were two packed four 32bit signed integers.  u32x4_
ne target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 4 thirtytwobit integers.  u32x4_
relaxed_ dot_ i8x16_ i7x16_ add target_family="wasm"
andrelaxedsimd
Similar toi16x8_relaxed_dot_i8x16_i7x16
except that the intermediatei16x8
result is fed intoi32x4_extadd_pairwise_i16x8
followed byi32x4_add
to add the valuec
to the result.  u32x4_
relaxed_ laneselect target_family="wasm"
andrelaxedsimd
A relaxed version ofv128_bitselect
where this either behaves the same asv128_bitselect
or the high bit of each lanem
is inspected and the corresponding lane ofa
is chosen if the bit is 1 or the lane ofb
is chosen if it’s zero.  u32x4_
relaxed_ trunc_ f32x4 target_family="wasm"
andrelaxedsimd
A relaxed version ofu32x4_trunc_sat_f32x4(a)
converts thef32
lanes ofa
to unsigned 32bit integers.  u32x4_
relaxed_ trunc_ f64x2_ zero target_family="wasm"
andrelaxedsimd
A relaxed version ofu32x4_trunc_sat_f64x2_zero(a)
converts thef64
lanes ofa
to unsigned 32bit integers and the upper two lanes are zero.  u32x4_
replace_ lane target_family="wasm"
andsimd128
Replaces a lane from a 128bit vector interpreted as 4 packed u32 numbers.  u32x4_
shl target_family="wasm"
andsimd128
Shifts each lane to the left by the specified number of bits.  u32x4_
shr target_family="wasm"
andsimd128
Shifts each lane to the right by the specified number of bits, shifting in zeros.  u32x4_
shuffle target_family="wasm"
andsimd128
Same asi8x16_shuffle
, except operates as if the inputs were four 32bit integers, only taking 4 indices to shuffle.  u32x4_
splat target_family="wasm"
andsimd128
Creates a vector with identical lanes.  u32x4_
sub target_family="wasm"
andsimd128
Subtracts two 128bit vectors as if they were two packed four 32bit integers.  u32x4_
trunc_ sat_ f32x4 target_family="wasm"
andsimd128
Converts a 128bit vector interpreted as four 32bit floating point numbers into a 128bit vector of four 32bit unsigned integers.  u32x4_
trunc_ sat_ f64x2_ zero target_family="wasm"
andsimd128
Saturating conversion of the two doubleprecision floating point lanes to two lower integer lanes using the IEEEconvertToIntegerTowardZero
function.  u64x2
target_family="wasm"
Materializes a SIMD value from the provided operands.  u64x2_
add target_family="wasm"
andsimd128
Adds two 128bit vectors as if they were two packed two 64bit integers.  u64x2_
all_ true target_family="wasm"
andsimd128
Returns true if all lanes are nonzero, false otherwise.  u64x2_
bitmask target_family="wasm"
andsimd128
Extracts the high bit for each lane ina
and produce a scalar mask with all bits concatenated.  u64x2_
eq target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 2 sixtyfourbit integers.  u64x2_
extend_ high_ u32x4 target_family="wasm"
andsimd128
Converts high half of the smaller lane vector to a larger lane vector, zero extended.  u64x2_
extend_ low_ u32x4 target_family="wasm"
andsimd128
Converts low half of the smaller lane vector to a larger lane vector, zero extended.  u64x2_
extmul_ high_ u32x4 target_family="wasm"
andsimd128
Lanewise integer extended multiplication producing twice wider result than the inputs.  u64x2_
extmul_ low_ u32x4 target_family="wasm"
andsimd128
Lanewise integer extended multiplication producing twice wider result than the inputs.  u64x2_
extract_ lane target_family="wasm"
andsimd128
Extracts a lane from a 128bit vector interpreted as 2 packed u64 numbers.  u64x2_
load_ ^{⚠}extend_ u32x2 target_family="wasm"
andsimd128
Load two 32bit integers and zero extend each one to a 64bit lane  u64x2_
mul target_family="wasm"
andsimd128
Multiplies two 128bit vectors as if they were two packed two 64bit integers.  u64x2_
ne target_family="wasm"
andsimd128
Compares two 128bit vectors as if they were two vectors of 2 sixtyfourbit integers.  u64x2_
relaxed_ laneselect target_family="wasm"
andrelaxedsimd
A relaxed version ofv128_bitselect
where this either behaves the same asv128_bitselect
or the high bit of each lanem
is inspected and the corresponding lane ofa
is chosen if the bit is 1 or the lane ofb
is chosen if it’s zero.  u64x2_
replace_ lane target_family="wasm"
andsimd128
Replaces a lane from a 128bit vector interpreted as 2 packed u64 numbers.  u64x2_
shl target_family="wasm"
andsimd128
Shifts each lane to the left by the specified number of bits.  u64x2_
shr target_family="wasm"
andsimd128
Shifts each lane to the right by the specified number of bits, shifting in zeros.  u64x2_
shuffle target_family="wasm"
andsimd128
Same asi8x16_shuffle
, except operates as if the inputs were two 64bit integers, only taking 2 indices to shuffle.  u64x2_
splat target_family="wasm"
andsimd128
Creates a vector with identical lanes.  u64x2_
sub target_family="wasm"
andsimd128
Subtracts two 128bit vectors as if they were two packed two 64bit integers.  unreachable
target_family="wasm"
Generates theunreachable
instruction, which causes an unconditional trap.  v128_
and target_family="wasm"
andsimd128
Performs a bitwise and of the two input 128bit vectors, returning the resulting vector.  v128_
andnot target_family="wasm"
andsimd128
Bitwise AND of bits ofa
and the logical inverse of bits ofb
.  v128_
any_ true target_family="wasm"
andsimd128
Returnstrue
if any bit ina
is set, orfalse
otherwise.  v128_
bitselect target_family="wasm"
andsimd128
Use the bitmask inc
to select bits fromv1
when 1 andv2
when 0.  v128_
load ^{⚠}target_family="wasm"
andsimd128
Loads av128
vector from the given heap address.  v128_
load8_ ^{⚠}lane target_family="wasm"
andsimd128
Loads an 8bit value fromm
and sets laneL
ofv
to that value.  v128_
load8_ ^{⚠}splat target_family="wasm"
andsimd128
Load a single element and splat to all lanes of a v128 vector.  v128_
load16_ ^{⚠}lane target_family="wasm"
andsimd128
Loads a 16bit value fromm
and sets laneL
ofv
to that value.  v128_
load16_ ^{⚠}splat target_family="wasm"
andsimd128
Load a single element and splat to all lanes of a v128 vector.  v128_
load32_ ^{⚠}lane target_family="wasm"
andsimd128
Loads a 32bit value fromm
and sets laneL
ofv
to that value.  v128_
load32_ ^{⚠}splat target_family="wasm"
andsimd128
Load a single element and splat to all lanes of a v128 vector.  v128_
load32_ ^{⚠}zero target_family="wasm"
andsimd128
Load a 32bit element into the low bits of the vector and sets all other bits to zero.  v128_
load64_ ^{⚠}lane target_family="wasm"
andsimd128
Loads a 64bit value fromm
and sets laneL
ofv
to that value.  v128_
load64_ ^{⚠}splat target_family="wasm"
andsimd128
Load a single element and splat to all lanes of a v128 vector.  v128_
load64_ ^{⚠}zero target_family="wasm"
andsimd128
Load a 64bit element into the low bits of the vector and sets all other bits to zero.  v128_
not target_family="wasm"
andsimd128
Flips each bit of the 128bit input vector.  v128_or
target_family="wasm"
andsimd128
Performs a bitwise or of the two input 128bit vectors, returning the resulting vector.  v128_
store ^{⚠}target_family="wasm"
andsimd128
Stores av128
vector to the given heap address.  v128_
store8_ ^{⚠}lane target_family="wasm"
andsimd128
Stores the 8bit value from laneL
ofv
intom
 v128_
store16_ ^{⚠}lane target_family="wasm"
andsimd128
Stores the 16bit value from laneL
ofv
intom
 v128_
store32_ ^{⚠}lane target_family="wasm"
andsimd128
Stores the 32bit value from laneL
ofv
intom
 v128_
store64_ ^{⚠}lane target_family="wasm"
andsimd128
Stores the 64bit value from laneL
ofv
intom
 v128_
xor target_family="wasm"
andsimd128
Performs a bitwise xor of the two input 128bit vectors, returning the resulting vector.  memory_
atomic_ ^{⚠}notify Experimental target_family="wasm"
andatomics
Corresponding intrinsic to wasm’smemory.atomic.notify
instruction  memory_
atomic_ ^{⚠}wait32 Experimental target_family="wasm"
andatomics
Corresponding intrinsic to wasm’smemory.atomic.wait32
instruction  memory_
atomic_ ^{⚠}wait64 Experimental target_family="wasm"
andatomics
Corresponding intrinsic to wasm’smemory.atomic.wait64
instruction  throw^{⚠}
Experimental target_family="wasm"
Generates thethrow
instruction from the exceptionhandling proposal for WASM.