🔬This is a nightly-only experimental API. (

`riscv_ext_intrinsics`

#114544)Available on

**RISC-V RV32**only.## Expand description

Platform-specific intrinsics for the `riscv32`

platform.

See the module documentation for more details.

## Functions§

- add8ExperimentalAdds packed 8-bit signed numbers, discarding overflow bits
- add16ExperimentalAdds packed 16-bit signed numbers, discarding overflow bits
- AES final round decryption instruction for RV32.
- AES middle round decryption instruction for RV32.
- AES final round encryption instruction for RV32.
- AES middle round encryption instruction for RV32 with.
- Carry-less multiply (low-part)
- Carry-less multiply (high-part)
- Carry-less multiply (reversed)
- clrs8ExperimentalCount the number of redundant sign bits of the packed 8-bit elements
- clrs16ExperimentalCount the number of redundant sign bits of the packed 16-bit elements
- clrs32ExperimentalCount the number of redundant sign bits of the packed 32-bit elements
- clz8ExperimentalCount the number of leading zero bits of the packed 8-bit elements
- clz16ExperimentalCount the number of leading zero bits of the packed 16-bit elements
- clz32ExperimentalCount the number of leading zero bits of the packed 32-bit elements
- cmpeq8ExperimentalCompare equality for packed 8-bit elements
- cmpeq16ExperimentalCompare equality for packed 16-bit elements
- cras16ExperimentalCross adds and subtracts packed 16-bit signed numbers, discarding overflow bits
- crsa16ExperimentalCross subtracts and adds packed 16-bit signed numbers, discarding overflow bits
- Generates the
`FENCE.I`

instruction - frrmExperimentalReads the floating-point rounding mode register
`frm`

- Hypervisor memory management fence for guest physical address and virtual machine
- Hypervisor memory management fence for all virtual machines and guest physical addresses
- Hypervisor memory management fence for guest physical address
- Hypervisor memory management fence for given virtual machine
- Hypervisor memory management fence for given guest virtual address and guest address space
- Hypervisor memory management fence for all guest address spaces and guest virtual addresses
- Hypervisor memory management fence for given guest address space
- Hypervisor memory management fence for given guest virtual address
- Invalidate hypervisor translation cache for guest physical address and virtual machine
- Invalidate hypervisor translation cache for all virtual machines and guest physical addresses
- Invalidate hypervisor translation cache for guest physical address
- Invalidate hypervisor translation cache for given virtual machine
- Invalidate hypervisor translation cache for given guest virtual address and guest address space
- Invalidate hypervisor translation cache for all guest address spaces and guest virtual addresses
- Invalidate hypervisor translation cache for given guest address space
- Invalidate hypervisor translation cache for given guest virtual address
- Loads virtual machine memory by signed byte integer
- Loads virtual machine memory by unsigned byte integer
- Loads virtual machine memory by signed half integer
- Loads virtual machine memory by unsigned half integer
- Loads virtual machine memory by signed word integer
- Accesses virtual machine instruction by unsigned half integer
- Accesses virtual machine instruction by unsigned word integer
- Stores virtual machine memory by byte integer
- Stores virtual machine memory by half integer
- Stores virtual machine memory by word integer
- kabs8ExperimentalCompute the absolute value of packed 8-bit signed integers
- kabs16ExperimentalCompute the absolute value of packed 16-bit signed integers
- kadd8ExperimentalAdds packed 8-bit signed numbers, saturating at the numeric bounds
- kadd16ExperimentalAdds packed 16-bit signed numbers, saturating at the numeric bounds
- kaddhExperimentalAdds signed lower 16-bit content of two registers with Q15 saturation
- kcras16ExperimentalCross adds and subtracts packed 16-bit signed numbers, saturating at the numeric bounds
- kcrsa16ExperimentalCross subtracts and adds packed 16-bit signed numbers, saturating at the numeric bounds
- ksll8ExperimentalLogical left shift packed 8-bit elements, saturating at the numeric bounds
- ksll16ExperimentalLogical left shift packed 16-bit elements, saturating at the numeric bounds
- kslra8ExperimentalLogical saturating left then arithmetic right shift packed 8-bit elements
- kslra8uExperimentalLogical saturating left then arithmetic right shift packed 8-bit elements
- kslra16ExperimentalLogical saturating left then arithmetic right shift packed 16-bit elements
- kslra16uExperimentalLogical saturating left then arithmetic right shift packed 16-bit elements
- kstas16ExperimentalStraight adds and subtracts packed 16-bit signed numbers, saturating at the numeric bounds
- kstsa16ExperimentalStraight subtracts and adds packed 16-bit signed numbers, saturating at the numeric bounds
- ksub8ExperimentalSubtracts packed 8-bit signed numbers, saturating at the numeric bounds
- ksub16ExperimentalSubtracts packed 16-bit signed numbers, saturating at the numeric bounds
- ksubhExperimentalSubtracts signed lower 16-bit content of two registers with Q15 saturation
- nopExperimentalGenerates the
`NOP`

instruction - Bitwise OR-Combine, byte granule
- pauseExperimentalGenerates the
`PAUSE`

instruction - pbsadExperimentalCalculate the sum of absolute difference of unsigned 8-bit data elements
- pbsadaExperimentalCalculate and accumulate the sum of absolute difference of unsigned 8-bit data elements
- pkbt16ExperimentalPack two 16-bit data from bottom and top half from 32-bit chunks
- pktb16ExperimentalPack two 16-bit data from top and bottom half from 32-bit chunks
- radd8ExperimentalHalves the sum of packed 8-bit signed numbers, dropping least bits
- radd16ExperimentalHalves the sum of packed 16-bit signed numbers, dropping least bits
- rcras16ExperimentalCross halves of adds and subtracts packed 16-bit signed numbers, dropping least bits
- rcrsa16ExperimentalCross halves of subtracts and adds packed 16-bit signed numbers, dropping least bits
- rstas16ExperimentalStraight halves of adds and subtracts packed 16-bit signed numbers, dropping least bits
- rstsa16ExperimentalStraight halves of subtracts and adds packed 16-bit signed numbers, dropping least bits
- rsub8ExperimentalHalves the subtraction result of packed 8-bit signed numbers, dropping least bits
- rsub16ExperimentalHalves the subtraction result of packed 16-bit signed numbers, dropping least bits
- scmple8ExperimentalCompare whether 8-bit packed signed integers are less than or equal to the others
- scmple16ExperimentalCompare whether 16-bit packed signed integers are less than or equal to the others
- scmplt8ExperimentalCompare whether 8-bit packed signed integers are less than the others
- scmplt16ExperimentalCompare whether 16-bit packed signed integers are less than the others
- Generates the
`SFENCE.INVAL.IR`

instruction - Supervisor memory management fence for given virtual address and address space
- Supervisor memory management fence for all address spaces and virtual addresses
- Supervisor memory management fence for given address space
- Supervisor memory management fence for given virtual address
- Generates the
`SFENCE.W.INVAL`

instruction - Implements the Sigma0 transformation function as used in the SHA2-256 hash function [49] (Section 4.1.2).
- Implements the Sigma1 transformation function as used in the SHA2-256 hash function [49] (Section 4.1.2).
- Implements the Sum0 transformation function as used in the SHA2-256 hash function [49] (Section 4.1.2).
- Implements the Sum1 transformation function as used in the SHA2-256 hash function [49] (Section 4.1.2).
- Implements the high half of the Sigma0 transformation, as used in the SHA2-512 hash function [49] (Section 4.1.3).
- Implements the low half of the Sigma0 transformation, as used in the SHA2-512 hash function [49] (Section 4.1.3).
- Implements the high half of the Sigma1 transformation, as used in the SHA2-512 hash function [49] (Section 4.1.3).
- Implements the low half of the Sigma1 transformation, as used in the SHA2-512 hash function [49] (Section 4.1.3).
- Implements the Sum0 transformation, as used in the SHA2-512 hash function [49] (Section 4.1.3).
- Implements the Sum1 transformation, as used in the SHA2-512 hash function [49] (Section 4.1.3).
- Invalidate supervisor translation cache for given virtual address and address space
- Invalidate supervisor translation cache for all address spaces and virtual addresses
- Invalidate supervisor translation cache for given address space
- Invalidate supervisor translation cache for given virtual address
- sll8ExperimentalLogical left shift packed 8-bit elements, discarding overflow bits
- sll16ExperimentalLogical left shift packed 16-bit elements, discarding overflow bits
- Implements the P0 transformation function as used in the SM3 hash function [4, 30].
- Implements the P1 transformation function as used in the SM3 hash function [4, 30].
- Accelerates the block encrypt/decrypt operation of the SM4 block cipher [5, 31].
- Accelerates the Key Schedule operation of the SM4 block cipher [5, 31] with
`bs=0`

. - smaqaExperimentalMultiply signed 8-bit elements and add 16-bit elements on results for packed 32-bit chunks
- smaqasuExperimentalMultiply signed to unsigned 8-bit and add 16-bit elements on results for packed 32-bit chunks
- smax8ExperimentalGet maximum values from 8-bit packed signed integers
- smax16ExperimentalGet maximum values from 16-bit packed signed integers
- smin8ExperimentalGet minimum values from 8-bit packed signed integers
- smin16ExperimentalGet minimum values from 16-bit packed signed integers
- sra8ExperimentalArithmetic right shift packed 8-bit elements without rounding up
- sra8uExperimentalArithmetic right shift packed 8-bit elements with rounding up
- sra16ExperimentalArithmetic right shift packed 16-bit elements without rounding up
- sra16uExperimentalArithmetic right shift packed 16-bit elements with rounding up
- srl8ExperimentalLogical right shift packed 8-bit elements without rounding up
- srl8uExperimentalLogical right shift packed 8-bit elements with rounding up
- srl16ExperimentalLogical right shift packed 16-bit elements without rounding up
- srl16uExperimentalLogical right shift packed 16-bit elements with rounding up
- stas16ExperimentalStraight adds and subtracts packed 16-bit signed numbers, discarding overflow bits
- stsa16ExperimentalStraight subtracts and adds packed 16-bit signed numbers, discarding overflow bits
- sub8ExperimentalSubtracts packed 8-bit signed numbers, discarding overflow bits
- sub16ExperimentalSubtracts packed 16-bit signed numbers, discarding overflow bits
- sunpkd810ExperimentalUnpack first and zeroth into two 16-bit signed halfwords in each 32-bit chunk
- sunpkd820ExperimentalUnpack second and zeroth into two 16-bit signed halfwords in each 32-bit chunk
- sunpkd830ExperimentalUnpack third and zeroth into two 16-bit signed halfwords in each 32-bit chunk
- sunpkd831ExperimentalUnpack third and first into two 16-bit signed halfwords in each 32-bit chunk
- sunpkd832ExperimentalUnpack third and second into two 16-bit signed halfwords in each 32-bit chunk
- swap8ExperimentalSwap the 8-bit bytes within each 16-bit halfword of a register.
- swap16ExperimentalSwap the 16-bit halfwords within each 32-bit word of a register
- ucmple8ExperimentalCompare whether 8-bit packed unsigned integers are less than or equal to the others
- ucmple16ExperimentalCompare whether 16-bit packed unsigned integers are less than or equal to the others
- ucmplt8ExperimentalCompare whether 8-bit packed unsigned integers are less than the others
- ucmplt16ExperimentalCompare whether 16-bit packed unsigned integers are less than the others
- ukadd8ExperimentalAdds packed 8-bit unsigned numbers, saturating at the numeric bounds
- ukadd16ExperimentalAdds packed 16-bit unsigned numbers, saturating at the numeric bounds
- ukaddhExperimentalAdds signed lower 16-bit content of two registers with U16 saturation
- ukcras16ExperimentalCross adds and subtracts packed 16-bit unsigned numbers, saturating at the numeric bounds
- ukcrsa16ExperimentalCross subtracts and adds packed 16-bit unsigned numbers, saturating at the numeric bounds
- ukstas16ExperimentalStraight adds and subtracts packed 16-bit unsigned numbers, saturating at the numeric bounds
- ukstsa16ExperimentalStraight subtracts and adds packed 16-bit unsigned numbers, saturating at the numeric bounds
- uksub8ExperimentalSubtracts packed 8-bit unsigned numbers, saturating at the numeric bounds
- uksub16ExperimentalSubtracts packed 16-bit unsigned numbers, saturating at the numeric bounds
- uksubhExperimentalSubtracts signed lower 16-bit content of two registers with U16 saturation
- umaqaExperimentalMultiply unsigned 8-bit elements and add 16-bit elements on results for packed 32-bit chunks
- umax8ExperimentalGet maximum values from 8-bit packed unsigned integers
- umax16ExperimentalGet maximum values from 16-bit packed unsigned integers
- umin8ExperimentalGet minimum values from 8-bit packed unsigned integers
- umin16ExperimentalGet minimum values from 16-bit packed unsigned integers
- Place odd and even bits of the source word into upper/lower halves of the destination.
- uradd8ExperimentalHalves the sum of packed 8-bit unsigned numbers, dropping least bits
- uradd16ExperimentalHalves the sum of packed 16-bit unsigned numbers, dropping least bits
- urcras16ExperimentalCross halves of adds and subtracts packed 16-bit unsigned numbers, dropping least bits
- urcrsa16ExperimentalCross halves of subtracts and adds packed 16-bit unsigned numbers, dropping least bits
- urstas16ExperimentalStraight halves of adds and subtracts packed 16-bit unsigned numbers, dropping least bits
- urstsa16ExperimentalStraight halves of subtracts and adds packed 16-bit unsigned numbers, dropping least bits
- ursub8ExperimentalHalves the subtraction result of packed 8-bit unsigned numbers, dropping least bits
- ursub16ExperimentalHalves the subtraction result of packed 16-bit unsigned numbers, dropping least bits
- Generates the
`WFI`

instruction - Nibble-wise lookup of indicies into a vector.
- Byte-wise lookup of indicies into a vector in registers.
- Place upper/lower halves of the source register into odd/even bits of the destination respectivley.
- zunpkd810ExperimentalUnpack first and zeroth into two 16-bit unsigned halfwords in each 32-bit chunk
- zunpkd820ExperimentalUnpack second and zeroth into two 16-bit unsigned halfwords in each 32-bit chunk
- zunpkd830ExperimentalUnpack third and zeroth into two 16-bit unsigned halfwords in each 32-bit chunk
- zunpkd831ExperimentalUnpack third and first into two 16-bit unsigned halfwords in each 32-bit chunk
- zunpkd832ExperimentalUnpack third and second into two 16-bit unsigned halfwords in each 32-bit chunk