Function core::arch::riscv32::aes32dsmi

source ·
pub unsafe fn aes32dsmi(rs1: u32, rs2: u32, const BS: u8) -> u32
🔬This is a nightly-only experimental API. (riscv_ext_intrinsics #114544)
Available on RISC-V RV32 and target feature zknd only.
Expand description

AES middle round decryption instruction for RV32.

This instruction sources a single byte from rs2 according to bs. To this it applies the inverse AES SBox operation, and a partial inverse MixColumn, before XOR’ing the result with rs1. This instruction must always be implemented such that its execution latency does not depend on the data being operated on.

Source: RISC-V Cryptography Extensions Volume I: Scalar & Entropy Source Instructions

Version: v1.0.1

Section: 3.2


The BS parameter is expected to be a constant value and only the bottom 2 bits of bs are used.


This function is safe to use if the zknd target feature is present.