Function core::arch::riscv32::srl16u

source ·
pub fn srl16u(a: usize, b: u32) -> usize
🔬This is a nightly-only experimental API. (riscv_ext_intrinsics #114544)
Available on RISC-V RV32 only.
Expand description

Logical right shift packed 16-bit elements with rounding up