rustc_target/spec/targets/
thumbv8r_none_eabihf.rs

1// Targets the Little-endian Cortex-R52 processor (ARMv8-R)
2
3use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
4
5pub(crate) fn target() -> Target {
6    Target {
7        llvm_target: "thumbv8r-none-eabihf".into(),
8        metadata: TargetMetadata {
9            description: Some("Thumb-mode Bare Armv8-R, hardfloat".into()),
10            tier: Some(2),
11            host_tools: Some(false),
12            std: Some(false),
13        },
14        pointer_width: 32,
15        data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
16        arch: Arch::Arm,
17
18        options: TargetOptions {
19            abi: Abi::EabiHf,
20            llvm_floatabi: Some(FloatAbi::Hard),
21            // Armv8-R requires a minimum set of floating-point features equivalent to:
22            // fp-armv8, SP-only, with 16 DP (32 SP) registers
23            // LLVM defines Armv8-R to include these features automatically.
24            //
25            // The Cortex-R52 supports these default features and optionally includes:
26            // neon-fp-armv8, SP+DP, with 32 DP registers
27            //
28            // Reference:
29            // Arm Cortex-R52 Processor Technical Reference Manual
30            // - Chapter 15 Advanced SIMD and floating-point support
31            max_atomic_width: Some(64),
32            has_thumb_interworking: true,
33            ..base::arm_none::opts()
34        },
35    }
36}
rustc_target/spec/targets/thumbv8r_none_eabihf.rs

rustc_target/spec/targets/
thumbv8r_none_eabihf.rs
