core/stdarch/crates/core_arch/src/x86/
avx512cd.rs

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1use crate::core_arch::{simd::*, x86::*};
2use crate::intrinsics::simd::*;
3
4#[cfg(test)]
5use stdarch_test::assert_instr;
6
7/// Broadcast the low 16-bits from input mask k to all 32-bit elements of dst.
8///
9/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_broadcastmw_epi32&expand=553)
10#[inline]
11#[target_feature(enable = "avx512cd")]
12#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
13#[cfg_attr(test, assert_instr(vpbroadcast))] // should be vpbroadcastmw2d
14pub unsafe fn _mm512_broadcastmw_epi32(k: __mmask16) -> __m512i {
15    _mm512_set1_epi32(k as i32)
16}
17
18/// Broadcast the low 16-bits from input mask k to all 32-bit elements of dst.
19///
20/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_broadcastmw_epi32&expand=552)
21#[inline]
22#[target_feature(enable = "avx512cd,avx512vl")]
23#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
24#[cfg_attr(test, assert_instr(vpbroadcast))] // should be vpbroadcastmw2d
25pub unsafe fn _mm256_broadcastmw_epi32(k: __mmask16) -> __m256i {
26    _mm256_set1_epi32(k as i32)
27}
28
29/// Broadcast the low 16-bits from input mask k to all 32-bit elements of dst.
30///
31/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_broadcastmw_epi32&expand=551)
32#[inline]
33#[target_feature(enable = "avx512cd,avx512vl")]
34#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
35#[cfg_attr(test, assert_instr(vpbroadcast))] // should be vpbroadcastmw2d
36pub unsafe fn _mm_broadcastmw_epi32(k: __mmask16) -> __m128i {
37    _mm_set1_epi32(k as i32)
38}
39
40/// Broadcast the low 8-bits from input mask k to all 64-bit elements of dst.
41///
42/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_broadcastmb_epi64&expand=550)
43#[inline]
44#[target_feature(enable = "avx512cd")]
45#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
46#[cfg_attr(test, assert_instr(vpbroadcast))] // should be vpbroadcastmb2q
47pub unsafe fn _mm512_broadcastmb_epi64(k: __mmask8) -> __m512i {
48    _mm512_set1_epi64(k as i64)
49}
50
51/// Broadcast the low 8-bits from input mask k to all 64-bit elements of dst.
52///
53/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_broadcastmb_epi64&expand=549)
54#[inline]
55#[target_feature(enable = "avx512cd,avx512vl")]
56#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
57#[cfg_attr(test, assert_instr(vpbroadcast))] // should be vpbroadcastmb2q
58pub unsafe fn _mm256_broadcastmb_epi64(k: __mmask8) -> __m256i {
59    _mm256_set1_epi64x(k as i64)
60}
61
62/// Broadcast the low 8-bits from input mask k to all 64-bit elements of dst.
63///
64/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_broadcastmb_epi64&expand=548)
65#[inline]
66#[target_feature(enable = "avx512cd,avx512vl")]
67#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
68#[cfg_attr(test, assert_instr(vpbroadcast))] // should be vpbroadcastmb2q
69pub unsafe fn _mm_broadcastmb_epi64(k: __mmask8) -> __m128i {
70    _mm_set1_epi64x(k as i64)
71}
72
73/// Test each 32-bit element of a for equality with all other elements in a closer to the least significant bit. Each element's comparison forms a zero extended bit vector in dst.
74///
75/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_conflict_epi32&expand=1248)
76#[inline]
77#[target_feature(enable = "avx512cd")]
78#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
79#[cfg_attr(test, assert_instr(vpconflictd))]
80pub unsafe fn _mm512_conflict_epi32(a: __m512i) -> __m512i {
81    transmute(vpconflictd(a.as_i32x16()))
82}
83
84/// Test each 32-bit element of a for equality with all other elements in a closer to the least significant bit using writemask k (elements are copied from src when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in dst.
85///
86/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_conflict_epi32&expand=1249)
87#[inline]
88#[target_feature(enable = "avx512cd")]
89#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
90#[cfg_attr(test, assert_instr(vpconflictd))]
91pub unsafe fn _mm512_mask_conflict_epi32(src: __m512i, k: __mmask16, a: __m512i) -> __m512i {
92    let conflict = _mm512_conflict_epi32(a).as_i32x16();
93    transmute(simd_select_bitmask(k, conflict, src.as_i32x16()))
94}
95
96/// Test each 32-bit element of a for equality with all other elements in a closer to the least significant bit using zeromask k (elements are zeroed out when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in dst.
97///
98/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_conflict_epi32&expand=1250)
99#[inline]
100#[target_feature(enable = "avx512cd")]
101#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
102#[cfg_attr(test, assert_instr(vpconflictd))]
103pub unsafe fn _mm512_maskz_conflict_epi32(k: __mmask16, a: __m512i) -> __m512i {
104    let conflict = _mm512_conflict_epi32(a).as_i32x16();
105    transmute(simd_select_bitmask(k, conflict, i32x16::ZERO))
106}
107
108/// Test each 32-bit element of a for equality with all other elements in a closer to the least significant bit. Each element's comparison forms a zero extended bit vector in dst.
109///
110/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_conflict_epi32&expand=1245)
111#[inline]
112#[target_feature(enable = "avx512cd,avx512vl")]
113#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
114#[cfg_attr(test, assert_instr(vpconflictd))]
115pub unsafe fn _mm256_conflict_epi32(a: __m256i) -> __m256i {
116    transmute(vpconflictd256(a.as_i32x8()))
117}
118
119/// Test each 32-bit element of a for equality with all other elements in a closer to the least significant bit using writemask k (elements are copied from src when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in dst.
120///
121/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_conflict_epi32&expand=1246)
122#[inline]
123#[target_feature(enable = "avx512cd,avx512vl")]
124#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
125#[cfg_attr(test, assert_instr(vpconflictd))]
126pub unsafe fn _mm256_mask_conflict_epi32(src: __m256i, k: __mmask8, a: __m256i) -> __m256i {
127    let conflict = _mm256_conflict_epi32(a).as_i32x8();
128    transmute(simd_select_bitmask(k, conflict, src.as_i32x8()))
129}
130
131/// Test each 32-bit element of a for equality with all other elements in a closer to the least significant bit using zeromask k (elements are zeroed out when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in dst.
132///
133/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_conflict_epi32&expand=1247)
134#[inline]
135#[target_feature(enable = "avx512cd,avx512vl")]
136#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
137#[cfg_attr(test, assert_instr(vpconflictd))]
138pub unsafe fn _mm256_maskz_conflict_epi32(k: __mmask8, a: __m256i) -> __m256i {
139    let conflict = _mm256_conflict_epi32(a).as_i32x8();
140    transmute(simd_select_bitmask(k, conflict, i32x8::ZERO))
141}
142
143/// Test each 32-bit element of a for equality with all other elements in a closer to the least significant bit. Each element's comparison forms a zero extended bit vector in dst.
144///
145/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_conflict_epi32&expand=1242)
146#[inline]
147#[target_feature(enable = "avx512cd,avx512vl")]
148#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
149#[cfg_attr(test, assert_instr(vpconflictd))]
150pub unsafe fn _mm_conflict_epi32(a: __m128i) -> __m128i {
151    transmute(vpconflictd128(a.as_i32x4()))
152}
153
154/// Test each 32-bit element of a for equality with all other elements in a closer to the least significant bit using writemask k (elements are copied from src when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in dst.
155///
156/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_conflict_epi32&expand=1243)
157#[inline]
158#[target_feature(enable = "avx512cd,avx512vl")]
159#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
160#[cfg_attr(test, assert_instr(vpconflictd))]
161pub unsafe fn _mm_mask_conflict_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
162    let conflict = _mm_conflict_epi32(a).as_i32x4();
163    transmute(simd_select_bitmask(k, conflict, src.as_i32x4()))
164}
165
166/// Test each 32-bit element of a for equality with all other elements in a closer to the least significant bit using zeromask k (elements are zeroed out when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in dst.
167///
168/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_conflict_epi32&expand=1244)
169#[inline]
170#[target_feature(enable = "avx512cd,avx512vl")]
171#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
172#[cfg_attr(test, assert_instr(vpconflictd))]
173pub unsafe fn _mm_maskz_conflict_epi32(k: __mmask8, a: __m128i) -> __m128i {
174    let conflict = _mm_conflict_epi32(a).as_i32x4();
175    transmute(simd_select_bitmask(k, conflict, i32x4::ZERO))
176}
177
178/// Test each 64-bit element of a for equality with all other elements in a closer to the least significant bit. Each element's comparison forms a zero extended bit vector in dst.
179///
180/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_conflict_epi64&expand=1257)
181#[inline]
182#[target_feature(enable = "avx512cd")]
183#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
184#[cfg_attr(test, assert_instr(vpconflictq))]
185pub unsafe fn _mm512_conflict_epi64(a: __m512i) -> __m512i {
186    transmute(vpconflictq(a.as_i64x8()))
187}
188
189/// Test each 64-bit element of a for equality with all other elements in a closer to the least significant bit using writemask k (elements are copied from src when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in dst.
190///
191/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_conflict_epi64&expand=1258)
192#[inline]
193#[target_feature(enable = "avx512cd")]
194#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
195#[cfg_attr(test, assert_instr(vpconflictq))]
196pub unsafe fn _mm512_mask_conflict_epi64(src: __m512i, k: __mmask8, a: __m512i) -> __m512i {
197    let conflict = _mm512_conflict_epi64(a).as_i64x8();
198    transmute(simd_select_bitmask(k, conflict, src.as_i64x8()))
199}
200
201/// Test each 64-bit element of a for equality with all other elements in a closer to the least significant bit using zeromask k (elements are zeroed out when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in dst.
202///
203/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_conflict_epi64&expand=1259)
204#[inline]
205#[target_feature(enable = "avx512cd")]
206#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
207#[cfg_attr(test, assert_instr(vpconflictq))]
208pub unsafe fn _mm512_maskz_conflict_epi64(k: __mmask8, a: __m512i) -> __m512i {
209    let conflict = _mm512_conflict_epi64(a).as_i64x8();
210    transmute(simd_select_bitmask(k, conflict, i64x8::ZERO))
211}
212
213/// Test each 64-bit element of a for equality with all other elements in a closer to the least significant bit. Each element's comparison forms a zero extended bit vector in dst.
214///
215/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_conflict_epi64&expand=1254)
216#[inline]
217#[target_feature(enable = "avx512cd,avx512vl")]
218#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
219#[cfg_attr(test, assert_instr(vpconflictq))]
220pub unsafe fn _mm256_conflict_epi64(a: __m256i) -> __m256i {
221    transmute(vpconflictq256(a.as_i64x4()))
222}
223
224/// Test each 64-bit element of a for equality with all other elements in a closer to the least significant bit using writemask k (elements are copied from src when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in dst.
225///
226/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_conflict_epi64&expand=1255)
227#[inline]
228#[target_feature(enable = "avx512cd,avx512vl")]
229#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
230#[cfg_attr(test, assert_instr(vpconflictq))]
231pub unsafe fn _mm256_mask_conflict_epi64(src: __m256i, k: __mmask8, a: __m256i) -> __m256i {
232    let conflict = _mm256_conflict_epi64(a).as_i64x4();
233    transmute(simd_select_bitmask(k, conflict, src.as_i64x4()))
234}
235
236/// Test each 64-bit element of a for equality with all other elements in a closer to the least significant bit using zeromask k (elements are zeroed out when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in dst.
237///
238/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_conflict_epi64&expand=1256)
239#[inline]
240#[target_feature(enable = "avx512cd,avx512vl")]
241#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
242#[cfg_attr(test, assert_instr(vpconflictq))]
243pub unsafe fn _mm256_maskz_conflict_epi64(k: __mmask8, a: __m256i) -> __m256i {
244    let conflict = _mm256_conflict_epi64(a).as_i64x4();
245    transmute(simd_select_bitmask(k, conflict, i64x4::ZERO))
246}
247
248/// Test each 64-bit element of a for equality with all other elements in a closer to the least significant bit. Each element's comparison forms a zero extended bit vector in dst.
249///
250/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_conflict_epi64&expand=1251)
251#[inline]
252#[target_feature(enable = "avx512cd,avx512vl")]
253#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
254#[cfg_attr(test, assert_instr(vpconflictq))]
255pub unsafe fn _mm_conflict_epi64(a: __m128i) -> __m128i {
256    transmute(vpconflictq128(a.as_i64x2()))
257}
258
259/// Test each 64-bit element of a for equality with all other elements in a closer to the least significant bit using writemask k (elements are copied from src when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in dst.
260///
261/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_conflict_epi64&expand=1252)
262#[inline]
263#[target_feature(enable = "avx512cd,avx512vl")]
264#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
265#[cfg_attr(test, assert_instr(vpconflictq))]
266pub unsafe fn _mm_mask_conflict_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
267    let conflict = _mm_conflict_epi64(a).as_i64x2();
268    transmute(simd_select_bitmask(k, conflict, src.as_i64x2()))
269}
270
271/// Test each 64-bit element of a for equality with all other elements in a closer to the least significant bit using zeromask k (elements are zeroed out when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in dst.
272///
273/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_conflict_epi64&expand=1253)
274#[inline]
275#[target_feature(enable = "avx512cd,avx512vl")]
276#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
277#[cfg_attr(test, assert_instr(vpconflictq))]
278pub unsafe fn _mm_maskz_conflict_epi64(k: __mmask8, a: __m128i) -> __m128i {
279    let conflict = _mm_conflict_epi64(a).as_i64x2();
280    transmute(simd_select_bitmask(k, conflict, i64x2::ZERO))
281}
282
283/// Counts the number of leading zero bits in each packed 32-bit integer in a, and store the results in dst.
284///
285/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_lzcnt_epi32&expand=3491)
286#[inline]
287#[target_feature(enable = "avx512cd")]
288#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
289#[cfg_attr(test, assert_instr(vplzcntd))]
290pub unsafe fn _mm512_lzcnt_epi32(a: __m512i) -> __m512i {
291    transmute(simd_ctlz(a.as_i32x16()))
292}
293
294/// Counts the number of leading zero bits in each packed 32-bit integer in a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
295///
296/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_lzcnt_epi32&expand=3492)
297#[inline]
298#[target_feature(enable = "avx512cd")]
299#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
300#[cfg_attr(test, assert_instr(vplzcntd))]
301pub unsafe fn _mm512_mask_lzcnt_epi32(src: __m512i, k: __mmask16, a: __m512i) -> __m512i {
302    let zerocount = _mm512_lzcnt_epi32(a).as_i32x16();
303    transmute(simd_select_bitmask(k, zerocount, src.as_i32x16()))
304}
305
306/// Counts the number of leading zero bits in each packed 32-bit integer in a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
307///
308/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_lzcnt_epi32&expand=3493)
309#[inline]
310#[target_feature(enable = "avx512cd")]
311#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
312#[cfg_attr(test, assert_instr(vplzcntd))]
313pub unsafe fn _mm512_maskz_lzcnt_epi32(k: __mmask16, a: __m512i) -> __m512i {
314    let zerocount = _mm512_lzcnt_epi32(a).as_i32x16();
315    transmute(simd_select_bitmask(k, zerocount, i32x16::ZERO))
316}
317
318/// Counts the number of leading zero bits in each packed 32-bit integer in a, and store the results in dst.
319///
320/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_lzcnt_epi32&expand=3488)
321#[inline]
322#[target_feature(enable = "avx512cd,avx512vl")]
323#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
324#[cfg_attr(test, assert_instr(vplzcntd))]
325pub unsafe fn _mm256_lzcnt_epi32(a: __m256i) -> __m256i {
326    transmute(simd_ctlz(a.as_i32x8()))
327}
328
329/// Counts the number of leading zero bits in each packed 32-bit integer in a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
330///
331/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_lzcnt_epi32&expand=3489)
332#[inline]
333#[target_feature(enable = "avx512cd,avx512vl")]
334#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
335#[cfg_attr(test, assert_instr(vplzcntd))]
336pub unsafe fn _mm256_mask_lzcnt_epi32(src: __m256i, k: __mmask8, a: __m256i) -> __m256i {
337    let zerocount = _mm256_lzcnt_epi32(a).as_i32x8();
338    transmute(simd_select_bitmask(k, zerocount, src.as_i32x8()))
339}
340
341/// Counts the number of leading zero bits in each packed 32-bit integer in a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
342///
343/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_lzcnt_epi32&expand=3490)
344#[inline]
345#[target_feature(enable = "avx512cd,avx512vl")]
346#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
347#[cfg_attr(test, assert_instr(vplzcntd))]
348pub unsafe fn _mm256_maskz_lzcnt_epi32(k: __mmask8, a: __m256i) -> __m256i {
349    let zerocount = _mm256_lzcnt_epi32(a).as_i32x8();
350    transmute(simd_select_bitmask(k, zerocount, i32x8::ZERO))
351}
352
353/// Counts the number of leading zero bits in each packed 32-bit integer in a, and store the results in dst.
354///
355/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_lzcnt_epi32&expand=3485)
356#[inline]
357#[target_feature(enable = "avx512cd,avx512vl")]
358#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
359#[cfg_attr(test, assert_instr(vplzcntd))]
360pub unsafe fn _mm_lzcnt_epi32(a: __m128i) -> __m128i {
361    transmute(simd_ctlz(a.as_i32x4()))
362}
363
364/// Counts the number of leading zero bits in each packed 32-bit integer in a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
365///
366/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_lzcnt_epi32&expand=3486)
367#[inline]
368#[target_feature(enable = "avx512cd,avx512vl")]
369#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
370#[cfg_attr(test, assert_instr(vplzcntd))]
371pub unsafe fn _mm_mask_lzcnt_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
372    let zerocount = _mm_lzcnt_epi32(a).as_i32x4();
373    transmute(simd_select_bitmask(k, zerocount, src.as_i32x4()))
374}
375
376/// Counts the number of leading zero bits in each packed 32-bit integer in a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
377///
378/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_lzcnt_epi32&expand=3487)
379#[inline]
380#[target_feature(enable = "avx512cd,avx512vl")]
381#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
382#[cfg_attr(test, assert_instr(vplzcntd))]
383pub unsafe fn _mm_maskz_lzcnt_epi32(k: __mmask8, a: __m128i) -> __m128i {
384    let zerocount = _mm_lzcnt_epi32(a).as_i32x4();
385    transmute(simd_select_bitmask(k, zerocount, i32x4::ZERO))
386}
387
388/// Counts the number of leading zero bits in each packed 64-bit integer in a, and store the results in dst.
389///
390/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_lzcnt_epi64&expand=3500)
391#[inline]
392#[target_feature(enable = "avx512cd")]
393#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
394#[cfg_attr(test, assert_instr(vplzcntq))]
395pub unsafe fn _mm512_lzcnt_epi64(a: __m512i) -> __m512i {
396    transmute(simd_ctlz(a.as_i64x8()))
397}
398
399/// Counts the number of leading zero bits in each packed 64-bit integer in a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
400///
401/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_lzcnt_epi64&expand=3501)
402#[inline]
403#[target_feature(enable = "avx512cd")]
404#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
405#[cfg_attr(test, assert_instr(vplzcntq))]
406pub unsafe fn _mm512_mask_lzcnt_epi64(src: __m512i, k: __mmask8, a: __m512i) -> __m512i {
407    let zerocount = _mm512_lzcnt_epi64(a).as_i64x8();
408    transmute(simd_select_bitmask(k, zerocount, src.as_i64x8()))
409}
410
411/// Counts the number of leading zero bits in each packed 64-bit integer in a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
412///
413/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_lzcnt_epi64&expand=3502)
414#[inline]
415#[target_feature(enable = "avx512cd")]
416#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
417#[cfg_attr(test, assert_instr(vplzcntq))]
418pub unsafe fn _mm512_maskz_lzcnt_epi64(k: __mmask8, a: __m512i) -> __m512i {
419    let zerocount = _mm512_lzcnt_epi64(a).as_i64x8();
420    transmute(simd_select_bitmask(k, zerocount, i64x8::ZERO))
421}
422
423/// Counts the number of leading zero bits in each packed 64-bit integer in a, and store the results in dst.
424///
425/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_lzcnt_epi64&expand=3497)
426#[inline]
427#[target_feature(enable = "avx512cd,avx512vl")]
428#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
429#[cfg_attr(test, assert_instr(vplzcntq))]
430pub unsafe fn _mm256_lzcnt_epi64(a: __m256i) -> __m256i {
431    transmute(simd_ctlz(a.as_i64x4()))
432}
433
434/// Counts the number of leading zero bits in each packed 64-bit integer in a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
435///
436/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_lzcnt_epi64&expand=3498)
437#[inline]
438#[target_feature(enable = "avx512cd,avx512vl")]
439#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
440#[cfg_attr(test, assert_instr(vplzcntq))]
441pub unsafe fn _mm256_mask_lzcnt_epi64(src: __m256i, k: __mmask8, a: __m256i) -> __m256i {
442    let zerocount = _mm256_lzcnt_epi64(a).as_i64x4();
443    transmute(simd_select_bitmask(k, zerocount, src.as_i64x4()))
444}
445
446/// Counts the number of leading zero bits in each packed 64-bit integer in a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
447///
448/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_lzcnt_epi64&expand=3499)
449#[inline]
450#[target_feature(enable = "avx512cd,avx512vl")]
451#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
452#[cfg_attr(test, assert_instr(vplzcntq))]
453pub unsafe fn _mm256_maskz_lzcnt_epi64(k: __mmask8, a: __m256i) -> __m256i {
454    let zerocount = _mm256_lzcnt_epi64(a).as_i64x4();
455    transmute(simd_select_bitmask(k, zerocount, i64x4::ZERO))
456}
457
458/// Counts the number of leading zero bits in each packed 64-bit integer in a, and store the results in dst.
459///
460/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_lzcnt_epi64&expand=3494)
461#[inline]
462#[target_feature(enable = "avx512cd,avx512vl")]
463#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
464#[cfg_attr(test, assert_instr(vplzcntq))]
465pub unsafe fn _mm_lzcnt_epi64(a: __m128i) -> __m128i {
466    transmute(simd_ctlz(a.as_i64x2()))
467}
468
469/// Counts the number of leading zero bits in each packed 64-bit integer in a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
470///
471/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_lzcnt_epi64&expand=3495)
472#[inline]
473#[target_feature(enable = "avx512cd,avx512vl")]
474#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
475#[cfg_attr(test, assert_instr(vplzcntq))]
476pub unsafe fn _mm_mask_lzcnt_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
477    let zerocount = _mm_lzcnt_epi64(a).as_i64x2();
478    transmute(simd_select_bitmask(k, zerocount, src.as_i64x2()))
479}
480
481/// Counts the number of leading zero bits in each packed 64-bit integer in a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
482///
483/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_lzcnt_epi64&expand=3496)
484#[inline]
485#[target_feature(enable = "avx512cd,avx512vl")]
486#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
487#[cfg_attr(test, assert_instr(vplzcntq))]
488pub unsafe fn _mm_maskz_lzcnt_epi64(k: __mmask8, a: __m128i) -> __m128i {
489    let zerocount = _mm_lzcnt_epi64(a).as_i64x2();
490    transmute(simd_select_bitmask(k, zerocount, i64x2::ZERO))
491}
492
493#[allow(improper_ctypes)]
494extern "C" {
495    #[link_name = "llvm.x86.avx512.conflict.d.512"]
496    fn vpconflictd(a: i32x16) -> i32x16;
497    #[link_name = "llvm.x86.avx512.conflict.d.256"]
498    fn vpconflictd256(a: i32x8) -> i32x8;
499    #[link_name = "llvm.x86.avx512.conflict.d.128"]
500    fn vpconflictd128(a: i32x4) -> i32x4;
501
502    #[link_name = "llvm.x86.avx512.conflict.q.512"]
503    fn vpconflictq(a: i64x8) -> i64x8;
504    #[link_name = "llvm.x86.avx512.conflict.q.256"]
505    fn vpconflictq256(a: i64x4) -> i64x4;
506    #[link_name = "llvm.x86.avx512.conflict.q.128"]
507    fn vpconflictq128(a: i64x2) -> i64x2;
508}
509
510#[cfg(test)]
511mod tests {
512
513    use crate::core_arch::x86::*;
514    use stdarch_test::simd_test;
515
516    #[simd_test(enable = "avx512cd")]
517    unsafe fn test_mm512_broadcastmw_epi32() {
518        let a: __mmask16 = 2;
519        let r = _mm512_broadcastmw_epi32(a);
520        let e = _mm512_set1_epi32(2);
521        assert_eq_m512i(r, e);
522    }
523
524    #[simd_test(enable = "avx512cd,avx512vl")]
525    unsafe fn test_mm256_broadcastmw_epi32() {
526        let a: __mmask16 = 2;
527        let r = _mm256_broadcastmw_epi32(a);
528        let e = _mm256_set1_epi32(2);
529        assert_eq_m256i(r, e);
530    }
531
532    #[simd_test(enable = "avx512cd,avx512vl")]
533    unsafe fn test_mm_broadcastmw_epi32() {
534        let a: __mmask16 = 2;
535        let r = _mm_broadcastmw_epi32(a);
536        let e = _mm_set1_epi32(2);
537        assert_eq_m128i(r, e);
538    }
539
540    #[simd_test(enable = "avx512cd")]
541    unsafe fn test_mm512_broadcastmb_epi64() {
542        let a: __mmask8 = 2;
543        let r = _mm512_broadcastmb_epi64(a);
544        let e = _mm512_set1_epi64(2);
545        assert_eq_m512i(r, e);
546    }
547
548    #[simd_test(enable = "avx512cd,avx512vl")]
549    unsafe fn test_mm256_broadcastmb_epi64() {
550        let a: __mmask8 = 2;
551        let r = _mm256_broadcastmb_epi64(a);
552        let e = _mm256_set1_epi64x(2);
553        assert_eq_m256i(r, e);
554    }
555
556    #[simd_test(enable = "avx512cd,avx512vl")]
557    unsafe fn test_mm_broadcastmb_epi64() {
558        let a: __mmask8 = 2;
559        let r = _mm_broadcastmb_epi64(a);
560        let e = _mm_set1_epi64x(2);
561        assert_eq_m128i(r, e);
562    }
563
564    #[simd_test(enable = "avx512cd")]
565    unsafe fn test_mm512_conflict_epi32() {
566        let a = _mm512_set1_epi32(1);
567        let r = _mm512_conflict_epi32(a);
568        let e = _mm512_set_epi32(
569            1 << 14
570                | 1 << 13
571                | 1 << 12
572                | 1 << 11
573                | 1 << 10
574                | 1 << 9
575                | 1 << 8
576                | 1 << 7
577                | 1 << 6
578                | 1 << 5
579                | 1 << 4
580                | 1 << 3
581                | 1 << 2
582                | 1 << 1
583                | 1 << 0,
584            1 << 13
585                | 1 << 12
586                | 1 << 11
587                | 1 << 10
588                | 1 << 9
589                | 1 << 8
590                | 1 << 7
591                | 1 << 6
592                | 1 << 5
593                | 1 << 4
594                | 1 << 3
595                | 1 << 2
596                | 1 << 1
597                | 1 << 0,
598            1 << 12
599                | 1 << 11
600                | 1 << 10
601                | 1 << 9
602                | 1 << 8
603                | 1 << 7
604                | 1 << 6
605                | 1 << 5
606                | 1 << 4
607                | 1 << 3
608                | 1 << 2
609                | 1 << 1
610                | 1 << 0,
611            1 << 11
612                | 1 << 10
613                | 1 << 9
614                | 1 << 8
615                | 1 << 7
616                | 1 << 6
617                | 1 << 5
618                | 1 << 4
619                | 1 << 3
620                | 1 << 2
621                | 1 << 1
622                | 1 << 0,
623            1 << 10
624                | 1 << 9
625                | 1 << 8
626                | 1 << 7
627                | 1 << 6
628                | 1 << 5
629                | 1 << 4
630                | 1 << 3
631                | 1 << 2
632                | 1 << 1
633                | 1 << 0,
634            1 << 9 | 1 << 8 | 1 << 7 | 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
635            1 << 8 | 1 << 7 | 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
636            1 << 7 | 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
637            1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
638            1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
639            1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
640            1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
641            1 << 2 | 1 << 1 | 1 << 0,
642            1 << 1 | 1 << 0,
643            1 << 0,
644            0,
645        );
646        assert_eq_m512i(r, e);
647    }
648
649    #[simd_test(enable = "avx512cd")]
650    unsafe fn test_mm512_mask_conflict_epi32() {
651        let a = _mm512_set1_epi32(1);
652        let r = _mm512_mask_conflict_epi32(a, 0, a);
653        assert_eq_m512i(r, a);
654        let r = _mm512_mask_conflict_epi32(a, 0b11111111_11111111, a);
655        let e = _mm512_set_epi32(
656            1 << 14
657                | 1 << 13
658                | 1 << 12
659                | 1 << 11
660                | 1 << 10
661                | 1 << 9
662                | 1 << 8
663                | 1 << 7
664                | 1 << 6
665                | 1 << 5
666                | 1 << 4
667                | 1 << 3
668                | 1 << 2
669                | 1 << 1
670                | 1 << 0,
671            1 << 13
672                | 1 << 12
673                | 1 << 11
674                | 1 << 10
675                | 1 << 9
676                | 1 << 8
677                | 1 << 7
678                | 1 << 6
679                | 1 << 5
680                | 1 << 4
681                | 1 << 3
682                | 1 << 2
683                | 1 << 1
684                | 1 << 0,
685            1 << 12
686                | 1 << 11
687                | 1 << 10
688                | 1 << 9
689                | 1 << 8
690                | 1 << 7
691                | 1 << 6
692                | 1 << 5
693                | 1 << 4
694                | 1 << 3
695                | 1 << 2
696                | 1 << 1
697                | 1 << 0,
698            1 << 11
699                | 1 << 10
700                | 1 << 9
701                | 1 << 8
702                | 1 << 7
703                | 1 << 6
704                | 1 << 5
705                | 1 << 4
706                | 1 << 3
707                | 1 << 2
708                | 1 << 1
709                | 1 << 0,
710            1 << 10
711                | 1 << 9
712                | 1 << 8
713                | 1 << 7
714                | 1 << 6
715                | 1 << 5
716                | 1 << 4
717                | 1 << 3
718                | 1 << 2
719                | 1 << 1
720                | 1 << 0,
721            1 << 9 | 1 << 8 | 1 << 7 | 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
722            1 << 8 | 1 << 7 | 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
723            1 << 7 | 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
724            1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
725            1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
726            1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
727            1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
728            1 << 2 | 1 << 1 | 1 << 0,
729            1 << 1 | 1 << 0,
730            1 << 0,
731            0,
732        );
733        assert_eq_m512i(r, e);
734    }
735
736    #[simd_test(enable = "avx512cd")]
737    unsafe fn test_mm512_maskz_conflict_epi32() {
738        let a = _mm512_set1_epi32(1);
739        let r = _mm512_maskz_conflict_epi32(0, a);
740        assert_eq_m512i(r, _mm512_setzero_si512());
741        let r = _mm512_maskz_conflict_epi32(0b11111111_11111111, a);
742        let e = _mm512_set_epi32(
743            1 << 14
744                | 1 << 13
745                | 1 << 12
746                | 1 << 11
747                | 1 << 10
748                | 1 << 9
749                | 1 << 8
750                | 1 << 7
751                | 1 << 6
752                | 1 << 5
753                | 1 << 4
754                | 1 << 3
755                | 1 << 2
756                | 1 << 1
757                | 1 << 0,
758            1 << 13
759                | 1 << 12
760                | 1 << 11
761                | 1 << 10
762                | 1 << 9
763                | 1 << 8
764                | 1 << 7
765                | 1 << 6
766                | 1 << 5
767                | 1 << 4
768                | 1 << 3
769                | 1 << 2
770                | 1 << 1
771                | 1 << 0,
772            1 << 12
773                | 1 << 11
774                | 1 << 10
775                | 1 << 9
776                | 1 << 8
777                | 1 << 7
778                | 1 << 6
779                | 1 << 5
780                | 1 << 4
781                | 1 << 3
782                | 1 << 2
783                | 1 << 1
784                | 1 << 0,
785            1 << 11
786                | 1 << 10
787                | 1 << 9
788                | 1 << 8
789                | 1 << 7
790                | 1 << 6
791                | 1 << 5
792                | 1 << 4
793                | 1 << 3
794                | 1 << 2
795                | 1 << 1
796                | 1 << 0,
797            1 << 10
798                | 1 << 9
799                | 1 << 8
800                | 1 << 7
801                | 1 << 6
802                | 1 << 5
803                | 1 << 4
804                | 1 << 3
805                | 1 << 2
806                | 1 << 1
807                | 1 << 0,
808            1 << 9 | 1 << 8 | 1 << 7 | 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
809            1 << 8 | 1 << 7 | 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
810            1 << 7 | 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
811            1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
812            1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
813            1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
814            1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
815            1 << 2 | 1 << 1 | 1 << 0,
816            1 << 1 | 1 << 0,
817            1 << 0,
818            0,
819        );
820        assert_eq_m512i(r, e);
821    }
822
823    #[simd_test(enable = "avx512cd,avx512vl")]
824    unsafe fn test_mm256_conflict_epi32() {
825        let a = _mm256_set1_epi32(1);
826        let r = _mm256_conflict_epi32(a);
827        let e = _mm256_set_epi32(
828            1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
829            1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
830            1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
831            1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
832            1 << 2 | 1 << 1 | 1 << 0,
833            1 << 1 | 1 << 0,
834            1 << 0,
835            0,
836        );
837        assert_eq_m256i(r, e);
838    }
839
840    #[simd_test(enable = "avx512cd,avx512vl")]
841    unsafe fn test_mm256_mask_conflict_epi32() {
842        let a = _mm256_set1_epi32(1);
843        let r = _mm256_mask_conflict_epi32(a, 0, a);
844        assert_eq_m256i(r, a);
845        let r = _mm256_mask_conflict_epi32(a, 0b11111111, a);
846        let e = _mm256_set_epi32(
847            1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
848            1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
849            1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
850            1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
851            1 << 2 | 1 << 1 | 1 << 0,
852            1 << 1 | 1 << 0,
853            1 << 0,
854            0,
855        );
856        assert_eq_m256i(r, e);
857    }
858
859    #[simd_test(enable = "avx512cd,avx512vl")]
860    unsafe fn test_mm256_maskz_conflict_epi32() {
861        let a = _mm256_set1_epi32(1);
862        let r = _mm256_maskz_conflict_epi32(0, a);
863        assert_eq_m256i(r, _mm256_setzero_si256());
864        let r = _mm256_maskz_conflict_epi32(0b11111111, a);
865        let e = _mm256_set_epi32(
866            1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
867            1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
868            1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
869            1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
870            1 << 2 | 1 << 1 | 1 << 0,
871            1 << 1 | 1 << 0,
872            1 << 0,
873            0,
874        );
875        assert_eq_m256i(r, e);
876    }
877
878    #[simd_test(enable = "avx512cd,avx512vl")]
879    unsafe fn test_mm_conflict_epi32() {
880        let a = _mm_set1_epi32(1);
881        let r = _mm_conflict_epi32(a);
882        let e = _mm_set_epi32(1 << 2 | 1 << 1 | 1 << 0, 1 << 1 | 1 << 0, 1 << 0, 0);
883        assert_eq_m128i(r, e);
884    }
885
886    #[simd_test(enable = "avx512cd,avx512vl")]
887    unsafe fn test_mm_mask_conflict_epi32() {
888        let a = _mm_set1_epi32(1);
889        let r = _mm_mask_conflict_epi32(a, 0, a);
890        assert_eq_m128i(r, a);
891        let r = _mm_mask_conflict_epi32(a, 0b00001111, a);
892        let e = _mm_set_epi32(1 << 2 | 1 << 1 | 1 << 0, 1 << 1 | 1 << 0, 1 << 0, 0);
893        assert_eq_m128i(r, e);
894    }
895
896    #[simd_test(enable = "avx512cd,avx512vl")]
897    unsafe fn test_mm_maskz_conflict_epi32() {
898        let a = _mm_set1_epi32(1);
899        let r = _mm_maskz_conflict_epi32(0, a);
900        assert_eq_m128i(r, _mm_setzero_si128());
901        let r = _mm_maskz_conflict_epi32(0b00001111, a);
902        let e = _mm_set_epi32(1 << 2 | 1 << 1 | 1 << 0, 1 << 1 | 1 << 0, 1 << 0, 0);
903        assert_eq_m128i(r, e);
904    }
905
906    #[simd_test(enable = "avx512cd")]
907    unsafe fn test_mm512_conflict_epi64() {
908        let a = _mm512_set1_epi64(1);
909        let r = _mm512_conflict_epi64(a);
910        let e = _mm512_set_epi64(
911            1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
912            1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
913            1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
914            1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
915            1 << 2 | 1 << 1 | 1 << 0,
916            1 << 1 | 1 << 0,
917            1 << 0,
918            0,
919        );
920        assert_eq_m512i(r, e);
921    }
922
923    #[simd_test(enable = "avx512cd")]
924    unsafe fn test_mm512_mask_conflict_epi64() {
925        let a = _mm512_set1_epi64(1);
926        let r = _mm512_mask_conflict_epi64(a, 0, a);
927        assert_eq_m512i(r, a);
928        let r = _mm512_mask_conflict_epi64(a, 0b11111111, a);
929        let e = _mm512_set_epi64(
930            1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
931            1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
932            1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
933            1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
934            1 << 2 | 1 << 1 | 1 << 0,
935            1 << 1 | 1 << 0,
936            1 << 0,
937            0,
938        );
939        assert_eq_m512i(r, e);
940    }
941
942    #[simd_test(enable = "avx512cd")]
943    unsafe fn test_mm512_maskz_conflict_epi64() {
944        let a = _mm512_set1_epi64(1);
945        let r = _mm512_maskz_conflict_epi64(0, a);
946        assert_eq_m512i(r, _mm512_setzero_si512());
947        let r = _mm512_maskz_conflict_epi64(0b11111111, a);
948        let e = _mm512_set_epi64(
949            1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
950            1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
951            1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
952            1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
953            1 << 2 | 1 << 1 | 1 << 0,
954            1 << 1 | 1 << 0,
955            1 << 0,
956            0,
957        );
958        assert_eq_m512i(r, e);
959    }
960
961    #[simd_test(enable = "avx512cd,avx512vl")]
962    unsafe fn test_mm256_conflict_epi64() {
963        let a = _mm256_set1_epi64x(1);
964        let r = _mm256_conflict_epi64(a);
965        let e = _mm256_set_epi64x(1 << 2 | 1 << 1 | 1 << 0, 1 << 1 | 1 << 0, 1 << 0, 0);
966        assert_eq_m256i(r, e);
967    }
968
969    #[simd_test(enable = "avx512cd,avx512vl")]
970    unsafe fn test_mm256_mask_conflict_epi64() {
971        let a = _mm256_set1_epi64x(1);
972        let r = _mm256_mask_conflict_epi64(a, 0, a);
973        assert_eq_m256i(r, a);
974        let r = _mm256_mask_conflict_epi64(a, 0b00001111, a);
975        let e = _mm256_set_epi64x(1 << 2 | 1 << 1 | 1 << 0, 1 << 1 | 1 << 0, 1 << 0, 0);
976        assert_eq_m256i(r, e);
977    }
978
979    #[simd_test(enable = "avx512cd,avx512vl")]
980    unsafe fn test_mm256_maskz_conflict_epi64() {
981        let a = _mm256_set1_epi64x(1);
982        let r = _mm256_maskz_conflict_epi64(0, a);
983        assert_eq_m256i(r, _mm256_setzero_si256());
984        let r = _mm256_maskz_conflict_epi64(0b00001111, a);
985        let e = _mm256_set_epi64x(1 << 2 | 1 << 1 | 1 << 0, 1 << 1 | 1 << 0, 1 << 0, 0);
986        assert_eq_m256i(r, e);
987    }
988
989    #[simd_test(enable = "avx512cd,avx512vl")]
990    unsafe fn test_mm_conflict_epi64() {
991        let a = _mm_set1_epi64x(1);
992        let r = _mm_conflict_epi64(a);
993        let e = _mm_set_epi64x(1 << 0, 0);
994        assert_eq_m128i(r, e);
995    }
996
997    #[simd_test(enable = "avx512cd,avx512vl")]
998    unsafe fn test_mm_mask_conflict_epi64() {
999        let a = _mm_set1_epi64x(1);
1000        let r = _mm_mask_conflict_epi64(a, 0, a);
1001        assert_eq_m128i(r, a);
1002        let r = _mm_mask_conflict_epi64(a, 0b00000011, a);
1003        let e = _mm_set_epi64x(1 << 0, 0);
1004        assert_eq_m128i(r, e);
1005    }
1006
1007    #[simd_test(enable = "avx512cd,avx512vl")]
1008    unsafe fn test_mm_maskz_conflict_epi64() {
1009        let a = _mm_set1_epi64x(1);
1010        let r = _mm_maskz_conflict_epi64(0, a);
1011        assert_eq_m128i(r, _mm_setzero_si128());
1012        let r = _mm_maskz_conflict_epi64(0b00000011, a);
1013        let e = _mm_set_epi64x(1 << 0, 0);
1014        assert_eq_m128i(r, e);
1015    }
1016
1017    #[simd_test(enable = "avx512cd")]
1018    unsafe fn test_mm512_lzcnt_epi32() {
1019        let a = _mm512_set1_epi32(1);
1020        let r = _mm512_lzcnt_epi32(a);
1021        let e = _mm512_set1_epi32(31);
1022        assert_eq_m512i(r, e);
1023    }
1024
1025    #[simd_test(enable = "avx512cd")]
1026    unsafe fn test_mm512_mask_lzcnt_epi32() {
1027        let a = _mm512_set1_epi32(1);
1028        let r = _mm512_mask_lzcnt_epi32(a, 0, a);
1029        assert_eq_m512i(r, a);
1030        let r = _mm512_mask_lzcnt_epi32(a, 0b11111111_11111111, a);
1031        let e = _mm512_set1_epi32(31);
1032        assert_eq_m512i(r, e);
1033    }
1034
1035    #[simd_test(enable = "avx512cd")]
1036    unsafe fn test_mm512_maskz_lzcnt_epi32() {
1037        let a = _mm512_set1_epi32(2);
1038        let r = _mm512_maskz_lzcnt_epi32(0, a);
1039        assert_eq_m512i(r, _mm512_setzero_si512());
1040        let r = _mm512_maskz_lzcnt_epi32(0b11111111_11111111, a);
1041        let e = _mm512_set1_epi32(30);
1042        assert_eq_m512i(r, e);
1043    }
1044
1045    #[simd_test(enable = "avx512cd,avx512vl")]
1046    unsafe fn test_mm256_lzcnt_epi32() {
1047        let a = _mm256_set1_epi32(1);
1048        let r = _mm256_lzcnt_epi32(a);
1049        let e = _mm256_set1_epi32(31);
1050        assert_eq_m256i(r, e);
1051    }
1052
1053    #[simd_test(enable = "avx512cd,avx512vl")]
1054    unsafe fn test_mm256_mask_lzcnt_epi32() {
1055        let a = _mm256_set1_epi32(1);
1056        let r = _mm256_mask_lzcnt_epi32(a, 0, a);
1057        assert_eq_m256i(r, a);
1058        let r = _mm256_mask_lzcnt_epi32(a, 0b11111111, a);
1059        let e = _mm256_set1_epi32(31);
1060        assert_eq_m256i(r, e);
1061    }
1062
1063    #[simd_test(enable = "avx512cd,avx512vl")]
1064    unsafe fn test_mm256_maskz_lzcnt_epi32() {
1065        let a = _mm256_set1_epi32(1);
1066        let r = _mm256_maskz_lzcnt_epi32(0, a);
1067        assert_eq_m256i(r, _mm256_setzero_si256());
1068        let r = _mm256_maskz_lzcnt_epi32(0b11111111, a);
1069        let e = _mm256_set1_epi32(31);
1070        assert_eq_m256i(r, e);
1071    }
1072
1073    #[simd_test(enable = "avx512cd,avx512vl")]
1074    unsafe fn test_mm_lzcnt_epi32() {
1075        let a = _mm_set1_epi32(1);
1076        let r = _mm_lzcnt_epi32(a);
1077        let e = _mm_set1_epi32(31);
1078        assert_eq_m128i(r, e);
1079    }
1080
1081    #[simd_test(enable = "avx512cd,avx512vl")]
1082    unsafe fn test_mm_mask_lzcnt_epi32() {
1083        let a = _mm_set1_epi32(1);
1084        let r = _mm_mask_lzcnt_epi32(a, 0, a);
1085        assert_eq_m128i(r, a);
1086        let r = _mm_mask_lzcnt_epi32(a, 0b00001111, a);
1087        let e = _mm_set1_epi32(31);
1088        assert_eq_m128i(r, e);
1089    }
1090
1091    #[simd_test(enable = "avx512cd,avx512vl")]
1092    unsafe fn test_mm_maskz_lzcnt_epi32() {
1093        let a = _mm_set1_epi32(1);
1094        let r = _mm_maskz_lzcnt_epi32(0, a);
1095        assert_eq_m128i(r, _mm_setzero_si128());
1096        let r = _mm_maskz_lzcnt_epi32(0b00001111, a);
1097        let e = _mm_set1_epi32(31);
1098        assert_eq_m128i(r, e);
1099    }
1100
1101    #[simd_test(enable = "avx512cd")]
1102    unsafe fn test_mm512_lzcnt_epi64() {
1103        let a = _mm512_set1_epi64(1);
1104        let r = _mm512_lzcnt_epi64(a);
1105        let e = _mm512_set1_epi64(63);
1106        assert_eq_m512i(r, e);
1107    }
1108
1109    #[simd_test(enable = "avx512cd")]
1110    unsafe fn test_mm512_mask_lzcnt_epi64() {
1111        let a = _mm512_set1_epi64(1);
1112        let r = _mm512_mask_lzcnt_epi64(a, 0, a);
1113        assert_eq_m512i(r, a);
1114        let r = _mm512_mask_lzcnt_epi64(a, 0b11111111, a);
1115        let e = _mm512_set1_epi64(63);
1116        assert_eq_m512i(r, e);
1117    }
1118
1119    #[simd_test(enable = "avx512cd")]
1120    unsafe fn test_mm512_maskz_lzcnt_epi64() {
1121        let a = _mm512_set1_epi64(2);
1122        let r = _mm512_maskz_lzcnt_epi64(0, a);
1123        assert_eq_m512i(r, _mm512_setzero_si512());
1124        let r = _mm512_maskz_lzcnt_epi64(0b11111111, a);
1125        let e = _mm512_set1_epi64(62);
1126        assert_eq_m512i(r, e);
1127    }
1128
1129    #[simd_test(enable = "avx512cd,avx512vl")]
1130    unsafe fn test_mm256_lzcnt_epi64() {
1131        let a = _mm256_set1_epi64x(1);
1132        let r = _mm256_lzcnt_epi64(a);
1133        let e = _mm256_set1_epi64x(63);
1134        assert_eq_m256i(r, e);
1135    }
1136
1137    #[simd_test(enable = "avx512cd,avx512vl")]
1138    unsafe fn test_mm256_mask_lzcnt_epi64() {
1139        let a = _mm256_set1_epi64x(1);
1140        let r = _mm256_mask_lzcnt_epi64(a, 0, a);
1141        assert_eq_m256i(r, a);
1142        let r = _mm256_mask_lzcnt_epi64(a, 0b00001111, a);
1143        let e = _mm256_set1_epi64x(63);
1144        assert_eq_m256i(r, e);
1145    }
1146
1147    #[simd_test(enable = "avx512cd,avx512vl")]
1148    unsafe fn test_mm256_maskz_lzcnt_epi64() {
1149        let a = _mm256_set1_epi64x(1);
1150        let r = _mm256_maskz_lzcnt_epi64(0, a);
1151        assert_eq_m256i(r, _mm256_setzero_si256());
1152        let r = _mm256_maskz_lzcnt_epi64(0b00001111, a);
1153        let e = _mm256_set1_epi64x(63);
1154        assert_eq_m256i(r, e);
1155    }
1156
1157    #[simd_test(enable = "avx512cd,avx512vl")]
1158    unsafe fn test_mm_lzcnt_epi64() {
1159        let a = _mm_set1_epi64x(1);
1160        let r = _mm_lzcnt_epi64(a);
1161        let e = _mm_set1_epi64x(63);
1162        assert_eq_m128i(r, e);
1163    }
1164
1165    #[simd_test(enable = "avx512cd,avx512vl")]
1166    unsafe fn test_mm_mask_lzcnt_epi64() {
1167        let a = _mm_set1_epi64x(1);
1168        let r = _mm_mask_lzcnt_epi64(a, 0, a);
1169        assert_eq_m128i(r, a);
1170        let r = _mm_mask_lzcnt_epi64(a, 0b00001111, a);
1171        let e = _mm_set1_epi64x(63);
1172        assert_eq_m128i(r, e);
1173    }
1174
1175    #[simd_test(enable = "avx512cd,avx512vl")]
1176    unsafe fn test_mm_maskz_lzcnt_epi64() {
1177        let a = _mm_set1_epi64x(1);
1178        let r = _mm_maskz_lzcnt_epi64(0, a);
1179        assert_eq_m128i(r, _mm_setzero_si128());
1180        let r = _mm_maskz_lzcnt_epi64(0b00001111, a);
1181        let e = _mm_set1_epi64x(63);
1182        assert_eq_m128i(r, e);
1183    }
1184}
core/stdarch/crates/core_arch/src/x86/avx512cd.rs

core/stdarch/crates/core_arch/src/x86/
avx512cd.rs
