1#![allow(non_camel_case_types)]
15
16use crate::{core_arch::simd::*, intrinsics::simd::*, mem, mem::transmute};
17
18#[cfg(test)]
19use stdarch_test::assert_instr;
20
21use super::macros::*;
22
23types! {
24 #![unstable(feature = "stdarch_powerpc", issue = "111145")]
25
26 pub struct vector_signed_char(16 x i8);
28 pub struct vector_unsigned_char(16 x u8);
30
31 pub struct vector_bool_char(16 x i8);
33 pub struct vector_signed_short(8 x i16);
35 pub struct vector_unsigned_short(8 x u16);
37 pub struct vector_bool_short(8 x i16);
39 pub struct vector_signed_int(4 x i32);
42 pub struct vector_unsigned_int(4 x u32);
44 pub struct vector_bool_int(4 x i32);
46 pub struct vector_float(4 x f32);
48}
49
50#[allow(improper_ctypes)]
51unsafe extern "C" {
52 #[link_name = "llvm.ppc.altivec.lvx"]
53 fn lvx(p: *const i8) -> vector_unsigned_int;
54
55 #[link_name = "llvm.ppc.altivec.lvebx"]
56 fn lvebx(p: *const i8) -> vector_signed_char;
57 #[link_name = "llvm.ppc.altivec.lvehx"]
58 fn lvehx(p: *const i8) -> vector_signed_short;
59 #[link_name = "llvm.ppc.altivec.lvewx"]
60 fn lvewx(p: *const i8) -> vector_signed_int;
61
62 #[link_name = "llvm.ppc.altivec.lvxl"]
63 fn lvxl(p: *const i8) -> vector_unsigned_int;
64
65 #[link_name = "llvm.ppc.altivec.stvx"]
66 fn stvx(a: vector_signed_int, p: *const i8);
67
68 #[link_name = "llvm.ppc.altivec.stvebx"]
69 fn stvebx(a: vector_signed_char, p: *const i8);
70 #[link_name = "llvm.ppc.altivec.stvehx"]
71 fn stvehx(a: vector_signed_short, p: *const i8);
72 #[link_name = "llvm.ppc.altivec.stvewx"]
73 fn stvewx(a: vector_signed_int, p: *const i8);
74
75 #[link_name = "llvm.ppc.altivec.stvxl"]
76 fn stvxl(a: vector_signed_int, p: *const i8);
77
78 #[link_name = "llvm.ppc.altivec.vperm"]
79 fn vperm(
80 a: vector_signed_int,
81 b: vector_signed_int,
82 c: vector_unsigned_char,
83 ) -> vector_signed_int;
84 #[link_name = "llvm.ppc.altivec.vmhaddshs"]
85 fn vmhaddshs(
86 a: vector_signed_short,
87 b: vector_signed_short,
88 c: vector_signed_short,
89 ) -> vector_signed_short;
90 #[link_name = "llvm.ppc.altivec.vmhraddshs"]
91 fn vmhraddshs(
92 a: vector_signed_short,
93 b: vector_signed_short,
94 c: vector_signed_short,
95 ) -> vector_signed_short;
96 #[link_name = "llvm.ppc.altivec.vmsumuhs"]
97 fn vmsumuhs(
98 a: vector_unsigned_short,
99 b: vector_unsigned_short,
100 c: vector_unsigned_int,
101 ) -> vector_unsigned_int;
102 #[link_name = "llvm.ppc.altivec.vmsumshs"]
103 fn vmsumshs(
104 a: vector_signed_short,
105 b: vector_signed_short,
106 c: vector_signed_int,
107 ) -> vector_signed_int;
108 #[link_name = "llvm.ppc.altivec.vmsumubm"]
109 fn vmsumubm(
110 a: vector_unsigned_char,
111 b: vector_unsigned_char,
112 c: vector_unsigned_int,
113 ) -> vector_unsigned_int;
114 #[link_name = "llvm.ppc.altivec.vmsummbm"]
115 fn vmsummbm(
116 a: vector_signed_char,
117 b: vector_unsigned_char,
118 c: vector_signed_int,
119 ) -> vector_signed_int;
120 #[link_name = "llvm.ppc.altivec.vmsumuhm"]
121 fn vmsumuhm(
122 a: vector_unsigned_short,
123 b: vector_unsigned_short,
124 c: vector_unsigned_int,
125 ) -> vector_unsigned_int;
126 #[link_name = "llvm.ppc.altivec.vmsumshm"]
127 fn vmsumshm(
128 a: vector_signed_short,
129 b: vector_signed_short,
130 c: vector_signed_int,
131 ) -> vector_signed_int;
132 #[link_name = "llvm.ppc.altivec.vnmsubfp"]
133 fn vnmsubfp(a: vector_float, b: vector_float, c: vector_float) -> vector_float;
134 #[link_name = "llvm.ppc.altivec.vsum2sws"]
135 fn vsum2sws(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int;
136 #[link_name = "llvm.ppc.altivec.vsum4ubs"]
137 fn vsum4ubs(a: vector_unsigned_char, b: vector_unsigned_int) -> vector_unsigned_int;
138 #[link_name = "llvm.ppc.altivec.vsum4sbs"]
139 fn vsum4sbs(a: vector_signed_char, b: vector_signed_int) -> vector_signed_int;
140 #[link_name = "llvm.ppc.altivec.vsum4shs"]
141 fn vsum4shs(a: vector_signed_short, b: vector_signed_int) -> vector_signed_int;
142 #[link_name = "llvm.ppc.altivec.vmuleub"]
143 fn vmuleub(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_short;
144 #[link_name = "llvm.ppc.altivec.vmulesb"]
145 fn vmulesb(a: vector_signed_char, b: vector_signed_char) -> vector_signed_short;
146 #[link_name = "llvm.ppc.altivec.vmuleuh"]
147 fn vmuleuh(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_int;
148 #[link_name = "llvm.ppc.altivec.vmulesh"]
149 fn vmulesh(a: vector_signed_short, b: vector_signed_short) -> vector_signed_int;
150 #[link_name = "llvm.ppc.altivec.vmuloub"]
151 fn vmuloub(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_short;
152 #[link_name = "llvm.ppc.altivec.vmulosb"]
153 fn vmulosb(a: vector_signed_char, b: vector_signed_char) -> vector_signed_short;
154 #[link_name = "llvm.ppc.altivec.vmulouh"]
155 fn vmulouh(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_int;
156 #[link_name = "llvm.ppc.altivec.vmulosh"]
157 fn vmulosh(a: vector_signed_short, b: vector_signed_short) -> vector_signed_int;
158
159 #[link_name = "llvm.smax.v16i8"]
160 fn vmaxsb(a: vector_signed_char, b: vector_signed_char) -> vector_signed_char;
161 #[link_name = "llvm.smax.v8i16"]
162 fn vmaxsh(a: vector_signed_short, b: vector_signed_short) -> vector_signed_short;
163 #[link_name = "llvm.smax.v4i32"]
164 fn vmaxsw(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int;
165
166 #[link_name = "llvm.umax.v16i8"]
167 fn vmaxub(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char;
168 #[link_name = "llvm.umax.v8i16"]
169 fn vmaxuh(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_short;
170 #[link_name = "llvm.umax.v4i32"]
171 fn vmaxuw(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int;
172
173 #[link_name = "llvm.smin.v16i8"]
174 fn vminsb(a: vector_signed_char, b: vector_signed_char) -> vector_signed_char;
175 #[link_name = "llvm.smin.v8i16"]
176 fn vminsh(a: vector_signed_short, b: vector_signed_short) -> vector_signed_short;
177 #[link_name = "llvm.smin.v4i32"]
178 fn vminsw(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int;
179
180 #[link_name = "llvm.umin.v16i8"]
181 fn vminub(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char;
182 #[link_name = "llvm.umin.v8i16"]
183 fn vminuh(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_short;
184 #[link_name = "llvm.umin.v4i32"]
185 fn vminuw(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int;
186
187 #[link_name = "llvm.ppc.altivec.vsubsbs"]
188 fn vsubsbs(a: vector_signed_char, b: vector_signed_char) -> vector_signed_char;
189 #[link_name = "llvm.ppc.altivec.vsubshs"]
190 fn vsubshs(a: vector_signed_short, b: vector_signed_short) -> vector_signed_short;
191 #[link_name = "llvm.ppc.altivec.vsubsws"]
192 fn vsubsws(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int;
193
194 #[link_name = "llvm.ppc.altivec.vsububs"]
195 fn vsububs(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char;
196 #[link_name = "llvm.ppc.altivec.vsubuhs"]
197 fn vsubuhs(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_short;
198 #[link_name = "llvm.ppc.altivec.vsubuws"]
199 fn vsubuws(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int;
200
201 #[link_name = "llvm.ppc.altivec.vsubcuw"]
202 fn vsubcuw(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int;
203
204 #[link_name = "llvm.ppc.altivec.vaddcuw"]
205 fn vaddcuw(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int;
206
207 #[link_name = "llvm.ppc.altivec.vaddsbs"]
208 fn vaddsbs(a: vector_signed_char, b: vector_signed_char) -> vector_signed_char;
209 #[link_name = "llvm.ppc.altivec.vaddshs"]
210 fn vaddshs(a: vector_signed_short, b: vector_signed_short) -> vector_signed_short;
211 #[link_name = "llvm.ppc.altivec.vaddsws"]
212 fn vaddsws(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int;
213
214 #[link_name = "llvm.ppc.altivec.vaddubs"]
215 fn vaddubs(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char;
216 #[link_name = "llvm.ppc.altivec.vadduhs"]
217 fn vadduhs(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_short;
218 #[link_name = "llvm.ppc.altivec.vadduws"]
219 fn vadduws(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int;
220
221 #[link_name = "llvm.ppc.altivec.vavgsb"]
222 fn vavgsb(a: vector_signed_char, b: vector_signed_char) -> vector_signed_char;
223 #[link_name = "llvm.ppc.altivec.vavgsh"]
224 fn vavgsh(a: vector_signed_short, b: vector_signed_short) -> vector_signed_short;
225 #[link_name = "llvm.ppc.altivec.vavgsw"]
226 fn vavgsw(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int;
227
228 #[link_name = "llvm.ppc.altivec.vavgub"]
229 fn vavgub(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char;
230 #[link_name = "llvm.ppc.altivec.vavguh"]
231 fn vavguh(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_short;
232 #[link_name = "llvm.ppc.altivec.vavguw"]
233 fn vavguw(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int;
234
235 #[link_name = "llvm.ppc.altivec.vcmpbfp"]
236 fn vcmpbfp(a: vector_float, b: vector_float) -> vector_signed_int;
237
238 #[link_name = "llvm.ppc.altivec.vcmpequb"]
239 fn vcmpequb(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_bool_char;
240 #[link_name = "llvm.ppc.altivec.vcmpequh"]
241 fn vcmpequh(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_bool_short;
242 #[link_name = "llvm.ppc.altivec.vcmpequw"]
243 fn vcmpequw(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_bool_int;
244
245 #[link_name = "llvm.ppc.altivec.vcmpneb"]
246 fn vcmpneb(a: vector_signed_char, b: vector_signed_char) -> vector_bool_char;
247 #[link_name = "llvm.ppc.altivec.vcmpneh"]
248 fn vcmpneh(a: vector_signed_short, b: vector_signed_short) -> vector_bool_short;
249 #[link_name = "llvm.ppc.altivec.vcmpnew"]
250 fn vcmpnew(a: vector_signed_int, b: vector_signed_int) -> vector_bool_int;
251
252 #[link_name = "llvm.ppc.altivec.vcmpgefp"]
253 fn vcmpgefp(a: vector_float, b: vector_float) -> vector_bool_int;
254
255 #[link_name = "llvm.ppc.altivec.vcmpgtub"]
256 fn vcmpgtub(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_bool_char;
257 #[link_name = "llvm.ppc.altivec.vcmpgtuh"]
258 fn vcmpgtuh(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_bool_short;
259 #[link_name = "llvm.ppc.altivec.vcmpgtuw"]
260 fn vcmpgtuw(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_bool_int;
261
262 #[link_name = "llvm.ppc.altivec.vcmpgtsb"]
263 fn vcmpgtsb(a: vector_signed_char, b: vector_signed_char) -> vector_bool_char;
264 #[link_name = "llvm.ppc.altivec.vcmpgtsh"]
265 fn vcmpgtsh(a: vector_signed_short, b: vector_signed_short) -> vector_bool_short;
266 #[link_name = "llvm.ppc.altivec.vcmpgtsw"]
267 fn vcmpgtsw(a: vector_signed_int, b: vector_signed_int) -> vector_bool_int;
268
269 #[link_name = "llvm.ppc.altivec.vexptefp"]
270 fn vexptefp(a: vector_float) -> vector_float;
271
272 #[link_name = "llvm.ppc.altivec.vcmpequb.p"]
273 fn vcmpequb_p(cr: i32, a: vector_unsigned_char, b: vector_unsigned_char) -> i32;
274 #[link_name = "llvm.ppc.altivec.vcmpequh.p"]
275 fn vcmpequh_p(cr: i32, a: vector_unsigned_short, b: vector_unsigned_short) -> i32;
276 #[link_name = "llvm.ppc.altivec.vcmpequw.p"]
277 fn vcmpequw_p(cr: i32, a: vector_unsigned_int, b: vector_unsigned_int) -> i32;
278
279 #[link_name = "llvm.ppc.altivec.vcmpeqfp.p"]
280 fn vcmpeqfp_p(cr: i32, a: vector_float, b: vector_float) -> i32;
281
282 #[link_name = "llvm.ppc.altivec.vcmpgtub.p"]
283 fn vcmpgtub_p(cr: i32, a: vector_unsigned_char, b: vector_unsigned_char) -> i32;
284 #[link_name = "llvm.ppc.altivec.vcmpgtuh.p"]
285 fn vcmpgtuh_p(cr: i32, a: vector_unsigned_short, b: vector_unsigned_short) -> i32;
286 #[link_name = "llvm.ppc.altivec.vcmpgtuw.p"]
287 fn vcmpgtuw_p(cr: i32, a: vector_unsigned_int, b: vector_unsigned_int) -> i32;
288 #[link_name = "llvm.ppc.altivec.vcmpgtsb.p"]
289 fn vcmpgtsb_p(cr: i32, a: vector_signed_char, b: vector_signed_char) -> i32;
290 #[link_name = "llvm.ppc.altivec.vcmpgtsh.p"]
291 fn vcmpgtsh_p(cr: i32, a: vector_signed_short, b: vector_signed_short) -> i32;
292 #[link_name = "llvm.ppc.altivec.vcmpgtsw.p"]
293 fn vcmpgtsw_p(cr: i32, a: vector_signed_int, b: vector_signed_int) -> i32;
294
295 #[link_name = "llvm.ppc.altivec.vcmpgefp.p"]
296 fn vcmpgefp_p(cr: i32, a: vector_float, b: vector_float) -> i32;
297 #[link_name = "llvm.ppc.altivec.vcmpgtfp.p"]
298 fn vcmpgtfp_p(cr: i32, a: vector_float, b: vector_float) -> i32;
299 #[link_name = "llvm.ppc.altivec.vcmpbfp.p"]
300 fn vcmpbfp_p(cr: i32, a: vector_float, b: vector_float) -> i32;
301
302 #[link_name = "llvm.ppc.altivec.vcfsx"]
303 fn vcfsx(a: vector_signed_int, b: i32) -> vector_float;
304 #[link_name = "llvm.ppc.altivec.vcfux"]
305 fn vcfux(a: vector_unsigned_int, b: i32) -> vector_float;
306
307 #[link_name = "llvm.ppc.altivec.vctsxs"]
308 fn vctsxs(a: vector_float, b: i32) -> vector_signed_int;
309 #[link_name = "llvm.ppc.altivec.vctuxs"]
310 fn vctuxs(a: vector_float, b: i32) -> vector_unsigned_int;
311
312 #[link_name = "llvm.ppc.altivec.vpkshss"]
313 fn vpkshss(a: vector_signed_short, b: vector_signed_short) -> vector_signed_char;
314 #[link_name = "llvm.ppc.altivec.vpkshus"]
315 fn vpkshus(a: vector_signed_short, b: vector_signed_short) -> vector_unsigned_char;
316 #[link_name = "llvm.ppc.altivec.vpkuhus"]
317 fn vpkuhus(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_char;
318 #[link_name = "llvm.ppc.altivec.vpkswss"]
319 fn vpkswss(a: vector_signed_int, b: vector_signed_int) -> vector_signed_short;
320 #[link_name = "llvm.ppc.altivec.vpkswus"]
321 fn vpkswus(a: vector_signed_int, b: vector_signed_int) -> vector_unsigned_short;
322 #[link_name = "llvm.ppc.altivec.vpkuwus"]
323 fn vpkuwus(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_short;
324
325 #[link_name = "llvm.ppc.altivec.vupkhsb"]
326 fn vupkhsb(a: vector_signed_char) -> vector_signed_short;
327 #[link_name = "llvm.ppc.altivec.vupklsb"]
328 fn vupklsb(a: vector_signed_char) -> vector_signed_short;
329
330 #[link_name = "llvm.ppc.altivec.vupkhsh"]
331 fn vupkhsh(a: vector_signed_short) -> vector_signed_int;
332 #[link_name = "llvm.ppc.altivec.vupklsh"]
333 fn vupklsh(a: vector_signed_short) -> vector_signed_int;
334
335 #[link_name = "llvm.ppc.altivec.mfvscr"]
336 fn mfvscr() -> vector_unsigned_short;
337
338 #[link_name = "llvm.ppc.altivec.vlogefp"]
339 fn vlogefp(a: vector_float) -> vector_float;
340
341 #[link_name = "llvm.ppc.altivec.sll"]
342 fn vsl(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int;
343 #[link_name = "llvm.ppc.altivec.slo"]
344 fn vslo(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int;
345
346 #[link_name = "llvm.ppc.altivec.srab"]
347 fn vsrab(a: vector_signed_char, b: vector_unsigned_char) -> vector_signed_char;
348 #[link_name = "llvm.ppc.altivec.srah"]
349 fn vsrah(a: vector_signed_short, b: vector_unsigned_short) -> vector_signed_short;
350 #[link_name = "llvm.ppc.altivec.sraw"]
351 fn vsraw(a: vector_signed_int, b: vector_unsigned_int) -> vector_signed_int;
352
353 #[link_name = "llvm.ppc.altivec.srl"]
354 fn vsr(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int;
355 #[link_name = "llvm.ppc.altivec.sro"]
356 fn vsro(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int;
357
358 #[link_name = "llvm.ppc.altivec.slv"]
359 fn vslv(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char;
360 #[link_name = "llvm.ppc.altivec.srv"]
361 fn vsrv(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char;
362
363 #[link_name = "llvm.fshl.v16i8"]
364 fn fshlb(
365 a: vector_unsigned_char,
366 b: vector_unsigned_char,
367 c: vector_unsigned_char,
368 ) -> vector_unsigned_char;
369 #[link_name = "llvm.fshl.v8i16"]
370 fn fshlh(
371 a: vector_unsigned_short,
372 b: vector_unsigned_short,
373 c: vector_unsigned_short,
374 ) -> vector_unsigned_short;
375 #[link_name = "llvm.fshl.v4i32"]
376 fn fshlw(
377 a: vector_unsigned_int,
378 b: vector_unsigned_int,
379 c: vector_unsigned_int,
380 ) -> vector_unsigned_int;
381
382 #[link_name = "llvm.nearbyint.v4f32"]
383 fn vrfin(a: vector_float) -> vector_float;
384}
385
386impl_from! { i8x16, u8x16, i16x8, u16x8, i32x4, u32x4, f32x4 }
387
388impl_neg! { i8x16 : 0 }
389impl_neg! { i16x8 : 0 }
390impl_neg! { i32x4 : 0 }
391impl_neg! { f32x4 : 0f32 }
392
393#[macro_use]
394mod sealed {
395 use super::*;
396
397 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
398 pub trait VectorInsert {
399 type Scalar;
400 unsafe fn vec_insert<const IDX: u32>(self, s: Self::Scalar) -> Self;
401 }
402
403 const fn idx_in_vec<T, const IDX: u32>() -> u32 {
404 IDX & (16 / crate::mem::size_of::<T>() as u32)
405 }
406
407 macro_rules! impl_vec_insert {
408 ($ty:ident) => {
409 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
410 impl VectorInsert for t_t_l!($ty) {
411 type Scalar = $ty;
412 #[inline]
413 #[target_feature(enable = "altivec")]
414 unsafe fn vec_insert<const IDX: u32>(self, s: Self::Scalar) -> Self {
415 simd_insert(self, const { idx_in_vec::<Self::Scalar, IDX>() }, s)
416 }
417 }
418 };
419 }
420
421 impl_vec_insert! { i8 }
422 impl_vec_insert! { u8 }
423 impl_vec_insert! { i16 }
424 impl_vec_insert! { u16 }
425 impl_vec_insert! { i32 }
426 impl_vec_insert! { u32 }
427 impl_vec_insert! { f32 }
428
429 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
430 pub trait VectorExtract {
431 type Scalar;
432 unsafe fn vec_extract<const IDX: u32>(self) -> Self::Scalar;
433 }
434
435 macro_rules! impl_vec_extract {
436 ($ty:ident) => {
437 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
438 impl VectorExtract for t_t_l!($ty) {
439 type Scalar = $ty;
440 #[inline]
441 #[target_feature(enable = "altivec")]
442 unsafe fn vec_extract<const IDX: u32>(self) -> Self::Scalar {
443 simd_extract(self, const { idx_in_vec::<Self::Scalar, IDX>() })
444 }
445 }
446 };
447 }
448
449 impl_vec_extract! { i8 }
450 impl_vec_extract! { u8 }
451 impl_vec_extract! { i16 }
452 impl_vec_extract! { u16 }
453 impl_vec_extract! { i32 }
454 impl_vec_extract! { u32 }
455 impl_vec_extract! { f32 }
456
457 macro_rules! impl_vec_cmp {
458 ([$Trait:ident $m:ident] ($b:ident, $h:ident, $w:ident)) => {
459 impl_vec_cmp! { [$Trait $m] ($b, $b, $h, $h, $w, $w) }
460 };
461 ([$Trait:ident $m:ident] ($ub:ident, $sb:ident, $uh:ident, $sh:ident, $uw:ident, $sw:ident)) => {
462 impl_vec_trait!{ [$Trait $m] $ub (vector_unsigned_char, vector_unsigned_char) -> vector_bool_char }
463 impl_vec_trait!{ [$Trait $m] $sb (vector_signed_char, vector_signed_char) -> vector_bool_char }
464 impl_vec_trait!{ [$Trait $m] $uh (vector_unsigned_short, vector_unsigned_short) -> vector_bool_short }
465 impl_vec_trait!{ [$Trait $m] $sh (vector_signed_short, vector_signed_short) -> vector_bool_short }
466 impl_vec_trait!{ [$Trait $m] $uw (vector_unsigned_int, vector_unsigned_int) -> vector_bool_int }
467 impl_vec_trait!{ [$Trait $m] $sw (vector_signed_int, vector_signed_int) -> vector_bool_int }
468 }
469 }
470
471 macro_rules! impl_vec_any_all {
472 ([$Trait:ident $m:ident] ($b:ident, $h:ident, $w:ident)) => {
473 impl_vec_any_all! { [$Trait $m] ($b, $b, $h, $h, $w, $w) }
474 };
475 ([$Trait:ident $m:ident] ($ub:ident, $sb:ident, $uh:ident, $sh:ident, $uw:ident, $sw:ident)) => {
476 impl_vec_trait!{ [$Trait $m] $ub (vector_unsigned_char, vector_unsigned_char) -> bool }
477 impl_vec_trait!{ [$Trait $m] $sb (vector_signed_char, vector_signed_char) -> bool }
478 impl_vec_trait!{ [$Trait $m] $uh (vector_unsigned_short, vector_unsigned_short) -> bool }
479 impl_vec_trait!{ [$Trait $m] $sh (vector_signed_short, vector_signed_short) -> bool }
480 impl_vec_trait!{ [$Trait $m] $uw (vector_unsigned_int, vector_unsigned_int) -> bool }
481 impl_vec_trait!{ [$Trait $m] $sw (vector_signed_int, vector_signed_int) -> bool }
482 }
483 }
484
485 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
486 pub trait VectorLd {
487 type Result;
488 unsafe fn vec_ld(self, off: isize) -> Self::Result;
489 unsafe fn vec_ldl(self, off: isize) -> Self::Result;
490 }
491
492 macro_rules! impl_vec_ld {
493 ($fun:ident $fun_lru:ident $ty:ident) => {
494 #[inline]
495 #[target_feature(enable = "altivec")]
496 #[cfg_attr(test, assert_instr(lvx))]
497 pub unsafe fn $fun(off: isize, p: *const $ty) -> t_t_l!($ty) {
498 let addr = (p as *const i8).offset(off);
499 transmute(lvx(addr))
500 }
501
502 #[inline]
503 #[target_feature(enable = "altivec")]
504 #[cfg_attr(test, assert_instr(lvxl))]
505 pub unsafe fn $fun_lru(off: isize, p: *const $ty) -> t_t_l!($ty) {
506 let addr = (p as *const i8).offset(off);
507 transmute(lvxl(addr))
508 }
509
510 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
511 impl VectorLd for *const $ty {
512 type Result = t_t_l!($ty);
513 #[inline]
514 #[target_feature(enable = "altivec")]
515 unsafe fn vec_ld(self, off: isize) -> Self::Result {
516 $fun(off, self)
517 }
518 #[inline]
519 #[target_feature(enable = "altivec")]
520 unsafe fn vec_ldl(self, off: isize) -> Self::Result {
521 $fun_lru(off, self)
522 }
523 }
524 };
525 }
526
527 impl_vec_ld! { vec_ld_u8 vec_ldl_u8 u8 }
528 impl_vec_ld! { vec_ld_i8 vec_ldl_i8 i8 }
529
530 impl_vec_ld! { vec_ld_u16 vec_ldl_u16 u16 }
531 impl_vec_ld! { vec_ld_i16 vec_ldl_i16 i16 }
532
533 impl_vec_ld! { vec_ld_u32 vec_ldl_u32 u32 }
534 impl_vec_ld! { vec_ld_i32 vec_ldl_i32 i32 }
535
536 impl_vec_ld! { vec_ld_f32 vec_ldl_f32 f32 }
537
538 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
539 pub trait VectorLde {
540 type Result;
541 unsafe fn vec_lde(self, a: isize) -> Self::Result;
542 }
543
544 macro_rules! impl_vec_lde {
545 ($fun:ident $instr:ident $ty:ident) => {
546 #[inline]
547 #[target_feature(enable = "altivec")]
548 #[cfg_attr(test, assert_instr($instr))]
549 pub unsafe fn $fun(a: isize, b: *const $ty) -> t_t_l!($ty) {
550 let addr = (b as *const i8).offset(a);
551 transmute($instr(addr))
552 }
553
554 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
555 impl VectorLde for *const $ty {
556 type Result = t_t_l!($ty);
557 #[inline]
558 #[target_feature(enable = "altivec")]
559 unsafe fn vec_lde(self, a: isize) -> Self::Result {
560 $fun(a, self)
561 }
562 }
563 };
564 }
565
566 impl_vec_lde! { vec_lde_u8 lvebx u8 }
567 impl_vec_lde! { vec_lde_i8 lvebx i8 }
568
569 impl_vec_lde! { vec_lde_u16 lvehx u16 }
570 impl_vec_lde! { vec_lde_i16 lvehx i16 }
571
572 impl_vec_lde! { vec_lde_u32 lvewx u32 }
573 impl_vec_lde! { vec_lde_i32 lvewx i32 }
574
575 impl_vec_lde! { vec_lde_f32 lvewx f32 }
576
577 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
578 pub trait VectorSt {
579 type Target;
580 unsafe fn vec_st(self, off: isize, p: Self::Target);
581 unsafe fn vec_stl(self, off: isize, p: Self::Target);
582 }
583
584 macro_rules! impl_vec_st {
585 ($fun:ident $fun_lru:ident $ty:ident) => {
586 #[inline]
587 #[target_feature(enable = "altivec")]
588 #[cfg_attr(test, assert_instr(stvx))]
589 pub unsafe fn $fun(a: t_t_l!($ty), off: isize, p: *const $ty) {
590 let addr = (p as *const i8).offset(off);
591 stvx(transmute(a), addr)
592 }
593
594 #[inline]
595 #[target_feature(enable = "altivec")]
596 #[cfg_attr(test, assert_instr(stvxl))]
597 pub unsafe fn $fun_lru(a: t_t_l!($ty), off: isize, p: *const $ty) {
598 let addr = (p as *const i8).offset(off as isize);
599 stvxl(transmute(a), addr)
600 }
601
602 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
603 impl VectorSt for t_t_l!($ty) {
604 type Target = *const $ty;
605 #[inline]
606 #[target_feature(enable = "altivec")]
607 unsafe fn vec_st(self, off: isize, p: Self::Target) {
608 $fun(self, off, p)
609 }
610 #[inline]
611 #[target_feature(enable = "altivec")]
612 unsafe fn vec_stl(self, off: isize, p: Self::Target) {
613 $fun(self, off, p)
614 }
615 }
616 };
617 }
618
619 impl_vec_st! { vec_st_u8 vec_stl_u8 u8 }
620 impl_vec_st! { vec_st_i8 vec_stl_i8 i8 }
621
622 impl_vec_st! { vec_st_u16 vec_stl_u16 u16 }
623 impl_vec_st! { vec_st_i16 vec_stl_i16 i16 }
624
625 impl_vec_st! { vec_st_u32 vec_stl_u32 u32 }
626 impl_vec_st! { vec_st_i32 vec_stl_i32 i32 }
627
628 impl_vec_st! { vec_st_f32 vec_stl_f32 f32 }
629
630 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
631 pub trait VectorSte {
632 type Target;
633 unsafe fn vec_ste(self, off: isize, p: Self::Target);
634 }
635
636 macro_rules! impl_vec_ste {
637 ($fun:ident $instr:ident $ty:ident) => {
638 #[inline]
639 #[target_feature(enable = "altivec")]
640 #[cfg_attr(test, assert_instr($instr))]
641 pub unsafe fn $fun(a: t_t_l!($ty), off: isize, p: *const $ty) {
642 let addr = (p as *const i8).offset(off);
643 $instr(transmute(a), addr)
644 }
645
646 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
647 impl VectorSte for t_t_l!($ty) {
648 type Target = *const $ty;
649 #[inline]
650 #[target_feature(enable = "altivec")]
651 unsafe fn vec_ste(self, off: isize, p: Self::Target) {
652 $fun(self, off, p)
653 }
654 }
655 };
656 }
657
658 impl_vec_ste! { vec_ste_u8 stvebx u8 }
659 impl_vec_ste! { vec_ste_i8 stvebx i8 }
660
661 impl_vec_ste! { vec_ste_u16 stvehx u16 }
662 impl_vec_ste! { vec_ste_i16 stvehx i16 }
663
664 impl_vec_ste! { vec_ste_u32 stvewx u32 }
665 impl_vec_ste! { vec_ste_i32 stvewx i32 }
666
667 impl_vec_ste! { vec_ste_f32 stvewx f32 }
668
669 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
670 pub trait VectorXl {
671 type Result;
672 unsafe fn vec_xl(self, a: isize) -> Self::Result;
673 }
674
675 macro_rules! impl_vec_xl {
676 ($fun:ident $notpwr9:ident / $pwr9:ident $ty:ident) => {
677 #[inline]
678 #[target_feature(enable = "altivec")]
679 #[cfg_attr(
680 all(test, not(target_feature = "power9-altivec")),
681 assert_instr($notpwr9)
682 )]
683 #[cfg_attr(all(test, target_feature = "power9-altivec"), assert_instr($pwr9))]
684 pub unsafe fn $fun(a: isize, b: *const $ty) -> t_t_l!($ty) {
685 let addr = (b as *const u8).offset(a);
686
687 let mut r = mem::MaybeUninit::uninit();
688
689 crate::ptr::copy_nonoverlapping(
690 addr,
691 r.as_mut_ptr() as *mut u8,
692 mem::size_of::<t_t_l!($ty)>(),
693 );
694
695 r.assume_init()
696 }
697
698 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
699 impl VectorXl for *const $ty {
700 type Result = t_t_l!($ty);
701 #[inline]
702 #[target_feature(enable = "altivec")]
703 unsafe fn vec_xl(self, a: isize) -> Self::Result {
704 $fun(a, self)
705 }
706 }
707 };
708 }
709
710 impl_vec_xl! { vec_xl_i8 lxvd2x / lxv i8 }
711 impl_vec_xl! { vec_xl_u8 lxvd2x / lxv u8 }
712 impl_vec_xl! { vec_xl_i16 lxvd2x / lxv i16 }
713 impl_vec_xl! { vec_xl_u16 lxvd2x / lxv u16 }
714 impl_vec_xl! { vec_xl_i32 lxvd2x / lxv i32 }
715 impl_vec_xl! { vec_xl_u32 lxvd2x / lxv u32 }
716 impl_vec_xl! { vec_xl_f32 lxvd2x / lxv f32 }
717
718 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
719 pub trait VectorXst {
720 type Out;
721 unsafe fn vec_xst(self, a: isize, p: Self::Out);
722 }
723
724 macro_rules! impl_vec_xst {
725 ($fun:ident $notpwr9:ident / $pwr9:ident $ty:ident) => {
726 #[inline]
727 #[target_feature(enable = "altivec")]
728 #[cfg_attr(
729 all(test, not(target_feature = "power9-altivec")),
730 assert_instr($notpwr9)
731 )]
732 #[cfg_attr(all(test, target_feature = "power9-altivec"), assert_instr($pwr9))]
733 pub unsafe fn $fun(s: t_t_l!($ty), a: isize, b: *mut $ty) {
734 let addr = (b as *mut u8).offset(a);
735
736 crate::ptr::copy_nonoverlapping(
737 &s as *const _ as *const u8,
738 addr,
739 mem::size_of::<t_t_l!($ty)>(),
740 );
741 }
742
743 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
744 impl VectorXst for t_t_l!($ty) {
745 type Out = *mut $ty;
746 #[inline]
747 #[target_feature(enable = "altivec")]
748 unsafe fn vec_xst(self, a: isize, b: Self::Out) {
749 $fun(self, a, b)
750 }
751 }
752 };
753 }
754
755 impl_vec_xst! { vec_xst_i8 stxvd2x / stxv i8 }
756 impl_vec_xst! { vec_xst_u8 stxvd2x / stxv u8 }
757 impl_vec_xst! { vec_xst_i16 stxvd2x / stxv i16 }
758 impl_vec_xst! { vec_xst_u16 stxvd2x / stxv u16 }
759 impl_vec_xst! { vec_xst_i32 stxvd2x / stxv i32 }
760 impl_vec_xst! { vec_xst_u32 stxvd2x / stxv u32 }
761 impl_vec_xst! { vec_xst_f32 stxvd2x / stxv f32 }
762
763 test_impl! { vec_floor(a: vector_float) -> vector_float [ simd_floor, vrfim / xvrspim ] }
764
765 test_impl! { vec_vexptefp(a: vector_float) -> vector_float [ vexptefp, vexptefp ] }
766
767 test_impl! { vec_vcmpgtub(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_bool_char [ vcmpgtub, vcmpgtub ] }
768 test_impl! { vec_vcmpgtuh(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_bool_short [ vcmpgtuh, vcmpgtuh ] }
769 test_impl! { vec_vcmpgtuw(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_bool_int [ vcmpgtuw, vcmpgtuw ] }
770
771 test_impl! { vec_vcmpgtsb(a: vector_signed_char, b: vector_signed_char) -> vector_bool_char [ vcmpgtsb, vcmpgtsb ] }
772 test_impl! { vec_vcmpgtsh(a: vector_signed_short, b: vector_signed_short) -> vector_bool_short [ vcmpgtsh, vcmpgtsh ] }
773 test_impl! { vec_vcmpgtsw(a: vector_signed_int, b: vector_signed_int) -> vector_bool_int [ vcmpgtsw, vcmpgtsw ] }
774
775 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
776 pub trait VectorCmpGt<Other> {
777 type Result;
778 unsafe fn vec_cmpgt(self, b: Other) -> Self::Result;
779 }
780
781 impl_vec_cmp! { [VectorCmpGt vec_cmpgt] ( vec_vcmpgtub, vec_vcmpgtsb, vec_vcmpgtuh, vec_vcmpgtsh, vec_vcmpgtuw, vec_vcmpgtsw ) }
782
783 test_impl! { vec_vcmpgefp(a: vector_float, b: vector_float) -> vector_bool_int [ vcmpgefp, vcmpgefp ] }
784
785 test_impl! { vec_vcmpequb(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_bool_char [ vcmpequb, vcmpequb ] }
786 test_impl! { vec_vcmpequh(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_bool_short [ vcmpequh, vcmpequh ] }
787 test_impl! { vec_vcmpequw(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_bool_int [ vcmpequw, vcmpequw ] }
788
789 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
790 pub trait VectorCmpEq<Other> {
791 type Result;
792 unsafe fn vec_cmpeq(self, b: Other) -> Self::Result;
793 }
794
795 impl_vec_cmp! { [VectorCmpEq vec_cmpeq] (vec_vcmpequb, vec_vcmpequh, vec_vcmpequw) }
796
797 macro_rules! impl_cmpne {
798 ($fun:ident ($ty:ident) -> $r:ident $([ $pwr9:ident ])? ) => {
799 #[inline]
800 #[target_feature(enable = "altivec")]
801 $( #[cfg_attr(all(test, target_feature = "power9-altivec"), assert_instr($pwr9))] )?
802 unsafe fn $fun(a: $ty, b: $ty) -> $r {
803 $( if cfg!(target_feature = "power9-altivec") {
804 transmute($pwr9(transmute(a), transmute(b)))
805 } else )? {
806 let zero = transmute(i32x4::new(0, 0, 0, 0));
807 vec_nor(vec_cmpeq(a, b), zero)
808 }
809 }
810 };
811 }
812
813 impl_cmpne! { vec_vcmpneb(vector_signed_char) -> vector_bool_char [ vcmpneb ] }
814 impl_cmpne! { vec_vcmpneh(vector_signed_short) -> vector_bool_short [ vcmpneh ] }
815 impl_cmpne! { vec_vcmpnew(vector_signed_int) -> vector_bool_int [ vcmpnew ] }
816
817 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
818 pub trait VectorCmpNe<Other> {
819 type Result;
820 unsafe fn vec_cmpne(self, b: Other) -> Self::Result;
821 }
822
823 impl_vec_cmp! { [VectorCmpNe vec_cmpne] (vec_vcmpneb, vec_vcmpneh, vec_vcmpnew) }
824
825 test_impl! { vec_vcmpbfp(a: vector_float, b: vector_float) -> vector_signed_int [vcmpbfp, vcmpbfp] }
826
827 #[inline]
828 #[target_feature(enable = "altivec")]
829 #[cfg_attr(test, assert_instr(vcmpequb.))]
830 unsafe fn vcmpequb_all(a: vector_unsigned_char, b: vector_unsigned_char) -> bool {
831 vcmpequb_p(2, a, b) != 0
832 }
833
834 #[inline]
835 #[target_feature(enable = "altivec")]
836 #[cfg_attr(test, assert_instr(vcmpequb.))]
837 unsafe fn vcmpequb_any(a: vector_unsigned_char, b: vector_unsigned_char) -> bool {
838 vcmpequb_p(1, a, b) != 0
839 }
840
841 #[inline]
842 #[target_feature(enable = "altivec")]
843 #[cfg_attr(test, assert_instr(vcmpequh.))]
844 unsafe fn vcmpequh_all(a: vector_unsigned_short, b: vector_unsigned_short) -> bool {
845 vcmpequh_p(2, a, b) != 0
846 }
847
848 #[inline]
849 #[target_feature(enable = "altivec")]
850 #[cfg_attr(test, assert_instr(vcmpequh.))]
851 unsafe fn vcmpequh_any(a: vector_unsigned_short, b: vector_unsigned_short) -> bool {
852 vcmpequh_p(1, a, b) != 0
853 }
854
855 #[inline]
856 #[target_feature(enable = "altivec")]
857 #[cfg_attr(test, assert_instr(vcmpequw.))]
858 unsafe fn vcmpequw_all(a: vector_unsigned_int, b: vector_unsigned_int) -> bool {
859 vcmpequw_p(2, a, b) != 0
860 }
861
862 #[inline]
863 #[target_feature(enable = "altivec")]
864 #[cfg_attr(test, assert_instr(vcmpequw.))]
865 unsafe fn vcmpequw_any(a: vector_unsigned_int, b: vector_unsigned_int) -> bool {
866 vcmpequw_p(1, a, b) != 0
867 }
868
869 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
870 pub trait VectorAllEq<Other> {
871 type Result;
872 unsafe fn vec_all_eq(self, b: Other) -> Self::Result;
873 }
874
875 impl_vec_any_all! { [VectorAllEq vec_all_eq] (vcmpequb_all, vcmpequh_all, vcmpequw_all) }
876
877 #[inline]
879 #[target_feature(enable = "altivec")]
880 #[cfg_attr(test, assert_instr(vcmpeqfp.))]
881 unsafe fn vcmpeqfp_all(a: vector_float, b: vector_float) -> bool {
882 vcmpeqfp_p(2, a, b) != 0
883 }
884
885 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
886 impl VectorAllEq<vector_float> for vector_float {
887 type Result = bool;
888 #[inline]
889 unsafe fn vec_all_eq(self, b: vector_float) -> Self::Result {
890 vcmpeqfp_all(self, b)
891 }
892 }
893
894 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
895 pub trait VectorAnyEq<Other> {
896 type Result;
897 unsafe fn vec_any_eq(self, b: Other) -> Self::Result;
898 }
899
900 impl_vec_any_all! { [VectorAnyEq vec_any_eq] (vcmpequb_any, vcmpequh_any, vcmpequw_any) }
901
902 #[inline]
903 #[target_feature(enable = "altivec")]
904 #[cfg_attr(test, assert_instr(vcmpeqfp.))]
905 unsafe fn vcmpeqfp_any(a: vector_float, b: vector_float) -> bool {
906 vcmpeqfp_p(1, a, b) != 0
907 }
908
909 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
910 impl VectorAnyEq<vector_float> for vector_float {
911 type Result = bool;
912 #[inline]
913 unsafe fn vec_any_eq(self, b: vector_float) -> Self::Result {
914 vcmpeqfp_any(self, b)
915 }
916 }
917
918 #[inline]
921 #[target_feature(enable = "altivec")]
922 #[cfg_attr(test, assert_instr(vcmpgtsb.))]
923 unsafe fn vcmpgesb_all(a: vector_signed_char, b: vector_signed_char) -> bool {
924 vcmpgtsb_p(0, b, a) != 0
925 }
926
927 #[inline]
928 #[target_feature(enable = "altivec")]
929 #[cfg_attr(test, assert_instr(vcmpgtsb.))]
930 unsafe fn vcmpgesb_any(a: vector_signed_char, b: vector_signed_char) -> bool {
931 vcmpgtsb_p(3, b, a) != 0
932 }
933
934 #[inline]
935 #[target_feature(enable = "altivec")]
936 #[cfg_attr(test, assert_instr(vcmpgtsh.))]
937 unsafe fn vcmpgesh_all(a: vector_signed_short, b: vector_signed_short) -> bool {
938 vcmpgtsh_p(0, b, a) != 0
939 }
940
941 #[inline]
942 #[target_feature(enable = "altivec")]
943 #[cfg_attr(test, assert_instr(vcmpgtsh.))]
944 unsafe fn vcmpgesh_any(a: vector_signed_short, b: vector_signed_short) -> bool {
945 vcmpgtsh_p(3, b, a) != 0
946 }
947
948 #[inline]
949 #[target_feature(enable = "altivec")]
950 #[cfg_attr(test, assert_instr(vcmpgtsw.))]
951 unsafe fn vcmpgesw_all(a: vector_signed_int, b: vector_signed_int) -> bool {
952 vcmpgtsw_p(0, b, a) != 0
953 }
954
955 #[inline]
956 #[target_feature(enable = "altivec")]
957 #[cfg_attr(test, assert_instr(vcmpgtsw.))]
958 unsafe fn vcmpgesw_any(a: vector_signed_int, b: vector_signed_int) -> bool {
959 vcmpgtsw_p(3, b, a) != 0
960 }
961
962 #[inline]
963 #[target_feature(enable = "altivec")]
964 #[cfg_attr(test, assert_instr(vcmpgtub.))]
965 unsafe fn vcmpgeub_all(a: vector_unsigned_char, b: vector_unsigned_char) -> bool {
966 vcmpgtub_p(0, b, a) != 0
967 }
968
969 #[inline]
970 #[target_feature(enable = "altivec")]
971 #[cfg_attr(test, assert_instr(vcmpgtub.))]
972 unsafe fn vcmpgeub_any(a: vector_unsigned_char, b: vector_unsigned_char) -> bool {
973 vcmpgtub_p(3, b, a) != 0
974 }
975
976 #[inline]
977 #[target_feature(enable = "altivec")]
978 #[cfg_attr(test, assert_instr(vcmpgtuh.))]
979 unsafe fn vcmpgeuh_all(a: vector_unsigned_short, b: vector_unsigned_short) -> bool {
980 vcmpgtuh_p(0, b, a) != 0
981 }
982
983 #[inline]
984 #[target_feature(enable = "altivec")]
985 #[cfg_attr(test, assert_instr(vcmpgtuh.))]
986 unsafe fn vcmpgeuh_any(a: vector_unsigned_short, b: vector_unsigned_short) -> bool {
987 vcmpgtuh_p(3, b, a) != 0
988 }
989
990 #[inline]
991 #[target_feature(enable = "altivec")]
992 #[cfg_attr(test, assert_instr(vcmpgtuw.))]
993 unsafe fn vcmpgeuw_all(a: vector_unsigned_int, b: vector_unsigned_int) -> bool {
994 vcmpgtuw_p(0, b, a) != 0
995 }
996
997 #[inline]
998 #[target_feature(enable = "altivec")]
999 #[cfg_attr(test, assert_instr(vcmpgtuw.))]
1000 unsafe fn vcmpgeuw_any(a: vector_unsigned_int, b: vector_unsigned_int) -> bool {
1001 vcmpgtuw_p(3, b, a) != 0
1002 }
1003
1004 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1005 pub trait VectorAllGe<Other> {
1006 type Result;
1007 unsafe fn vec_all_ge(self, b: Other) -> Self::Result;
1008 }
1009
1010 impl_vec_any_all! { [VectorAllGe vec_all_ge] (
1011 vcmpgeub_all, vcmpgesb_all,
1012 vcmpgeuh_all, vcmpgesh_all,
1013 vcmpgeuw_all, vcmpgesw_all
1014 ) }
1015
1016 #[inline]
1018 #[target_feature(enable = "altivec")]
1019 #[cfg_attr(test, assert_instr(vcmpgefp.))]
1020 unsafe fn vcmpgefp_all(a: vector_float, b: vector_float) -> bool {
1021 vcmpgefp_p(2, a, b) != 0
1022 }
1023
1024 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1025 impl VectorAllGe<vector_float> for vector_float {
1026 type Result = bool;
1027 #[inline]
1028 unsafe fn vec_all_ge(self, b: vector_float) -> Self::Result {
1029 vcmpgefp_all(self, b)
1030 }
1031 }
1032
1033 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1034 pub trait VectorAnyGe<Other> {
1035 type Result;
1036 unsafe fn vec_any_ge(self, b: Other) -> Self::Result;
1037 }
1038
1039 impl_vec_any_all! { [VectorAnyGe vec_any_ge] (
1040 vcmpgeub_any, vcmpgesb_any,
1041 vcmpgeuh_any, vcmpgesh_any,
1042 vcmpgeuw_any, vcmpgesw_any
1043 ) }
1044
1045 #[inline]
1046 #[target_feature(enable = "altivec")]
1047 #[cfg_attr(test, assert_instr(vcmpgefp.))]
1048 unsafe fn vcmpgefp_any(a: vector_float, b: vector_float) -> bool {
1049 vcmpgefp_p(1, a, b) != 0
1050 }
1051
1052 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1053 impl VectorAnyGe<vector_float> for vector_float {
1054 type Result = bool;
1055 #[inline]
1056 unsafe fn vec_any_ge(self, b: vector_float) -> Self::Result {
1057 vcmpgefp_any(self, b)
1058 }
1059 }
1060
1061 #[inline]
1064 #[target_feature(enable = "altivec")]
1065 #[cfg_attr(test, assert_instr(vcmpgtsb.))]
1066 unsafe fn vcmpgtsb_all(a: vector_signed_char, b: vector_signed_char) -> bool {
1067 vcmpgtsb_p(2, a, b) != 0
1068 }
1069
1070 #[inline]
1071 #[target_feature(enable = "altivec")]
1072 #[cfg_attr(test, assert_instr(vcmpgtsb.))]
1073 unsafe fn vcmpgtsb_any(a: vector_signed_char, b: vector_signed_char) -> bool {
1074 vcmpgtsb_p(1, a, b) != 0
1075 }
1076
1077 #[inline]
1078 #[target_feature(enable = "altivec")]
1079 #[cfg_attr(test, assert_instr(vcmpgtsh.))]
1080 unsafe fn vcmpgtsh_all(a: vector_signed_short, b: vector_signed_short) -> bool {
1081 vcmpgtsh_p(2, a, b) != 0
1082 }
1083
1084 #[inline]
1085 #[target_feature(enable = "altivec")]
1086 #[cfg_attr(test, assert_instr(vcmpgtsh.))]
1087 unsafe fn vcmpgtsh_any(a: vector_signed_short, b: vector_signed_short) -> bool {
1088 vcmpgtsh_p(1, a, b) != 0
1089 }
1090
1091 #[inline]
1092 #[target_feature(enable = "altivec")]
1093 #[cfg_attr(test, assert_instr(vcmpgtsw.))]
1094 unsafe fn vcmpgtsw_all(a: vector_signed_int, b: vector_signed_int) -> bool {
1095 vcmpgtsw_p(2, a, b) != 0
1096 }
1097
1098 #[inline]
1099 #[target_feature(enable = "altivec")]
1100 #[cfg_attr(test, assert_instr(vcmpgtsw.))]
1101 unsafe fn vcmpgtsw_any(a: vector_signed_int, b: vector_signed_int) -> bool {
1102 vcmpgtsw_p(1, a, b) != 0
1103 }
1104
1105 #[inline]
1106 #[target_feature(enable = "altivec")]
1107 #[cfg_attr(test, assert_instr(vcmpgtub.))]
1108 unsafe fn vcmpgtub_all(a: vector_unsigned_char, b: vector_unsigned_char) -> bool {
1109 vcmpgtub_p(2, a, b) != 0
1110 }
1111
1112 #[inline]
1113 #[target_feature(enable = "altivec")]
1114 #[cfg_attr(test, assert_instr(vcmpgtub.))]
1115 unsafe fn vcmpgtub_any(a: vector_unsigned_char, b: vector_unsigned_char) -> bool {
1116 vcmpgtub_p(1, a, b) != 0
1117 }
1118
1119 #[inline]
1120 #[target_feature(enable = "altivec")]
1121 #[cfg_attr(test, assert_instr(vcmpgtuh.))]
1122 unsafe fn vcmpgtuh_all(a: vector_unsigned_short, b: vector_unsigned_short) -> bool {
1123 vcmpgtuh_p(2, a, b) != 0
1124 }
1125
1126 #[inline]
1127 #[target_feature(enable = "altivec")]
1128 #[cfg_attr(test, assert_instr(vcmpgtuh.))]
1129 unsafe fn vcmpgtuh_any(a: vector_unsigned_short, b: vector_unsigned_short) -> bool {
1130 vcmpgtuh_p(1, a, b) != 0
1131 }
1132
1133 #[inline]
1134 #[target_feature(enable = "altivec")]
1135 #[cfg_attr(test, assert_instr(vcmpgtuw.))]
1136 unsafe fn vcmpgtuw_all(a: vector_unsigned_int, b: vector_unsigned_int) -> bool {
1137 vcmpgtuw_p(2, a, b) != 0
1138 }
1139
1140 #[inline]
1141 #[target_feature(enable = "altivec")]
1142 #[cfg_attr(test, assert_instr(vcmpgtuw.))]
1143 unsafe fn vcmpgtuw_any(a: vector_unsigned_int, b: vector_unsigned_int) -> bool {
1144 vcmpgtuw_p(1, a, b) != 0
1145 }
1146
1147 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1148 pub trait VectorAllGt<Other> {
1149 type Result;
1150 unsafe fn vec_all_gt(self, b: Other) -> Self::Result;
1151 }
1152
1153 impl_vec_any_all! { [VectorAllGt vec_all_gt] (
1154 vcmpgtub_all, vcmpgtsb_all,
1155 vcmpgtuh_all, vcmpgtsh_all,
1156 vcmpgtuw_all, vcmpgtsw_all
1157 ) }
1158
1159 #[inline]
1161 #[target_feature(enable = "altivec")]
1162 #[cfg_attr(test, assert_instr(vcmpgtfp.))]
1163 unsafe fn vcmpgtfp_all(a: vector_float, b: vector_float) -> bool {
1164 vcmpgtfp_p(2, a, b) != 0
1165 }
1166
1167 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1168 impl VectorAllGt<vector_float> for vector_float {
1169 type Result = bool;
1170 #[inline]
1171 unsafe fn vec_all_gt(self, b: vector_float) -> Self::Result {
1172 vcmpgtfp_all(self, b)
1173 }
1174 }
1175
1176 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1177 pub trait VectorAnyGt<Other> {
1178 type Result;
1179 unsafe fn vec_any_gt(self, b: Other) -> Self::Result;
1180 }
1181
1182 impl_vec_any_all! { [VectorAnyGt vec_any_gt] (
1183 vcmpgtub_any, vcmpgtsb_any,
1184 vcmpgtuh_any, vcmpgtsh_any,
1185 vcmpgtuw_any, vcmpgtsw_any
1186 ) }
1187
1188 #[inline]
1189 #[target_feature(enable = "altivec")]
1190 #[cfg_attr(test, assert_instr(vcmpgtfp.))]
1191 unsafe fn vcmpgtfp_any(a: vector_float, b: vector_float) -> bool {
1192 vcmpgtfp_p(1, a, b) != 0
1193 }
1194
1195 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1196 impl VectorAnyGt<vector_float> for vector_float {
1197 type Result = bool;
1198 #[inline]
1199 unsafe fn vec_any_gt(self, b: vector_float) -> Self::Result {
1200 vcmpgtfp_any(self, b)
1201 }
1202 }
1203
1204 #[inline]
1207 #[target_feature(enable = "altivec")]
1208 #[cfg_attr(test, assert_instr(vcmpequb.))]
1209 unsafe fn vcmpneub_all(a: vector_unsigned_char, b: vector_unsigned_char) -> bool {
1210 vcmpequb_p(0, a, b) != 0
1211 }
1212
1213 #[inline]
1214 #[target_feature(enable = "altivec")]
1215 #[cfg_attr(test, assert_instr(vcmpequb.))]
1216 unsafe fn vcmpneub_any(a: vector_unsigned_char, b: vector_unsigned_char) -> bool {
1217 vcmpequb_p(3, a, b) != 0
1218 }
1219
1220 #[inline]
1221 #[target_feature(enable = "altivec")]
1222 #[cfg_attr(test, assert_instr(vcmpequh.))]
1223 unsafe fn vcmpneuh_all(a: vector_unsigned_short, b: vector_unsigned_short) -> bool {
1224 vcmpequh_p(0, a, b) != 0
1225 }
1226
1227 #[inline]
1228 #[target_feature(enable = "altivec")]
1229 #[cfg_attr(test, assert_instr(vcmpequh.))]
1230 unsafe fn vcmpneuh_any(a: vector_unsigned_short, b: vector_unsigned_short) -> bool {
1231 vcmpequh_p(3, a, b) != 0
1232 }
1233
1234 #[inline]
1235 #[target_feature(enable = "altivec")]
1236 #[cfg_attr(test, assert_instr(vcmpequw.))]
1237 unsafe fn vcmpneuw_all(a: vector_unsigned_int, b: vector_unsigned_int) -> bool {
1238 vcmpequw_p(0, a, b) != 0
1239 }
1240
1241 #[inline]
1242 #[target_feature(enable = "altivec")]
1243 #[cfg_attr(test, assert_instr(vcmpequw.))]
1244 unsafe fn vcmpneuw_any(a: vector_unsigned_int, b: vector_unsigned_int) -> bool {
1245 vcmpequw_p(3, a, b) != 0
1246 }
1247
1248 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1249 pub trait VectorAllNe<Other> {
1250 type Result;
1251 unsafe fn vec_all_ne(self, b: Other) -> Self::Result;
1252 }
1253
1254 impl_vec_any_all! { [VectorAllNe vec_all_ne] (vcmpneub_all, vcmpneuh_all, vcmpneuw_all) }
1255
1256 #[inline]
1258 #[target_feature(enable = "altivec")]
1259 #[cfg_attr(test, assert_instr(vcmpeqfp.))]
1260 unsafe fn vcmpnefp_all(a: vector_float, b: vector_float) -> bool {
1261 vcmpeqfp_p(0, a, b) != 0
1262 }
1263
1264 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1265 impl VectorAllNe<vector_float> for vector_float {
1266 type Result = bool;
1267 #[inline]
1268 unsafe fn vec_all_ne(self, b: vector_float) -> Self::Result {
1269 vcmpnefp_all(self, b)
1270 }
1271 }
1272
1273 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1274 pub trait VectorAnyNe<Other> {
1275 type Result;
1276 unsafe fn vec_any_ne(self, b: Other) -> Self::Result;
1277 }
1278
1279 impl_vec_any_all! { [VectorAnyNe vec_any_ne] (vcmpneub_any, vcmpneuh_any, vcmpneuw_any) }
1280
1281 #[inline]
1282 #[target_feature(enable = "altivec")]
1283 #[cfg_attr(test, assert_instr(vcmpeqfp.))]
1284 unsafe fn vcmpnefp_any(a: vector_float, b: vector_float) -> bool {
1285 vcmpeqfp_p(3, a, b) != 0
1286 }
1287
1288 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1289 impl VectorAnyNe<vector_float> for vector_float {
1290 type Result = bool;
1291 #[inline]
1292 unsafe fn vec_any_ne(self, b: vector_float) -> Self::Result {
1293 vcmpnefp_any(self, b)
1294 }
1295 }
1296
1297 test_impl! { vec_vceil(a: vector_float) -> vector_float [simd_ceil, vrfip / xvrspip ] }
1298
1299 test_impl! { vec_vavgsb(a: vector_signed_char, b: vector_signed_char) -> vector_signed_char [ vavgsb, vavgsb ] }
1300 test_impl! { vec_vavgsh(a: vector_signed_short, b: vector_signed_short) -> vector_signed_short [ vavgsh, vavgsh ] }
1301 test_impl! { vec_vavgsw(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int [ vavgsw, vavgsw ] }
1302 test_impl! { vec_vavgub(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char [ vavgub, vavgub ] }
1303 test_impl! { vec_vavguh(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_short [ vavguh, vavguh ] }
1304 test_impl! { vec_vavguw(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int [ vavguw, vavguw ] }
1305
1306 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1307 pub trait VectorAvg<Other> {
1308 type Result;
1309 unsafe fn vec_avg(self, b: Other) -> Self::Result;
1310 }
1311
1312 impl_vec_trait! { [VectorAvg vec_avg] 2 (vec_vavgub, vec_vavgsb, vec_vavguh, vec_vavgsh, vec_vavguw, vec_vavgsw) }
1313
1314 #[inline]
1315 #[target_feature(enable = "altivec")]
1316 #[cfg_attr(all(test, not(target_feature = "vsx")), assert_instr(vandc))]
1317 #[cfg_attr(all(test, target_feature = "vsx"), assert_instr(xxlandc))]
1318 unsafe fn andc(a: vector_signed_char, b: vector_signed_char) -> vector_signed_char {
1319 let a = transmute(a);
1320 let b = transmute(b);
1321 transmute(simd_and(simd_xor(u8x16::splat(0xff), b), a))
1322 }
1323
1324 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1325 pub trait VectorAndc<Other> {
1326 type Result;
1327 unsafe fn vec_andc(self, b: Other) -> Self::Result;
1328 }
1329
1330 impl_vec_trait! { [VectorAndc vec_andc]+ 2b (andc) }
1331
1332 #[inline]
1333 #[target_feature(enable = "altivec")]
1334 #[cfg_attr(all(test, not(target_feature = "vsx")), assert_instr(vorc))]
1335 #[cfg_attr(all(test, target_feature = "vsx"), assert_instr(xxlorc))]
1336 unsafe fn orc(a: vector_signed_char, b: vector_signed_char) -> vector_signed_char {
1337 let a = transmute(a);
1338 let b = transmute(b);
1339 transmute(simd_or(simd_xor(u8x16::splat(0xff), b), a))
1340 }
1341
1342 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1343 pub trait VectorOrc<Other> {
1344 type Result;
1345 unsafe fn vec_orc(self, b: Other) -> Self::Result;
1346 }
1347
1348 impl_vec_trait! { [VectorOrc vec_orc]+ 2b (orc) }
1349
1350 test_impl! { vec_vand(a: vector_signed_char, b: vector_signed_char) -> vector_signed_char [ simd_and, vand / xxland ] }
1351
1352 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1353 pub trait VectorAnd<Other> {
1354 type Result;
1355 unsafe fn vec_and(self, b: Other) -> Self::Result;
1356 }
1357
1358 impl_vec_trait! { [VectorAnd vec_and] ~(simd_and) }
1359
1360 test_impl! { vec_vaddsbs(a: vector_signed_char, b: vector_signed_char) -> vector_signed_char [ vaddsbs, vaddsbs ] }
1361 test_impl! { vec_vaddshs(a: vector_signed_short, b: vector_signed_short) -> vector_signed_short [ vaddshs, vaddshs ] }
1362 test_impl! { vec_vaddsws(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int [ vaddsws, vaddsws ] }
1363 test_impl! { vec_vaddubs(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char [ vaddubs, vaddubs ] }
1364 test_impl! { vec_vadduhs(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_short [ vadduhs, vadduhs ] }
1365 test_impl! { vec_vadduws(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int [ vadduws, vadduws ] }
1366
1367 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1368 pub trait VectorAdds<Other> {
1369 type Result;
1370 unsafe fn vec_adds(self, b: Other) -> Self::Result;
1371 }
1372
1373 impl_vec_trait! { [VectorAdds vec_adds] ~(vaddubs, vaddsbs, vadduhs, vaddshs, vadduws, vaddsws) }
1374
1375 test_impl! { vec_vaddcuw(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int [vaddcuw, vaddcuw] }
1376
1377 test_impl! { vec_vsubsbs(a: vector_signed_char, b: vector_signed_char) -> vector_signed_char [ vsubsbs, vsubsbs ] }
1378 test_impl! { vec_vsubshs(a: vector_signed_short, b: vector_signed_short) -> vector_signed_short [ vsubshs, vsubshs ] }
1379 test_impl! { vec_vsubsws(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int [ vsubsws, vsubsws ] }
1380 test_impl! { vec_vsububs(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char [ vsububs, vsububs ] }
1381 test_impl! { vec_vsubuhs(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_short [ vsubuhs, vsubuhs ] }
1382 test_impl! { vec_vsubuws(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int [ vsubuws, vsubuws ] }
1383
1384 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1385 pub trait VectorSubs<Other> {
1386 type Result;
1387 unsafe fn vec_subs(self, b: Other) -> Self::Result;
1388 }
1389
1390 impl_vec_trait! { [VectorSubs vec_subs] ~(vsububs, vsubsbs, vsubuhs, vsubshs, vsubuws, vsubsws) }
1391
1392 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1393 pub trait VectorAbs {
1394 unsafe fn vec_abs(self) -> Self;
1395 }
1396
1397 macro_rules! impl_abs {
1398 ($name:ident, $ty: ident) => {
1399 #[inline]
1400 #[target_feature(enable = "altivec")]
1401 unsafe fn $name(v: s_t_l!($ty)) -> s_t_l!($ty) {
1402 v.vec_max(-v)
1403 }
1404
1405 impl_vec_trait! { [VectorAbs vec_abs] $name (s_t_l!($ty)) }
1406 };
1407 }
1408
1409 impl_abs! { vec_abs_i8, i8x16 }
1410 impl_abs! { vec_abs_i16, i16x8 }
1411 impl_abs! { vec_abs_i32, i32x4 }
1412
1413 #[inline]
1414 #[target_feature(enable = "altivec")]
1415 unsafe fn vec_abs_f32(v: vector_float) -> vector_float {
1416 let v: u32x4 = transmute(v);
1417
1418 transmute(simd_and(v, u32x4::splat(0x7FFFFFFF)))
1419 }
1420
1421 impl_vec_trait! { [VectorAbs vec_abs] vec_abs_f32 (vector_float) }
1422
1423 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1424 pub trait VectorAbss {
1425 unsafe fn vec_abss(self) -> Self;
1426 }
1427
1428 macro_rules! impl_abss {
1429 ($name:ident, $ty: ident) => {
1430 #[inline]
1431 #[target_feature(enable = "altivec")]
1432 unsafe fn $name(v: s_t_l!($ty)) -> s_t_l!($ty) {
1433 let zero: s_t_l!($ty) = transmute(0u8.vec_splats());
1434 v.vec_max(zero.vec_subs(v))
1435 }
1436
1437 impl_vec_trait! { [VectorAbss vec_abss] $name (s_t_l!($ty)) }
1438 };
1439 }
1440
1441 impl_abss! { vec_abss_i8, i8x16 }
1442 impl_abss! { vec_abss_i16, i16x8 }
1443 impl_abss! { vec_abss_i32, i32x4 }
1444
1445 #[inline]
1446 #[target_feature(enable = "altivec")]
1447 #[cfg_attr(test, assert_instr(vspltb, IMM4 = 15))]
1448 unsafe fn vspltb<const IMM4: u32>(a: vector_signed_char) -> vector_signed_char {
1449 static_assert_uimm_bits!(IMM4, 4);
1450 simd_shuffle(a, a, const { u32x16::from_array([IMM4; 16]) })
1451 }
1452
1453 #[inline]
1454 #[target_feature(enable = "altivec")]
1455 #[cfg_attr(test, assert_instr(vsplth, IMM3 = 7))]
1456 unsafe fn vsplth<const IMM3: u32>(a: vector_signed_short) -> vector_signed_short {
1457 static_assert_uimm_bits!(IMM3, 3);
1458 simd_shuffle(a, a, const { u32x8::from_array([IMM3; 8]) })
1459 }
1460
1461 #[inline]
1462 #[target_feature(enable = "altivec")]
1463 #[cfg_attr(all(test, not(target_feature = "vsx")), assert_instr(vspltw, IMM2 = 3))]
1464 #[cfg_attr(all(test, target_feature = "vsx"), assert_instr(xxspltw, IMM2 = 3))]
1465 unsafe fn vspltw<const IMM2: u32>(a: vector_signed_int) -> vector_signed_int {
1466 static_assert_uimm_bits!(IMM2, 2);
1467 simd_shuffle(a, a, const { u32x4::from_array([IMM2; 4]) })
1468 }
1469
1470 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1471 pub trait VectorSplat {
1472 unsafe fn vec_splat<const IMM: u32>(self) -> Self;
1473 }
1474
1475 macro_rules! impl_vec_splat {
1476 ($ty:ty, $fun:ident) => {
1477 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1478 impl VectorSplat for $ty {
1479 #[inline]
1480 #[target_feature(enable = "altivec")]
1481 unsafe fn vec_splat<const IMM: u32>(self) -> Self {
1482 transmute($fun::<IMM>(transmute(self)))
1483 }
1484 }
1485 };
1486 }
1487
1488 impl_vec_splat! { vector_signed_char, vspltb }
1489 impl_vec_splat! { vector_unsigned_char, vspltb }
1490 impl_vec_splat! { vector_bool_char, vspltb }
1491 impl_vec_splat! { vector_signed_short, vsplth }
1492 impl_vec_splat! { vector_unsigned_short, vsplth }
1493 impl_vec_splat! { vector_bool_short, vsplth }
1494 impl_vec_splat! { vector_signed_int, vspltw }
1495 impl_vec_splat! { vector_unsigned_int, vspltw }
1496 impl_vec_splat! { vector_bool_int, vspltw }
1497
1498 macro_rules! splat {
1499 ($name:ident, $v:ident, $r:ident [$instr_altivec:ident / $instr_pwr9:ident, $doc:literal]) => {
1500 #[doc = $doc]
1501 #[inline]
1502 #[target_feature(enable = "altivec")]
1503 #[cfg_attr(
1504 all(test, not(target_feature = "vsx")),
1505 assert_instr($instr_altivec, IMM5 = 1)
1506 )]
1507 #[cfg_attr(
1508 all(test, target_feature = "power9-vector"),
1509 assert_instr($instr_pwr9, IMM5 = 1)
1510 )]
1511 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1512 pub unsafe fn $name<const IMM5: i8>() -> s_t_l!($r) {
1513 static_assert_simm_bits!(IMM5, 5);
1514 transmute($r::splat(IMM5 as $v))
1515 }
1516 };
1517 ($name:ident, $v:ident, $r:ident [$instr:ident, $doc:literal]) => {
1518 splat! { $name, $v, $r [$instr / $instr, $doc] }
1519 };
1520 }
1521
1522 macro_rules! splats {
1523 ($name:ident, $v:ident, $r:ident) => {
1524 #[inline]
1525 #[target_feature(enable = "altivec")]
1526 unsafe fn $name(v: $v) -> s_t_l!($r) {
1527 transmute($r::splat(v))
1528 }
1529 };
1530 }
1531
1532 splats! { splats_u8, u8, u8x16 }
1533 splats! { splats_u16, u16, u16x8 }
1534 splats! { splats_u32, u32, u32x4 }
1535 splats! { splats_i8, i8, i8x16 }
1536 splats! { splats_i16, i16, i16x8 }
1537 splats! { splats_i32, i32, i32x4 }
1538 splats! { splats_f32, f32, f32x4 }
1539
1540 test_impl! { vec_splats_u8 (v: u8) -> vector_unsigned_char [splats_u8, vspltb] }
1541 test_impl! { vec_splats_u16 (v: u16) -> vector_unsigned_short [splats_u16, vsplth] }
1542 test_impl! { vec_splats_u32 (v: u32) -> vector_unsigned_int [splats_u32, vspltw / xxspltw / mtvsrws] }
1543 test_impl! { vec_splats_i8 (v: i8) -> vector_signed_char [splats_i8, vspltb] }
1544 test_impl! { vec_splats_i16 (v: i16) -> vector_signed_short [splats_i16, vsplth] }
1545 test_impl! { vec_splats_i32 (v: i32) -> vector_signed_int [splats_i32, vspltw / xxspltw / mtvsrws] }
1546 test_impl! { vec_splats_f32 (v: f32) -> vector_float [splats_f32, vspltw / xxspltw / mtvsrws] }
1547
1548 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1549 pub trait VectorSplats {
1550 type Result;
1551 unsafe fn vec_splats(self) -> Self::Result;
1552 }
1553
1554 macro_rules! impl_vec_splats {
1555 ($(($fn:ident ($ty:ty) -> $r:ty)),*) => {
1556 $(
1557 impl_vec_trait!{ [VectorSplats vec_splats] $fn ($ty) -> $r }
1558 )*
1559 }
1560 }
1561
1562 impl_vec_splats! {
1563 (vec_splats_u8 (u8) -> vector_unsigned_char),
1564 (vec_splats_i8 (i8) -> vector_signed_char),
1565 (vec_splats_u16 (u16) -> vector_unsigned_short),
1566 (vec_splats_i16 (i16) -> vector_signed_short),
1567 (vec_splats_u32 (u32) -> vector_unsigned_int),
1568 (vec_splats_i32 (i32) -> vector_signed_int),
1569 (vec_splats_f32 (f32) -> vector_float)
1570 }
1571
1572 test_impl! { vec_vsububm (a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char [simd_sub, vsububm] }
1573 test_impl! { vec_vsubuhm (a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_short [simd_sub, vsubuhm] }
1574 test_impl! { vec_vsubuwm (a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int [simd_sub, vsubuwm] }
1575
1576 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1577 pub trait VectorSub<Other> {
1578 type Result;
1579 unsafe fn vec_sub(self, b: Other) -> Self::Result;
1580 }
1581
1582 impl_vec_trait! { [VectorSub vec_sub] ~(simd_sub, simd_sub, simd_sub, simd_sub, simd_sub, simd_sub) }
1583 impl_vec_trait! { [VectorSub vec_sub] simd_sub(vector_float, vector_float) -> vector_float }
1584
1585 test_impl! { vec_vsubcuw (a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int [vsubcuw, vsubcuw] }
1586
1587 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1588 pub trait VectorSubc<Other> {
1589 type Result;
1590 unsafe fn vec_subc(self, b: Other) -> Self::Result;
1591 }
1592
1593 impl_vec_trait! {[VectorSubc vec_subc]+ vec_vsubcuw(vector_unsigned_int, vector_unsigned_int) -> vector_unsigned_int }
1594 impl_vec_trait! {[VectorSubc vec_subc]+ vec_vsubcuw(vector_signed_int, vector_signed_int) -> vector_signed_int }
1595
1596 test_impl! { vec_vminsb (a: vector_signed_char, b: vector_signed_char) -> vector_signed_char [vminsb, vminsb] }
1597 test_impl! { vec_vminsh (a: vector_signed_short, b: vector_signed_short) -> vector_signed_short [vminsh, vminsh] }
1598 test_impl! { vec_vminsw (a: vector_signed_int, b: vector_signed_int) -> vector_signed_int [vminsw, vminsw] }
1599
1600 test_impl! { vec_vminub (a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char [vminub, vminub] }
1601 test_impl! { vec_vminuh (a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_short [vminuh, vminuh] }
1602 test_impl! { vec_vminuw (a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int [vminuw, vminuw] }
1603
1604 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1605 pub trait VectorMin<Other> {
1606 type Result;
1607 unsafe fn vec_min(self, b: Other) -> Self::Result;
1608 }
1609
1610 impl_vec_trait! { [VectorMin vec_min] ~(vminub, vminsb, vminuh, vminsh, vminuw, vminsw) }
1611
1612 test_impl! { vec_vmaxsb (a: vector_signed_char, b: vector_signed_char) -> vector_signed_char [vmaxsb, vmaxsb] }
1613 test_impl! { vec_vmaxsh (a: vector_signed_short, b: vector_signed_short) -> vector_signed_short [vmaxsh, vmaxsh] }
1614 test_impl! { vec_vmaxsw (a: vector_signed_int, b: vector_signed_int) -> vector_signed_int [vmaxsw, vmaxsw] }
1615
1616 test_impl! { vec_vmaxub (a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char [vmaxub, vmaxub] }
1617 test_impl! { vec_vmaxuh (a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_short [vmaxuh, vmaxuh] }
1618 test_impl! { vec_vmaxuw (a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int [vmaxuw, vmaxuw] }
1619
1620 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1621 pub trait VectorMax<Other> {
1622 type Result;
1623 unsafe fn vec_max(self, b: Other) -> Self::Result;
1624 }
1625
1626 impl_vec_trait! { [VectorMax vec_max] ~(vmaxub, vmaxsb, vmaxuh, vmaxsh, vmaxuw, vmaxsw) }
1627
1628 #[inline]
1629 #[target_feature(enable = "altivec")]
1630 #[cfg_attr(test, assert_instr(vmuleub))]
1631 unsafe fn vec_vmuleub(
1632 a: vector_unsigned_char,
1633 b: vector_unsigned_char,
1634 ) -> vector_unsigned_short {
1635 vmuleub(a, b)
1636 }
1637 #[inline]
1638 #[target_feature(enable = "altivec")]
1639 #[cfg_attr(test, assert_instr(vmulesb))]
1640 unsafe fn vec_vmulesb(a: vector_signed_char, b: vector_signed_char) -> vector_signed_short {
1641 vmulesb(a, b)
1642 }
1643 #[inline]
1644 #[target_feature(enable = "altivec")]
1645 #[cfg_attr(test, assert_instr(vmuleuh))]
1646 unsafe fn vec_vmuleuh(
1647 a: vector_unsigned_short,
1648 b: vector_unsigned_short,
1649 ) -> vector_unsigned_int {
1650 vmuleuh(a, b)
1651 }
1652 #[inline]
1653 #[target_feature(enable = "altivec")]
1654 #[cfg_attr(test, assert_instr(vmulesh))]
1655 unsafe fn vec_vmulesh(a: vector_signed_short, b: vector_signed_short) -> vector_signed_int {
1656 vmulesh(a, b)
1657 }
1658
1659 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1660 pub trait VectorMul {
1661 unsafe fn vec_mul(self, b: Self) -> Self;
1662 }
1663
1664 #[inline]
1665 #[target_feature(enable = "altivec")]
1666 #[cfg_attr(test, assert_instr(vmuluwm))]
1667 unsafe fn vec_vmuluwm(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int {
1668 transmute(simd_mul::<i32x4>(transmute(a), transmute(b)))
1669 }
1670
1671 #[inline]
1672 #[target_feature(enable = "altivec")]
1673 #[cfg_attr(test, assert_instr(xvmulsp))]
1674 unsafe fn vec_xvmulsp(a: vector_float, b: vector_float) -> vector_float {
1675 transmute(simd_mul::<f32x4>(transmute(a), transmute(b)))
1676 }
1677
1678 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1679 impl VectorMul for vector_signed_int {
1680 #[inline]
1681 #[target_feature(enable = "altivec")]
1682 unsafe fn vec_mul(self, b: Self) -> Self {
1683 vec_vmuluwm(self, b)
1684 }
1685 }
1686
1687 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1688 impl VectorMul for vector_unsigned_int {
1689 #[inline]
1690 #[target_feature(enable = "altivec")]
1691 unsafe fn vec_mul(self, b: Self) -> Self {
1692 transmute(simd_mul::<u32x4>(transmute(self), transmute(b)))
1693 }
1694 }
1695
1696 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1697 impl VectorMul for vector_float {
1698 #[inline]
1699 #[target_feature(enable = "altivec")]
1700 unsafe fn vec_mul(self, b: Self) -> Self {
1701 vec_xvmulsp(self, b)
1702 }
1703 }
1704
1705 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1706 pub trait VectorMule<Result> {
1707 unsafe fn vec_mule(self, b: Self) -> Result;
1708 }
1709
1710 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1711 impl VectorMule<vector_unsigned_short> for vector_unsigned_char {
1712 #[inline]
1713 #[target_feature(enable = "altivec")]
1714 unsafe fn vec_mule(self, b: Self) -> vector_unsigned_short {
1715 vmuleub(self, b)
1716 }
1717 }
1718 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1719 impl VectorMule<vector_signed_short> for vector_signed_char {
1720 #[inline]
1721 #[target_feature(enable = "altivec")]
1722 unsafe fn vec_mule(self, b: Self) -> vector_signed_short {
1723 vmulesb(self, b)
1724 }
1725 }
1726 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1727 impl VectorMule<vector_unsigned_int> for vector_unsigned_short {
1728 #[inline]
1729 #[target_feature(enable = "altivec")]
1730 unsafe fn vec_mule(self, b: Self) -> vector_unsigned_int {
1731 vmuleuh(self, b)
1732 }
1733 }
1734 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1735 impl VectorMule<vector_signed_int> for vector_signed_short {
1736 #[inline]
1737 #[target_feature(enable = "altivec")]
1738 unsafe fn vec_mule(self, b: Self) -> vector_signed_int {
1739 vmulesh(self, b)
1740 }
1741 }
1742
1743 #[inline]
1744 #[target_feature(enable = "altivec")]
1745 #[cfg_attr(test, assert_instr(vmuloub))]
1746 unsafe fn vec_vmuloub(
1747 a: vector_unsigned_char,
1748 b: vector_unsigned_char,
1749 ) -> vector_unsigned_short {
1750 vmuloub(a, b)
1751 }
1752 #[inline]
1753 #[target_feature(enable = "altivec")]
1754 #[cfg_attr(test, assert_instr(vmulosb))]
1755 unsafe fn vec_vmulosb(a: vector_signed_char, b: vector_signed_char) -> vector_signed_short {
1756 vmulosb(a, b)
1757 }
1758 #[inline]
1759 #[target_feature(enable = "altivec")]
1760 #[cfg_attr(test, assert_instr(vmulouh))]
1761 unsafe fn vec_vmulouh(
1762 a: vector_unsigned_short,
1763 b: vector_unsigned_short,
1764 ) -> vector_unsigned_int {
1765 vmulouh(a, b)
1766 }
1767 #[inline]
1768 #[target_feature(enable = "altivec")]
1769 #[cfg_attr(test, assert_instr(vmulosh))]
1770 unsafe fn vec_vmulosh(a: vector_signed_short, b: vector_signed_short) -> vector_signed_int {
1771 vmulosh(a, b)
1772 }
1773
1774 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1775 pub trait VectorMulo<Result> {
1776 unsafe fn vec_mulo(self, b: Self) -> Result;
1777 }
1778
1779 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1780 impl VectorMulo<vector_unsigned_short> for vector_unsigned_char {
1781 #[inline]
1782 #[target_feature(enable = "altivec")]
1783 unsafe fn vec_mulo(self, b: Self) -> vector_unsigned_short {
1784 vmuloub(self, b)
1785 }
1786 }
1787 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1788 impl VectorMulo<vector_signed_short> for vector_signed_char {
1789 #[inline]
1790 #[target_feature(enable = "altivec")]
1791 unsafe fn vec_mulo(self, b: Self) -> vector_signed_short {
1792 vmulosb(self, b)
1793 }
1794 }
1795 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1796 impl VectorMulo<vector_unsigned_int> for vector_unsigned_short {
1797 #[inline]
1798 #[target_feature(enable = "altivec")]
1799 unsafe fn vec_mulo(self, b: Self) -> vector_unsigned_int {
1800 vmulouh(self, b)
1801 }
1802 }
1803 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1804 impl VectorMulo<vector_signed_int> for vector_signed_short {
1805 #[inline]
1806 #[target_feature(enable = "altivec")]
1807 unsafe fn vec_mulo(self, b: Self) -> vector_signed_int {
1808 vmulosh(self, b)
1809 }
1810 }
1811
1812 #[inline]
1813 #[target_feature(enable = "altivec")]
1814 #[cfg_attr(test, assert_instr(vsum4ubs))]
1815 unsafe fn vec_vsum4ubs(a: vector_unsigned_char, b: vector_unsigned_int) -> vector_unsigned_int {
1816 vsum4ubs(a, b)
1817 }
1818
1819 #[inline]
1820 #[target_feature(enable = "altivec")]
1821 #[cfg_attr(test, assert_instr(vsum4sbs))]
1822 unsafe fn vec_vsum4sbs(a: vector_signed_char, b: vector_signed_int) -> vector_signed_int {
1823 vsum4sbs(a, b)
1824 }
1825
1826 #[inline]
1827 #[target_feature(enable = "altivec")]
1828 #[cfg_attr(test, assert_instr(vsum4shs))]
1829 unsafe fn vec_vsum4shs(a: vector_signed_short, b: vector_signed_int) -> vector_signed_int {
1830 vsum4shs(a, b)
1831 }
1832
1833 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1834 pub trait VectorSum4s<Other> {
1835 unsafe fn vec_sum4s(self, b: Other) -> Other;
1836 }
1837
1838 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1839 impl VectorSum4s<vector_unsigned_int> for vector_unsigned_char {
1840 #[inline]
1841 #[target_feature(enable = "altivec")]
1842 unsafe fn vec_sum4s(self, b: vector_unsigned_int) -> vector_unsigned_int {
1843 vsum4ubs(self, b)
1844 }
1845 }
1846
1847 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1848 impl VectorSum4s<vector_signed_int> for vector_signed_char {
1849 #[inline]
1850 #[target_feature(enable = "altivec")]
1851 unsafe fn vec_sum4s(self, b: vector_signed_int) -> vector_signed_int {
1852 vsum4sbs(self, b)
1853 }
1854 }
1855
1856 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1857 impl VectorSum4s<vector_signed_int> for vector_signed_short {
1858 #[inline]
1859 #[target_feature(enable = "altivec")]
1860 unsafe fn vec_sum4s(self, b: vector_signed_int) -> vector_signed_int {
1861 vsum4shs(self, b)
1862 }
1863 }
1864
1865 #[inline]
1866 #[target_feature(enable = "altivec")]
1867 #[cfg_attr(test, assert_instr(vsum2sws))]
1868 unsafe fn vec_vsum2sws(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int {
1869 vsum2sws(a, b)
1870 }
1871
1872 #[inline]
1873 #[target_feature(enable = "altivec")]
1874 #[cfg_attr(test, assert_instr(vnmsubfp))]
1875 unsafe fn vec_vnmsubfp(a: vector_float, b: vector_float, c: vector_float) -> vector_float {
1876 vnmsubfp(a, b, c)
1877 }
1878
1879 #[inline]
1880 #[target_feature(enable = "altivec")]
1881 #[cfg_attr(test, assert_instr(vmaddfp))]
1882 pub unsafe fn vec_vmaddfp(a: vector_float, b: vector_float, c: vector_float) -> vector_float {
1883 simd_fma(a, b, c)
1884 }
1885
1886 #[inline]
1887 #[target_feature(enable = "altivec")]
1888 #[cfg_attr(test, assert_instr(vmsumubm))]
1889 unsafe fn vec_vmsumubm(
1890 a: vector_unsigned_char,
1891 b: vector_unsigned_char,
1892 c: vector_unsigned_int,
1893 ) -> vector_unsigned_int {
1894 vmsumubm(a, b, c)
1895 }
1896
1897 #[inline]
1898 #[target_feature(enable = "altivec")]
1899 #[cfg_attr(test, assert_instr(vmsummbm))]
1900 unsafe fn vec_vmsummbm(
1901 a: vector_signed_char,
1902 b: vector_unsigned_char,
1903 c: vector_signed_int,
1904 ) -> vector_signed_int {
1905 vmsummbm(a, b, c)
1906 }
1907
1908 #[inline]
1909 #[target_feature(enable = "altivec")]
1910 #[cfg_attr(test, assert_instr(vmsumuhm))]
1911 unsafe fn vec_vmsumuhm(
1912 a: vector_unsigned_short,
1913 b: vector_unsigned_short,
1914 c: vector_unsigned_int,
1915 ) -> vector_unsigned_int {
1916 vmsumuhm(a, b, c)
1917 }
1918
1919 #[inline]
1920 #[target_feature(enable = "altivec")]
1921 #[cfg_attr(test, assert_instr(vmsumshm))]
1922 unsafe fn vec_vmsumshm(
1923 a: vector_signed_short,
1924 b: vector_signed_short,
1925 c: vector_signed_int,
1926 ) -> vector_signed_int {
1927 vmsumshm(a, b, c)
1928 }
1929
1930 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1931 pub trait VectorMsum<B, Other> {
1932 unsafe fn vec_msum(self, b: B, c: Other) -> Other;
1933 }
1934
1935 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1936 impl VectorMsum<vector_unsigned_char, vector_unsigned_int> for vector_unsigned_char {
1937 #[inline]
1938 #[target_feature(enable = "altivec")]
1939 unsafe fn vec_msum(
1940 self,
1941 b: vector_unsigned_char,
1942 c: vector_unsigned_int,
1943 ) -> vector_unsigned_int {
1944 vmsumubm(self, b, c)
1945 }
1946 }
1947
1948 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1949 impl VectorMsum<vector_unsigned_char, vector_signed_int> for vector_signed_char {
1950 #[inline]
1951 #[target_feature(enable = "altivec")]
1952 unsafe fn vec_msum(
1953 self,
1954 b: vector_unsigned_char,
1955 c: vector_signed_int,
1956 ) -> vector_signed_int {
1957 vmsummbm(self, b, c)
1958 }
1959 }
1960
1961 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1962 impl VectorMsum<vector_unsigned_short, vector_unsigned_int> for vector_unsigned_short {
1963 #[inline]
1964 #[target_feature(enable = "altivec")]
1965 unsafe fn vec_msum(
1966 self,
1967 b: vector_unsigned_short,
1968 c: vector_unsigned_int,
1969 ) -> vector_unsigned_int {
1970 vmsumuhm(self, b, c)
1971 }
1972 }
1973
1974 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1975 impl VectorMsum<vector_signed_short, vector_signed_int> for vector_signed_short {
1976 #[inline]
1977 #[target_feature(enable = "altivec")]
1978 unsafe fn vec_msum(
1979 self,
1980 b: vector_signed_short,
1981 c: vector_signed_int,
1982 ) -> vector_signed_int {
1983 vmsumshm(self, b, c)
1984 }
1985 }
1986
1987 #[inline]
1988 #[target_feature(enable = "altivec")]
1989 #[cfg_attr(test, assert_instr(vmsumuhs))]
1990 unsafe fn vec_vmsumuhs(
1991 a: vector_unsigned_short,
1992 b: vector_unsigned_short,
1993 c: vector_unsigned_int,
1994 ) -> vector_unsigned_int {
1995 vmsumuhs(a, b, c)
1996 }
1997
1998 #[inline]
1999 #[target_feature(enable = "altivec")]
2000 #[cfg_attr(test, assert_instr(vmsumshs))]
2001 unsafe fn vec_vmsumshs(
2002 a: vector_signed_short,
2003 b: vector_signed_short,
2004 c: vector_signed_int,
2005 ) -> vector_signed_int {
2006 vmsumshs(a, b, c)
2007 }
2008
2009 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2010 pub trait VectorMsums<Other> {
2011 unsafe fn vec_msums(self, b: Self, c: Other) -> Other;
2012 }
2013
2014 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2015 impl VectorMsums<vector_unsigned_int> for vector_unsigned_short {
2016 #[inline]
2017 #[target_feature(enable = "altivec")]
2018 unsafe fn vec_msums(self, b: Self, c: vector_unsigned_int) -> vector_unsigned_int {
2019 vmsumuhs(self, b, c)
2020 }
2021 }
2022
2023 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2024 impl VectorMsums<vector_signed_int> for vector_signed_short {
2025 #[inline]
2026 #[target_feature(enable = "altivec")]
2027 unsafe fn vec_msums(self, b: Self, c: vector_signed_int) -> vector_signed_int {
2028 vmsumshs(self, b, c)
2029 }
2030 }
2031
2032 #[inline]
2033 #[target_feature(enable = "altivec")]
2034 #[cfg_attr(test, assert_instr(vperm))]
2035 unsafe fn vec_vperm(
2036 a: vector_signed_int,
2037 b: vector_signed_int,
2038 c: vector_unsigned_char,
2039 ) -> vector_signed_int {
2040 vperm(a, b, c)
2041 }
2042
2043 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2044 pub trait VectorPerm {
2045 unsafe fn vec_vperm(self, b: Self, c: vector_unsigned_char) -> Self;
2046 }
2047
2048 macro_rules! vector_perm {
2049 {$impl: ident} => {
2050 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2051 impl VectorPerm for $impl {
2052 #[inline]
2053 #[target_feature(enable = "altivec")]
2054 unsafe fn vec_vperm(self, b: Self, c: vector_unsigned_char) -> Self {
2055 transmute(vec_vperm(transmute(self), transmute(b), c))
2056 }
2057 }
2058 }
2059 }
2060
2061 vector_perm! { vector_signed_char }
2062 vector_perm! { vector_unsigned_char }
2063 vector_perm! { vector_bool_char }
2064
2065 vector_perm! { vector_signed_short }
2066 vector_perm! { vector_unsigned_short }
2067 vector_perm! { vector_bool_short }
2068
2069 vector_perm! { vector_signed_int }
2070 vector_perm! { vector_unsigned_int }
2071 vector_perm! { vector_bool_int }
2072
2073 vector_perm! { vector_float }
2074
2075 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2076 pub trait VectorAdd<Other> {
2077 type Result;
2078 unsafe fn vec_add(self, other: Other) -> Self::Result;
2079 }
2080
2081 #[inline]
2082 #[target_feature(enable = "altivec")]
2083 #[cfg_attr(test, assert_instr(vaddubm))]
2084 pub unsafe fn vec_add_bc_sc(a: vector_bool_char, b: vector_signed_char) -> vector_signed_char {
2085 simd_add(transmute(a), b)
2086 }
2087 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2088 impl VectorAdd<vector_signed_char> for vector_bool_char {
2089 type Result = vector_signed_char;
2090 #[inline]
2091 #[target_feature(enable = "altivec")]
2092 unsafe fn vec_add(self, other: vector_signed_char) -> Self::Result {
2093 vec_add_bc_sc(self, other)
2094 }
2095 }
2096 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2097 impl VectorAdd<vector_bool_char> for vector_signed_char {
2098 type Result = vector_signed_char;
2099 #[inline]
2100 #[target_feature(enable = "altivec")]
2101 unsafe fn vec_add(self, other: vector_bool_char) -> Self::Result {
2102 other.vec_add(self)
2103 }
2104 }
2105
2106 #[inline]
2107 #[target_feature(enable = "altivec")]
2108 #[cfg_attr(test, assert_instr(vaddubm))]
2109 pub unsafe fn vec_add_sc_sc(
2110 a: vector_signed_char,
2111 b: vector_signed_char,
2112 ) -> vector_signed_char {
2113 simd_add(a, b)
2114 }
2115 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2116 impl VectorAdd<vector_signed_char> for vector_signed_char {
2117 type Result = vector_signed_char;
2118 #[inline]
2119 #[target_feature(enable = "altivec")]
2120 unsafe fn vec_add(self, other: vector_signed_char) -> Self::Result {
2121 vec_add_sc_sc(self, other)
2122 }
2123 }
2124
2125 #[inline]
2126 #[target_feature(enable = "altivec")]
2127 #[cfg_attr(test, assert_instr(vaddubm))]
2128 pub unsafe fn vec_add_bc_uc(
2129 a: vector_bool_char,
2130 b: vector_unsigned_char,
2131 ) -> vector_unsigned_char {
2132 simd_add(transmute(a), b)
2133 }
2134 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2135 impl VectorAdd<vector_unsigned_char> for vector_bool_char {
2136 type Result = vector_unsigned_char;
2137 #[inline]
2138 #[target_feature(enable = "altivec")]
2139 unsafe fn vec_add(self, other: vector_unsigned_char) -> Self::Result {
2140 vec_add_bc_uc(self, other)
2141 }
2142 }
2143 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2144 impl VectorAdd<vector_bool_char> for vector_unsigned_char {
2145 type Result = vector_unsigned_char;
2146 #[inline]
2147 #[target_feature(enable = "altivec")]
2148 unsafe fn vec_add(self, other: vector_bool_char) -> Self::Result {
2149 other.vec_add(self)
2150 }
2151 }
2152
2153 #[inline]
2154 #[target_feature(enable = "altivec")]
2155 #[cfg_attr(test, assert_instr(vaddubm))]
2156 pub unsafe fn vec_add_uc_uc(
2157 a: vector_unsigned_char,
2158 b: vector_unsigned_char,
2159 ) -> vector_unsigned_char {
2160 simd_add(a, b)
2161 }
2162 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2163 impl VectorAdd<vector_unsigned_char> for vector_unsigned_char {
2164 type Result = vector_unsigned_char;
2165 #[inline]
2166 #[target_feature(enable = "altivec")]
2167 unsafe fn vec_add(self, other: vector_unsigned_char) -> Self::Result {
2168 vec_add_uc_uc(self, other)
2169 }
2170 }
2171
2172 #[inline]
2173 #[target_feature(enable = "altivec")]
2174 #[cfg_attr(test, assert_instr(vadduhm))]
2175 pub unsafe fn vec_add_bs_ss(
2176 a: vector_bool_short,
2177 b: vector_signed_short,
2178 ) -> vector_signed_short {
2179 let a: i16x8 = transmute(a);
2180 let a: vector_signed_short = simd_cast(a);
2181 simd_add(a, b)
2182 }
2183
2184 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2185 impl VectorAdd<vector_signed_short> for vector_bool_short {
2186 type Result = vector_signed_short;
2187 #[inline]
2188 #[target_feature(enable = "altivec")]
2189 unsafe fn vec_add(self, other: vector_signed_short) -> Self::Result {
2190 vec_add_bs_ss(self, other)
2191 }
2192 }
2193 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2194 impl VectorAdd<vector_bool_short> for vector_signed_short {
2195 type Result = vector_signed_short;
2196 #[inline]
2197 #[target_feature(enable = "altivec")]
2198 unsafe fn vec_add(self, other: vector_bool_short) -> Self::Result {
2199 other.vec_add(self)
2200 }
2201 }
2202
2203 #[inline]
2204 #[target_feature(enable = "altivec")]
2205 #[cfg_attr(test, assert_instr(vadduhm))]
2206 pub unsafe fn vec_add_ss_ss(
2207 a: vector_signed_short,
2208 b: vector_signed_short,
2209 ) -> vector_signed_short {
2210 simd_add(a, b)
2211 }
2212 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2213 impl VectorAdd<vector_signed_short> for vector_signed_short {
2214 type Result = vector_signed_short;
2215 #[inline]
2216 #[target_feature(enable = "altivec")]
2217 unsafe fn vec_add(self, other: vector_signed_short) -> Self::Result {
2218 vec_add_ss_ss(self, other)
2219 }
2220 }
2221
2222 #[inline]
2223 #[target_feature(enable = "altivec")]
2224 #[cfg_attr(test, assert_instr(vadduhm))]
2225 pub unsafe fn vec_add_bs_us(
2226 a: vector_bool_short,
2227 b: vector_unsigned_short,
2228 ) -> vector_unsigned_short {
2229 let a: i16x8 = transmute(a);
2230 let a: vector_unsigned_short = simd_cast(a);
2231 simd_add(a, b)
2232 }
2233 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2234 impl VectorAdd<vector_unsigned_short> for vector_bool_short {
2235 type Result = vector_unsigned_short;
2236 #[inline]
2237 #[target_feature(enable = "altivec")]
2238 unsafe fn vec_add(self, other: vector_unsigned_short) -> Self::Result {
2239 vec_add_bs_us(self, other)
2240 }
2241 }
2242 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2243 impl VectorAdd<vector_bool_short> for vector_unsigned_short {
2244 type Result = vector_unsigned_short;
2245 #[inline]
2246 #[target_feature(enable = "altivec")]
2247 unsafe fn vec_add(self, other: vector_bool_short) -> Self::Result {
2248 other.vec_add(self)
2249 }
2250 }
2251
2252 #[inline]
2253 #[target_feature(enable = "altivec")]
2254 #[cfg_attr(test, assert_instr(vadduhm))]
2255 pub unsafe fn vec_add_us_us(
2256 a: vector_unsigned_short,
2257 b: vector_unsigned_short,
2258 ) -> vector_unsigned_short {
2259 simd_add(a, b)
2260 }
2261
2262 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2263 impl VectorAdd<vector_unsigned_short> for vector_unsigned_short {
2264 type Result = vector_unsigned_short;
2265 #[inline]
2266 #[target_feature(enable = "altivec")]
2267 unsafe fn vec_add(self, other: vector_unsigned_short) -> Self::Result {
2268 vec_add_us_us(self, other)
2269 }
2270 }
2271
2272 #[inline]
2273 #[target_feature(enable = "altivec")]
2274 #[cfg_attr(test, assert_instr(vadduwm))]
2275 pub unsafe fn vec_add_bi_si(a: vector_bool_int, b: vector_signed_int) -> vector_signed_int {
2276 let a: i32x4 = transmute(a);
2277 let a: vector_signed_int = simd_cast(a);
2278 simd_add(a, b)
2279 }
2280 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2281 impl VectorAdd<vector_signed_int> for vector_bool_int {
2282 type Result = vector_signed_int;
2283 #[inline]
2284 #[target_feature(enable = "altivec")]
2285 unsafe fn vec_add(self, other: vector_signed_int) -> Self::Result {
2286 vec_add_bi_si(self, other)
2287 }
2288 }
2289 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2290 impl VectorAdd<vector_bool_int> for vector_signed_int {
2291 type Result = vector_signed_int;
2292 #[inline]
2293 #[target_feature(enable = "altivec")]
2294 unsafe fn vec_add(self, other: vector_bool_int) -> Self::Result {
2295 other.vec_add(self)
2296 }
2297 }
2298
2299 #[inline]
2300 #[target_feature(enable = "altivec")]
2301 #[cfg_attr(test, assert_instr(vadduwm))]
2302 pub unsafe fn vec_add_si_si(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int {
2303 simd_add(a, b)
2304 }
2305 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2306 impl VectorAdd<vector_signed_int> for vector_signed_int {
2307 type Result = vector_signed_int;
2308 #[inline]
2309 #[target_feature(enable = "altivec")]
2310 unsafe fn vec_add(self, other: vector_signed_int) -> Self::Result {
2311 vec_add_si_si(self, other)
2312 }
2313 }
2314
2315 #[inline]
2316 #[target_feature(enable = "altivec")]
2317 #[cfg_attr(test, assert_instr(vadduwm))]
2318 pub unsafe fn vec_add_bi_ui(a: vector_bool_int, b: vector_unsigned_int) -> vector_unsigned_int {
2319 let a: i32x4 = transmute(a);
2320 let a: vector_unsigned_int = simd_cast(a);
2321 simd_add(a, b)
2322 }
2323 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2324 impl VectorAdd<vector_unsigned_int> for vector_bool_int {
2325 type Result = vector_unsigned_int;
2326 #[inline]
2327 #[target_feature(enable = "altivec")]
2328 unsafe fn vec_add(self, other: vector_unsigned_int) -> Self::Result {
2329 vec_add_bi_ui(self, other)
2330 }
2331 }
2332 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2333 impl VectorAdd<vector_bool_int> for vector_unsigned_int {
2334 type Result = vector_unsigned_int;
2335 #[inline]
2336 #[target_feature(enable = "altivec")]
2337 unsafe fn vec_add(self, other: vector_bool_int) -> Self::Result {
2338 other.vec_add(self)
2339 }
2340 }
2341
2342 #[inline]
2343 #[target_feature(enable = "altivec")]
2344 #[cfg_attr(test, assert_instr(vadduwm))]
2345 pub unsafe fn vec_add_ui_ui(
2346 a: vector_unsigned_int,
2347 b: vector_unsigned_int,
2348 ) -> vector_unsigned_int {
2349 simd_add(a, b)
2350 }
2351 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2352 impl VectorAdd<vector_unsigned_int> for vector_unsigned_int {
2353 type Result = vector_unsigned_int;
2354 #[inline]
2355 #[target_feature(enable = "altivec")]
2356 unsafe fn vec_add(self, other: vector_unsigned_int) -> Self::Result {
2357 vec_add_ui_ui(self, other)
2358 }
2359 }
2360
2361 #[inline]
2362 #[target_feature(enable = "altivec")]
2363 #[cfg_attr(test, assert_instr(xvaddsp))]
2364 pub unsafe fn vec_add_float_float(a: vector_float, b: vector_float) -> vector_float {
2365 simd_add(a, b)
2366 }
2367
2368 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2369 impl VectorAdd<vector_float> for vector_float {
2370 type Result = vector_float;
2371 #[inline]
2372 #[target_feature(enable = "altivec")]
2373 unsafe fn vec_add(self, other: vector_float) -> Self::Result {
2374 vec_add_float_float(self, other)
2375 }
2376 }
2377
2378 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2379 pub trait VectorAdde {
2380 unsafe fn vec_adde(self, b: Self, c: Self) -> Self;
2381 }
2382
2383 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2384 impl VectorAdde for vector_unsigned_int {
2385 #[inline]
2386 #[target_feature(enable = "altivec")]
2387 unsafe fn vec_adde(self, b: Self, c: Self) -> Self {
2388 let mask: vector_unsigned_int = transmute(u32x4::new(1, 1, 1, 1));
2389 let carry = vec_and(c, mask);
2390 vec_add(vec_add(self, b), carry)
2391 }
2392 }
2393
2394 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2395 impl VectorAdde for vector_signed_int {
2396 #[inline]
2397 #[target_feature(enable = "altivec")]
2398 unsafe fn vec_adde(self, b: Self, c: Self) -> Self {
2399 let mask: vector_signed_int = transmute(i32x4::new(1, 1, 1, 1));
2400 let carry = vec_and(c, mask);
2401 vec_add(vec_add(self, b), carry)
2402 }
2403 }
2404
2405 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2406 pub trait VectorMladd<Other> {
2407 type Result;
2408 unsafe fn vec_mladd(self, b: Other, c: Other) -> Self::Result;
2409 }
2410
2411 #[inline]
2412 #[target_feature(enable = "altivec")]
2413 #[cfg_attr(test, assert_instr(vmladduhm))]
2414 unsafe fn mladd(
2415 a: vector_signed_short,
2416 b: vector_signed_short,
2417 c: vector_signed_short,
2418 ) -> vector_signed_short {
2419 let a: i16x8 = transmute(a);
2420 let b: i16x8 = transmute(b);
2421 let c: i16x8 = transmute(c);
2422 transmute(simd_add(simd_mul(a, b), c))
2423 }
2424
2425 macro_rules! vector_mladd {
2426 ($a: ident, $bc: ident, $d: ident) => {
2427 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2428 impl VectorMladd<$bc> for $a {
2429 type Result = $d;
2430 #[inline]
2431 #[target_feature(enable = "altivec")]
2432 unsafe fn vec_mladd(self, b: $bc, c: $bc) -> Self::Result {
2433 let a = transmute(self);
2434 let b = transmute(b);
2435 let c = transmute(c);
2436
2437 transmute(mladd(a, b, c))
2438 }
2439 }
2440 };
2441 }
2442
2443 vector_mladd! { vector_unsigned_short, vector_unsigned_short, vector_unsigned_short }
2444 vector_mladd! { vector_unsigned_short, vector_signed_short, vector_signed_short }
2445 vector_mladd! { vector_signed_short, vector_unsigned_short, vector_signed_short }
2446 vector_mladd! { vector_signed_short, vector_signed_short, vector_signed_short }
2447
2448 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2449 pub trait VectorOr<Other> {
2450 type Result;
2451 unsafe fn vec_or(self, b: Other) -> Self::Result;
2452 }
2453
2454 impl_vec_trait! { [VectorOr vec_or] ~(simd_or) }
2455
2456 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2457 pub trait VectorXor<Other> {
2458 type Result;
2459 unsafe fn vec_xor(self, b: Other) -> Self::Result;
2460 }
2461
2462 impl_vec_trait! { [VectorXor vec_xor] ~(simd_xor) }
2463
2464 macro_rules! vector_vnor {
2465 ($fun:ident $ty:ident) => {
2466 #[inline]
2467 #[target_feature(enable = "altivec")]
2468 #[cfg_attr(all(test, not(target_feature = "vsx")), assert_instr(vnor))]
2469 #[cfg_attr(all(test, target_feature = "vsx"), assert_instr(xxlnor))]
2470 pub unsafe fn $fun(a: t_t_l!($ty), b: t_t_l!($ty)) -> t_t_l!($ty) {
2471 let o = vec_splats(!0 as $ty);
2472 vec_xor(vec_or(a, b), o)
2473 }
2474 };
2475 }
2476
2477 vector_vnor! { vec_vnorsb i8 }
2478 vector_vnor! { vec_vnorsh i16 }
2479 vector_vnor! { vec_vnorsw i32 }
2480
2481 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2482 pub trait VectorNor<Other> {
2483 type Result;
2484 unsafe fn vec_nor(self, b: Other) -> Self::Result;
2485 }
2486
2487 impl_vec_trait! { [VectorNor vec_nor]+ 2b (vec_vnorsb, vec_vnorsh, vec_vnorsw) }
2488
2489 macro_rules! vector_vnand {
2490 ($fun:ident $ty:ident) => {
2491 #[inline]
2492 #[target_feature(enable = "altivec")]
2493 #[cfg_attr(all(test, not(target_feature = "vsx")), assert_instr(vnand))]
2494 #[cfg_attr(all(test, target_feature = "vsx"), assert_instr(xxlnand))]
2495 pub unsafe fn $fun(a: t_t_l!($ty), b: t_t_l!($ty)) -> t_t_l!($ty) {
2496 let o = vec_splats(!0 as $ty);
2497 vec_xor(vec_and(a, b), o)
2498 }
2499 };
2500 }
2501
2502 vector_vnand! { vec_vnandsb i8 }
2503 vector_vnand! { vec_vnandsh i16 }
2504 vector_vnand! { vec_vnandsw i32 }
2505
2506 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2507 pub trait VectorNand<Other> {
2508 type Result;
2509 unsafe fn vec_nand(self, b: Other) -> Self::Result;
2510 }
2511
2512 impl_vec_trait! { [VectorNand vec_nand]+ 2b (vec_vnandsb, vec_vnandsh, vec_vnandsw) }
2513
2514 #[inline]
2515 #[target_feature(enable = "altivec")]
2516 #[cfg_attr(all(test, not(target_feature = "vsx")), assert_instr(vsel))]
2517 #[cfg_attr(all(test, target_feature = "vsx"), assert_instr(xxsel))]
2518 pub unsafe fn vec_vsel(
2519 a: vector_signed_char,
2520 b: vector_signed_char,
2521 c: vector_signed_char,
2522 ) -> vector_signed_char {
2523 let a: i8x16 = transmute(a);
2524 let b: i8x16 = transmute(b);
2525 let c: i8x16 = transmute(c);
2526 let not_c = simd_xor(c, i8x16::splat(!0));
2527
2528 transmute(simd_or(simd_and(a, not_c), simd_and(b, c)))
2529 }
2530
2531 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2532 pub trait VectorSel<Mask> {
2533 unsafe fn vec_sel(self, b: Self, c: Mask) -> Self;
2534 }
2535
2536 macro_rules! vector_sel {
2537 ($ty: ty, $m: ty) => {
2538 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2539 impl VectorSel<$m> for $ty {
2540 #[inline]
2541 #[target_feature(enable = "altivec")]
2542 unsafe fn vec_sel(self, b: Self, c: $m) -> Self {
2543 let a = transmute(self);
2544 let b = transmute(b);
2545 let c = transmute(c);
2546
2547 transmute(vec_vsel(a, b, c))
2548 }
2549 }
2550 };
2551 ($ty: ident) => {
2552 vector_sel! { $ty, t_b!{ $ty } }
2553 vector_sel! { $ty, t_u!{ $ty } }
2554 vector_sel! { t_u!{ $ty }, t_b!{ $ty } }
2555 vector_sel! { t_u!{ $ty }, t_u!{ $ty } }
2556 vector_sel! { t_b!{ $ty }, t_b!{ $ty } }
2557 vector_sel! { t_b!{ $ty }, t_u!{ $ty } }
2558 };
2559 (- $ty: ident) => {
2560 vector_sel! { $ty, t_b!{ $ty } }
2561 vector_sel! { $ty, t_u!{ $ty } }
2562 };
2563 }
2564
2565 vector_sel! { vector_signed_char }
2566 vector_sel! { vector_signed_short }
2567 vector_sel! { vector_signed_int }
2568 vector_sel! {- vector_float }
2569
2570 #[inline]
2571 #[target_feature(enable = "altivec")]
2572 #[cfg_attr(test, assert_instr(vcfsx, IMM5 = 1))]
2573 unsafe fn vec_ctf_i32<const IMM5: i32>(a: vector_signed_int) -> vector_float {
2574 static_assert_uimm_bits!(IMM5, 5);
2575 vcfsx(a, IMM5)
2576 }
2577
2578 #[inline]
2579 #[target_feature(enable = "altivec")]
2580 #[cfg_attr(test, assert_instr(vcfux, IMM5 = 1))]
2581 unsafe fn vec_ctf_u32<const IMM5: i32>(a: vector_unsigned_int) -> vector_float {
2582 static_assert_uimm_bits!(IMM5, 5);
2583 vcfux(a, IMM5)
2584 }
2585
2586 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2587 pub trait VectorCtf {
2588 unsafe fn vec_ctf<const IMM5: i32>(self) -> vector_float;
2589 }
2590
2591 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2592 impl VectorCtf for vector_signed_int {
2593 unsafe fn vec_ctf<const IMM5: i32>(self) -> vector_float {
2594 vec_ctf_i32::<IMM5>(self)
2595 }
2596 }
2597
2598 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2599 impl VectorCtf for vector_unsigned_int {
2600 unsafe fn vec_ctf<const IMM5: i32>(self) -> vector_float {
2601 vec_ctf_u32::<IMM5>(self)
2602 }
2603 }
2604
2605 #[inline]
2606 #[target_feature(enable = "altivec")]
2607 #[cfg_attr(all(test, target_endian = "little"), assert_instr(vmrghb))]
2608 #[cfg_attr(all(test, target_endian = "big"), assert_instr(vmrglb))]
2609 unsafe fn vec_vmrglb(a: vector_signed_char, b: vector_signed_char) -> vector_signed_char {
2610 let mergel_perm = transmute(u8x16::new(
2611 0x08, 0x18, 0x09, 0x19, 0x0A, 0x1A, 0x0B, 0x1B, 0x0C, 0x1C, 0x0D, 0x1D, 0x0E, 0x1E,
2612 0x0F, 0x1F,
2613 ));
2614 vec_perm(a, b, mergel_perm)
2615 }
2616
2617 #[inline]
2618 #[target_feature(enable = "altivec")]
2619 #[cfg_attr(all(test, target_endian = "little"), assert_instr(vmrghh))]
2620 #[cfg_attr(all(test, target_endian = "big"), assert_instr(vmrglh))]
2621 unsafe fn vec_vmrglh(a: vector_signed_short, b: vector_signed_short) -> vector_signed_short {
2622 let mergel_perm = transmute(u8x16::new(
2623 0x08, 0x09, 0x18, 0x19, 0x0A, 0x0B, 0x1A, 0x1B, 0x0C, 0x0D, 0x1C, 0x1D, 0x0E, 0x0F,
2624 0x1E, 0x1F,
2625 ));
2626 vec_perm(a, b, mergel_perm)
2627 }
2628
2629 #[inline]
2630 #[target_feature(enable = "altivec")]
2631 #[cfg_attr(
2632 all(test, target_endian = "little", not(target_feature = "vsx")),
2633 assert_instr(vmrghw)
2634 )]
2635 #[cfg_attr(
2636 all(test, target_endian = "little", target_feature = "vsx"),
2637 assert_instr(xxmrghw)
2638 )]
2639 #[cfg_attr(
2640 all(test, target_endian = "big", not(target_feature = "vsx")),
2641 assert_instr(vmrglw)
2642 )]
2643 #[cfg_attr(
2644 all(test, target_endian = "big", target_feature = "vsx"),
2645 assert_instr(xxmrglw)
2646 )]
2647 unsafe fn vec_vmrglw(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int {
2648 let mergel_perm = transmute(u8x16::new(
2649 0x08, 0x09, 0x0A, 0x0B, 0x18, 0x19, 0x1A, 0x1B, 0x0C, 0x0D, 0x0E, 0x0F, 0x1C, 0x1D,
2650 0x1E, 0x1F,
2651 ));
2652 vec_perm(a, b, mergel_perm)
2653 }
2654
2655 #[inline]
2656 #[target_feature(enable = "altivec")]
2657 #[cfg_attr(all(test, target_endian = "little"), assert_instr(vmrglb))]
2658 #[cfg_attr(all(test, target_endian = "big"), assert_instr(vmrghb))]
2659 unsafe fn vec_vmrghb(a: vector_signed_char, b: vector_signed_char) -> vector_signed_char {
2660 let mergel_perm = transmute(u8x16::new(
2661 0x00, 0x10, 0x01, 0x11, 0x02, 0x12, 0x03, 0x13, 0x04, 0x14, 0x05, 0x15, 0x06, 0x16,
2662 0x07, 0x17,
2663 ));
2664 vec_perm(a, b, mergel_perm)
2665 }
2666
2667 #[inline]
2668 #[target_feature(enable = "altivec")]
2669 #[cfg_attr(all(test, target_endian = "little"), assert_instr(vmrglh))]
2670 #[cfg_attr(all(test, target_endian = "big"), assert_instr(vmrghh))]
2671 unsafe fn vec_vmrghh(a: vector_signed_short, b: vector_signed_short) -> vector_signed_short {
2672 let mergel_perm = transmute(u8x16::new(
2673 0x00, 0x01, 0x10, 0x11, 0x02, 0x03, 0x12, 0x13, 0x04, 0x05, 0x14, 0x15, 0x06, 0x07,
2674 0x16, 0x17,
2675 ));
2676 vec_perm(a, b, mergel_perm)
2677 }
2678
2679 #[inline]
2680 #[target_feature(enable = "altivec")]
2681 #[cfg_attr(
2682 all(test, target_endian = "little", not(target_feature = "vsx")),
2683 assert_instr(vmrglw)
2684 )]
2685 #[cfg_attr(
2686 all(test, target_endian = "little", target_feature = "vsx"),
2687 assert_instr(xxmrglw)
2688 )]
2689 #[cfg_attr(
2690 all(test, target_endian = "big", not(target_feature = "vsx")),
2691 assert_instr(vmrghw)
2692 )]
2693 #[cfg_attr(
2694 all(test, target_endian = "big", target_feature = "vsx"),
2695 assert_instr(xxmrghw)
2696 )]
2697 unsafe fn vec_vmrghw(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int {
2698 let mergel_perm = transmute(u8x16::new(
2699 0x00, 0x01, 0x02, 0x03, 0x10, 0x11, 0x12, 0x13, 0x04, 0x05, 0x06, 0x07, 0x14, 0x15,
2700 0x16, 0x17,
2701 ));
2702 vec_perm(a, b, mergel_perm)
2703 }
2704
2705 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2706 pub trait VectorMergeh<Other> {
2707 type Result;
2708 unsafe fn vec_mergeh(self, b: Other) -> Self::Result;
2709 }
2710
2711 impl_vec_trait! { [VectorMergeh vec_mergeh]+ 2b (vec_vmrghb, vec_vmrghh, vec_vmrghw) }
2712 impl_vec_trait! { [VectorMergeh vec_mergeh]+ vec_vmrghw (vector_float, vector_float) -> vector_float }
2713
2714 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2715 pub trait VectorMergel<Other> {
2716 type Result;
2717 unsafe fn vec_mergel(self, b: Other) -> Self::Result;
2718 }
2719
2720 impl_vec_trait! { [VectorMergel vec_mergel]+ 2b (vec_vmrglb, vec_vmrglh, vec_vmrglw) }
2721 impl_vec_trait! { [VectorMergel vec_mergel]+ vec_vmrglw (vector_float, vector_float) -> vector_float }
2722
2723 #[inline]
2724 #[target_feature(enable = "altivec")]
2725 #[cfg_attr(test, assert_instr(vpkuhum))]
2726 unsafe fn vec_vpkuhum(a: vector_signed_short, b: vector_signed_short) -> vector_signed_char {
2727 let pack_perm = if cfg!(target_endian = "little") {
2728 transmute(u8x16::new(
2729 0x00, 0x02, 0x04, 0x06, 0x08, 0x0A, 0x0C, 0x0E, 0x10, 0x12, 0x14, 0x16, 0x18, 0x1A,
2730 0x1C, 0x1E,
2731 ))
2732 } else {
2733 transmute(u8x16::new(
2734 0x01, 0x03, 0x05, 0x07, 0x09, 0x0B, 0x0D, 0x0F, 0x11, 0x13, 0x15, 0x17, 0x19, 0x1B,
2735 0x1D, 0x1F,
2736 ))
2737 };
2738
2739 transmute(vec_perm(a, b, pack_perm))
2740 }
2741
2742 #[inline]
2743 #[target_feature(enable = "altivec")]
2744 #[cfg_attr(test, assert_instr(vpkuwum))]
2745 unsafe fn vec_vpkuwum(a: vector_signed_int, b: vector_signed_int) -> vector_signed_short {
2746 let pack_perm = if cfg!(target_endian = "little") {
2747 transmute(u8x16::new(
2748 0x00, 0x01, 0x04, 0x05, 0x08, 0x09, 0x0C, 0x0D, 0x10, 0x11, 0x14, 0x15, 0x18, 0x19,
2749 0x1C, 0x1D,
2750 ))
2751 } else {
2752 transmute(u8x16::new(
2753 0x02, 0x03, 0x06, 0x07, 0x0A, 0x0B, 0x0E, 0x0F, 0x12, 0x13, 0x16, 0x17, 0x1A, 0x1B,
2754 0x1E, 0x1F,
2755 ))
2756 };
2757
2758 transmute(vec_perm(a, b, pack_perm))
2759 }
2760
2761 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2762 pub trait VectorPack<Other> {
2763 type Result;
2764 unsafe fn vec_pack(self, b: Other) -> Self::Result;
2765 }
2766
2767 impl_vec_trait! { [VectorPack vec_pack]+ vec_vpkuhum (vector_signed_short, vector_signed_short) -> vector_signed_char }
2768 impl_vec_trait! { [VectorPack vec_pack]+ vec_vpkuhum (vector_unsigned_short, vector_unsigned_short) -> vector_unsigned_char }
2769 impl_vec_trait! { [VectorPack vec_pack]+ vec_vpkuhum (vector_bool_short, vector_bool_short) -> vector_bool_char }
2770 impl_vec_trait! { [VectorPack vec_pack]+ vec_vpkuwum (vector_signed_int, vector_signed_int) -> vector_signed_short }
2771 impl_vec_trait! { [VectorPack vec_pack]+ vec_vpkuwum (vector_unsigned_int, vector_unsigned_int) -> vector_unsigned_short }
2772 impl_vec_trait! { [VectorPack vec_pack]+ vec_vpkuwum (vector_bool_int, vector_bool_int) -> vector_bool_short }
2773
2774 #[inline]
2775 #[target_feature(enable = "altivec")]
2776 #[cfg_attr(test, assert_instr(vpkshss))]
2777 unsafe fn vec_vpkshss(a: vector_signed_short, b: vector_signed_short) -> vector_signed_char {
2778 if cfg!(target_endian = "little") {
2779 vpkshss(b, a)
2780 } else {
2781 vpkshss(a, b)
2782 }
2783 }
2784
2785 #[inline]
2786 #[target_feature(enable = "altivec")]
2787 #[cfg_attr(test, assert_instr(vpkshus))]
2788 unsafe fn vec_vpkshus(a: vector_signed_short, b: vector_signed_short) -> vector_unsigned_char {
2789 if cfg!(target_endian = "little") {
2790 vpkshus(b, a)
2791 } else {
2792 vpkshus(a, b)
2793 }
2794 }
2795
2796 #[inline]
2797 #[target_feature(enable = "altivec")]
2798 #[cfg_attr(test, assert_instr(vpkuhus))]
2799 unsafe fn vec_vpkuhus(
2800 a: vector_unsigned_short,
2801 b: vector_unsigned_short,
2802 ) -> vector_unsigned_char {
2803 if cfg!(target_endian = "little") {
2804 vpkuhus(b, a)
2805 } else {
2806 vpkuhus(a, b)
2807 }
2808 }
2809
2810 #[inline]
2811 #[target_feature(enable = "altivec")]
2812 #[cfg_attr(test, assert_instr(vpkswss))]
2813 unsafe fn vec_vpkswss(a: vector_signed_int, b: vector_signed_int) -> vector_signed_short {
2814 if cfg!(target_endian = "little") {
2815 vpkswss(b, a)
2816 } else {
2817 vpkswss(a, b)
2818 }
2819 }
2820
2821 #[inline]
2822 #[target_feature(enable = "altivec")]
2823 #[cfg_attr(test, assert_instr(vpkswus))]
2824 unsafe fn vec_vpkswus(a: vector_signed_int, b: vector_signed_int) -> vector_unsigned_short {
2825 if cfg!(target_endian = "little") {
2826 vpkswus(b, a)
2827 } else {
2828 vpkswus(a, b)
2829 }
2830 }
2831
2832 #[inline]
2833 #[target_feature(enable = "altivec")]
2834 #[cfg_attr(test, assert_instr(vpkuwus))]
2835 unsafe fn vec_vpkuwus(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_short {
2836 if cfg!(target_endian = "little") {
2837 vpkuwus(b, a)
2838 } else {
2839 vpkuwus(a, b)
2840 }
2841 }
2842
2843 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2844 pub trait VectorPacks<Other> {
2845 type Result;
2846 unsafe fn vec_packs(self, b: Other) -> Self::Result;
2847 }
2848
2849 impl_vec_trait! { [VectorPacks vec_packs] vec_vpkshss (vector_signed_short, vector_signed_short) -> vector_signed_char }
2850 impl_vec_trait! { [VectorPacks vec_packs] vec_vpkuhus (vector_unsigned_short, vector_unsigned_short) -> vector_unsigned_char }
2851 impl_vec_trait! { [VectorPacks vec_packs] vec_vpkswss (vector_signed_int, vector_signed_int) -> vector_signed_short }
2852 impl_vec_trait! { [VectorPacks vec_packs] vec_vpkuwus (vector_unsigned_int, vector_unsigned_int) -> vector_unsigned_short }
2853
2854 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2855 pub trait VectorPacksu<Other> {
2856 type Result;
2857 unsafe fn vec_packsu(self, b: Other) -> Self::Result;
2858 }
2859
2860 impl_vec_trait! { [VectorPacksu vec_packsu] vec_vpkshus (vector_signed_short, vector_signed_short) -> vector_unsigned_char }
2861 impl_vec_trait! { [VectorPacksu vec_packsu] vec_vpkuhus (vector_unsigned_short, vector_unsigned_short) -> vector_unsigned_char }
2862 impl_vec_trait! { [VectorPacksu vec_packsu] vec_vpkswus (vector_signed_int, vector_signed_int) -> vector_unsigned_short }
2863 impl_vec_trait! { [VectorPacksu vec_packsu] vec_vpkuwus (vector_unsigned_int, vector_unsigned_int) -> vector_unsigned_short }
2864
2865 macro_rules! impl_vec_unpack {
2866 ($fun:ident ($a:ident) -> $r:ident [$little:ident, $big:ident]) => {
2867 #[inline]
2868 #[target_feature(enable = "altivec")]
2869 #[cfg_attr(all(test, target_endian = "little"), assert_instr($little))]
2870 #[cfg_attr(all(test, target_endian = "big"), assert_instr($big))]
2871 unsafe fn $fun(a: $a) -> $r {
2872 if cfg!(target_endian = "little") {
2873 $little(a)
2874 } else {
2875 $big(a)
2876 }
2877 }
2878 };
2879 }
2880
2881 impl_vec_unpack! { vec_vupkhsb (vector_signed_char) -> vector_signed_short [vupklsb, vupkhsb] }
2882 impl_vec_unpack! { vec_vupklsb (vector_signed_char) -> vector_signed_short [vupkhsb, vupklsb] }
2883 impl_vec_unpack! { vec_vupkhsh (vector_signed_short) -> vector_signed_int [vupklsh, vupkhsh] }
2884 impl_vec_unpack! { vec_vupklsh (vector_signed_short) -> vector_signed_int [vupkhsh, vupklsh] }
2885
2886 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2887 pub trait VectorUnpackh {
2888 type Result;
2889 unsafe fn vec_unpackh(self) -> Self::Result;
2890 }
2891
2892 impl_vec_trait! { [VectorUnpackh vec_unpackh] vec_vupkhsb (vector_signed_char) -> vector_signed_short }
2893 impl_vec_trait! { [VectorUnpackh vec_unpackh]+ vec_vupkhsb (vector_bool_char) -> vector_bool_short }
2894 impl_vec_trait! { [VectorUnpackh vec_unpackh] vec_vupkhsh (vector_signed_short) -> vector_signed_int }
2895 impl_vec_trait! { [VectorUnpackh vec_unpackh]+ vec_vupkhsh (vector_bool_short) -> vector_bool_int }
2896
2897 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2898 pub trait VectorUnpackl {
2899 type Result;
2900 unsafe fn vec_unpackl(self) -> Self::Result;
2901 }
2902
2903 impl_vec_trait! { [VectorUnpackl vec_unpackl] vec_vupklsb (vector_signed_char) -> vector_signed_short }
2904 impl_vec_trait! { [VectorUnpackl vec_unpackl]+ vec_vupklsb (vector_bool_char) -> vector_bool_short }
2905 impl_vec_trait! { [VectorUnpackl vec_unpackl] vec_vupklsh (vector_signed_short) -> vector_signed_int }
2906 impl_vec_trait! { [VectorUnpackl vec_unpackl]+ vec_vupklsh (vector_bool_short) -> vector_bool_int }
2907
2908 macro_rules! impl_vec_shift {
2909 ([$Trait:ident $m:ident] ($b:ident, $h:ident, $w:ident)) => {
2910 impl_vec_trait!{ [$Trait $m]+ $b (vector_unsigned_char, vector_unsigned_char) -> vector_unsigned_char }
2911 impl_vec_trait!{ [$Trait $m]+ $b (vector_signed_char, vector_unsigned_char) -> vector_signed_char }
2912 impl_vec_trait!{ [$Trait $m]+ $h (vector_unsigned_short, vector_unsigned_short) -> vector_unsigned_short }
2913 impl_vec_trait!{ [$Trait $m]+ $h (vector_signed_short, vector_unsigned_short) -> vector_signed_short }
2914 impl_vec_trait!{ [$Trait $m]+ $w (vector_unsigned_int, vector_unsigned_int) -> vector_unsigned_int }
2915 impl_vec_trait!{ [$Trait $m]+ $w (vector_signed_int, vector_unsigned_int) -> vector_signed_int }
2916 };
2917 }
2918
2919 macro_rules! impl_shift {
2920 ($fun:ident $intr:ident $ty:ident) => {
2921 #[inline]
2922 #[target_feature(enable = "altivec")]
2923 #[cfg_attr(test, assert_instr($fun))]
2924 unsafe fn $fun(a: t_t_l!($ty), b: t_t_l!($ty)) -> t_t_l!($ty) {
2925 let a = transmute(a);
2926 let b = simd_rem(
2927 transmute(b),
2928 <t_t_s!($ty)>::splat(mem::size_of::<$ty>() as $ty * $ty::BITS as $ty),
2929 );
2930
2931 transmute($intr(a, b))
2932 }
2933 };
2934 }
2935
2936 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2937 pub trait VectorSl<Other> {
2938 type Result;
2939 unsafe fn vec_sl(self, b: Other) -> Self::Result;
2940 }
2941
2942 impl_shift! { vslb simd_shl u8 }
2943 impl_shift! { vslh simd_shl u16 }
2944 impl_shift! { vslw simd_shl u32 }
2945
2946 impl_vec_shift! { [VectorSl vec_sl] (vslb, vslh, vslw) }
2947
2948 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2949 pub trait VectorSr<Other> {
2950 type Result;
2951 unsafe fn vec_sr(self, b: Other) -> Self::Result;
2952 }
2953
2954 impl_shift! { vsrb simd_shr u8 }
2955 impl_shift! { vsrh simd_shr u16 }
2956 impl_shift! { vsrw simd_shr u32 }
2957
2958 impl_vec_shift! { [VectorSr vec_sr] (vsrb, vsrh, vsrw) }
2959
2960 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2961 pub trait VectorSra<Other> {
2962 type Result;
2963 unsafe fn vec_sra(self, b: Other) -> Self::Result;
2964 }
2965
2966 impl_vec_shift! { [VectorSra vec_sra] (vsrab, vsrah, vsraw) }
2967
2968 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2969 pub trait VectorSld {
2970 unsafe fn vec_sld<const UIMM4: i32>(self, b: Self) -> Self;
2971 unsafe fn vec_sldw<const UIMM2: i32>(self, b: Self) -> Self;
2972 }
2973
2974 #[inline]
2975 #[target_feature(enable = "altivec")]
2976 #[cfg_attr(test, assert_instr(vsldoi, UIMM4 = 1))]
2977 unsafe fn vsldoi<const UIMM4: i32>(
2978 a: vector_unsigned_char,
2979 b: vector_unsigned_char,
2980 ) -> vector_unsigned_char {
2981 static_assert_uimm_bits!(UIMM4, 4);
2982 let d = UIMM4 as u8;
2983 if cfg!(target_endian = "little") {
2984 let perm = u8x16::new(
2985 16 - d,
2986 17 - d,
2987 18 - d,
2988 19 - d,
2989 20 - d,
2990 21 - d,
2991 22 - d,
2992 23 - d,
2993 24 - d,
2994 25 - d,
2995 26 - d,
2996 27 - d,
2997 28 - d,
2998 29 - d,
2999 30 - d,
3000 31 - d,
3001 );
3002
3003 vec_perm(b, a, transmute(perm))
3004 } else {
3005 let perm = u8x16::new(
3006 d,
3007 d + 1,
3008 d + 2,
3009 d + 3,
3010 d + 4,
3011 d + 5,
3012 d + 6,
3013 d + 7,
3014 d + 8,
3015 d + 9,
3016 d + 10,
3017 d + 11,
3018 d + 12,
3019 d + 13,
3020 d + 14,
3021 d + 15,
3022 );
3023 vec_perm(a, b, transmute(perm))
3024 }
3025 }
3026
3027 #[inline]
3029 #[target_feature(enable = "altivec")]
3030 #[cfg_attr(test, assert_instr(xxsldwi, UIMM2 = 1))]
3031 unsafe fn xxsldwi<const UIMM2: i32>(
3032 a: vector_unsigned_char,
3033 b: vector_unsigned_char,
3034 ) -> vector_unsigned_char {
3035 static_assert_uimm_bits!(UIMM2, 2);
3036 let d = (UIMM2 << 2) as u8;
3037 if cfg!(target_endian = "little") {
3038 let perm = u8x16::new(
3039 16 - d,
3040 17 - d,
3041 18 - d,
3042 19 - d,
3043 20 - d,
3044 21 - d,
3045 22 - d,
3046 23 - d,
3047 24 - d,
3048 25 - d,
3049 26 - d,
3050 27 - d,
3051 28 - d,
3052 29 - d,
3053 30 - d,
3054 31 - d,
3055 );
3056
3057 vec_perm(b, a, transmute(perm))
3058 } else {
3059 let perm = u8x16::new(
3060 d,
3061 d + 1,
3062 d + 2,
3063 d + 3,
3064 d + 4,
3065 d + 5,
3066 d + 6,
3067 d + 7,
3068 d + 8,
3069 d + 9,
3070 d + 10,
3071 d + 11,
3072 d + 12,
3073 d + 13,
3074 d + 14,
3075 d + 15,
3076 );
3077 vec_perm(a, b, transmute(perm))
3078 }
3079 }
3080
3081 macro_rules! impl_vec_sld {
3082 ($($ty:ident),+) => { $(
3083 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
3084 impl VectorSld for $ty {
3085 #[inline]
3086 #[target_feature(enable = "altivec")]
3087 unsafe fn vec_sld<const UIMM4: i32>(self, b: Self) -> Self {
3088 transmute(vsldoi::<UIMM4>(transmute(self), transmute(b)))
3089 }
3090 #[inline]
3091 #[target_feature(enable = "altivec")]
3092 unsafe fn vec_sldw<const UIMM2: i32>(self, b: Self) -> Self {
3093 transmute(xxsldwi::<UIMM2>(transmute(self), transmute(b)))
3094 }
3095 }
3096 )+ };
3097 }
3098
3099 impl_vec_sld! { vector_bool_char, vector_signed_char, vector_unsigned_char }
3100 impl_vec_sld! { vector_bool_short, vector_signed_short, vector_unsigned_short }
3101 impl_vec_sld! { vector_bool_int, vector_signed_int, vector_unsigned_int }
3102 impl_vec_sld! { vector_float }
3103
3104 macro_rules! impl_vec_shift_long {
3105 ([$Trait:ident $m:ident] ($f:ident)) => {
3106 impl_vec_trait!{ [$Trait $m]+ $f (vector_unsigned_char, vector_unsigned_char) -> vector_unsigned_char }
3107 impl_vec_trait!{ [$Trait $m]+ $f (vector_signed_char, vector_unsigned_char) -> vector_signed_char }
3108 impl_vec_trait!{ [$Trait $m]+ $f (vector_unsigned_short, vector_unsigned_char) -> vector_unsigned_short }
3109 impl_vec_trait!{ [$Trait $m]+ $f (vector_signed_short, vector_unsigned_char) -> vector_signed_short }
3110 impl_vec_trait!{ [$Trait $m]+ $f (vector_unsigned_int, vector_unsigned_char) -> vector_unsigned_int }
3111 impl_vec_trait!{ [$Trait $m]+ $f (vector_signed_int, vector_unsigned_char) -> vector_signed_int }
3112 };
3113 }
3114
3115 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
3116 pub trait VectorSll<Other> {
3117 type Result;
3118 unsafe fn vec_sll(self, b: Other) -> Self::Result;
3119 }
3120
3121 impl_vec_shift_long! { [VectorSll vec_sll] (vsl) }
3122
3123 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
3124 pub trait VectorSrl<Other> {
3125 type Result;
3126 unsafe fn vec_srl(self, b: Other) -> Self::Result;
3127 }
3128
3129 impl_vec_shift_long! { [VectorSrl vec_srl] (vsr) }
3130
3131 macro_rules! impl_vec_shift_octect {
3132 ([$Trait:ident $m:ident] ($f:ident)) => {
3133 impl_vec_trait!{ [$Trait $m]+ $f (vector_unsigned_char, vector_signed_char) -> vector_unsigned_char }
3134 impl_vec_trait!{ [$Trait $m]+ $f (vector_signed_char, vector_signed_char) -> vector_signed_char }
3135 impl_vec_trait!{ [$Trait $m]+ $f (vector_unsigned_short, vector_signed_char) -> vector_unsigned_short }
3136 impl_vec_trait!{ [$Trait $m]+ $f (vector_signed_short, vector_signed_char) -> vector_signed_short }
3137 impl_vec_trait!{ [$Trait $m]+ $f (vector_unsigned_int, vector_signed_char) -> vector_unsigned_int }
3138 impl_vec_trait!{ [$Trait $m]+ $f (vector_signed_int, vector_signed_char) -> vector_signed_int }
3139 impl_vec_trait!{ [$Trait $m]+ $f (vector_float, vector_signed_char) -> vector_float }
3140 impl_vec_trait!{ [$Trait $m]+ $f (vector_unsigned_char, vector_unsigned_char) -> vector_unsigned_char }
3141 impl_vec_trait!{ [$Trait $m]+ $f (vector_signed_char, vector_unsigned_char) -> vector_signed_char }
3142 impl_vec_trait!{ [$Trait $m]+ $f (vector_unsigned_short, vector_unsigned_char) -> vector_unsigned_short }
3143 impl_vec_trait!{ [$Trait $m]+ $f (vector_signed_short, vector_unsigned_char) -> vector_signed_short }
3144 impl_vec_trait!{ [$Trait $m]+ $f (vector_unsigned_int, vector_unsigned_char) -> vector_unsigned_int }
3145 impl_vec_trait!{ [$Trait $m]+ $f (vector_signed_int, vector_unsigned_char) -> vector_signed_int }
3146 impl_vec_trait!{ [$Trait $m]+ $f (vector_float, vector_unsigned_char) -> vector_float }
3147 };
3148 }
3149
3150 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
3151 pub trait VectorSlo<Other> {
3152 type Result;
3153 unsafe fn vec_slo(self, b: Other) -> Self::Result;
3154 }
3155
3156 impl_vec_shift_octect! { [VectorSlo vec_slo] (vslo) }
3157
3158 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
3159 pub trait VectorSro<Other> {
3160 type Result;
3161 unsafe fn vec_sro(self, b: Other) -> Self::Result;
3162 }
3163
3164 impl_vec_shift_octect! { [VectorSro vec_sro] (vsro) }
3165
3166 test_impl! { vec_vcntlzb(a: vector_signed_char) -> vector_signed_char [simd_ctlz, vclzb] }
3167 test_impl! { vec_vcntlzh(a: vector_signed_short) -> vector_signed_short [simd_ctlz, vclzh] }
3168 test_impl! { vec_vcntlzw(a: vector_signed_int) -> vector_signed_int [simd_ctlz, vclzw] }
3169
3170 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
3171 pub trait VectorCntlz {
3172 unsafe fn vec_cntlz(self) -> Self;
3173 }
3174
3175 macro_rules! impl_vec_cntlz {
3176 ($fun:ident ($a:ty)) => {
3177 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
3178 impl VectorCntlz for $a {
3179 #[inline]
3180 #[target_feature(enable = "altivec")]
3181 unsafe fn vec_cntlz(self) -> Self {
3182 transmute($fun(transmute(self)))
3183 }
3184 }
3185 };
3186 }
3187
3188 impl_vec_cntlz! { vec_vcntlzb(vector_signed_char) }
3189 impl_vec_cntlz! { vec_vcntlzb(vector_unsigned_char) }
3190 impl_vec_cntlz! { vec_vcntlzh(vector_signed_short) }
3191 impl_vec_cntlz! { vec_vcntlzh(vector_unsigned_short) }
3192 impl_vec_cntlz! { vec_vcntlzw(vector_signed_int) }
3193 impl_vec_cntlz! { vec_vcntlzw(vector_unsigned_int) }
3194
3195 macro_rules! impl_vrl {
3196 ($fun:ident $intr:ident $ty:ident) => {
3197 #[inline]
3198 #[target_feature(enable = "altivec")]
3199 #[cfg_attr(test, assert_instr($fun))]
3200 unsafe fn $fun(a: t_t_l!($ty), b: t_t_l!($ty)) -> t_t_l!($ty) {
3201 transmute($intr(transmute(a), transmute(a), transmute(b)))
3202 }
3203 };
3204 }
3205
3206 impl_vrl! { vrlb fshlb u8 }
3207 impl_vrl! { vrlh fshlh u16 }
3208 impl_vrl! { vrlw fshlw u32 }
3209
3210 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
3211 pub trait VectorRl {
3212 type Shift;
3213 unsafe fn vec_rl(self, b: Self::Shift) -> Self;
3214 }
3215
3216 macro_rules! impl_vec_rl {
3217 ($fun:ident ($a:ident)) => {
3218 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
3219 impl VectorRl for $a {
3220 type Shift = t_u!($a);
3221 #[inline]
3222 #[target_feature(enable = "altivec")]
3223 unsafe fn vec_rl(self, b: Self::Shift) -> Self {
3224 transmute($fun(transmute(self), b))
3225 }
3226 }
3227 };
3228 }
3229
3230 impl_vec_rl! { vrlb(vector_signed_char) }
3231 impl_vec_rl! { vrlh(vector_signed_short) }
3232 impl_vec_rl! { vrlw(vector_signed_int) }
3233 impl_vec_rl! { vrlb(vector_unsigned_char) }
3234 impl_vec_rl! { vrlh(vector_unsigned_short) }
3235 impl_vec_rl! { vrlw(vector_unsigned_int) }
3236
3237 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
3238 pub trait VectorRound {
3239 unsafe fn vec_round(self) -> Self;
3240 }
3241
3242 test_impl! { vec_vrfin(a: vector_float) -> vector_float [vrfin, vrfin] }
3243
3244 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
3245 impl VectorRound for vector_float {
3246 #[inline]
3247 #[target_feature(enable = "altivec")]
3248 unsafe fn vec_round(self) -> Self {
3249 vec_vrfin(self)
3250 }
3251 }
3252}
3253
3254#[inline]
3265#[target_feature(enable = "altivec")]
3266#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3267pub unsafe fn vec_insert<T, const IDX: u32>(a: T, b: <T as sealed::VectorInsert>::Scalar) -> T
3268where
3269 T: sealed::VectorInsert,
3270{
3271 a.vec_insert::<IDX>(b)
3272}
3273
3274#[inline]
3283#[target_feature(enable = "altivec")]
3284#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3285pub unsafe fn vec_extract<T, const IDX: u32>(a: T) -> <T as sealed::VectorExtract>::Scalar
3286where
3287 T: sealed::VectorExtract,
3288{
3289 a.vec_extract::<IDX>()
3290}
3291
3292#[inline]
3294#[target_feature(enable = "altivec")]
3295#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3296pub unsafe fn vec_mergel<T, U>(a: T, b: U) -> <T as sealed::VectorMergel<U>>::Result
3297where
3298 T: sealed::VectorMergel<U>,
3299{
3300 a.vec_mergel(b)
3301}
3302
3303#[inline]
3305#[target_feature(enable = "altivec")]
3306#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3307pub unsafe fn vec_mergeh<T, U>(a: T, b: U) -> <T as sealed::VectorMergeh<U>>::Result
3308where
3309 T: sealed::VectorMergeh<U>,
3310{
3311 a.vec_mergeh(b)
3312}
3313
3314#[inline]
3316#[target_feature(enable = "altivec")]
3317#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3318pub unsafe fn vec_pack<T, U>(a: T, b: U) -> <T as sealed::VectorPack<U>>::Result
3319where
3320 T: sealed::VectorPack<U>,
3321{
3322 a.vec_pack(b)
3323}
3324
3325#[inline]
3327#[target_feature(enable = "altivec")]
3328#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3329pub unsafe fn vec_packs<T, U>(a: T, b: U) -> <T as sealed::VectorPacks<U>>::Result
3330where
3331 T: sealed::VectorPacks<U>,
3332{
3333 a.vec_packs(b)
3334}
3335
3336#[inline]
3338#[target_feature(enable = "altivec")]
3339#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3340pub unsafe fn vec_packsu<T, U>(a: T, b: U) -> <T as sealed::VectorPacksu<U>>::Result
3341where
3342 T: sealed::VectorPacksu<U>,
3343{
3344 a.vec_packsu(b)
3345}
3346
3347#[inline]
3349#[target_feature(enable = "altivec")]
3350#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3351pub unsafe fn vec_unpackh<T>(a: T) -> <T as sealed::VectorUnpackh>::Result
3352where
3353 T: sealed::VectorUnpackh,
3354{
3355 a.vec_unpackh()
3356}
3357
3358#[inline]
3360#[target_feature(enable = "altivec")]
3361#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3362pub unsafe fn vec_unpackl<T>(a: T) -> <T as sealed::VectorUnpackl>::Result
3363where
3364 T: sealed::VectorUnpackl,
3365{
3366 a.vec_unpackl()
3367}
3368
3369#[inline]
3371#[target_feature(enable = "altivec")]
3372#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3373pub unsafe fn vec_sl<T, U>(a: T, b: U) -> <T as sealed::VectorSl<U>>::Result
3374where
3375 T: sealed::VectorSl<U>,
3376{
3377 a.vec_sl(b)
3378}
3379
3380#[inline]
3382#[target_feature(enable = "altivec")]
3383#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3384pub unsafe fn vec_sr<T, U>(a: T, b: U) -> <T as sealed::VectorSr<U>>::Result
3385where
3386 T: sealed::VectorSr<U>,
3387{
3388 a.vec_sr(b)
3389}
3390
3391#[inline]
3393#[target_feature(enable = "altivec")]
3394#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3395pub unsafe fn vec_sra<T, U>(a: T, b: U) -> <T as sealed::VectorSra<U>>::Result
3396where
3397 T: sealed::VectorSra<U>,
3398{
3399 a.vec_sra(b)
3400}
3401
3402#[inline]
3416#[target_feature(enable = "altivec")]
3417#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3418pub unsafe fn vec_sld<T, const UIMM4: i32>(a: T, b: T) -> T
3419where
3420 T: sealed::VectorSld,
3421{
3422 a.vec_sld::<UIMM4>(b)
3423}
3424
3425#[inline]
3435#[target_feature(enable = "altivec")]
3436#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3437pub unsafe fn vec_sldw<T, const UIMM2: i32>(a: T, b: T) -> T
3438where
3439 T: sealed::VectorSld,
3440{
3441 a.vec_sldw::<UIMM2>(b)
3442}
3443
3444#[inline]
3450#[target_feature(enable = "altivec")]
3451#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3452pub unsafe fn vec_sll<T, U>(a: T, b: U) -> <T as sealed::VectorSll<U>>::Result
3453where
3454 T: sealed::VectorSll<U>,
3455{
3456 a.vec_sll(b)
3457}
3458
3459#[inline]
3465#[target_feature(enable = "altivec")]
3466#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3467pub unsafe fn vec_srl<T, U>(a: T, b: U) -> <T as sealed::VectorSrl<U>>::Result
3468where
3469 T: sealed::VectorSrl<U>,
3470{
3471 a.vec_srl(b)
3472}
3473
3474#[inline]
3481#[target_feature(enable = "altivec")]
3482#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3483pub unsafe fn vec_slo<T, U>(a: T, b: U) -> <T as sealed::VectorSlo<U>>::Result
3484where
3485 T: sealed::VectorSlo<U>,
3486{
3487 a.vec_slo(b)
3488}
3489
3490#[inline]
3497#[target_feature(enable = "altivec")]
3498#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3499pub unsafe fn vec_sro<T, U>(a: T, b: U) -> <T as sealed::VectorSro<U>>::Result
3500where
3501 T: sealed::VectorSro<U>,
3502{
3503 a.vec_sro(b)
3504}
3505
3506#[inline]
3518#[target_feature(enable = "power9-altivec")]
3519#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3520pub unsafe fn vec_slv(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char {
3521 vslv(a, b)
3522}
3523
3524#[inline]
3536#[target_feature(enable = "power9-altivec")]
3537#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3538pub unsafe fn vec_srv(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char {
3539 vsrv(a, b)
3540}
3541
3542#[inline]
3544#[target_feature(enable = "altivec")]
3545#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3546pub unsafe fn vec_ld<T>(off: isize, p: T) -> <T as sealed::VectorLd>::Result
3547where
3548 T: sealed::VectorLd,
3549{
3550 p.vec_ld(off)
3551}
3552
3553#[inline]
3555#[target_feature(enable = "altivec")]
3556#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3557pub unsafe fn vec_ldl<T>(off: isize, p: T) -> <T as sealed::VectorLd>::Result
3558where
3559 T: sealed::VectorLd,
3560{
3561 p.vec_ldl(off)
3562}
3563
3564#[inline]
3566#[target_feature(enable = "altivec")]
3567#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3568pub unsafe fn vec_lde<T>(off: isize, p: T) -> <T as sealed::VectorLde>::Result
3569where
3570 T: sealed::VectorLde,
3571{
3572 p.vec_lde(off)
3573}
3574
3575#[inline]
3585#[target_feature(enable = "altivec")]
3586#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3587pub unsafe fn vec_st<T>(a: T, off: isize, c: <T as sealed::VectorSt>::Target)
3588where
3589 T: sealed::VectorSt,
3590{
3591 a.vec_st(off, c)
3592}
3593
3594#[inline]
3610#[target_feature(enable = "altivec")]
3611#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3612pub unsafe fn vec_stl<T>(a: T, off: isize, c: <T as sealed::VectorSt>::Target)
3613where
3614 T: sealed::VectorSt,
3615{
3616 a.vec_stl(off, c)
3617}
3618
3619#[inline]
3636#[target_feature(enable = "altivec")]
3637#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3638pub unsafe fn vec_ste<T>(a: T, off: isize, c: <T as sealed::VectorSte>::Target)
3639where
3640 T: sealed::VectorSte,
3641{
3642 a.vec_ste(off, c)
3643}
3644
3645#[inline]
3647#[target_feature(enable = "altivec")]
3648#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3649pub unsafe fn vec_xl<T>(off: isize, p: T) -> <T as sealed::VectorXl>::Result
3650where
3651 T: sealed::VectorXl,
3652{
3653 p.vec_xl(off)
3654}
3655
3656#[inline]
3658#[target_feature(enable = "altivec")]
3659#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3660pub unsafe fn vec_xst<T>(v: T, off: isize, p: <T as sealed::VectorXst>::Out)
3661where
3662 T: sealed::VectorXst,
3663{
3664 v.vec_xst(off, p)
3665}
3666
3667#[inline]
3669#[target_feature(enable = "altivec")]
3670#[cfg_attr(test, assert_instr(vlogefp))]
3671#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3672pub unsafe fn vec_loge(a: vector_float) -> vector_float {
3673 vlogefp(a)
3674}
3675
3676#[inline]
3678#[target_feature(enable = "altivec")]
3679#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3680pub unsafe fn vec_floor(a: vector_float) -> vector_float {
3681 sealed::vec_floor(a)
3682}
3683
3684#[inline]
3686#[target_feature(enable = "altivec")]
3687#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3688pub unsafe fn vec_expte(a: vector_float) -> vector_float {
3689 sealed::vec_vexptefp(a)
3690}
3691
3692#[inline]
3694#[target_feature(enable = "altivec")]
3695#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3696pub unsafe fn vec_cmplt<T, U>(a: U, b: T) -> <T as sealed::VectorCmpGt<U>>::Result
3697where
3698 T: sealed::VectorCmpGt<U>,
3699{
3700 vec_cmpgt(b, a)
3701}
3702
3703#[inline]
3705#[target_feature(enable = "altivec")]
3706#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3707pub unsafe fn vec_cmple(a: vector_float, b: vector_float) -> vector_bool_int {
3708 vec_cmpge(b, a)
3709}
3710
3711#[inline]
3713#[target_feature(enable = "altivec")]
3714#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3715pub unsafe fn vec_cmpgt<T, U>(a: T, b: U) -> <T as sealed::VectorCmpGt<U>>::Result
3716where
3717 T: sealed::VectorCmpGt<U>,
3718{
3719 a.vec_cmpgt(b)
3720}
3721
3722#[inline]
3724#[target_feature(enable = "altivec")]
3725#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3726pub unsafe fn vec_cmpge(a: vector_float, b: vector_float) -> vector_bool_int {
3727 sealed::vec_vcmpgefp(a, b)
3728}
3729
3730#[inline]
3732#[target_feature(enable = "altivec")]
3733#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3734pub unsafe fn vec_cmpeq<T, U>(a: T, b: U) -> <T as sealed::VectorCmpEq<U>>::Result
3735where
3736 T: sealed::VectorCmpEq<U>,
3737{
3738 a.vec_cmpeq(b)
3739}
3740
3741#[inline]
3747#[target_feature(enable = "altivec")]
3748#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3749pub unsafe fn vec_cmpne<T, U>(a: T, b: U) -> <T as sealed::VectorCmpNe<U>>::Result
3750where
3751 T: sealed::VectorCmpNe<U>,
3752{
3753 a.vec_cmpne(b)
3754}
3755
3756#[inline]
3758#[target_feature(enable = "altivec")]
3759#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3760pub unsafe fn vec_cmpb(a: vector_float, b: vector_float) -> vector_signed_int {
3761 sealed::vec_vcmpbfp(a, b)
3762}
3763
3764#[inline]
3766#[target_feature(enable = "altivec")]
3767#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3768pub unsafe fn vec_ceil(a: vector_float) -> vector_float {
3769 sealed::vec_vceil(a)
3770}
3771
3772#[inline]
3774#[target_feature(enable = "altivec")]
3775#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3776pub unsafe fn vec_avg<T, U>(a: T, b: U) -> <T as sealed::VectorAvg<U>>::Result
3777where
3778 T: sealed::VectorAvg<U>,
3779{
3780 a.vec_avg(b)
3781}
3782
3783#[inline]
3785#[target_feature(enable = "altivec")]
3786#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3787pub unsafe fn vec_andc<T, U>(a: T, b: U) -> <T as sealed::VectorAndc<U>>::Result
3788where
3789 T: sealed::VectorAndc<U>,
3790{
3791 a.vec_andc(b)
3792}
3793
3794#[inline]
3802#[target_feature(enable = "altivec")]
3803#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3804pub unsafe fn vec_orc<T, U>(a: T, b: U) -> <T as sealed::VectorOrc<U>>::Result
3805where
3806 T: sealed::VectorOrc<U>,
3807{
3808 a.vec_orc(b)
3809}
3810
3811#[inline]
3813#[target_feature(enable = "altivec")]
3814#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3815pub unsafe fn vec_and<T, U>(a: T, b: U) -> <T as sealed::VectorAnd<U>>::Result
3816where
3817 T: sealed::VectorAnd<U>,
3818{
3819 a.vec_and(b)
3820}
3821
3822#[inline]
3824#[target_feature(enable = "altivec")]
3825#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3826pub unsafe fn vec_or<T, U>(a: T, b: U) -> <T as sealed::VectorOr<U>>::Result
3827where
3828 T: sealed::VectorOr<U>,
3829{
3830 a.vec_or(b)
3831}
3832
3833#[inline]
3841#[target_feature(enable = "altivec")]
3842#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3843pub unsafe fn vec_nand<T, U>(a: T, b: U) -> <T as sealed::VectorNand<U>>::Result
3844where
3845 T: sealed::VectorNand<U>,
3846{
3847 a.vec_nand(b)
3848}
3849
3850#[inline]
3852#[target_feature(enable = "altivec")]
3853#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3854pub unsafe fn vec_nor<T, U>(a: T, b: U) -> <T as sealed::VectorNor<U>>::Result
3855where
3856 T: sealed::VectorNor<U>,
3857{
3858 a.vec_nor(b)
3859}
3860
3861#[inline]
3863#[target_feature(enable = "altivec")]
3864#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3865pub unsafe fn vec_xor<T, U>(a: T, b: U) -> <T as sealed::VectorXor<U>>::Result
3866where
3867 T: sealed::VectorXor<U>,
3868{
3869 a.vec_xor(b)
3870}
3871
3872#[inline]
3874#[target_feature(enable = "altivec")]
3875#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3876pub unsafe fn vec_adds<T, U>(a: T, b: U) -> <T as sealed::VectorAdds<U>>::Result
3877where
3878 T: sealed::VectorAdds<U>,
3879{
3880 a.vec_adds(b)
3881}
3882
3883#[inline]
3885#[target_feature(enable = "altivec")]
3886#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3887pub unsafe fn vec_addc(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int {
3888 sealed::vec_vaddcuw(a, b)
3889}
3890
3891#[inline]
3893#[target_feature(enable = "altivec")]
3894#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3895pub unsafe fn vec_abs<T>(a: T) -> T
3896where
3897 T: sealed::VectorAbs,
3898{
3899 a.vec_abs()
3900}
3901
3902#[inline]
3904#[target_feature(enable = "altivec")]
3905#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3906pub unsafe fn vec_abss<T>(a: T) -> T
3907where
3908 T: sealed::VectorAbss,
3909{
3910 a.vec_abss()
3911}
3912
3913#[inline]
3922#[target_feature(enable = "altivec")]
3923#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3924pub unsafe fn vec_rl<T>(a: T, b: <T as sealed::VectorRl>::Shift) -> T
3925where
3926 T: sealed::VectorRl,
3927{
3928 a.vec_rl(b)
3929}
3930
3931#[inline]
3943#[target_feature(enable = "altivec")]
3944#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3945pub unsafe fn vec_round<T>(a: T) -> T
3946where
3947 T: sealed::VectorRound,
3948{
3949 a.vec_round()
3950}
3951
3952#[inline]
3954#[target_feature(enable = "altivec")]
3955#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3956pub unsafe fn vec_splat<T, const IMM: u32>(a: T) -> T
3957where
3958 T: sealed::VectorSplat,
3959{
3960 a.vec_splat::<IMM>()
3961}
3962
3963splat! { vec_splat_u8, u8, u8x16 [vspltisb / xxspltib, "Vector Splat to Unsigned Byte"] }
3964splat! { vec_splat_s8, i8, i8x16 [vspltisb / xxspltib, "Vector Splat to Signed Byte"] }
3965splat! { vec_splat_u16, u16, u16x8 [vspltish, "Vector Splat to Unsigned Halfword"] }
3966splat! { vec_splat_s16, i16, i16x8 [vspltish, "Vector Splat to Signed Halfword"] }
3967splat! { vec_splat_u32, u32, u32x4 [vspltisw, "Vector Splat to Unsigned Word"] }
3968splat! { vec_splat_s32, i32, i32x4 [vspltisw, "Vector Splat to Signed Word"] }
3969
3970#[inline]
3972#[target_feature(enable = "altivec")]
3973#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3974pub unsafe fn vec_splats<T>(a: T) -> <T as sealed::VectorSplats>::Result
3975where
3976 T: sealed::VectorSplats,
3977{
3978 a.vec_splats()
3979}
3980
3981#[inline]
3983#[target_feature(enable = "altivec")]
3984#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3985pub unsafe fn vec_sub<T, U>(a: T, b: U) -> <T as sealed::VectorSub<U>>::Result
3986where
3987 T: sealed::VectorSub<U>,
3988{
3989 a.vec_sub(b)
3990}
3991
3992#[inline]
4003#[target_feature(enable = "altivec")]
4004#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4005pub unsafe fn vec_subc<T, U>(a: T, b: U) -> <T as sealed::VectorSubc<U>>::Result
4006where
4007 T: sealed::VectorSubc<U>,
4008{
4009 a.vec_subc(b)
4010}
4011
4012#[inline]
4014#[target_feature(enable = "altivec")]
4015#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4016pub unsafe fn vec_subs<T, U>(a: T, b: U) -> <T as sealed::VectorSubs<U>>::Result
4017where
4018 T: sealed::VectorSubs<U>,
4019{
4020 a.vec_subs(b)
4021}
4022
4023#[inline]
4025#[target_feature(enable = "altivec")]
4026#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4027pub unsafe fn vec_min<T, U>(a: T, b: U) -> <T as sealed::VectorMin<U>>::Result
4028where
4029 T: sealed::VectorMin<U>,
4030{
4031 a.vec_min(b)
4032}
4033
4034#[inline]
4036#[target_feature(enable = "altivec")]
4037#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4038pub unsafe fn vec_max<T, U>(a: T, b: U) -> <T as sealed::VectorMax<U>>::Result
4039where
4040 T: sealed::VectorMax<U>,
4041{
4042 a.vec_max(b)
4043}
4044
4045#[inline]
4047#[target_feature(enable = "altivec")]
4048#[cfg_attr(test, assert_instr(mfvscr))]
4049#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4050pub unsafe fn vec_mfvscr() -> vector_unsigned_short {
4051 mfvscr()
4052}
4053
4054#[inline]
4056#[target_feature(enable = "altivec")]
4057#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4058pub unsafe fn vec_add<T, U>(a: T, b: U) -> <T as sealed::VectorAdd<U>>::Result
4059where
4060 T: sealed::VectorAdd<U>,
4061{
4062 a.vec_add(b)
4063}
4064
4065#[inline]
4072#[target_feature(enable = "altivec")]
4073#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4074pub unsafe fn vec_adde<T>(a: T, b: T, c: T) -> T
4075where
4076 T: sealed::VectorAdde,
4077{
4078 a.vec_adde(b, c)
4079}
4080
4081#[inline]
4083#[target_feature(enable = "altivec")]
4084#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4085pub unsafe fn vec_ctf<const IMM5: i32, T>(a: T) -> vector_float
4086where
4087 T: sealed::VectorCtf,
4088{
4089 a.vec_ctf::<IMM5>()
4090}
4091
4092#[inline]
4094#[target_feature(enable = "altivec")]
4095#[cfg_attr(test, assert_instr(vctsxs, IMM5 = 1))]
4096#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4097pub unsafe fn vec_cts<const IMM5: i32>(a: vector_float) -> vector_signed_int {
4098 static_assert_uimm_bits!(IMM5, 5);
4099
4100 vctsxs(a, IMM5)
4101}
4102
4103#[inline]
4105#[target_feature(enable = "altivec")]
4106#[cfg_attr(test, assert_instr(vctuxs, IMM5 = 1))]
4107#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4108pub unsafe fn vec_ctu<const IMM5: i32>(a: vector_float) -> vector_unsigned_int {
4109 static_assert_uimm_bits!(IMM5, 5);
4110
4111 vctuxs(a, IMM5)
4112}
4113
4114#[cfg(target_endian = "little")]
4116mod endian {
4117 use super::*;
4118 #[inline]
4120 #[target_feature(enable = "altivec")]
4121 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
4122 pub unsafe fn vec_perm<T>(a: T, b: T, c: vector_unsigned_char) -> T
4123 where
4124 T: sealed::VectorPerm,
4125 {
4126 let d = transmute(u8x16::new(
4130 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
4131 ));
4132 let c = simd_xor(c, d);
4133
4134 b.vec_vperm(a, c)
4135 }
4136
4137 #[inline]
4139 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
4140 #[target_feature(enable = "altivec")]
4141 pub unsafe fn vec_sum2s(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int {
4142 let flip = transmute(u8x16::new(
4146 4, 5, 6, 7, 0, 1, 2, 3, 12, 13, 14, 15, 8, 9, 10, 11,
4147 ));
4148 let b = vec_perm(b, b, flip);
4149 let c = vsum2sws(a, b);
4150
4151 vec_perm(c, c, flip)
4152 }
4153
4154 #[inline]
4157 #[target_feature(enable = "altivec")]
4158 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
4159 pub unsafe fn vec_mule<T, U>(a: T, b: T) -> U
4160 where
4161 T: sealed::VectorMulo<U>,
4162 {
4163 a.vec_mulo(b)
4164 }
4165 #[inline]
4167 #[target_feature(enable = "altivec")]
4168 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
4169 pub unsafe fn vec_mulo<T, U>(a: T, b: T) -> U
4170 where
4171 T: sealed::VectorMule<U>,
4172 {
4173 a.vec_mule(b)
4174 }
4175}
4176
4177#[inline]
4185#[target_feature(enable = "altivec")]
4186#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4187pub unsafe fn vec_mul<T>(a: T, b: T) -> T
4188where
4189 T: sealed::VectorMul,
4190{
4191 a.vec_mul(b)
4192}
4193
4194#[inline]
4196#[target_feature(enable = "altivec")]
4197#[cfg_attr(test, assert_instr(vmhaddshs))]
4198#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4199pub unsafe fn vec_madds(
4200 a: vector_signed_short,
4201 b: vector_signed_short,
4202 c: vector_signed_short,
4203) -> vector_signed_short {
4204 vmhaddshs(a, b, c)
4205}
4206
4207#[inline]
4209#[target_feature(enable = "altivec")]
4210#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4211pub unsafe fn vec_mladd<T, U>(a: T, b: U, c: U) -> <T as sealed::VectorMladd<U>>::Result
4212where
4213 T: sealed::VectorMladd<U>,
4214{
4215 a.vec_mladd(b, c)
4216}
4217
4218#[inline]
4220#[target_feature(enable = "altivec")]
4221#[cfg_attr(test, assert_instr(vmhraddshs))]
4222#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4223pub unsafe fn vec_mradds(
4224 a: vector_signed_short,
4225 b: vector_signed_short,
4226 c: vector_signed_short,
4227) -> vector_signed_short {
4228 vmhraddshs(a, b, c)
4229}
4230
4231#[inline]
4233#[target_feature(enable = "altivec")]
4234#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4235pub unsafe fn vec_msum<T, B, U>(a: T, b: B, c: U) -> U
4236where
4237 T: sealed::VectorMsum<B, U>,
4238{
4239 a.vec_msum(b, c)
4240}
4241
4242#[inline]
4244#[target_feature(enable = "altivec")]
4245#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4246pub unsafe fn vec_msums<T, U>(a: T, b: T, c: U) -> U
4247where
4248 T: sealed::VectorMsums<U>,
4249{
4250 a.vec_msums(b, c)
4251}
4252
4253#[inline]
4255#[target_feature(enable = "altivec")]
4256#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4257pub unsafe fn vec_madd(a: vector_float, b: vector_float, c: vector_float) -> vector_float {
4258 sealed::vec_vmaddfp(a, b, c)
4259}
4260
4261#[inline]
4263#[target_feature(enable = "altivec")]
4264#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4265pub unsafe fn vec_nmsub(a: vector_float, b: vector_float, c: vector_float) -> vector_float {
4266 vnmsubfp(a, b, c)
4267}
4268
4269#[inline]
4279#[target_feature(enable = "altivec")]
4280#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4281pub unsafe fn vec_sel<T, U>(a: T, b: T, c: U) -> T
4282where
4283 T: sealed::VectorSel<U>,
4284{
4285 a.vec_sel(b, c)
4286}
4287
4288#[inline]
4290#[target_feature(enable = "altivec")]
4291#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4292pub unsafe fn vec_sum4s<T, U>(a: T, b: U) -> U
4293where
4294 T: sealed::VectorSum4s<U>,
4295{
4296 a.vec_sum4s(b)
4297}
4298
4299#[inline]
4301#[target_feature(enable = "altivec")]
4302#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4303pub unsafe fn vec_all_eq<T, U>(a: T, b: U) -> <T as sealed::VectorAllEq<U>>::Result
4304where
4305 T: sealed::VectorAllEq<U>,
4306{
4307 a.vec_all_eq(b)
4308}
4309
4310#[inline]
4312#[target_feature(enable = "altivec")]
4313#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4314pub unsafe fn vec_any_eq<T, U>(a: T, b: U) -> <T as sealed::VectorAnyEq<U>>::Result
4315where
4316 T: sealed::VectorAnyEq<U>,
4317{
4318 a.vec_any_eq(b)
4319}
4320
4321#[inline]
4323#[target_feature(enable = "altivec")]
4324#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4325pub unsafe fn vec_all_ge<T, U>(a: T, b: U) -> <T as sealed::VectorAllGe<U>>::Result
4326where
4327 T: sealed::VectorAllGe<U>,
4328{
4329 a.vec_all_ge(b)
4330}
4331
4332#[inline]
4334#[target_feature(enable = "altivec")]
4335#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4336pub unsafe fn vec_any_ge<T, U>(a: T, b: U) -> <T as sealed::VectorAnyGe<U>>::Result
4337where
4338 T: sealed::VectorAnyGe<U>,
4339{
4340 a.vec_any_ge(b)
4341}
4342
4343#[inline]
4345#[target_feature(enable = "altivec")]
4346#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4347pub unsafe fn vec_all_gt<T, U>(a: T, b: U) -> <T as sealed::VectorAllGt<U>>::Result
4348where
4349 T: sealed::VectorAllGt<U>,
4350{
4351 a.vec_all_gt(b)
4352}
4353
4354#[inline]
4356#[target_feature(enable = "altivec")]
4357#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4358pub unsafe fn vec_any_gt<T, U>(a: T, b: U) -> <T as sealed::VectorAnyGt<U>>::Result
4359where
4360 T: sealed::VectorAnyGt<U>,
4361{
4362 a.vec_any_gt(b)
4363}
4364
4365#[inline]
4367#[target_feature(enable = "altivec")]
4368#[cfg_attr(test, assert_instr("vcmpbfp."))]
4369#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4370pub unsafe fn vec_all_in(a: vector_float, b: vector_float) -> bool {
4371 vcmpbfp_p(0, a, b) != 0
4372}
4373
4374#[inline]
4376#[target_feature(enable = "altivec")]
4377#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4378pub unsafe fn vec_all_le<T, U>(a: U, b: T) -> <T as sealed::VectorAllGe<U>>::Result
4379where
4380 T: sealed::VectorAllGe<U>,
4381{
4382 b.vec_all_ge(a)
4383}
4384
4385#[inline]
4387#[target_feature(enable = "altivec")]
4388#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4389pub unsafe fn vec_any_le<T, U>(a: U, b: T) -> <T as sealed::VectorAnyGe<U>>::Result
4390where
4391 T: sealed::VectorAnyGe<U>,
4392{
4393 b.vec_any_ge(a)
4394}
4395
4396#[inline]
4398#[target_feature(enable = "altivec")]
4399#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4400pub unsafe fn vec_all_lt<T, U>(a: U, b: T) -> <T as sealed::VectorAllGt<U>>::Result
4401where
4402 T: sealed::VectorAllGt<U>,
4403{
4404 b.vec_all_gt(a)
4405}
4406
4407#[inline]
4409#[target_feature(enable = "altivec")]
4410#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4411pub unsafe fn vec_any_lt<T, U>(a: U, b: T) -> <T as sealed::VectorAnyGt<U>>::Result
4412where
4413 T: sealed::VectorAnyGt<U>,
4414{
4415 b.vec_any_gt(a)
4416}
4417
4418#[inline]
4420#[target_feature(enable = "altivec")]
4421#[cfg_attr(test, assert_instr("vcmpeqfp."))]
4422#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4423pub unsafe fn vec_all_nan(a: vector_float) -> bool {
4424 vcmpeqfp_p(0, a, a) != 0
4425}
4426
4427#[inline]
4429#[target_feature(enable = "altivec")]
4430#[cfg_attr(test, assert_instr("vcmpeqfp."))]
4431#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4432pub unsafe fn vec_any_nan(a: vector_float) -> bool {
4433 vcmpeqfp_p(3, a, a) != 0
4434}
4435
4436#[inline]
4438#[target_feature(enable = "altivec")]
4439#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4440pub unsafe fn vec_all_ne<T, U>(a: T, b: U) -> <T as sealed::VectorAllNe<U>>::Result
4441where
4442 T: sealed::VectorAllNe<U>,
4443{
4444 a.vec_all_ne(b)
4445}
4446
4447#[inline]
4449#[target_feature(enable = "altivec")]
4450#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4451pub unsafe fn vec_any_ne<T, U>(a: T, b: U) -> <T as sealed::VectorAnyNe<U>>::Result
4452where
4453 T: sealed::VectorAnyNe<U>,
4454{
4455 a.vec_any_ne(b)
4456}
4457
4458#[inline]
4460#[target_feature(enable = "altivec")]
4461#[cfg_attr(test, assert_instr("vcmpgefp."))]
4462#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4463pub unsafe fn vec_all_nge(a: vector_float, b: vector_float) -> bool {
4464 vcmpgefp_p(0, a, b) != 0
4465}
4466
4467#[inline]
4469#[target_feature(enable = "altivec")]
4470#[cfg_attr(test, assert_instr("vcmpgtfp."))]
4471#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4472pub unsafe fn vec_all_ngt(a: vector_float, b: vector_float) -> bool {
4473 vcmpgtfp_p(0, a, b) != 0
4474}
4475
4476#[inline]
4478#[target_feature(enable = "altivec")]
4479#[cfg_attr(test, assert_instr("vcmpgefp."))]
4480#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4481pub unsafe fn vec_all_nle(a: vector_float, b: vector_float) -> bool {
4482 vcmpgefp_p(0, b, a) != 0
4483}
4484
4485#[inline]
4487#[target_feature(enable = "altivec")]
4488#[cfg_attr(test, assert_instr("vcmpgtfp."))]
4489#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4490pub unsafe fn vec_all_nlt(a: vector_float, b: vector_float) -> bool {
4491 vcmpgtfp_p(0, b, a) != 0
4492}
4493
4494#[inline]
4496#[target_feature(enable = "altivec")]
4497#[cfg_attr(test, assert_instr("vcmpgefp."))]
4498#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4499pub unsafe fn vec_all_numeric(a: vector_float) -> bool {
4500 vcmpgefp_p(2, a, a) != 0
4501}
4502
4503#[inline]
4505#[target_feature(enable = "altivec")]
4506#[cfg_attr(test, assert_instr("vcmpgefp."))]
4507#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4508pub unsafe fn vec_any_nge(a: vector_float, b: vector_float) -> bool {
4509 vcmpgefp_p(3, a, b) != 0
4510}
4511
4512#[inline]
4514#[target_feature(enable = "altivec")]
4515#[cfg_attr(test, assert_instr("vcmpgtfp."))]
4516#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4517pub unsafe fn vec_any_ngt(a: vector_float, b: vector_float) -> bool {
4518 vcmpgtfp_p(3, a, b) != 0
4519}
4520
4521#[inline]
4523#[target_feature(enable = "altivec")]
4524#[cfg_attr(test, assert_instr("vcmpgefp."))]
4525#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4526pub unsafe fn vec_any_nle(a: vector_float, b: vector_float) -> bool {
4527 vcmpgefp_p(3, b, a) != 0
4528}
4529
4530#[inline]
4532#[target_feature(enable = "altivec")]
4533#[cfg_attr(test, assert_instr("vcmpgtfp."))]
4534#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4535pub unsafe fn vec_any_nlt(a: vector_float, b: vector_float) -> bool {
4536 vcmpgtfp_p(3, b, a) != 0
4537}
4538
4539#[inline]
4541#[target_feature(enable = "altivec")]
4542#[cfg_attr(test, assert_instr("vcmpgefp."))]
4543#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4544pub unsafe fn vec_any_numeric(a: vector_float) -> bool {
4545 vcmpgefp_p(1, a, a) != 0
4546}
4547
4548#[inline]
4558#[target_feature(enable = "altivec")]
4559#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4560pub unsafe fn vec_cntlz<T>(a: T) -> T
4561where
4562 T: sealed::VectorCntlz,
4563{
4564 a.vec_cntlz()
4565}
4566
4567#[inline]
4569#[target_feature(enable = "altivec")]
4570#[cfg_attr(test, assert_instr("vcmpeqfp."))]
4571#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4572pub unsafe fn vec_any_out(a: vector_float) -> bool {
4573 vcmpeqfp_p(1, a, a) != 0
4574}
4575
4576#[cfg(target_endian = "big")]
4577mod endian {
4578 use super::*;
4579 #[inline]
4581 #[target_feature(enable = "altivec")]
4582 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
4583 pub unsafe fn vec_perm<T>(a: T, b: T, c: vector_unsigned_char) -> T
4584 where
4585 T: sealed::VectorPerm,
4586 {
4587 a.vec_vperm(b, c)
4588 }
4589
4590 #[inline]
4592 #[target_feature(enable = "altivec")]
4593 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
4594 pub unsafe fn vec_sum2s(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int {
4595 vsum2sws(a, b)
4596 }
4597
4598 #[inline]
4600 #[target_feature(enable = "altivec")]
4601 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
4602 pub unsafe fn vec_mule<T, U>(a: T, b: T) -> U
4603 where
4604 T: sealed::VectorMule<U>,
4605 {
4606 a.vec_mule(b)
4607 }
4608 #[inline]
4610 #[target_feature(enable = "altivec")]
4611 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
4612 pub unsafe fn vec_mulo<T, U>(a: T, b: T) -> U
4613 where
4614 T: sealed::VectorMulo<U>,
4615 {
4616 a.vec_mulo(b)
4617 }
4618}
4619
4620#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4621pub use self::endian::*;
4622
4623#[cfg(test)]
4624mod tests {
4625 use super::*;
4626
4627 use std::mem::transmute;
4628
4629 use crate::core_arch::simd::*;
4630 use stdarch_test::simd_test;
4631
4632 macro_rules! test_vec_2 {
4633 { $name: ident, $fn:ident, $ty: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => {
4634 test_vec_2! { $name, $fn, $ty -> $ty, [$($a),+], [$($b),+], [$($d),+] }
4635 };
4636 { $name: ident, $fn:ident, $ty: ident -> $ty_out: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => {
4637 #[simd_test(enable = "altivec")]
4638 unsafe fn $name() {
4639 let a: s_t_l!($ty) = transmute($ty::new($($a),+));
4640 let b: s_t_l!($ty) = transmute($ty::new($($b),+));
4641
4642 let d = $ty_out::new($($d),+);
4643 let r : $ty_out = transmute($fn(a, b));
4644 assert_eq!(d, r);
4645 }
4646 };
4647 { $name: ident, $fn:ident, $ty: ident -> $ty_out: ident, [$($a:expr),+], [$($b:expr),+], $d:expr } => {
4648 #[simd_test(enable = "altivec")]
4649 unsafe fn $name() {
4650 let a: s_t_l!($ty) = transmute($ty::new($($a),+));
4651 let b: s_t_l!($ty) = transmute($ty::new($($b),+));
4652
4653 let r : $ty_out = transmute($fn(a, b));
4654 assert_eq!($d, r);
4655 }
4656 }
4657 }
4658
4659 macro_rules! test_vec_1 {
4660 { $name: ident, $fn:ident, f32x4, [$($a:expr),+], ~[$($d:expr),+] } => {
4661 #[simd_test(enable = "altivec")]
4662 unsafe fn $name() {
4663 let a: vector_float = transmute(f32x4::new($($a),+));
4664
4665 let d: vector_float = transmute(f32x4::new($($d),+));
4666 let r = transmute(vec_cmple(vec_abs(vec_sub($fn(a), d)), vec_splats(f32::EPSILON)));
4667 let e = m32x4::new(true, true, true, true);
4668 assert_eq!(e, r);
4669 }
4670 };
4671 { $name: ident, $fn:ident, $ty: ident, [$($a:expr),+], [$($d:expr),+] } => {
4672 test_vec_1! { $name, $fn, $ty -> $ty, [$($a),+], [$($d),+] }
4673 };
4674 { $name: ident, $fn:ident, $ty: ident -> $ty_out: ident, [$($a:expr),+], [$($d:expr),+] } => {
4675 #[simd_test(enable = "altivec")]
4676 unsafe fn $name() {
4677 let a: s_t_l!($ty) = transmute($ty::new($($a),+));
4678
4679 let d = $ty_out::new($($d),+);
4680 let r : $ty_out = transmute($fn(a));
4681 assert_eq!(d, r);
4682 }
4683 }
4684 }
4685
4686 #[simd_test(enable = "altivec")]
4687 unsafe fn test_vec_ld() {
4688 let pat = [
4689 u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15),
4690 u8x16::new(
4691 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
4692 ),
4693 ];
4694
4695 for off in 0..16 {
4696 let v: u8x16 = transmute(vec_ld(0, (pat.as_ptr() as *const u8).offset(off)));
4697 assert_eq!(
4698 v,
4699 u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
4700 );
4701 }
4702 for off in 16..32 {
4703 let v: u8x16 = transmute(vec_ld(0, (pat.as_ptr() as *const u8).offset(off)));
4704 assert_eq!(
4705 v,
4706 u8x16::new(
4707 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
4708 )
4709 );
4710 }
4711 }
4712
4713 #[simd_test(enable = "altivec")]
4714 unsafe fn test_vec_xl() {
4715 let pat = [
4716 u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15),
4717 u8x16::new(
4718 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
4719 ),
4720 ];
4721
4722 for off in 0..16 {
4723 let val: u8x16 = transmute(vec_xl(0, (pat.as_ptr() as *const u8).offset(off)));
4724 for i in 0..16 {
4725 let v = val.extract(i);
4726 assert_eq!(off as usize + i, v as usize);
4727 }
4728 }
4729 }
4730
4731 #[simd_test(enable = "altivec")]
4732 unsafe fn test_vec_xst() {
4733 let v: vector_unsigned_char = transmute(u8x16::new(
4734 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
4735 ));
4736
4737 for off in 0..16 {
4738 let mut buf = [0u8; 32];
4739 vec_xst(v, 0, (buf.as_mut_ptr() as *mut u8).offset(off));
4740 for i in 0..16 {
4741 assert_eq!(i as u8, buf[off as usize..][i]);
4742 }
4743 }
4744 }
4745
4746 #[simd_test(enable = "altivec")]
4747 unsafe fn test_vec_ldl() {
4748 let pat = [
4749 u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15),
4750 u8x16::new(
4751 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
4752 ),
4753 ];
4754
4755 for off in 0..16 {
4756 let v: u8x16 = transmute(vec_ldl(0, (pat.as_ptr() as *const u8).offset(off)));
4757 assert_eq!(
4758 v,
4759 u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
4760 );
4761 }
4762 for off in 16..32 {
4763 let v: u8x16 = transmute(vec_ldl(0, (pat.as_ptr() as *const u8).offset(off)));
4764 assert_eq!(
4765 v,
4766 u8x16::new(
4767 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
4768 )
4769 );
4770 }
4771 }
4772
4773 #[simd_test(enable = "altivec")]
4774 unsafe fn test_vec_lde_u8() {
4775 let pat = [u8x16::new(
4776 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
4777 )];
4778 for off in 0..16 {
4779 let v: u8x16 = transmute(vec_lde(off, pat.as_ptr() as *const u8));
4780 assert_eq!(off as u8, v.extract(off as _));
4781 }
4782 }
4783
4784 #[simd_test(enable = "altivec")]
4785 unsafe fn test_vec_lde_u16() {
4786 let pat = [u16x8::new(0, 1, 2, 3, 4, 5, 6, 7)];
4787 for off in 0..8 {
4788 let v: u16x8 = transmute(vec_lde(off * 2, pat.as_ptr() as *const u8));
4789 assert_eq!(off as u16, v.extract(off as _));
4790 }
4791 }
4792
4793 #[simd_test(enable = "altivec")]
4794 unsafe fn test_vec_lde_u32() {
4795 let pat = [u32x4::new(0, 1, 2, 3)];
4796 for off in 0..4 {
4797 let v: u32x4 = transmute(vec_lde(off * 4, pat.as_ptr() as *const u8));
4798 assert_eq!(off as u32, v.extract(off as _));
4799 }
4800 }
4801
4802 test_vec_1! { test_vec_floor, vec_floor, f32x4,
4803 [1.1, 1.9, -0.5, -0.9],
4804 [1.0, 1.0, -1.0, -1.0]
4805 }
4806
4807 test_vec_1! { test_vec_expte, vec_expte, f32x4,
4808 [0.0, 2.0, 2.0, -1.0],
4809 ~[1.0, 4.0, 4.0, 0.5]
4810 }
4811
4812 test_vec_2! { test_vec_cmpgt_i8, vec_cmpgt, i8x16 -> m8x16,
4813 [1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
4814 [0, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
4815 [true, false, true, false, false, false, false, false, false, false, false, false, false, false, false, false]
4816 }
4817
4818 test_vec_2! { test_vec_cmpgt_u8, vec_cmpgt, u8x16 -> m8x16,
4819 [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
4820 [0, 0, 255, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
4821 [true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false]
4822 }
4823
4824 test_vec_2! { test_vec_cmpgt_i16, vec_cmpgt, i16x8 -> m16x8,
4825 [1, -1, 0, 0, 0, 0, 0, 0],
4826 [0, 0, -1, 1, 0, 0, 0, 0],
4827 [true, false, true, false, false, false, false, false]
4828 }
4829
4830 test_vec_2! { test_vec_cmpgt_u16, vec_cmpgt, u16x8 -> m16x8,
4831 [1, 255, 0, 0, 0, 0, 0, 0],
4832 [0, 0, 255, 1, 0, 0, 0, 0],
4833 [true, true, false, false, false, false, false, false]
4834 }
4835
4836 test_vec_2! { test_vec_cmpgt_i32, vec_cmpgt, i32x4 -> m32x4,
4837 [1, -1, 0, 0],
4838 [0, -1, 0, 1],
4839 [true, false, false, false]
4840 }
4841
4842 test_vec_2! { test_vec_cmpgt_u32, vec_cmpgt, u32x4 -> m32x4,
4843 [1, 255, 0, 0],
4844 [0, 255, 0, 1],
4845 [true, false, false, false]
4846 }
4847
4848 test_vec_2! { test_vec_cmpge, vec_cmpge, f32x4 -> m32x4,
4849 [0.1, -0.1, 0.0, 0.99],
4850 [0.1, 0.0, 0.1, 1.0],
4851 [true, false, false, false]
4852 }
4853
4854 test_vec_2! { test_vec_cmpeq_i8, vec_cmpeq, i8x16 -> m8x16,
4855 [1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
4856 [0, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
4857 [false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true]
4858 }
4859
4860 test_vec_2! { test_vec_cmpeq_u8, vec_cmpeq, u8x16 -> m8x16,
4861 [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
4862 [0, 0, 255, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
4863 [false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true]
4864 }
4865
4866 test_vec_2! { test_vec_cmpeq_i16, vec_cmpeq, i16x8 -> m16x8,
4867 [1, -1, 0, 0, 0, 0, 0, 0],
4868 [0, 0, -1, 1, 0, 0, 0, 0],
4869 [false, false, false, false, true, true, true, true]
4870 }
4871
4872 test_vec_2! { test_vec_cmpeq_u16, vec_cmpeq, u16x8 -> m16x8,
4873 [1, 255, 0, 0, 0, 0, 0, 0],
4874 [0, 0, 255, 1, 0, 0, 0, 0],
4875 [false, false, false, false, true, true, true, true]
4876 }
4877
4878 test_vec_2! { test_vec_cmpeq_i32, vec_cmpeq, i32x4 -> m32x4,
4879 [1, -1, 0, 0],
4880 [0, -1, 0, 1],
4881 [false, true, true, false]
4882 }
4883
4884 test_vec_2! { test_vec_cmpeq_u32, vec_cmpeq, u32x4 -> m32x4,
4885 [1, 255, 0, 0],
4886 [0, 255, 0, 1],
4887 [false, true, true, false]
4888 }
4889
4890 test_vec_2! { test_vec_cmpne_i8, vec_cmpne, i8x16 -> m8x16,
4891 [1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
4892 [0, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
4893 [true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false]
4894 }
4895
4896 test_vec_2! { test_vec_cmpne_u8, vec_cmpne, u8x16 -> m8x16,
4897 [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
4898 [0, 0, 255, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
4899 [true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false]
4900 }
4901
4902 test_vec_2! { test_vec_cmpne_i16, vec_cmpne, i16x8 -> m16x8,
4903 [1, -1, 0, 0, 0, 0, 0, 0],
4904 [0, 0, -1, 1, 0, 0, 0, 0],
4905 [true, true, true, true, false, false, false, false]
4906 }
4907
4908 test_vec_2! { test_vec_cmpne_u16, vec_cmpne, u16x8 -> m16x8,
4909 [1, 255, 0, 0, 0, 0, 0, 0],
4910 [0, 0, 255, 1, 0, 0, 0, 0],
4911 [true, true, true, true, false, false, false, false]
4912 }
4913
4914 test_vec_2! { test_vec_cmpne_i32, vec_cmpne, i32x4 -> m32x4,
4915 [1, -1, 0, 0],
4916 [0, -1, 0, 1],
4917 [true, false, false, true]
4918 }
4919
4920 test_vec_2! { test_vec_cmpne_u32, vec_cmpne, u32x4 -> m32x4,
4921 [1, 255, 0, 0],
4922 [0, 255, 0, 1],
4923 [true, false, false, true]
4924 }
4925
4926 test_vec_2! { test_vec_all_eq_i8_false, vec_all_eq, i8x16 -> bool,
4927 [1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
4928 [0, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
4929 false
4930 }
4931
4932 test_vec_2! { test_vec_all_eq_u8_false, vec_all_eq, u8x16 -> bool,
4933 [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
4934 [0, 0, 255, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
4935 false
4936 }
4937
4938 test_vec_2! { test_vec_all_eq_i16_false, vec_all_eq, i16x8 -> bool,
4939 [1, -1, 0, 0, 0, 0, 0, 0],
4940 [0, 0, -1, 1, 0, 0, 0, 0],
4941 false
4942 }
4943
4944 test_vec_2! { test_vec_all_eq_u16_false, vec_all_eq, u16x8 -> bool,
4945 [1, 255, 0, 0, 0, 0, 0, 0],
4946 [0, 0, 255, 1, 0, 0, 0, 0],
4947 false
4948 }
4949
4950 test_vec_2! { test_vec_all_eq_i32_false, vec_all_eq, i32x4 -> bool,
4951 [1, -1, 0, 0],
4952 [0, -1, 0, 1],
4953 false
4954 }
4955
4956 test_vec_2! { test_vec_all_eq_u32_false, vec_all_eq, u32x4 -> bool,
4957 [1, 255, 0, 0],
4958 [0, 255, 0, 1],
4959 false
4960 }
4961
4962 test_vec_2! { test_vec_all_eq_i8_true, vec_all_eq, i8x16 -> bool,
4963 [0, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
4964 [0, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
4965 true
4966 }
4967
4968 test_vec_2! { test_vec_all_eq_u8_true, vec_all_eq, u8x16 -> bool,
4969 [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
4970 [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
4971 true
4972 }
4973
4974 test_vec_2! { test_vec_all_eq_i16_true, vec_all_eq, i16x8 -> bool,
4975 [1, -1, 1, 0, 0, 0, 0, 0],
4976 [1, -1, 1, 0, 0, 0, 0, 0],
4977 true
4978 }
4979
4980 test_vec_2! { test_vec_all_eq_u16_true, vec_all_eq, u16x8 -> bool,
4981 [1, 255, 1, 0, 0, 0, 0, 0],
4982 [1, 255, 1, 0, 0, 0, 0, 0],
4983 true
4984 }
4985
4986 test_vec_2! { test_vec_all_eq_i32_true, vec_all_eq, i32x4 -> bool,
4987 [1, -1, 0, 1],
4988 [1, -1, 0, 1],
4989 true
4990 }
4991
4992 test_vec_2! { test_vec_all_eq_u32_true, vec_all_eq, u32x4 -> bool,
4993 [1, 255, 0, 1],
4994 [1, 255, 0, 1],
4995 true
4996 }
4997
4998 test_vec_2! { test_vec_any_eq_i8_false, vec_any_eq, i8x16 -> bool,
4999 [1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5000 [0, 0, -1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1],
5001 false
5002 }
5003
5004 test_vec_2! { test_vec_any_eq_u8_false, vec_any_eq, u8x16 -> bool,
5005 [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5006 [0, 0, 255, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1],
5007 false
5008 }
5009
5010 test_vec_2! { test_vec_any_eq_i16_false, vec_any_eq, i16x8 -> bool,
5011 [1, -1, 0, 0, 0, 0, 0, 0],
5012 [0, 0, -1, 1, 1, 1, 1, 1],
5013 false
5014 }
5015
5016 test_vec_2! { test_vec_any_eq_u16_false, vec_any_eq, u16x8 -> bool,
5017 [1, 255, 0, 0, 0, 0, 0, 0],
5018 [0, 0, 255, 1, 1, 1, 1, 1],
5019 false
5020 }
5021
5022 test_vec_2! { test_vec_any_eq_i32_false, vec_any_eq, i32x4 -> bool,
5023 [1, -1, 0, 0],
5024 [0, -2, 1, 1],
5025 false
5026 }
5027
5028 test_vec_2! { test_vec_any_eq_u32_false, vec_any_eq, u32x4 -> bool,
5029 [1, 2, 1, 0],
5030 [0, 255, 0, 1],
5031 false
5032 }
5033
5034 test_vec_2! { test_vec_any_eq_i8_true, vec_any_eq, i8x16 -> bool,
5035 [1, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5036 [0, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5037 true
5038 }
5039
5040 test_vec_2! { test_vec_any_eq_u8_true, vec_any_eq, u8x16 -> bool,
5041 [0, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5042 [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5043 true
5044 }
5045
5046 test_vec_2! { test_vec_any_eq_i16_true, vec_any_eq, i16x8 -> bool,
5047 [0, -1, 1, 0, 0, 0, 0, 0],
5048 [1, -1, 1, 0, 0, 0, 0, 0],
5049 true
5050 }
5051
5052 test_vec_2! { test_vec_any_eq_u16_true, vec_any_eq, u16x8 -> bool,
5053 [0, 255, 1, 0, 0, 0, 0, 0],
5054 [1, 255, 1, 0, 0, 0, 0, 0],
5055 true
5056 }
5057
5058 test_vec_2! { test_vec_any_eq_i32_true, vec_any_eq, i32x4 -> bool,
5059 [0, -1, 0, 1],
5060 [1, -1, 0, 1],
5061 true
5062 }
5063
5064 test_vec_2! { test_vec_any_eq_u32_true, vec_any_eq, u32x4 -> bool,
5065 [0, 255, 0, 1],
5066 [1, 255, 0, 1],
5067 true
5068 }
5069
5070 test_vec_2! { test_vec_all_ge_i8_false, vec_all_ge, i8x16 -> bool,
5071 [1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5072 [0, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5073 false
5074 }
5075
5076 test_vec_2! { test_vec_all_ge_u8_false, vec_all_ge, u8x16 -> bool,
5077 [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5078 [0, 0, 255, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5079 false
5080 }
5081
5082 test_vec_2! { test_vec_all_ge_i16_false, vec_all_ge, i16x8 -> bool,
5083 [1, -1, 0, 0, 0, 0, 0, 0],
5084 [0, 0, -1, 1, 0, 0, 0, 0],
5085 false
5086 }
5087
5088 test_vec_2! { test_vec_all_ge_u16_false, vec_all_ge, u16x8 -> bool,
5089 [1, 255, 0, 0, 0, 0, 0, 0],
5090 [0, 0, 255, 1, 0, 0, 0, 0],
5091 false
5092 }
5093
5094 test_vec_2! { test_vec_all_ge_i32_false, vec_all_ge, i32x4 -> bool,
5095 [1, -1, 0, 0],
5096 [0, -1, 0, 1],
5097 false
5098 }
5099
5100 test_vec_2! { test_vec_all_ge_u32_false, vec_all_ge, u32x4 -> bool,
5101 [1, 255, 0, 0],
5102 [0, 255, 1, 1],
5103 false
5104 }
5105
5106 test_vec_2! { test_vec_all_ge_i8_true, vec_all_ge, i8x16 -> bool,
5107 [0, 0, -1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0],
5108 [0, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5109 true
5110 }
5111
5112 test_vec_2! { test_vec_all_ge_u8_true, vec_all_ge, u8x16 -> bool,
5113 [1, 255, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5114 [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5115 true
5116 }
5117
5118 test_vec_2! { test_vec_all_ge_i16_true, vec_all_ge, i16x8 -> bool,
5119 [1, -1, 42, 0, 0, 0, 0, 0],
5120 [1, -5, 2, 0, 0, 0, 0, 0],
5121 true
5122 }
5123
5124 test_vec_2! { test_vec_all_ge_u16_true, vec_all_ge, u16x8 -> bool,
5125 [42, 255, 1, 0, 0, 0, 0, 0],
5126 [2, 255, 1, 0, 0, 0, 0, 0],
5127 true
5128 }
5129
5130 test_vec_2! { test_vec_all_ge_i32_true, vec_all_ge, i32x4 -> bool,
5131 [1, -1, 0, 1],
5132 [0, -1, 0, 1],
5133 true
5134 }
5135
5136 test_vec_2! { test_vec_all_ge_u32_true, vec_all_ge, u32x4 -> bool,
5137 [1, 255, 0, 1],
5138 [1, 254, 0, 0],
5139 true
5140 }
5141
5142 test_vec_2! { test_vec_any_ge_i8_false, vec_any_ge, i8x16 -> bool,
5143 [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5144 [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1],
5145 false
5146 }
5147
5148 test_vec_2! { test_vec_any_ge_u8_false, vec_any_ge, u8x16 -> bool,
5149 [1, 254, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5150 [42, 255, 255, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1],
5151 false
5152 }
5153
5154 test_vec_2! { test_vec_any_ge_i16_false, vec_any_ge, i16x8 -> bool,
5155 [1, -1, -2, 0, 0, 0, 0, 0],
5156 [2, 0, -1, 1, 1, 1, 1, 1],
5157 false
5158 }
5159
5160 test_vec_2! { test_vec_any_ge_u16_false, vec_any_ge, u16x8 -> bool,
5161 [1, 2, 0, 0, 0, 0, 0, 0],
5162 [2, 42, 255, 1, 1, 1, 1, 1],
5163 false
5164 }
5165
5166 test_vec_2! { test_vec_any_ge_i32_false, vec_any_ge, i32x4 -> bool,
5167 [1, -1, 0, 0],
5168 [2, 0, 1, 1],
5169 false
5170 }
5171
5172 test_vec_2! { test_vec_any_ge_u32_false, vec_any_ge, u32x4 -> bool,
5173 [1, 2, 1, 0],
5174 [4, 255, 4, 1],
5175 false
5176 }
5177
5178 test_vec_2! { test_vec_any_ge_i8_true, vec_any_ge, i8x16 -> bool,
5179 [1, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5180 [0, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5181 true
5182 }
5183
5184 test_vec_2! { test_vec_any_ge_u8_true, vec_any_ge, u8x16 -> bool,
5185 [0, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5186 [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5187 true
5188 }
5189
5190 test_vec_2! { test_vec_any_ge_i16_true, vec_any_ge, i16x8 -> bool,
5191 [0, -1, 1, 0, 0, 0, 0, 0],
5192 [1, -1, 1, 0, 0, 0, 0, 0],
5193 true
5194 }
5195
5196 test_vec_2! { test_vec_any_ge_u16_true, vec_any_ge, u16x8 -> bool,
5197 [0, 255, 1, 0, 0, 0, 0, 0],
5198 [1, 255, 1, 0, 0, 0, 0, 0],
5199 true
5200 }
5201
5202 test_vec_2! { test_vec_any_ge_i32_true, vec_any_ge, i32x4 -> bool,
5203 [0, -1, 0, 1],
5204 [1, -1, 0, 1],
5205 true
5206 }
5207
5208 test_vec_2! { test_vec_any_ge_u32_true, vec_any_ge, u32x4 -> bool,
5209 [0, 255, 0, 1],
5210 [1, 255, 0, 1],
5211 true
5212 }
5213
5214 test_vec_2! { test_vec_all_gt_i8_false, vec_all_gt, i8x16 -> bool,
5215 [1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5216 [0, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5217 false
5218 }
5219
5220 test_vec_2! { test_vec_all_gt_u8_false, vec_all_gt, u8x16 -> bool,
5221 [1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5222 [0, 0, 255, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5223 false
5224 }
5225
5226 test_vec_2! { test_vec_all_gt_i16_false, vec_all_gt, i16x8 -> bool,
5227 [1, 0, 0, 0, 0, 0, 0, 0],
5228 [0, 0, -1, 1, 0, 0, 0, 0],
5229 false
5230 }
5231
5232 test_vec_2! { test_vec_all_gt_u16_false, vec_all_gt, u16x8 -> bool,
5233 [1, 0, 0, 0, 0, 0, 0, 0],
5234 [0, 0, 255, 1, 0, 0, 0, 0],
5235 false
5236 }
5237
5238 test_vec_2! { test_vec_all_gt_i32_false, vec_all_gt, i32x4 -> bool,
5239 [1, -1, 0, 0],
5240 [0, -1, 0, 1],
5241 false
5242 }
5243
5244 test_vec_2! { test_vec_all_gt_u32_false, vec_all_gt, u32x4 -> bool,
5245 [1, 255, 0, 0],
5246 [0, 255, 1, 1],
5247 false
5248 }
5249
5250 test_vec_2! { test_vec_all_gt_i8_true, vec_all_gt, i8x16 -> bool,
5251 [2, 1, -1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0],
5252 [0, 0, -2, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1],
5253 true
5254 }
5255
5256 test_vec_2! { test_vec_all_gt_u8_true, vec_all_gt, u8x16 -> bool,
5257 [1, 255, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1],
5258 [0, 254, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5259 true
5260 }
5261
5262 test_vec_2! { test_vec_all_gt_i16_true, vec_all_gt, i16x8 -> bool,
5263 [1, -1, 42, 1, 1, 1, 1, 1],
5264 [0, -5, 2, 0, 0, 0, 0, 0],
5265 true
5266 }
5267
5268 test_vec_2! { test_vec_all_gt_u16_true, vec_all_gt, u16x8 -> bool,
5269 [42, 255, 1, 1, 1, 1, 1, 1],
5270 [2, 254, 0, 0, 0, 0, 0, 0],
5271 true
5272 }
5273
5274 test_vec_2! { test_vec_all_gt_i32_true, vec_all_gt, i32x4 -> bool,
5275 [1, -1, 1, 1],
5276 [0, -2, 0, 0],
5277 true
5278 }
5279
5280 test_vec_2! { test_vec_all_gt_u32_true, vec_all_gt, u32x4 -> bool,
5281 [1, 255, 1, 1],
5282 [0, 254, 0, 0],
5283 true
5284 }
5285
5286 test_vec_2! { test_vec_any_gt_i8_false, vec_any_gt, i8x16 -> bool,
5287 [1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5288 [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1],
5289 false
5290 }
5291
5292 test_vec_2! { test_vec_any_gt_u8_false, vec_any_gt, u8x16 -> bool,
5293 [1, 254, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5294 [42, 255, 255, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1],
5295 false
5296 }
5297
5298 test_vec_2! { test_vec_any_gt_i16_false, vec_any_gt, i16x8 -> bool,
5299 [1, -1, -2, 0, 0, 0, 0, 0],
5300 [2, 0, -1, 1, 1, 1, 1, 1],
5301 false
5302 }
5303
5304 test_vec_2! { test_vec_any_gt_u16_false, vec_any_gt, u16x8 -> bool,
5305 [1, 2, 0, 0, 0, 0, 0, 0],
5306 [2, 42, 255, 1, 1, 1, 1, 1],
5307 false
5308 }
5309
5310 test_vec_2! { test_vec_any_gt_i32_false, vec_any_gt, i32x4 -> bool,
5311 [1, -1, 0, 0],
5312 [2, 0, 1, 1],
5313 false
5314 }
5315
5316 test_vec_2! { test_vec_any_gt_u32_false, vec_any_gt, u32x4 -> bool,
5317 [1, 2, 1, 0],
5318 [4, 255, 4, 1],
5319 false
5320 }
5321
5322 test_vec_2! { test_vec_any_gt_i8_true, vec_any_gt, i8x16 -> bool,
5323 [1, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5324 [0, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5325 true
5326 }
5327
5328 test_vec_2! { test_vec_any_gt_u8_true, vec_any_gt, u8x16 -> bool,
5329 [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5330 [0, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5331 true
5332 }
5333
5334 test_vec_2! { test_vec_any_gt_i16_true, vec_any_gt, i16x8 -> bool,
5335 [1, -1, 1, 0, 0, 0, 0, 0],
5336 [0, -1, 1, 0, 0, 0, 0, 0],
5337 true
5338 }
5339
5340 test_vec_2! { test_vec_any_gt_u16_true, vec_any_gt, u16x8 -> bool,
5341 [1, 255, 1, 0, 0, 0, 0, 0],
5342 [0, 255, 1, 0, 0, 0, 0, 0],
5343 true
5344 }
5345
5346 test_vec_2! { test_vec_any_gt_i32_true, vec_any_gt, i32x4 -> bool,
5347 [1, -1, 0, 1],
5348 [0, -1, 0, 1],
5349 true
5350 }
5351
5352 test_vec_2! { test_vec_any_gt_u32_true, vec_any_gt, u32x4 -> bool,
5353 [1, 255, 0, 1],
5354 [0, 255, 0, 1],
5355 true
5356 }
5357
5358 test_vec_2! { test_vec_all_in_true, vec_all_in, f32x4 -> bool,
5359 [0.0, -0.1, 0.0, 0.0],
5360 [0.1, 0.2, 0.0, 0.0],
5361 true
5362 }
5363
5364 test_vec_2! { test_vec_all_in_false, vec_all_in, f32x4 -> bool,
5365 [0.5, 0.4, -0.5, 0.8],
5366 [0.1, 0.4, -0.5, 0.8],
5367 false
5368 }
5369
5370 test_vec_2! { test_vec_all_le_i8_false, vec_all_le, i8x16 -> bool,
5371 [0, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5372 [1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5373 false
5374 }
5375
5376 test_vec_2! { test_vec_all_le_u8_false, vec_all_le, u8x16 -> bool,
5377 [0, 0, 255, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5378 [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5379 false
5380 }
5381
5382 test_vec_2! { test_vec_all_le_i16_false, vec_all_le, i16x8 -> bool,
5383 [0, 0, -1, 1, 0, 0, 0, 0],
5384 [1, -1, 0, 0, 0, 0, 0, 0],
5385 false
5386 }
5387
5388 test_vec_2! { test_vec_all_le_u16_false, vec_all_le, u16x8 -> bool,
5389 [0, 0, 255, 1, 0, 0, 0, 0],
5390 [1, 255, 0, 0, 0, 0, 0, 0],
5391 false
5392 }
5393
5394 test_vec_2! { test_vec_all_le_i32_false, vec_all_le, i32x4 -> bool,
5395 [0, -1, 0, 1],
5396 [1, -1, 0, 0],
5397 false
5398 }
5399
5400 test_vec_2! { test_vec_all_le_u32_false, vec_all_le, u32x4 -> bool,
5401 [0, 255, 1, 1],
5402 [1, 255, 0, 0],
5403 false
5404 }
5405
5406 test_vec_2! { test_vec_all_le_i8_true, vec_all_le, i8x16 -> bool,
5407 [0, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5408 [0, 0, -1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0],
5409 true
5410 }
5411
5412 test_vec_2! { test_vec_all_le_u8_true, vec_all_le, u8x16 -> bool,
5413 [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5414 [1, 255, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5415 true
5416 }
5417
5418 test_vec_2! { test_vec_all_le_i16_true, vec_all_le, i16x8 -> bool,
5419 [1, -5, 2, 0, 0, 0, 0, 0],
5420 [1, -1, 42, 0, 0, 0, 0, 0],
5421 true
5422 }
5423
5424 test_vec_2! { test_vec_all_le_u16_true, vec_all_le, u16x8 -> bool,
5425 [2, 255, 1, 0, 0, 0, 0, 0],
5426 [42, 255, 1, 0, 0, 0, 0, 0],
5427 true
5428 }
5429
5430 test_vec_2! { test_vec_all_le_i32_true, vec_all_le, i32x4 -> bool,
5431 [0, -1, 0, 1],
5432 [1, -1, 0, 1],
5433 true
5434 }
5435
5436 test_vec_2! { test_vec_all_le_u32_true, vec_all_le, u32x4 -> bool,
5437 [1, 254, 0, 0],
5438 [1, 255, 0, 1],
5439 true
5440 }
5441
5442 test_vec_2! { test_vec_any_le_i8_false, vec_any_le, i8x16 -> bool,
5443 [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1],
5444 [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5445 false
5446 }
5447
5448 test_vec_2! { test_vec_any_le_u8_false, vec_any_le, u8x16 -> bool,
5449 [42, 255, 255, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1],
5450 [1, 254, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5451 false
5452 }
5453
5454 test_vec_2! { test_vec_any_le_i16_false, vec_any_le, i16x8 -> bool,
5455 [2, 0, -1, 1, 1, 1, 1, 1],
5456 [1, -1, -2, 0, 0, 0, 0, 0],
5457 false
5458 }
5459
5460 test_vec_2! { test_vec_any_le_u16_false, vec_any_le, u16x8 -> bool,
5461 [2, 42, 255, 1, 1, 1, 1, 1],
5462 [1, 2, 0, 0, 0, 0, 0, 0],
5463 false
5464 }
5465
5466 test_vec_2! { test_vec_any_le_i32_false, vec_any_le, i32x4 -> bool,
5467 [2, 0, 1, 1],
5468 [1, -1, 0, 0],
5469 false
5470 }
5471
5472 test_vec_2! { test_vec_any_le_u32_false, vec_any_le, u32x4 -> bool,
5473 [4, 255, 4, 1],
5474 [1, 2, 1, 0],
5475 false
5476 }
5477
5478 test_vec_2! { test_vec_any_le_i8_true, vec_any_le, i8x16 -> bool,
5479 [0, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5480 [1, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5481 true
5482 }
5483
5484 test_vec_2! { test_vec_any_le_u8_true, vec_any_le, u8x16 -> bool,
5485 [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5486 [0, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5487 true
5488 }
5489
5490 test_vec_2! { test_vec_any_le_i16_true, vec_any_le, i16x8 -> bool,
5491 [1, -1, 1, 0, 0, 0, 0, 0],
5492 [0, -1, 1, 0, 0, 0, 0, 0],
5493 true
5494 }
5495
5496 test_vec_2! { test_vec_any_le_u16_true, vec_any_le, u16x8 -> bool,
5497 [1, 255, 1, 0, 0, 0, 0, 0],
5498 [0, 255, 1, 0, 0, 0, 0, 0],
5499 true
5500 }
5501
5502 test_vec_2! { test_vec_any_le_i32_true, vec_any_le, i32x4 -> bool,
5503 [1, -1, 0, 1],
5504 [0, -1, 0, 1],
5505 true
5506 }
5507
5508 test_vec_2! { test_vec_any_le_u32_true, vec_any_le, u32x4 -> bool,
5509 [1, 255, 0, 1],
5510 [0, 255, 0, 1],
5511 true
5512 }
5513
5514 test_vec_2! { test_vec_all_lt_i8_false, vec_all_lt, i8x16 -> bool,
5515 [0, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5516 [1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5517 false
5518 }
5519
5520 test_vec_2! { test_vec_all_lt_u8_false, vec_all_lt, u8x16 -> bool,
5521 [0, 0, 255, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5522 [1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5523 false
5524 }
5525
5526 test_vec_2! { test_vec_all_lt_i16_false, vec_all_lt, i16x8 -> bool,
5527 [0, 0, -1, 1, 0, 0, 0, 0],
5528 [1, 0, 0, 0, 0, 0, 0, 0],
5529 false
5530 }
5531
5532 test_vec_2! { test_vec_all_lt_u16_false, vec_all_lt, u16x8 -> bool,
5533 [0, 0, 255, 1, 0, 0, 0, 0],
5534 [1, 0, 0, 0, 0, 0, 0, 0],
5535 false
5536 }
5537
5538 test_vec_2! { test_vec_all_lt_i32_false, vec_all_lt, i32x4 -> bool,
5539 [0, -1, 0, 1],
5540 [1, -1, 0, 0],
5541 false
5542 }
5543
5544 test_vec_2! { test_vec_all_lt_u32_false, vec_all_lt, u32x4 -> bool,
5545 [0, 255, 1, 1],
5546 [1, 255, 0, 0],
5547 false
5548 }
5549
5550 test_vec_2! { test_vec_all_lt_i8_true, vec_all_lt, i8x16 -> bool,
5551 [0, 0, -2, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1],
5552 [2, 1, -1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0],
5553 true
5554 }
5555
5556 test_vec_2! { test_vec_all_lt_u8_true, vec_all_lt, u8x16 -> bool,
5557 [0, 254, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5558 [1, 255, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1],
5559 true
5560 }
5561
5562 test_vec_2! { test_vec_all_lt_i16_true, vec_all_lt, i16x8 -> bool,
5563 [0, -5, 2, 0, 0, 0, 0, 0],
5564 [1, -1, 42, 1, 1, 1, 1, 1],
5565 true
5566 }
5567
5568 test_vec_2! { test_vec_all_lt_u16_true, vec_all_lt, u16x8 -> bool,
5569 [2, 254, 0, 0, 0, 0, 0, 0],
5570 [42, 255, 1, 1, 1, 1, 1, 1],
5571 true
5572 }
5573
5574 test_vec_2! { test_vec_all_lt_i32_true, vec_all_lt, i32x4 -> bool,
5575 [0, -2, 0, 0],
5576 [1, -1, 1, 1],
5577 true
5578 }
5579
5580 test_vec_2! { test_vec_all_lt_u32_true, vec_all_lt, u32x4 -> bool,
5581 [0, 254, 0, 0],
5582 [1, 255, 1, 1],
5583 true
5584 }
5585
5586 test_vec_2! { test_vec_any_lt_i8_false, vec_any_lt, i8x16 -> bool,
5587 [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1],
5588 [1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5589 false
5590 }
5591
5592 test_vec_2! { test_vec_any_lt_u8_false, vec_any_lt, u8x16 -> bool,
5593 [42, 255, 255, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1],
5594 [1, 254, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5595 false
5596 }
5597
5598 test_vec_2! { test_vec_any_lt_i16_false, vec_any_lt, i16x8 -> bool,
5599 [2, 0, -1, 1, 1, 1, 1, 1],
5600 [1, -1, -2, 0, 0, 0, 0, 0],
5601 false
5602 }
5603
5604 test_vec_2! { test_vec_any_lt_u16_false, vec_any_lt, u16x8 -> bool,
5605 [2, 42, 255, 1, 1, 1, 1, 1],
5606 [1, 2, 0, 0, 0, 0, 0, 0],
5607 false
5608 }
5609
5610 test_vec_2! { test_vec_any_lt_i32_false, vec_any_lt, i32x4 -> bool,
5611 [2, 0, 1, 1],
5612 [1, -1, 0, 0],
5613 false
5614 }
5615
5616 test_vec_2! { test_vec_any_lt_u32_false, vec_any_lt, u32x4 -> bool,
5617 [4, 255, 4, 1],
5618 [1, 2, 1, 0],
5619 false
5620 }
5621
5622 test_vec_2! { test_vec_any_lt_i8_true, vec_any_lt, i8x16 -> bool,
5623 [0, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5624 [1, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5625 true
5626 }
5627
5628 test_vec_2! { test_vec_any_lt_u8_true, vec_any_lt, u8x16 -> bool,
5629 [0, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5630 [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5631 true
5632 }
5633
5634 test_vec_2! { test_vec_any_lt_i16_true, vec_any_lt, i16x8 -> bool,
5635 [0, -1, 1, 0, 0, 0, 0, 0],
5636 [1, -1, 1, 0, 0, 0, 0, 0],
5637 true
5638 }
5639
5640 test_vec_2! { test_vec_any_lt_u16_true, vec_any_lt, u16x8 -> bool,
5641 [0, 255, 1, 0, 0, 0, 0, 0],
5642 [1, 255, 1, 0, 0, 0, 0, 0],
5643 true
5644 }
5645
5646 test_vec_2! { test_vec_any_lt_i32_true, vec_any_lt, i32x4 -> bool,
5647 [0, -1, 0, 1],
5648 [1, -1, 0, 1],
5649 true
5650 }
5651
5652 test_vec_2! { test_vec_any_lt_u32_true, vec_any_lt, u32x4 -> bool,
5653 [0, 255, 0, 1],
5654 [1, 255, 0, 1],
5655 true
5656 }
5657
5658 test_vec_2! { test_vec_all_ne_i8_false, vec_all_ne, i8x16 -> bool,
5659 [1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5660 [0, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5661 false
5662 }
5663
5664 test_vec_2! { test_vec_all_ne_u8_false, vec_all_ne, u8x16 -> bool,
5665 [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5666 [0, 0, 255, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5667 false
5668 }
5669
5670 test_vec_2! { test_vec_all_ne_i16_false, vec_all_ne, i16x8 -> bool,
5671 [1, -1, 0, 0, 0, 0, 0, 0],
5672 [0, -1, 1, 0, 0, 0, 0, 0],
5673 false
5674 }
5675
5676 test_vec_2! { test_vec_all_ne_u16_false, vec_all_ne, u16x8 -> bool,
5677 [1, 255, 0, 0, 0, 0, 0, 0],
5678 [0, 255, 0, 1, 0, 0, 0, 0],
5679 false
5680 }
5681
5682 test_vec_2! { test_vec_all_ne_i32_false, vec_all_ne, i32x4 -> bool,
5683 [1, -1, 0, 0],
5684 [0, -1, 0, 1],
5685 false
5686 }
5687
5688 test_vec_2! { test_vec_all_ne_u32_false, vec_all_ne, u32x4 -> bool,
5689 [1, 255, 0, 0],
5690 [0, 255, 0, 1],
5691 false
5692 }
5693
5694 test_vec_2! { test_vec_all_ne_i8_true, vec_all_ne, i8x16 -> bool,
5695 [0, -1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1],
5696 [1, 0, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5697 true
5698 }
5699
5700 test_vec_2! { test_vec_all_ne_u8_true, vec_all_ne, u8x16 -> bool,
5701 [0, 254, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1],
5702 [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5703 true
5704 }
5705
5706 test_vec_2! { test_vec_all_ne_i16_true, vec_all_ne, i16x8 -> bool,
5707 [2, -2, 0, 1, 1, 1, 1, 1],
5708 [1, -1, 1, 0, 0, 0, 0, 0],
5709 true
5710 }
5711
5712 test_vec_2! { test_vec_all_ne_u16_true, vec_all_ne, u16x8 -> bool,
5713 [0, 254, 1, 1, 0, 0, 1, 0],
5714 [1, 255, 0, 0, 1, 1, 0, 1],
5715 true
5716 }
5717
5718 test_vec_2! { test_vec_all_ne_i32_true, vec_all_ne, i32x4 -> bool,
5719 [0, -2, 0, 0],
5720 [1, -1, 1, 1],
5721 true
5722 }
5723
5724 test_vec_2! { test_vec_all_ne_u32_true, vec_all_ne, u32x4 -> bool,
5725 [1, 255, 0, 0],
5726 [0, 254, 1, 1],
5727 true
5728 }
5729
5730 test_vec_2! { test_vec_any_ne_i8_false, vec_any_ne, i8x16 -> bool,
5731 [1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5732 [1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5733 false
5734 }
5735
5736 test_vec_2! { test_vec_any_ne_u8_false, vec_any_ne, u8x16 -> bool,
5737 [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5738 [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5739 false
5740 }
5741
5742 test_vec_2! { test_vec_any_ne_i16_false, vec_any_ne, i16x8 -> bool,
5743 [1, -1, 0, 0, 0, 0, 0, 0],
5744 [1, -1, 0, 0, 0, 0, 0, 0],
5745 false
5746 }
5747
5748 test_vec_2! { test_vec_any_ne_u16_false, vec_any_ne, u16x8 -> bool,
5749 [1, 255, 1, 1, 1, 1, 1, 0],
5750 [1, 255, 1, 1, 1, 1, 1, 0],
5751 false
5752 }
5753
5754 test_vec_2! { test_vec_any_ne_i32_false, vec_any_ne, i32x4 -> bool,
5755 [0, -1, 1, 1],
5756 [0, -1, 1, 1],
5757 false
5758 }
5759
5760 test_vec_2! { test_vec_any_ne_u32_false, vec_any_ne, u32x4 -> bool,
5761 [1, 2, 1, 255],
5762 [1, 2, 1, 255],
5763 false
5764 }
5765
5766 test_vec_2! { test_vec_any_ne_i8_true, vec_any_ne, i8x16 -> bool,
5767 [1, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5768 [0, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5769 true
5770 }
5771
5772 test_vec_2! { test_vec_any_ne_u8_true, vec_any_ne, u8x16 -> bool,
5773 [0, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5774 [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5775 true
5776 }
5777
5778 test_vec_2! { test_vec_any_ne_i16_true, vec_any_ne, i16x8 -> bool,
5779 [0, -1, 1, 0, 0, 0, 0, 0],
5780 [1, -1, 1, 0, 0, 0, 0, 0],
5781 true
5782 }
5783
5784 test_vec_2! { test_vec_any_ne_u16_true, vec_any_ne, u16x8 -> bool,
5785 [0, 255, 1, 0, 0, 0, 0, 0],
5786 [1, 255, 1, 0, 0, 0, 0, 0],
5787 true
5788 }
5789
5790 test_vec_2! { test_vec_any_ne_i32_true, vec_any_ne, i32x4 -> bool,
5791 [0, -1, 0, 1],
5792 [1, -1, 0, 1],
5793 true
5794 }
5795
5796 test_vec_2! { test_vec_any_ne_u32_true, vec_any_ne, u32x4 -> bool,
5797 [0, 255, 0, 1],
5798 [1, 255, 0, 1],
5799 true
5800 }
5801
5802 #[simd_test(enable = "altivec")]
5803 unsafe fn test_vec_cmpb() {
5804 let a: vector_float = transmute(f32x4::new(0.1, 0.5, 0.6, 0.9));
5805 let b: vector_float = transmute(f32x4::new(-0.1, 0.5, -0.6, 0.9));
5806 let d = i32x4::new(
5807 -0b10000000000000000000000000000000,
5808 0,
5809 -0b10000000000000000000000000000000,
5810 0,
5811 );
5812
5813 assert_eq!(d, transmute(vec_cmpb(a, b)));
5814 }
5815
5816 #[simd_test(enable = "altivec")]
5817 unsafe fn test_vec_ceil() {
5818 let a: vector_float = transmute(f32x4::new(0.1, 0.5, 0.6, 0.9));
5819 let d = f32x4::new(1.0, 1.0, 1.0, 1.0);
5820
5821 assert_eq!(d, transmute(vec_ceil(a)));
5822 }
5823
5824 test_vec_2! { test_vec_andc, vec_andc, i32x4,
5825 [0b11001100, 0b11001100, 0b11001100, 0b11001100],
5826 [0b00110011, 0b11110011, 0b00001100, 0b10000000],
5827 [0b11001100, 0b00001100, 0b11000000, 0b01001100] }
5828
5829 test_vec_2! { test_vec_and, vec_and, i32x4,
5830 [0b11001100, 0b11001100, 0b11001100, 0b11001100],
5831 [0b00110011, 0b11110011, 0b00001100, 0b00000000],
5832 [0b00000000, 0b11000000, 0b00001100, 0b00000000] }
5833
5834 macro_rules! test_vec_avg {
5835 { $name: ident, $ty: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => {
5836 test_vec_2! {$name, vec_avg, $ty, [$($a),+], [$($b),+], [$($d),+] }
5837 }
5838 }
5839
5840 test_vec_avg! { test_vec_avg_i32x4, i32x4,
5841 [i32::MIN, i32::MAX, 1, -1],
5842 [-1, 1, 1, -1],
5843 [-1073741824, 1073741824, 1, -1] }
5844
5845 test_vec_avg! { test_vec_avg_u32x4, u32x4,
5846 [u32::MAX, 0, 1, 2],
5847 [2, 1, 0, 0],
5848 [2147483649, 1, 1, 1] }
5849
5850 test_vec_avg! { test_vec_avg_i16x8, i16x8,
5851 [i16::MIN, i16::MAX, 1, -1, 0, 0, 0, 0],
5852 [-1, 1, 1, -1, 0, 0, 0, 0],
5853 [-16384, 16384, 1, -1, 0, 0, 0, 0] }
5854
5855 test_vec_avg! { test_vec_avg_u16x8, u16x8,
5856 [u16::MAX, 0, 1, 2, 0, 0, 0, 0],
5857 [2, 1, 0, 0, 0, 0, 0, 0],
5858 [32769, 1, 1, 1, 0, 0, 0, 0] }
5859
5860 test_vec_avg! { test_vec_avg_i8x16, i8x16,
5861 [i8::MIN, i8::MAX, 1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5862 [-1, 1, 1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5863 [-64, 64, 1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] }
5864
5865 test_vec_avg! { test_vec_avg_u8x16, u8x16,
5866 [u8::MAX, 0, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5867 [2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5868 [129, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] }
5869
5870 macro_rules! test_vec_adds {
5871 { $name: ident, $ty: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => {
5872 test_vec_2! {$name, vec_adds, $ty, [$($a),+], [$($b),+], [$($d),+] }
5873 }
5874 }
5875
5876 test_vec_adds! { test_vec_adds_i32x4, i32x4,
5877 [i32::MIN, i32::MAX, 1, -1],
5878 [-1, 1, 1, -1],
5879 [i32::MIN, i32::MAX, 2, -2] }
5880
5881 test_vec_adds! { test_vec_adds_u32x4, u32x4,
5882 [u32::MAX, 0, 1, 2],
5883 [2, 1, 0, 0],
5884 [u32::MAX, 1, 1, 2] }
5885
5886 test_vec_adds! { test_vec_adds_i16x8, i16x8,
5887 [i16::MIN, i16::MAX, 1, -1, 0, 0, 0, 0],
5888 [-1, 1, 1, -1, 0, 0, 0, 0],
5889 [i16::MIN, i16::MAX, 2, -2, 0, 0, 0, 0] }
5890
5891 test_vec_adds! { test_vec_adds_u16x8, u16x8,
5892 [u16::MAX, 0, 1, 2, 0, 0, 0, 0],
5893 [2, 1, 0, 0, 0, 0, 0, 0],
5894 [u16::MAX, 1, 1, 2, 0, 0, 0, 0] }
5895
5896 test_vec_adds! { test_vec_adds_i8x16, i8x16,
5897 [i8::MIN, i8::MAX, 1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5898 [-1, 1, 1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5899 [i8::MIN, i8::MAX, 2, -2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] }
5900
5901 test_vec_adds! { test_vec_adds_u8x16, u8x16,
5902 [u8::MAX, 0, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5903 [2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5904 [u8::MAX, 1, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] }
5905
5906 test_vec_2! { test_vec_addc, vec_addc, u32x4, [u32::MAX, 0, 0, 0], [1, 1, 1, 1], [1, 0, 0, 0] }
5907
5908 macro_rules! test_vec_abs {
5909 { $name: ident, $ty: ident, $a: expr, $d: expr } => {
5910 #[simd_test(enable = "altivec")]
5911 unsafe fn $name() {
5912 let a = vec_splats($a);
5913 let a: s_t_l!($ty) = vec_abs(a);
5914 let d = $ty::splat($d);
5915 assert_eq!(d, transmute(a));
5916 }
5917 }
5918 }
5919
5920 test_vec_abs! { test_vec_abs_i8, i8x16, -42i8, 42i8 }
5921 test_vec_abs! { test_vec_abs_i16, i16x8, -42i16, 42i16 }
5922 test_vec_abs! { test_vec_abs_i32, i32x4, -42i32, 42i32 }
5923 test_vec_abs! { test_vec_abs_f32, f32x4, -42f32, 42f32 }
5924
5925 macro_rules! test_vec_abss {
5926 { $name: ident, $ty: ident, $a: expr, $d: expr } => {
5927 #[simd_test(enable = "altivec")]
5928 unsafe fn $name() {
5929 let a = vec_splats($a);
5930 let a: s_t_l!($ty) = vec_abss(a);
5931 let d = $ty::splat($d);
5932 assert_eq!(d, transmute(a));
5933 }
5934 }
5935 }
5936
5937 test_vec_abss! { test_vec_abss_i8, i8x16, -127i8, 127i8 }
5938 test_vec_abss! { test_vec_abss_i16, i16x8, -42i16, 42i16 }
5939 test_vec_abss! { test_vec_abss_i32, i32x4, -42i32, 42i32 }
5940
5941 macro_rules! test_vec_splats {
5942 { $name: ident, $ty: ident, $a: expr } => {
5943 #[simd_test(enable = "altivec")]
5944 unsafe fn $name() {
5945 let a: s_t_l!($ty) = vec_splats($a);
5946 let d = $ty::splat($a);
5947 assert_eq!(d, transmute(a));
5948 }
5949 }
5950 }
5951
5952 test_vec_splats! { test_vec_splats_u8, u8x16, 42u8 }
5953 test_vec_splats! { test_vec_splats_u16, u16x8, 42u16 }
5954 test_vec_splats! { test_vec_splats_u32, u32x4, 42u32 }
5955 test_vec_splats! { test_vec_splats_i8, i8x16, 42i8 }
5956 test_vec_splats! { test_vec_splats_i16, i16x8, 42i16 }
5957 test_vec_splats! { test_vec_splats_i32, i32x4, 42i32 }
5958 test_vec_splats! { test_vec_splats_f32, f32x4, 42f32 }
5959
5960 macro_rules! test_vec_splat {
5961 { $name: ident, $fun: ident, $ty: ident, $a: expr, $b: expr} => {
5962 #[simd_test(enable = "altivec")]
5963 unsafe fn $name() {
5964 let a = $fun::<$a>();
5965 let d = $ty::splat($b);
5966 assert_eq!(d, transmute(a));
5967 }
5968 }
5969 }
5970
5971 test_vec_splat! { test_vec_splat_u8, vec_splat_u8, u8x16, -1, u8::MAX }
5972 test_vec_splat! { test_vec_splat_u16, vec_splat_u16, u16x8, -1, u16::MAX }
5973 test_vec_splat! { test_vec_splat_u32, vec_splat_u32, u32x4, -1, u32::MAX }
5974 test_vec_splat! { test_vec_splat_s8, vec_splat_s8, i8x16, -1, -1 }
5975 test_vec_splat! { test_vec_splat_s16, vec_splat_s16, i16x8, -1, -1 }
5976 test_vec_splat! { test_vec_splat_s32, vec_splat_s32, i32x4, -1, -1 }
5977
5978 macro_rules! test_vec_sub {
5979 { $name: ident, $ty: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => {
5980 test_vec_2! {$name, vec_sub, $ty, [$($a),+], [$($b),+], [$($d),+] }
5981 }
5982 }
5983
5984 test_vec_sub! { test_vec_sub_f32x4, f32x4,
5985 [-1.0, 0.0, 1.0, 2.0],
5986 [2.0, 1.0, -1.0, -2.0],
5987 [-3.0, -1.0, 2.0, 4.0] }
5988
5989 test_vec_sub! { test_vec_sub_i32x4, i32x4,
5990 [-1, 0, 1, 2],
5991 [2, 1, -1, -2],
5992 [-3, -1, 2, 4] }
5993
5994 test_vec_sub! { test_vec_sub_u32x4, u32x4,
5995 [0, 0, 1, 2],
5996 [2, 1, 0, 0],
5997 [4294967294, 4294967295, 1, 2] }
5998
5999 test_vec_sub! { test_vec_sub_i16x8, i16x8,
6000 [-1, 0, 1, 2, -1, 0, 1, 2],
6001 [2, 1, -1, -2, 2, 1, -1, -2],
6002 [-3, -1, 2, 4, -3, -1, 2, 4] }
6003
6004 test_vec_sub! { test_vec_sub_u16x8, u16x8,
6005 [0, 0, 1, 2, 0, 0, 1, 2],
6006 [2, 1, 0, 0, 2, 1, 0, 0],
6007 [65534, 65535, 1, 2, 65534, 65535, 1, 2] }
6008
6009 test_vec_sub! { test_vec_sub_i8x16, i8x16,
6010 [-1, 0, 1, 2, -1, 0, 1, 2, -1, 0, 1, 2, -1, 0, 1, 2],
6011 [2, 1, -1, -2, 2, 1, -1, -2, 2, 1, -1, -2, 2, 1, -1, -2],
6012 [-3, -1, 2, 4, -3, -1, 2, 4, -3, -1, 2, 4, -3, -1, 2, 4] }
6013
6014 test_vec_sub! { test_vec_sub_u8x16, u8x16,
6015 [0, 0, 1, 2, 0, 0, 1, 2, 0, 0, 1, 2, 0, 0, 1, 2],
6016 [2, 1, 0, 0, 2, 1, 0, 0, 2, 1, 0, 0, 2, 1, 0, 0],
6017 [254, 255, 1, 2, 254, 255, 1, 2, 254, 255, 1, 2, 254, 255, 1, 2] }
6018
6019 macro_rules! test_vec_subs {
6020 { $name: ident, $ty: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => {
6021 test_vec_2! {$name, vec_subs, $ty, [$($a),+], [$($b),+], [$($d),+] }
6022 }
6023 }
6024
6025 test_vec_subs! { test_vec_subs_i32x4, i32x4,
6026 [-1, 0, 1, 2],
6027 [2, 1, -1, -2],
6028 [-3, -1, 2, 4] }
6029
6030 test_vec_subs! { test_vec_subs_u32x4, u32x4,
6031 [0, 0, 1, 2],
6032 [2, 1, 0, 0],
6033 [0, 0, 1, 2] }
6034
6035 test_vec_subs! { test_vec_subs_i16x8, i16x8,
6036 [-1, 0, 1, 2, -1, 0, 1, 2],
6037 [2, 1, -1, -2, 2, 1, -1, -2],
6038 [-3, -1, 2, 4, -3, -1, 2, 4] }
6039
6040 test_vec_subs! { test_vec_subs_u16x8, u16x8,
6041 [0, 0, 1, 2, 0, 0, 1, 2],
6042 [2, 1, 0, 0, 2, 1, 0, 0],
6043 [0, 0, 1, 2, 0, 0, 1, 2] }
6044
6045 test_vec_subs! { test_vec_subs_i8x16, i8x16,
6046 [-1, 0, 1, 2, -1, 0, 1, 2, -1, 0, 1, 2, -1, 0, 1, 2],
6047 [2, 1, -1, -2, 2, 1, -1, -2, 2, 1, -1, -2, 2, 1, -1, -2],
6048 [-3, -1, 2, 4, -3, -1, 2, 4, -3, -1, 2, 4, -3, -1, 2, 4] }
6049
6050 test_vec_subs! { test_vec_subs_u8x16, u8x16,
6051 [0, 0, 1, 2, 0, 0, 1, 2, 0, 0, 1, 2, 0, 0, 1, 2],
6052 [2, 1, 0, 0, 2, 1, 0, 0, 2, 1, 0, 0, 2, 1, 0, 0],
6053 [0, 0, 1, 2, 0, 0, 1, 2, 0, 0, 1, 2, 0, 0, 1, 2] }
6054
6055 macro_rules! test_vec_min {
6056 { $name: ident, $ty: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => {
6057 #[simd_test(enable = "altivec")]
6058 unsafe fn $name() {
6059 let a: s_t_l!($ty) = transmute($ty::new($($a),+));
6060 let b: s_t_l!($ty) = transmute($ty::new($($b),+));
6061
6062 let d = $ty::new($($d),+);
6063 let r : $ty = transmute(vec_min(a, b));
6064 assert_eq!(d, r);
6065 }
6066 }
6067 }
6068
6069 test_vec_min! { test_vec_min_i32x4, i32x4,
6070 [-1, 0, 1, 2],
6071 [2, 1, -1, -2],
6072 [-1, 0, -1, -2] }
6073
6074 test_vec_min! { test_vec_min_u32x4, u32x4,
6075 [0, 0, 1, 2],
6076 [2, 1, 0, 0],
6077 [0, 0, 0, 0] }
6078
6079 test_vec_min! { test_vec_min_i16x8, i16x8,
6080 [-1, 0, 1, 2, -1, 0, 1, 2],
6081 [2, 1, -1, -2, 2, 1, -1, -2],
6082 [-1, 0, -1, -2, -1, 0, -1, -2] }
6083
6084 test_vec_min! { test_vec_min_u16x8, u16x8,
6085 [0, 0, 1, 2, 0, 0, 1, 2],
6086 [2, 1, 0, 0, 2, 1, 0, 0],
6087 [0, 0, 0, 0, 0, 0, 0, 0] }
6088
6089 test_vec_min! { test_vec_min_i8x16, i8x16,
6090 [-1, 0, 1, 2, -1, 0, 1, 2, -1, 0, 1, 2, -1, 0, 1, 2],
6091 [2, 1, -1, -2, 2, 1, -1, -2, 2, 1, -1, -2, 2, 1, -1, -2],
6092 [-1, 0, -1, -2, -1, 0, -1, -2, -1, 0, -1, -2, -1, 0, -1, -2] }
6093
6094 test_vec_min! { test_vec_min_u8x16, u8x16,
6095 [0, 0, 1, 2, 0, 0, 1, 2, 0, 0, 1, 2, 0, 0, 1, 2],
6096 [2, 1, 0, 0, 2, 1, 0, 0, 2, 1, 0, 0, 2, 1, 0, 0],
6097 [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] }
6098
6099 macro_rules! test_vec_max {
6100 { $name: ident, $ty: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => {
6101 #[simd_test(enable = "altivec")]
6102 unsafe fn $name() {
6103 let a: s_t_l!($ty) = transmute($ty::new($($a),+));
6104 let b: s_t_l!($ty) = transmute($ty::new($($b),+));
6105
6106 let d = $ty::new($($d),+);
6107 let r : $ty = transmute(vec_max(a, b));
6108 assert_eq!(d, r);
6109 }
6110 }
6111 }
6112
6113 test_vec_max! { test_vec_max_i32x4, i32x4,
6114 [-1, 0, 1, 2],
6115 [2, 1, -1, -2],
6116 [2, 1, 1, 2] }
6117
6118 test_vec_max! { test_vec_max_u32x4, u32x4,
6119 [0, 0, 1, 2],
6120 [2, 1, 0, 0],
6121 [2, 1, 1, 2] }
6122
6123 test_vec_max! { test_vec_max_i16x8, i16x8,
6124 [-1, 0, 1, 2, -1, 0, 1, 2],
6125 [2, 1, -1, -2, 2, 1, -1, -2],
6126 [2, 1, 1, 2, 2, 1, 1, 2] }
6127
6128 test_vec_max! { test_vec_max_u16x8, u16x8,
6129 [0, 0, 1, 2, 0, 0, 1, 2],
6130 [2, 1, 0, 0, 2, 1, 0, 0],
6131 [2, 1, 1, 2, 2, 1, 1, 2] }
6132
6133 test_vec_max! { test_vec_max_i8x16, i8x16,
6134 [-1, 0, 1, 2, -1, 0, 1, 2, -1, 0, 1, 2, -1, 0, 1, 2],
6135 [2, 1, -1, -2, 2, 1, -1, -2, 2, 1, -1, -2, 2, 1, -1, -2],
6136 [2, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, 2] }
6137
6138 test_vec_max! { test_vec_max_u8x16, u8x16,
6139 [0, 0, 1, 2, 0, 0, 1, 2, 0, 0, 1, 2, 0, 0, 1, 2],
6140 [2, 1, 0, 0, 2, 1, 0, 0, 2, 1, 0, 0, 2, 1, 0, 0],
6141 [2, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, 2] }
6142
6143 macro_rules! test_vec_perm {
6144 {$name:ident,
6145 $shorttype:ident, $longtype:ident,
6146 [$($a:expr),+], [$($b:expr),+], [$($c:expr),+], [$($d:expr),+]} => {
6147 #[simd_test(enable = "altivec")]
6148 unsafe fn $name() {
6149 let a: $longtype = transmute($shorttype::new($($a),+));
6150 let b: $longtype = transmute($shorttype::new($($b),+));
6151 let c: vector_unsigned_char = transmute(u8x16::new($($c),+));
6152 let d = $shorttype::new($($d),+);
6153
6154 let r: $shorttype = transmute(vec_perm(a, b, c));
6155 assert_eq!(d, r);
6156 }
6157 }
6158 }
6159
6160 test_vec_perm! {test_vec_perm_u8x16,
6161 u8x16, vector_unsigned_char,
6162 [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15],
6163 [100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115],
6164 [0x00, 0x01, 0x10, 0x11, 0x02, 0x03, 0x12, 0x13,
6165 0x04, 0x05, 0x14, 0x15, 0x06, 0x07, 0x16, 0x17],
6166 [0, 1, 100, 101, 2, 3, 102, 103, 4, 5, 104, 105, 6, 7, 106, 107]}
6167 test_vec_perm! {test_vec_perm_i8x16,
6168 i8x16, vector_signed_char,
6169 [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15],
6170 [100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115],
6171 [0x00, 0x01, 0x10, 0x11, 0x02, 0x03, 0x12, 0x13,
6172 0x04, 0x05, 0x14, 0x15, 0x06, 0x07, 0x16, 0x17],
6173 [0, 1, 100, 101, 2, 3, 102, 103, 4, 5, 104, 105, 6, 7, 106, 107]}
6174
6175 test_vec_perm! {test_vec_perm_m8x16,
6176 m8x16, vector_bool_char,
6177 [false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false],
6178 [true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true],
6179 [0x00, 0x01, 0x10, 0x11, 0x02, 0x03, 0x12, 0x13,
6180 0x04, 0x05, 0x14, 0x15, 0x06, 0x07, 0x16, 0x17],
6181 [false, false, true, true, false, false, true, true, false, false, true, true, false, false, true, true]}
6182 test_vec_perm! {test_vec_perm_u16x8,
6183 u16x8, vector_unsigned_short,
6184 [0, 1, 2, 3, 4, 5, 6, 7],
6185 [10, 11, 12, 13, 14, 15, 16, 17],
6186 [0x00, 0x01, 0x10, 0x11, 0x02, 0x03, 0x12, 0x13,
6187 0x04, 0x05, 0x14, 0x15, 0x06, 0x07, 0x16, 0x17],
6188 [0, 10, 1, 11, 2, 12, 3, 13]}
6189 test_vec_perm! {test_vec_perm_i16x8,
6190 i16x8, vector_signed_short,
6191 [0, 1, 2, 3, 4, 5, 6, 7],
6192 [10, 11, 12, 13, 14, 15, 16, 17],
6193 [0x00, 0x01, 0x10, 0x11, 0x02, 0x03, 0x12, 0x13,
6194 0x04, 0x05, 0x14, 0x15, 0x06, 0x07, 0x16, 0x17],
6195 [0, 10, 1, 11, 2, 12, 3, 13]}
6196 test_vec_perm! {test_vec_perm_m16x8,
6197 m16x8, vector_bool_short,
6198 [false, false, false, false, false, false, false, false],
6199 [true, true, true, true, true, true, true, true],
6200 [0x00, 0x01, 0x10, 0x11, 0x02, 0x03, 0x12, 0x13,
6201 0x04, 0x05, 0x14, 0x15, 0x06, 0x07, 0x16, 0x17],
6202 [false, true, false, true, false, true, false, true]}
6203
6204 test_vec_perm! {test_vec_perm_u32x4,
6205 u32x4, vector_unsigned_int,
6206 [0, 1, 2, 3],
6207 [10, 11, 12, 13],
6208 [0x00, 0x01, 0x02, 0x03, 0x10, 0x11, 0x12, 0x13,
6209 0x04, 0x05, 0x06, 0x07, 0x14, 0x15, 0x16, 0x17],
6210 [0, 10, 1, 11]}
6211 test_vec_perm! {test_vec_perm_i32x4,
6212 i32x4, vector_signed_int,
6213 [0, 1, 2, 3],
6214 [10, 11, 12, 13],
6215 [0x00, 0x01, 0x02, 0x03, 0x10, 0x11, 0x12, 0x13,
6216 0x04, 0x05, 0x06, 0x07, 0x14, 0x15, 0x16, 0x17],
6217 [0, 10, 1, 11]}
6218 test_vec_perm! {test_vec_perm_m32x4,
6219 m32x4, vector_bool_int,
6220 [false, false, false, false],
6221 [true, true, true, true],
6222 [0x00, 0x01, 0x02, 0x03, 0x10, 0x11, 0x12, 0x13,
6223 0x04, 0x05, 0x06, 0x07, 0x14, 0x15, 0x16, 0x17],
6224 [false, true, false, true]}
6225 test_vec_perm! {test_vec_perm_f32x4,
6226 f32x4, vector_float,
6227 [0.0, 1.0, 2.0, 3.0],
6228 [1.0, 1.1, 1.2, 1.3],
6229 [0x00, 0x01, 0x02, 0x03, 0x10, 0x11, 0x12, 0x13,
6230 0x04, 0x05, 0x06, 0x07, 0x14, 0x15, 0x16, 0x17],
6231 [0.0, 1.0, 1.0, 1.1]}
6232
6233 #[simd_test(enable = "altivec")]
6234 unsafe fn test_vec_madds() {
6235 let a: vector_signed_short = transmute(i16x8::new(
6236 0 * 256,
6237 1 * 256,
6238 2 * 256,
6239 3 * 256,
6240 4 * 256,
6241 5 * 256,
6242 6 * 256,
6243 7 * 256,
6244 ));
6245 let b: vector_signed_short = transmute(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256));
6246 let c: vector_signed_short = transmute(i16x8::new(0, 1, 2, 3, 4, 5, 6, 7));
6247
6248 let d = i16x8::new(0, 3, 6, 9, 12, 15, 18, 21);
6249
6250 assert_eq!(d, transmute(vec_madds(a, b, c)));
6251 }
6252
6253 #[simd_test(enable = "altivec")]
6254 unsafe fn test_vec_madd_float() {
6255 let a: vector_float = transmute(f32x4::new(0.1, 0.2, 0.3, 0.4));
6256 let b: vector_float = transmute(f32x4::new(0.1, 0.2, 0.3, 0.4));
6257 let c: vector_float = transmute(f32x4::new(0.1, 0.2, 0.3, 0.4));
6258 let d = f32x4::new(
6259 0.1 * 0.1 + 0.1,
6260 0.2 * 0.2 + 0.2,
6261 0.3 * 0.3 + 0.3,
6262 0.4 * 0.4 + 0.4,
6263 );
6264
6265 assert_eq!(d, transmute(vec_madd(a, b, c)));
6266 }
6267
6268 #[simd_test(enable = "altivec")]
6269 unsafe fn test_vec_nmsub_float() {
6270 let a: vector_float = transmute(f32x4::new(0.1, 0.2, 0.3, 0.4));
6271 let b: vector_float = transmute(f32x4::new(0.1, 0.2, 0.3, 0.4));
6272 let c: vector_float = transmute(f32x4::new(0.1, 0.2, 0.3, 0.4));
6273 let d = f32x4::new(
6274 -(0.1 * 0.1 - 0.1),
6275 -(0.2 * 0.2 - 0.2),
6276 -(0.3 * 0.3 - 0.3),
6277 -(0.4 * 0.4 - 0.4),
6278 );
6279 assert_eq!(d, transmute(vec_nmsub(a, b, c)));
6280 }
6281
6282 #[simd_test(enable = "altivec")]
6283 unsafe fn test_vec_mradds() {
6284 let a: vector_signed_short = transmute(i16x8::new(
6285 0 * 256,
6286 1 * 256,
6287 2 * 256,
6288 3 * 256,
6289 4 * 256,
6290 5 * 256,
6291 6 * 256,
6292 7 * 256,
6293 ));
6294 let b: vector_signed_short = transmute(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256));
6295 let c: vector_signed_short = transmute(i16x8::new(0, 1, 2, 3, 4, 5, 6, i16::MAX - 1));
6296
6297 let d = i16x8::new(0, 3, 6, 9, 12, 15, 18, i16::MAX);
6298
6299 assert_eq!(d, transmute(vec_mradds(a, b, c)));
6300 }
6301
6302 macro_rules! test_vec_mladd {
6303 {$name:ident, $sa:ident, $la:ident, $sbc:ident, $lbc:ident, $sd:ident,
6304 [$($a:expr),+], [$($b:expr),+], [$($c:expr),+], [$($d:expr),+]} => {
6305 #[simd_test(enable = "altivec")]
6306 unsafe fn $name() {
6307 let a: $la = transmute($sa::new($($a),+));
6308 let b: $lbc = transmute($sbc::new($($b),+));
6309 let c = transmute($sbc::new($($c),+));
6310 let d = $sd::new($($d),+);
6311
6312 assert_eq!(d, transmute(vec_mladd(a, b, c)));
6313 }
6314 }
6315 }
6316
6317 test_vec_mladd! { test_vec_mladd_u16x8_u16x8, u16x8, vector_unsigned_short, u16x8, vector_unsigned_short, u16x8,
6318 [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 2, 6, 12, 20, 30, 42, 56]
6319 }
6320 test_vec_mladd! { test_vec_mladd_u16x8_i16x8, u16x8, vector_unsigned_short, i16x8, vector_unsigned_short, i16x8,
6321 [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 2, 6, 12, 20, 30, 42, 56]
6322 }
6323 test_vec_mladd! { test_vec_mladd_i16x8_u16x8, i16x8, vector_signed_short, u16x8, vector_unsigned_short, i16x8,
6324 [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 2, 6, 12, 20, 30, 42, 56]
6325 }
6326 test_vec_mladd! { test_vec_mladd_i16x8_i16x8, i16x8, vector_signed_short, i16x8, vector_unsigned_short, i16x8,
6327 [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 2, 6, 12, 20, 30, 42, 56]
6328 }
6329
6330 #[simd_test(enable = "altivec")]
6331 unsafe fn test_vec_msum_unsigned_char() {
6332 let a: vector_unsigned_char =
6333 transmute(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
6334 let b: vector_unsigned_char = transmute(u8x16::new(
6335 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
6336 ));
6337 let c: vector_unsigned_int = transmute(u32x4::new(0, 1, 2, 3));
6338 let d = u32x4::new(
6339 (0 + 1 + 2 + 3) * 255 + 0,
6340 (4 + 5 + 6 + 7) * 255 + 1,
6341 (0 + 1 + 2 + 3) * 255 + 2,
6342 (4 + 5 + 6 + 7) * 255 + 3,
6343 );
6344
6345 assert_eq!(d, transmute(vec_msum(a, b, c)));
6346 }
6347
6348 #[simd_test(enable = "altivec")]
6349 unsafe fn test_vec_msum_signed_char() {
6350 let a: vector_signed_char = transmute(i8x16::new(
6351 0, -1, 2, -3, 1, -1, 1, -1, 0, 1, 2, 3, 4, -5, -6, -7,
6352 ));
6353 let b: vector_unsigned_char =
6354 transmute(i8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1));
6355 let c: vector_signed_int = transmute(u32x4::new(0, 1, 2, 3));
6356 let d = i32x4::new(
6357 (0 - 1 + 2 - 3) + 0,
6358 (0) + 1,
6359 (0 + 1 + 2 + 3) + 2,
6360 (4 - 5 - 6 - 7) + 3,
6361 );
6362
6363 assert_eq!(d, transmute(vec_msum(a, b, c)));
6364 }
6365 #[simd_test(enable = "altivec")]
6366 unsafe fn test_vec_msum_unsigned_short() {
6367 let a: vector_unsigned_short = transmute(u16x8::new(
6368 0 * 256,
6369 1 * 256,
6370 2 * 256,
6371 3 * 256,
6372 4 * 256,
6373 5 * 256,
6374 6 * 256,
6375 7 * 256,
6376 ));
6377 let b: vector_unsigned_short =
6378 transmute(u16x8::new(256, 256, 256, 256, 256, 256, 256, 256));
6379 let c: vector_unsigned_int = transmute(u32x4::new(0, 1, 2, 3));
6380 let d = u32x4::new(
6381 (0 + 1) * 256 * 256 + 0,
6382 (2 + 3) * 256 * 256 + 1,
6383 (4 + 5) * 256 * 256 + 2,
6384 (6 + 7) * 256 * 256 + 3,
6385 );
6386
6387 assert_eq!(d, transmute(vec_msum(a, b, c)));
6388 }
6389
6390 #[simd_test(enable = "altivec")]
6391 unsafe fn test_vec_msum_signed_short() {
6392 let a: vector_signed_short = transmute(i16x8::new(
6393 0 * 256,
6394 -1 * 256,
6395 2 * 256,
6396 -3 * 256,
6397 4 * 256,
6398 -5 * 256,
6399 6 * 256,
6400 -7 * 256,
6401 ));
6402 let b: vector_signed_short = transmute(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256));
6403 let c: vector_signed_int = transmute(i32x4::new(0, 1, 2, 3));
6404 let d = i32x4::new(
6405 (0 - 1) * 256 * 256 + 0,
6406 (2 - 3) * 256 * 256 + 1,
6407 (4 - 5) * 256 * 256 + 2,
6408 (6 - 7) * 256 * 256 + 3,
6409 );
6410
6411 assert_eq!(d, transmute(vec_msum(a, b, c)));
6412 }
6413
6414 #[simd_test(enable = "altivec")]
6415 unsafe fn test_vec_msums_unsigned() {
6416 let a: vector_unsigned_short = transmute(u16x8::new(
6417 0 * 256,
6418 1 * 256,
6419 2 * 256,
6420 3 * 256,
6421 4 * 256,
6422 5 * 256,
6423 6 * 256,
6424 7 * 256,
6425 ));
6426 let b: vector_unsigned_short =
6427 transmute(u16x8::new(256, 256, 256, 256, 256, 256, 256, 256));
6428 let c: vector_unsigned_int = transmute(u32x4::new(0, 1, 2, 3));
6429 let d = u32x4::new(
6430 (0 + 1) * 256 * 256 + 0,
6431 (2 + 3) * 256 * 256 + 1,
6432 (4 + 5) * 256 * 256 + 2,
6433 (6 + 7) * 256 * 256 + 3,
6434 );
6435
6436 assert_eq!(d, transmute(vec_msums(a, b, c)));
6437 }
6438
6439 #[simd_test(enable = "altivec")]
6440 unsafe fn test_vec_msums_signed() {
6441 let a: vector_signed_short = transmute(i16x8::new(
6442 0 * 256,
6443 -1 * 256,
6444 2 * 256,
6445 -3 * 256,
6446 4 * 256,
6447 -5 * 256,
6448 6 * 256,
6449 -7 * 256,
6450 ));
6451 let b: vector_signed_short = transmute(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256));
6452 let c: vector_signed_int = transmute(i32x4::new(0, 1, 2, 3));
6453 let d = i32x4::new(
6454 (0 - 1) * 256 * 256 + 0,
6455 (2 - 3) * 256 * 256 + 1,
6456 (4 - 5) * 256 * 256 + 2,
6457 (6 - 7) * 256 * 256 + 3,
6458 );
6459
6460 assert_eq!(d, transmute(vec_msums(a, b, c)));
6461 }
6462
6463 #[simd_test(enable = "altivec")]
6464 unsafe fn test_vec_sum2s() {
6465 let a: vector_signed_int = transmute(i32x4::new(0, 1, 2, 3));
6466 let b: vector_signed_int = transmute(i32x4::new(0, 1, 2, 3));
6467 let d = i32x4::new(0, 0 + 1 + 1, 0, 2 + 3 + 3);
6468
6469 assert_eq!(d, transmute(vec_sum2s(a, b)));
6470 }
6471
6472 #[simd_test(enable = "altivec")]
6473 unsafe fn test_vec_sum4s_unsigned_char() {
6474 let a: vector_unsigned_char =
6475 transmute(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
6476 let b: vector_unsigned_int = transmute(u32x4::new(0, 1, 2, 3));
6477 let d = u32x4::new(
6478 0 + 1 + 2 + 3 + 0,
6479 4 + 5 + 6 + 7 + 1,
6480 0 + 1 + 2 + 3 + 2,
6481 4 + 5 + 6 + 7 + 3,
6482 );
6483
6484 assert_eq!(d, transmute(vec_sum4s(a, b)));
6485 }
6486 #[simd_test(enable = "altivec")]
6487 unsafe fn test_vec_sum4s_signed_char() {
6488 let a: vector_signed_char =
6489 transmute(i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
6490 let b: vector_signed_int = transmute(i32x4::new(0, 1, 2, 3));
6491 let d = i32x4::new(
6492 0 + 1 + 2 + 3 + 0,
6493 4 + 5 + 6 + 7 + 1,
6494 0 + 1 + 2 + 3 + 2,
6495 4 + 5 + 6 + 7 + 3,
6496 );
6497
6498 assert_eq!(d, transmute(vec_sum4s(a, b)));
6499 }
6500 #[simd_test(enable = "altivec")]
6501 unsafe fn test_vec_sum4s_signed_short() {
6502 let a: vector_signed_short = transmute(i16x8::new(0, 1, 2, 3, 4, 5, 6, 7));
6503 let b: vector_signed_int = transmute(i32x4::new(0, 1, 2, 3));
6504 let d = i32x4::new(0 + 1 + 0, 2 + 3 + 1, 4 + 5 + 2, 6 + 7 + 3);
6505
6506 assert_eq!(d, transmute(vec_sum4s(a, b)));
6507 }
6508
6509 #[simd_test(enable = "altivec")]
6510 unsafe fn test_vec_mule_unsigned_char() {
6511 let a: vector_unsigned_char =
6512 transmute(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
6513 let d = u16x8::new(0 * 0, 2 * 2, 4 * 4, 6 * 6, 0 * 0, 2 * 2, 4 * 4, 6 * 6);
6514
6515 assert_eq!(d, transmute(vec_mule(a, a)));
6516 }
6517
6518 #[simd_test(enable = "altivec")]
6519 unsafe fn test_vec_mule_signed_char() {
6520 let a: vector_signed_char = transmute(i8x16::new(
6521 0, 1, -2, 3, -4, 5, -6, 7, 0, 1, 2, 3, 4, 5, 6, 7,
6522 ));
6523 let d = i16x8::new(0 * 0, 2 * 2, 4 * 4, 6 * 6, 0 * 0, 2 * 2, 4 * 4, 6 * 6);
6524
6525 assert_eq!(d, transmute(vec_mule(a, a)));
6526 }
6527
6528 #[simd_test(enable = "altivec")]
6529 unsafe fn test_vec_mule_unsigned_short() {
6530 let a: vector_unsigned_short = transmute(u16x8::new(0, 1, 2, 3, 4, 5, 6, 7));
6531 let d = u32x4::new(0 * 0, 2 * 2, 4 * 4, 6 * 6);
6532
6533 assert_eq!(d, transmute(vec_mule(a, a)));
6534 }
6535
6536 #[simd_test(enable = "altivec")]
6537 unsafe fn test_vec_mule_signed_short() {
6538 let a: vector_signed_short = transmute(i16x8::new(0, 1, -2, 3, -4, 5, -6, 7));
6539 let d = i32x4::new(0 * 0, 2 * 2, 4 * 4, 6 * 6);
6540
6541 assert_eq!(d, transmute(vec_mule(a, a)));
6542 }
6543
6544 #[simd_test(enable = "altivec")]
6545 unsafe fn test_vec_mulo_unsigned_char() {
6546 let a: vector_unsigned_char =
6547 transmute(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
6548 let d = u16x8::new(1 * 1, 3 * 3, 5 * 5, 7 * 7, 1 * 1, 3 * 3, 5 * 5, 7 * 7);
6549
6550 assert_eq!(d, transmute(vec_mulo(a, a)));
6551 }
6552
6553 #[simd_test(enable = "altivec")]
6554 unsafe fn test_vec_mulo_signed_char() {
6555 let a: vector_signed_char = transmute(i8x16::new(
6556 0, 1, -2, 3, -4, 5, -6, 7, 0, 1, 2, 3, 4, 5, 6, 7,
6557 ));
6558 let d = i16x8::new(1 * 1, 3 * 3, 5 * 5, 7 * 7, 1 * 1, 3 * 3, 5 * 5, 7 * 7);
6559
6560 assert_eq!(d, transmute(vec_mulo(a, a)));
6561 }
6562
6563 #[simd_test(enable = "altivec")]
6564 unsafe fn test_vec_mulo_unsigned_short() {
6565 let a: vector_unsigned_short = transmute(u16x8::new(0, 1, 2, 3, 4, 5, 6, 7));
6566 let d = u32x4::new(1 * 1, 3 * 3, 5 * 5, 7 * 7);
6567
6568 assert_eq!(d, transmute(vec_mulo(a, a)));
6569 }
6570
6571 #[simd_test(enable = "altivec")]
6572 unsafe fn test_vec_mulo_signed_short() {
6573 let a: vector_signed_short = transmute(i16x8::new(0, 1, -2, 3, -4, 5, -6, 7));
6574 let d = i32x4::new(1 * 1, 3 * 3, 5 * 5, 7 * 7);
6575
6576 assert_eq!(d, transmute(vec_mulo(a, a)));
6577 }
6578
6579 #[simd_test(enable = "altivec")]
6580 unsafe fn vec_add_i32x4_i32x4() {
6581 let x = i32x4::new(1, 2, 3, 4);
6582 let y = i32x4::new(4, 3, 2, 1);
6583 let x: vector_signed_int = transmute(x);
6584 let y: vector_signed_int = transmute(y);
6585 let z = vec_add(x, y);
6586 assert_eq!(i32x4::splat(5), transmute(z));
6587 }
6588
6589 #[simd_test(enable = "altivec")]
6590 unsafe fn vec_ctf_u32() {
6591 let v: vector_unsigned_int = transmute(u32x4::new(u32::MIN, u32::MAX, u32::MAX, 42));
6592 let v2 = vec_ctf::<1, _>(v);
6593 let r2: vector_float = transmute(f32x4::new(0.0, 2147483600.0, 2147483600.0, 21.0));
6594 let v4 = vec_ctf::<2, _>(v);
6595 let r4: vector_float = transmute(f32x4::new(0.0, 1073741800.0, 1073741800.0, 10.5));
6596 let v8 = vec_ctf::<3, _>(v);
6597 let r8: vector_float = transmute(f32x4::new(0.0, 536870900.0, 536870900.0, 5.25));
6598
6599 let check = |a, b| {
6600 let r = transmute(vec_cmple(vec_abs(vec_sub(a, b)), vec_splats(f32::EPSILON)));
6601 let e = m32x4::new(true, true, true, true);
6602 assert_eq!(e, r);
6603 };
6604
6605 check(v2, r2);
6606 check(v4, r4);
6607 check(v8, r8);
6608 }
6609
6610 #[simd_test(enable = "altivec")]
6611 unsafe fn test_vec_ctu() {
6612 let v = u32x4::new(u32::MIN, u32::MAX, u32::MAX, 42);
6613 let v2: u32x4 = transmute(vec_ctu::<1>(transmute(f32x4::new(
6614 0.0,
6615 2147483600.0,
6616 2147483600.0,
6617 21.0,
6618 ))));
6619 let v4: u32x4 = transmute(vec_ctu::<2>(transmute(f32x4::new(
6620 0.0,
6621 1073741800.0,
6622 1073741800.0,
6623 10.5,
6624 ))));
6625 let v8: u32x4 = transmute(vec_ctu::<3>(transmute(f32x4::new(
6626 0.0,
6627 536870900.0,
6628 536870900.0,
6629 5.25,
6630 ))));
6631
6632 assert_eq!(v2, v);
6633 assert_eq!(v4, v);
6634 assert_eq!(v8, v);
6635 }
6636
6637 #[simd_test(enable = "altivec")]
6638 unsafe fn vec_ctf_i32() {
6639 let v: vector_signed_int = transmute(i32x4::new(i32::MIN, i32::MAX, i32::MAX - 42, 42));
6640 let v2 = vec_ctf::<1, _>(v);
6641 let r2: vector_float =
6642 transmute(f32x4::new(-1073741800.0, 1073741800.0, 1073741800.0, 21.0));
6643 let v4 = vec_ctf::<2, _>(v);
6644 let r4: vector_float = transmute(f32x4::new(-536870900.0, 536870900.0, 536870900.0, 10.5));
6645 let v8 = vec_ctf::<3, _>(v);
6646 let r8: vector_float = transmute(f32x4::new(-268435460.0, 268435460.0, 268435460.0, 5.25));
6647
6648 let check = |a, b| {
6649 let r = transmute(vec_cmple(vec_abs(vec_sub(a, b)), vec_splats(f32::EPSILON)));
6650 println!("{:?} {:?}", a, b);
6651 let e = m32x4::new(true, true, true, true);
6652 assert_eq!(e, r);
6653 };
6654
6655 check(v2, r2);
6656 check(v4, r4);
6657 check(v8, r8);
6658 }
6659
6660 #[simd_test(enable = "altivec")]
6661 unsafe fn test_vec_cts() {
6662 let v = i32x4::new(i32::MIN, i32::MAX, i32::MAX, 42);
6663 let v2: i32x4 = transmute(vec_cts::<1>(transmute(f32x4::new(
6664 -1073741800.0,
6665 1073741800.0,
6666 1073741800.0,
6667 21.0,
6668 ))));
6669 let v4: i32x4 = transmute(vec_cts::<2>(transmute(f32x4::new(
6670 -536870900.0,
6671 536870900.0,
6672 536870900.0,
6673 10.5,
6674 ))));
6675 let v8: i32x4 = transmute(vec_cts::<3>(transmute(f32x4::new(
6676 -268435460.0,
6677 268435460.0,
6678 268435460.0,
6679 5.25,
6680 ))));
6681
6682 assert_eq!(v2, v);
6683 assert_eq!(v4, v);
6684 assert_eq!(v8, v);
6685 }
6686
6687 test_vec_2! { test_vec_rl, vec_rl, u32x4,
6688 [0x12345678, 0x9ABCDEF0, 0x0F0F0F0F, 0x12345678],
6689 [4, 8, 12, 68],
6690 [0x23456781, 0xBCDEF09A, 0xF0F0F0F0, 0x23456781]
6691 }
6692}