Keyboard shortcuts

Press or to navigate between chapters

Press S or / to search in the book

Press ? to show this help

Press Esc to hide this help

asm_experimental_reg

The tracking issue for this feature is: #133416


This tracks support for additional registers in architectures where inline assembly is already stable.

Register classes

ArchitectureRegister classRegistersLLVM constraint code
LoongArchvreg$vr[0-31]f
LoongArchxreg$xr[0-31]f
AArch64pregp[0-16]Upa

Register class supported types

ArchitectureRegister classTarget featureAllowed types
LoongArchvreglsxi128, f32, f64,
i8x16, i16x8, i32x4, i64x2, f32x4, f64x2
LoongArchxreglasxi128, f32, f64,
i8x16, i16x8, i32x4, i64x2, f32x4, f64x2,
i8x32, i16x16, i32x8, i64x4, f32x8, f64x4
AArch64vregsvei8xN, i16xB, i32xN, i64xN, f16xN, f32xN, f64xN (scalable vector)
AArch64pregsvei1xN (scalable vector predicate)

Register aliases

ArchitectureBase registerAliases
LoongArch$f[0-7]$fa[0-7], $vr[0-7], $xr[0-7]
LoongArch$f[8-23]$ft[0-15], $vr[8-23], $xr[8-23]
LoongArch$f[24-31]$fs[0-7], $vr[24-31], $xr[24-31]

Unsupported registers

ArchitectureUnsupported registerReason

Template modifiers

ArchitectureRegister classModifierExample outputLLVM modifier
LoongArchfregw$vr0w
LoongArchfregu$xr0u
LoongArchvregNone$vr0w
LoongArchvregu$xr0u
LoongArchxregNone$xr0u
LoongArchxregw$vr0w
AArch64vregzz0z