std_detect/detect/arch/
x86.rs

1//! This module implements minimal run-time feature detection for x86.
2//!
3//! The features are detected using the `detect_features` function below.
4//! This function uses the CPUID instruction to read the feature flags from the
5//! CPU and encodes them in a `usize` where each bit position represents
6//! whether a feature is available (bit is set) or unavailable (bit is cleared).
7//!
8//! The enum `Feature` is used to map bit positions to feature names, and the
9//! the `__crate::detect::check_for!` macro is used to map string literals (e.g.,
10//! "avx") to these bit positions (e.g., `Feature::avx`).
11//!
12//! The run-time feature detection is performed by the
13//! `__crate::detect::check_for(Feature) -> bool` function. On its first call,
14//! this functions queries the CPU for the available features and stores them
15//! in a global `AtomicUsize` variable. The query is performed by just checking
16//! whether the feature bit in this global variable is set or cleared.
17
18features! {
19    @TARGET: x86;
20    @CFG: any(target_arch = "x86", target_arch = "x86_64");
21    @MACRO_NAME: is_x86_feature_detected;
22    @MACRO_ATTRS:
23    /// Check for the presence of a CPU feature at runtime.
24    ///
25    /// When the feature is known to be enabled at compile time (e.g. via `-Ctarget-feature`)
26    /// the macro expands to `true`.
27    ///
28    /// Runtime detection currently relies mostly on the `cpuid` instruction.
29    ///
30    /// This macro only takes one argument which is a string literal of the feature
31    /// being tested for. The feature names supported are the lowercase versions of
32    /// the ones defined by Intel in [their documentation][docs].
33    ///
34    /// ## Supported arguments
35    ///
36    /// This macro supports the same names that `#[target_feature]` supports. Unlike
37    /// `#[target_feature]`, however, this macro does not support names separated
38    /// with a comma. Instead testing for multiple features must be done through
39    /// separate macro invocations for now.
40    ///
41    /// Supported arguments are:
42    ///
43    /// * `"aes"`
44    /// * `"pclmulqdq"`
45    /// * `"rdrand"`
46    /// * `"rdseed"`
47    /// * `"tsc"`
48    /// * `"mmx"`
49    /// * `"sse"`
50    /// * `"sse2"`
51    /// * `"sse3"`
52    /// * `"ssse3"`
53    /// * `"sse4.1"`
54    /// * `"sse4.2"`
55    /// * `"sse4a"`
56    /// * `"sha"`
57    /// * `"avx"`
58    /// * `"avx2"`
59    /// * `"sha512"`
60    /// * `"sm3"`
61    /// * `"sm4"`
62    /// * `"avx512f"`
63    /// * `"avx512cd"`
64    /// * `"avx512er"`
65    /// * `"avx512pf"`
66    /// * `"avx512bw"`
67    /// * `"avx512dq"`
68    /// * `"avx512vl"`
69    /// * `"avx512ifma"`
70    /// * `"avx512vbmi"`
71    /// * `"avx512vpopcntdq"`
72    /// * `"avx512vbmi2"`
73    /// * `"gfni"`
74    /// * `"vaes"`
75    /// * `"vpclmulqdq"`
76    /// * `"avx512vnni"`
77    /// * `"avx512bitalg"`
78    /// * `"avx512bf16"`
79    /// * `"avx512vp2intersect"`
80    /// * `"avx512fp16"`
81    /// * `"avxvnni"`
82    /// * `"avxifma"`
83    /// * `"avxneconvert"`
84    /// * `"avxvnniint8"`
85    /// * `"avxvnniint16"`
86    /// * `"amx-tile"`
87    /// * `"amx-int8"`
88    /// * `"amx-bf16"`
89    /// * `"amx-fp16"`
90    /// * `"amx-complex"`
91    /// * `"amx-avx512"`
92    /// * `"amx-fp8"`
93    /// * `"amx-movrs"`
94    /// * `"amx-tf32"`
95    /// * `"f16c"`
96    /// * `"fma"`
97    /// * `"bmi1"`
98    /// * `"bmi2"`
99    /// * `"abm"`
100    /// * `"lzcnt"`
101    /// * `"tbm"`
102    /// * `"popcnt"`
103    /// * `"fxsr"`
104    /// * `"xsave"`
105    /// * `"xsaveopt"`
106    /// * `"xsaves"`
107    /// * `"xsavec"`
108    /// * `"cmpxchg16b"`
109    /// * `"kl"`
110    /// * `"widekl"`
111    /// * `"adx"`
112    /// * `"rtm"`
113    /// * `"movbe"`
114    /// * `"ermsb"`
115    /// * `"movrs"`
116    /// * `"xop"`
117    ///
118    /// [docs]: https://software.intel.com/sites/landingpage/IntrinsicsGuide
119    #[stable(feature = "simd_x86", since = "1.27.0")]
120    @BIND_FEATURE_NAME: "abm"; "lzcnt"; // abm is a synonym for lzcnt
121    @BIND_FEATURE_NAME: "avx512gfni"; "gfni"; #[deprecated(since = "1.67.0", note = "the `avx512gfni` feature has been renamed to `gfni`")];
122    @BIND_FEATURE_NAME: "avx512vaes"; "vaes"; #[deprecated(since = "1.67.0", note = "the `avx512vaes` feature has been renamed to `vaes`")];
123    @BIND_FEATURE_NAME: "avx512vpclmulqdq"; "vpclmulqdq"; #[deprecated(since = "1.67.0", note = "the `avx512vpclmulqdq` feature has been renamed to `vpclmulqdq`")];
124    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] aes: "aes";
125    /// AES (Advanced Encryption Standard New Instructions AES-NI)
126    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] pclmulqdq: "pclmulqdq";
127    /// CLMUL (Carry-less Multiplication)
128    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] rdrand: "rdrand";
129    /// RDRAND
130    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] rdseed: "rdseed";
131    /// RDSEED
132    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] tsc: "tsc";
133    without cfg check: true;
134    /// TSC (Time Stamp Counter)
135    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] mmx: "mmx";
136    without cfg check: true;
137    /// MMX (MultiMedia eXtensions)
138    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] sse: "sse";
139    /// SSE (Streaming SIMD Extensions)
140    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] sse2: "sse2";
141    /// SSE2 (Streaming SIMD Extensions 2)
142    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] sse3: "sse3";
143    /// SSE3 (Streaming SIMD Extensions 3)
144    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] ssse3: "ssse3";
145    /// SSSE3 (Supplemental Streaming SIMD Extensions 3)
146    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] sse4_1: "sse4.1";
147    /// SSE4.1 (Streaming SIMD Extensions 4.1)
148    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] sse4_2: "sse4.2";
149    /// SSE4.2 (Streaming SIMD Extensions 4.2)
150    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] sse4a: "sse4a";
151    /// SSE4a (Streaming SIMD Extensions 4a)
152    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] sha: "sha";
153    /// SHA
154    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx: "avx";
155    /// AVX (Advanced Vector Extensions)
156    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx2: "avx2";
157    /// AVX2 (Advanced Vector Extensions 2)
158    @FEATURE: #[stable(feature = "sha512_sm_x86", since = "1.89.0")] sha512: "sha512";
159    /// SHA512
160    @FEATURE: #[stable(feature = "sha512_sm_x86", since = "1.89.0")] sm3: "sm3";
161    /// SM3
162    @FEATURE: #[stable(feature = "sha512_sm_x86", since = "1.89.0")] sm4: "sm4";
163    /// SM4
164    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512f: "avx512f" ;
165    /// AVX-512 F (Foundation)
166    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512cd: "avx512cd" ;
167    /// AVX-512 CD (Conflict Detection Instructions)
168    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512er: "avx512er";
169    without cfg check: true;
170    /// AVX-512 ER (Expo nential and Reciprocal Instructions)
171    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512pf: "avx512pf";
172    without cfg check: true;
173    /// AVX-512 PF (Prefetch Instructions)
174    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512bw: "avx512bw";
175    /// AVX-512 BW (Byte and Word Instructions)
176    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512dq: "avx512dq";
177    /// AVX-512 DQ (Doubleword and Quadword)
178    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512vl: "avx512vl";
179    /// AVX-512 VL (Vector Length Extensions)
180    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512ifma: "avx512ifma";
181    /// AVX-512 IFMA (Integer Fused Multiply Add)
182    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512vbmi: "avx512vbmi";
183    /// AVX-512 VBMI (Vector Byte Manipulation Instructions)
184    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512vpopcntdq: "avx512vpopcntdq";
185    /// AVX-512 VPOPCNTDQ (Vector Population Count Doubleword and Quadword)
186    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512vbmi2: "avx512vbmi2";
187    /// AVX-512 VBMI2 (Additional byte, word, dword and qword capabilities)
188    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] gfni: "gfni";
189    /// AVX-512 GFNI (Galois Field New Instruction)
190    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] vaes: "vaes";
191    /// AVX-512 VAES (Vector AES instruction)
192    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] vpclmulqdq: "vpclmulqdq";
193    /// AVX-512 VPCLMULQDQ (Vector PCLMULQDQ instructions)
194    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512vnni: "avx512vnni";
195    /// AVX-512 VNNI (Vector Neural Network Instructions)
196    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512bitalg: "avx512bitalg";
197    /// AVX-512 BITALG (Support for VPOPCNT\[B,W\] and VPSHUFBITQMB)
198    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512bf16: "avx512bf16";
199    /// AVX-512 BF16 (BFLOAT16 instructions)
200    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512vp2intersect: "avx512vp2intersect";
201    /// AVX-512 P2INTERSECT
202    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512fp16: "avx512fp16";
203    /// AVX-512 FP16 (FLOAT16 instructions)
204    @FEATURE: #[stable(feature = "avx512_target_feature", since = "1.89.0")] avxifma: "avxifma";
205    /// AVX-IFMA (Integer Fused Multiply Add)
206    @FEATURE: #[stable(feature = "avx512_target_feature", since = "1.89.0")] avxneconvert: "avxneconvert";
207    /// AVX-NE-CONVERT (Exceptionless Convert)
208    @FEATURE: #[stable(feature = "avx512_target_feature", since = "1.89.0")] avxvnni: "avxvnni";
209    /// AVX-VNNI (Vector Neural Network Instructions)
210    @FEATURE: #[stable(feature = "avx512_target_feature", since = "1.89.0")] avxvnniint16: "avxvnniint16";
211    /// AVX-VNNI_INT8 (VNNI with 16-bit Integers)
212    @FEATURE: #[stable(feature = "avx512_target_feature", since = "1.89.0")] avxvnniint8: "avxvnniint8";
213    /// AVX-VNNI_INT16 (VNNI with 8-bit integers)
214    @FEATURE: #[unstable(feature = "x86_amx_intrinsics", issue = "126622")] amx_tile: "amx-tile";
215    /// AMX (Advanced Matrix Extensions) - Tile load/store
216    @FEATURE: #[unstable(feature = "x86_amx_intrinsics", issue = "126622")] amx_int8: "amx-int8";
217    /// AMX-INT8 (Operations on 8-bit integers)
218    @FEATURE: #[unstable(feature = "x86_amx_intrinsics", issue = "126622")] amx_bf16: "amx-bf16";
219    /// AMX-BF16 (BFloat16 Operations)
220    @FEATURE: #[unstable(feature = "x86_amx_intrinsics", issue = "126622")] amx_fp16: "amx-fp16";
221    /// AMX-FP16 (Float16 Operations)
222    @FEATURE: #[unstable(feature = "x86_amx_intrinsics", issue = "126622")] amx_complex: "amx-complex";
223    /// AMX-COMPLEX (Complex number Operations)
224    @FEATURE: #[unstable(feature = "x86_amx_intrinsics", issue = "126622")] amx_avx512: "amx-avx512";
225    /// AMX-AVX512 (AVX512 operations extended to matrices)
226    @FEATURE: #[unstable(feature = "x86_amx_intrinsics", issue = "126622")] amx_fp8: "amx-fp8";
227    /// AMX-FP8 (Float8 Operations)
228    @FEATURE: #[unstable(feature = "x86_amx_intrinsics", issue = "126622")] amx_movrs: "amx-movrs";
229    /// AMX-MOVRS (Matrix MOVERS operations)
230    @FEATURE: #[unstable(feature = "x86_amx_intrinsics", issue = "126622")] amx_tf32: "amx-tf32";
231    /// AMX-TF32 (TensorFloat32 Operations)
232    @FEATURE: #[unstable(feature = "apx_target_feature", issue = "139284")] apxf: "apxf";
233    /// APX-F (Advanced Performance Extensions - Foundation)
234    @FEATURE: #[unstable(feature = "avx10_target_feature", issue = "138843")] avx10_1: "avx10.1";
235    /// AVX10.1
236    @FEATURE: #[unstable(feature = "avx10_target_feature", issue = "138843")] avx10_2: "avx10.2";
237    /// AVX10.2
238    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] f16c: "f16c";
239    /// F16C (Conversions between IEEE-754 `binary16` and `binary32` formats)
240    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] fma: "fma";
241    /// FMA (Fused Multiply Add)
242    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] bmi1: "bmi1" ;
243    /// BMI1 (Bit Manipulation Instructions 1)
244    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] bmi2: "bmi2" ;
245    /// BMI2 (Bit Manipulation Instructions 2)
246    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] lzcnt: "lzcnt";
247    /// ABM (Advanced Bit Manipulation) / LZCNT (Leading Zero Count)
248    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] tbm: "tbm";
249    /// TBM (Trailing Bit Manipulation)
250    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] popcnt: "popcnt";
251    /// POPCNT (Population Count)
252    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] fxsr: "fxsr";
253    /// FXSR (Floating-point context fast save and restore)
254    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] xsave: "xsave";
255    /// XSAVE (Save Processor Extended States)
256    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] xsaveopt: "xsaveopt";
257    /// XSAVEOPT (Save Processor Extended States Optimized)
258    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] xsaves: "xsaves";
259    /// XSAVES (Save Processor Extended States Supervisor)
260    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] xsavec: "xsavec";
261    /// XSAVEC (Save Processor Extended States Compacted)
262    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] cmpxchg16b: "cmpxchg16b";
263    /// CMPXCH16B (16-byte compare-and-swap instruction)
264    @FEATURE: #[stable(feature = "keylocker_x86", since = "1.89.0")] kl: "kl";
265    /// Intel Key Locker
266    @FEATURE: #[stable(feature = "keylocker_x86", since = "1.89.0")] widekl: "widekl";
267    /// Intel Key Locker Wide
268    @FEATURE: #[stable(feature = "simd_x86_adx", since = "1.33.0")] adx: "adx";
269    /// ADX, Intel ADX (Multi-Precision Add-Carry Instruction Extensions)
270    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] rtm: "rtm";
271    /// RTM, Intel (Restricted Transactional Memory)
272    @FEATURE: #[stable(feature = "movbe_target_feature", since = "1.67.0")] movbe: "movbe";
273    /// MOVBE (Move Data After Swapping Bytes)
274    @FEATURE: #[unstable(feature = "movrs_target_feature", issue = "137976")] movrs: "movrs";
275    /// MOVRS (Move data with the read-shared hint)
276    @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] ermsb: "ermsb";
277    /// ERMSB, Enhanced REP MOVSB and STOSB
278    @FEATURE: #[unstable(feature = "xop_target_feature", issue = "127208")] xop: "xop";
279    /// XOP: eXtended Operations (AMD)
280}
std_detect/detect/arch/x86.rs

std_detect/detect/arch/
x86.rs
