std_detect/detect/arch/riscv.rs
1//! Run-time feature detection on RISC-V.
2
3features! {
4 @TARGET: riscv;
5 @CFG: any(target_arch = "riscv32", target_arch = "riscv64");
6 @MACRO_NAME: is_riscv_feature_detected;
7 @MACRO_ATTRS:
8 /// Check for the presence of a CPU feature at runtime.
9 ///
10 /// When the feature is known to be enabled at compile time (e.g. via `-Ctarget-feature`)
11 /// the macro expands to `true`.
12 ///
13 /// RISC-V standard defined the base sets and the extension sets.
14 /// The base sets are RV32I, RV64I, RV32E or RV128I. Any RISC-V platform
15 /// must support one base set and/or multiple extension sets.
16 ///
17 /// Any RISC-V standard instruction sets can be in state of either ratified,
18 /// frozen or draft. The version and status of current standard instruction
19 /// sets can be checked out from preface section of the [ISA manual].
20 ///
21 /// Platform may define and support their own custom instruction sets with
22 /// ISA prefix X. These sets are highly platform specific and should be
23 /// detected with their own platform support crates.
24 ///
25 /// [ISA manual]: https://riscv.org/specifications/ratified/
26 ///
27 /// # Platform-specific/agnostic Behavior and Availability
28 ///
29 /// Runtime detection depends on the platform-specific feature detection
30 /// facility and its availability per feature is
31 /// highly platform/version-specific.
32 ///
33 /// Still, a best-effort attempt is performed to enable subset/dependent
34 /// features if a superset feature is enabled regardless of the platform.
35 /// For instance, if the A extension (`"a"`) is enabled, its subsets (the
36 /// Zalrsc and Zaamo extensions; `"zalrsc"` and `"zaamo"`) are also enabled.
37 /// Likewise, if the F extension (`"f"`) is enabled, one of its dependencies
38 /// (the Zicsr extension `"zicsr"`) is also enabled.
39 ///
40 /// # Unprivileged Specification
41 ///
42 /// The supported ratified RISC-V instruction sets are as follows (OS
43 /// columns denote runtime feature detection support with or without the
44 /// minimum supported version):
45 ///
46 /// | Literal | Base | Linux |
47 /// |:---------- |:------- |:---------- |
48 /// | `"rv32e"` | RV32E | No |
49 /// | `"rv32i"` | RV32I | Yes [^ima] |
50 /// | `"rv64i"` | RV64I | Yes [^ima] |
51 ///
52 /// | Literal | Extension | Linux |
53 /// |:--------------- |:----------- |:------------------- |
54 /// | `"a"` | A | Yes [^ima] |
55 /// | `"b"` | B | 6.5 |
56 /// | `"c"` | C | Yes |
57 /// | `"d"` | D | Yes |
58 /// | `"f"` | F | Yes |
59 /// | `"m"` | M | Yes [^ima] |
60 /// | `"q"` | Q | No |
61 /// | `"v"` | V | 6.5 |
62 /// | `"zaamo"` | Zaamo | 6.15 [^ima] [^dep] |
63 /// | `"zabha"` | Zabha | 6.16 |
64 /// | `"zacas"` | Zacas | 6.8 |
65 /// | `"zalrsc"` | Zalrsc | 6.15 [^ima] [^dep] |
66 /// | `"zawrs"` | Zawrs | 6.11 |
67 /// | `"zba"` | Zba | 6.5 |
68 /// | `"zbb"` | Zbb | 6.5 |
69 /// | `"zbc"` | Zbc | 6.8 |
70 /// | `"zbkb"` | Zbkb | 6.8 |
71 /// | `"zbkc"` | Zbkc | 6.8 |
72 /// | `"zbkx"` | Zbkx | 6.8 |
73 /// | `"zbs"` | Zbs | 6.5 |
74 /// | `"zca"` | Zca | 6.11 [^dep] |
75 /// | `"zcb"` | Zcb | 6.11 |
76 /// | `"zcd"` | Zcd | 6.11 [^dep] |
77 /// | `"zcf"` | Zcf | 6.11 [^dep] |
78 /// | `"zcmop"` | Zcmop | 6.11 |
79 /// | `"zdinx"` | Zdinx | No |
80 /// | `"zfa"` | Zfa | 6.8 |
81 /// | `"zfbfmin"` | Zfbfmin | 6.15 |
82 /// | `"zfh"` | Zfh | 6.8 |
83 /// | `"zfhmin"` | Zfhmin | 6.8 |
84 /// | `"zfinx"` | Zfinx | No |
85 /// | `"zhinx"` | Zhinx | No |
86 /// | `"zhinxmin"` | Zhinxmin | No |
87 /// | `"zicbom"` | Zicbom | 6.15 |
88 /// | `"zicboz"` | Zicboz | 6.7 |
89 /// | `"zicntr"` | Zicntr | 6.15 [^ima] [^cntr] |
90 /// | `"zicond"` | Zicond | 6.8 |
91 /// | `"zicsr"` | Zicsr | No [^ima] [^dep] |
92 /// | `"zifencei"` | Zifencei | No [^ima] |
93 /// | `"zihintntl"` | Zihintntl | 6.8 |
94 /// | `"zihintpause"` | Zihintpause | 6.10 |
95 /// | `"zihpm"` | Zihpm | 6.15 [^cntr] |
96 /// | `"zimop"` | Zimop | 6.11 |
97 /// | `"zk"` | Zk | No [^zkr] |
98 /// | `"zkn"` | Zkn | 6.8 |
99 /// | `"zknd"` | Zknd | 6.8 |
100 /// | `"zkne"` | Zkne | 6.8 |
101 /// | `"zknh"` | Zknh | 6.8 |
102 /// | `"zkr"` | Zkr | No [^zkr] |
103 /// | `"zks"` | Zks | 6.8 |
104 /// | `"zksed"` | Zksed | 6.8 |
105 /// | `"zksh"` | Zksh | 6.8 |
106 /// | `"zkt"` | Zkt | 6.8 |
107 /// | `"zmmul"` | Zmmul | No [^ima] [^dep] |
108 /// | `"ztso"` | Ztso | 6.8 |
109 /// | `"zvbb"` | Zvbb | 6.8 |
110 /// | `"zvbc"` | Zvbc | 6.8 |
111 /// | `"zve32f"` | Zve32f | 6.11 [^dep] |
112 /// | `"zve32x"` | Zve32x | 6.11 [^dep] |
113 /// | `"zve64d"` | Zve64d | 6.11 [^dep] |
114 /// | `"zve64f"` | Zve64f | 6.11 [^dep] |
115 /// | `"zve64x"` | Zve64x | 6.11 [^dep] |
116 /// | `"zvfbfmin"` | Zvfbfmin | 6.15 |
117 /// | `"zvfbfwma"` | Zvfbfwma | 6.15 |
118 /// | `"zvfh"` | Zvfh | 6.8 |
119 /// | `"zvfhmin"` | Zvfhmin | 6.8 |
120 /// | `"zvkb"` | Zvkb | 6.8 |
121 /// | `"zvkg"` | Zvkg | 6.8 |
122 /// | `"zvkn"` | Zvkn | 6.8 |
123 /// | `"zvknc"` | Zvknc | 6.8 |
124 /// | `"zvkned"` | Zvkned | 6.8 |
125 /// | `"zvkng"` | Zvkng | 6.8 |
126 /// | `"zvknha"` | Zvknha | 6.8 |
127 /// | `"zvknhb"` | Zvknhb | 6.8 |
128 /// | `"zvks"` | Zvks | 6.8 |
129 /// | `"zvksc"` | Zvksc | 6.8 |
130 /// | `"zvksed"` | Zvksed | 6.8 |
131 /// | `"zvksg"` | Zvksg | 6.8 |
132 /// | `"zvksh"` | Zvksh | 6.8 |
133 /// | `"zvkt"` | Zvkt | 6.8 |
134 ///
135 /// [^ima]: Or enabled when the IMA base behavior is detected on the Linux
136 /// kernel version 6.4 or later (for bases, the only matching one -- either
137 /// `"rv32i"` or `"rv64i"` -- is enabled).
138 ///
139 /// [^cntr]: Even if this extension is available, it does not necessarily
140 /// mean all performance counters are accessible.
141 /// For example, accesses to all performance counters except `time`
142 /// (wall-clock) are blocked by default on the Linux kernel
143 /// version 6.6 or later.
144 /// Also beware that, even if performance counters like `cycle` and
145 /// `instret` are accessible, their value can be unreliable (e.g. returning
146 /// the constant value) under certain circumstances.
147 ///
148 /// [^dep]: Or enabled as a dependency of another extension (a superset)
149 /// even if runtime detection of this feature itself is not supported (as
150 /// long as the runtime detection of the superset is supported).
151 ///
152 /// [^zkr]: Linux does not report existence of this extension even if
153 /// supported by the hardware mainly because the `seed` CSR on the Zkr
154 /// extension (which provides hardware-based randomness) is normally
155 /// inaccessible from the user mode.
156 /// For the Zk extension features except this CSR, check existence of both
157 /// `"zkn"` and `"zkt"` features instead.
158 ///
159 /// There's also bases and extensions marked as standard instruction set,
160 /// but they are in frozen or draft state. These instruction sets are also
161 /// reserved by this macro and can be detected in the future platforms.
162 ///
163 /// Draft RISC-V instruction sets:
164 ///
165 /// * RV128I: `"rv128i"`
166 /// * J: `"j"`
167 /// * P: `"p"`
168 /// * Zam: `"zam"`
169 ///
170 /// # Performance Hints
171 ///
172 /// The two features below define performance hints for unaligned
173 /// scalar/vector memory accesses, respectively. If enabled, it denotes that
174 /// corresponding unaligned memory access is reasonably fast.
175 ///
176 /// * `"unaligned-scalar-mem"`
177 /// * Runtime detection requires Linux kernel version 6.4 or later.
178 /// * `"unaligned-vector-mem"`
179 /// * Runtime detection requires Linux kernel version 6.13 or later.
180 #[stable(feature = "riscv_ratified", since = "1.78.0")]
181
182 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv32i: "rv32i";
183 without cfg check: true;
184 /// RV32I Base Integer Instruction Set
185 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv32e: "rv32e";
186 without cfg check: true;
187 /// RV32E Base Integer Instruction Set
188 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv64i: "rv64i";
189 without cfg check: true;
190 /// RV64I Base Integer Instruction Set
191 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv128i: "rv128i";
192 without cfg check: true;
193 /// RV128I Base Integer Instruction Set
194
195 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] unaligned_scalar_mem: "unaligned-scalar-mem";
196 /// Has reasonably performant unaligned scalar
197 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] unaligned_vector_mem: "unaligned-vector-mem";
198 /// Has reasonably performant unaligned vector
199
200 @FEATURE: #[stable(feature = "riscv_ratified_v2", since = "1.94.0")] zicsr: "zicsr";
201 /// "Zicsr" Extension for Control and Status Register (CSR) Instructions
202 @FEATURE: #[stable(feature = "riscv_ratified_v2", since = "1.94.0")] zicntr: "zicntr";
203 /// "Zicntr" Extension for Base Counters and Timers
204 @FEATURE: #[stable(feature = "riscv_ratified_v2", since = "1.94.0")] zihpm: "zihpm";
205 /// "Zihpm" Extension for Hardware Performance Counters
206 @FEATURE: #[stable(feature = "riscv_ratified_v2", since = "1.94.0")] zifencei: "zifencei";
207 /// "Zifencei" Extension for Instruction-Fetch Fence
208
209 @FEATURE: #[stable(feature = "riscv_ratified_v2", since = "1.94.0")] zihintntl: "zihintntl";
210 /// "Zihintntl" Extension for Non-Temporal Locality Hints
211 @FEATURE: #[stable(feature = "riscv_ratified_v2", since = "1.94.0")] zihintpause: "zihintpause";
212 /// "Zihintpause" Extension for Pause Hint
213 @FEATURE: #[stable(feature = "riscv_ratified_v2", since = "1.94.0")] zimop: "zimop";
214 /// "Zimop" Extension for May-Be-Operations
215 @FEATURE: #[stable(feature = "riscv_ratified_v2", since = "1.94.0")] zicbom: "zicbom";
216 /// "Zicbom" Extension for Cache-Block Management Instructions
217 @FEATURE: #[stable(feature = "riscv_ratified_v2", since = "1.94.0")] zicboz: "zicboz";
218 /// "Zicboz" Extension for Cache-Block Zero Instruction
219 @FEATURE: #[stable(feature = "riscv_ratified_v2", since = "1.94.0")] zicond: "zicond";
220 /// "Zicond" Extension for Integer Conditional Operations
221
222 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] m: "m";
223 /// "M" Extension for Integer Multiplication and Division
224 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zmmul: "zmmul";
225 /// "Zmmul" Extension for Integer Multiplication
226
227 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] a: "a";
228 /// "A" Extension for Atomic Instructions
229 @FEATURE: #[stable(feature = "riscv_ratified_v2", since = "1.94.0")] zalrsc: "zalrsc";
230 /// "Zalrsc" Extension for Load-Reserved/Store-Conditional Instructions
231 @FEATURE: #[stable(feature = "riscv_ratified_v2", since = "1.94.0")] zaamo: "zaamo";
232 /// "Zaamo" Extension for Atomic Memory Operations
233 @FEATURE: #[stable(feature = "riscv_ratified_v2", since = "1.94.0")] zawrs: "zawrs";
234 /// "Zawrs" Extension for Wait-on-Reservation-Set Instructions
235 @FEATURE: #[stable(feature = "riscv_ratified_v2", since = "1.94.0")] zabha: "zabha";
236 /// "Zabha" Extension for Byte and Halfword Atomic Memory Operations
237 @FEATURE: #[stable(feature = "riscv_ratified_v2", since = "1.94.0")] zacas: "zacas";
238 /// "Zacas" Extension for Atomic Compare-and-Swap (CAS) Instructions
239 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zam: "zam";
240 without cfg check: true;
241 /// "Zam" Extension for Misaligned Atomics
242 @FEATURE: #[stable(feature = "riscv_ratified_v2", since = "1.94.0")] ztso: "ztso";
243 /// "Ztso" Extension for Total Store Ordering
244
245 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] f: "f";
246 /// "F" Extension for Single-Precision Floating-Point
247 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] d: "d";
248 /// "D" Extension for Double-Precision Floating-Point
249 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] q: "q";
250 without cfg check: true;
251 /// "Q" Extension for Quad-Precision Floating-Point
252 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfh: "zfh";
253 /// "Zfh" Extension for Half-Precision Floating-Point
254 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfhmin: "zfhmin";
255 /// "Zfhmin" Extension for Minimal Half-Precision Floating-Point
256 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfa: "zfa";
257 /// "Zfa" Extension for Additional Floating-Point Instructions
258 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfbfmin: "zfbfmin";
259 /// "Zfbfmin" Extension for Scalar BF16 Converts
260
261 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfinx: "zfinx";
262 /// "Zfinx" Extension for Single-Precision Floating-Point in Integer Registers
263 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zdinx: "zdinx";
264 /// "Zdinx" Extension for Double-Precision Floating-Point in Integer Registers
265 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zhinx: "zhinx";
266 /// "Zhinx" Extension for Half-Precision Floating-Point in Integer Registers
267 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zhinxmin: "zhinxmin";
268 /// "Zhinxmin" Extension for Minimal Half-Precision Floating-Point in Integer Registers
269
270 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] c: "c";
271 /// "C" Extension for Compressed Instructions
272 @FEATURE: #[stable(feature = "riscv_ratified_v2", since = "1.94.0")] zca: "zca";
273 /// "Zca" Compressed Instructions excluding Floating-Point Loads/Stores
274 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zcf: "zcf";
275 without cfg check: true;
276 /// "Zcf" Compressed Instructions for Single-Precision Floating-Point Loads/Stores on RV32
277 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zcd: "zcd";
278 without cfg check: true;
279 /// "Zcd" Compressed Instructions for Double-Precision Floating-Point Loads/Stores
280 @FEATURE: #[stable(feature = "riscv_ratified_v2", since = "1.94.0")] zcb: "zcb";
281 /// "Zcb" Simple Code-size Saving Compressed Instructions
282 @FEATURE: #[stable(feature = "riscv_ratified_v2", since = "1.94.0")] zcmop: "zcmop";
283 /// "Zcmop" Extension for Compressed May-Be-Operations
284
285 @FEATURE: #[stable(feature = "riscv_ratified_v2", since = "1.94.0")] b: "b";
286 /// "B" Extension for Bit Manipulation
287 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zba: "zba";
288 /// "Zba" Extension for Address Generation
289 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zbb: "zbb";
290 /// "Zbb" Extension for Basic Bit-Manipulation
291 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zbc: "zbc";
292 /// "Zbc" Extension for Carry-less Multiplication
293 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zbs: "zbs";
294 /// "Zbs" Extension for Single-Bit Instructions
295
296 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zbkb: "zbkb";
297 /// "Zbkb" Extension for Bit-Manipulation for Cryptography
298 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zbkc: "zbkc";
299 /// "Zbkc" Extension for Carry-less Multiplication for Cryptography
300 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zbkx: "zbkx";
301 /// "Zbkx" Extension for Crossbar Permutations
302 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zknd: "zknd";
303 /// "Zknd" Cryptography Extension for NIST Suite: AES Decryption
304 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zkne: "zkne";
305 /// "Zkne" Cryptography Extension for NIST Suite: AES Encryption
306 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zknh: "zknh";
307 /// "Zknh" Cryptography Extension for NIST Suite: Hash Function Instructions
308 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zksed: "zksed";
309 /// "Zksed" Cryptography Extension for ShangMi Suite: SM4 Block Cipher Instructions
310 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zksh: "zksh";
311 /// "Zksh" Cryptography Extension for ShangMi Suite: SM3 Hash Function Instructions
312 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zkr: "zkr";
313 /// "Zkr" Entropy Source Extension
314 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zkn: "zkn";
315 /// "Zkn" Cryptography Extension for NIST Algorithm Suite
316 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zks: "zks";
317 /// "Zks" Cryptography Extension for ShangMi Algorithm Suite
318 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zk: "zk";
319 /// "Zk" Cryptography Extension for Standard Scalar Cryptography
320 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zkt: "zkt";
321 /// "Zkt" Cryptography Extension for Data Independent Execution Latency
322
323 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] v: "v";
324 /// "V" Extension for Vector Operations
325 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zve32x: "zve32x";
326 /// "Zve32x" Vector Extension for Embedded Processors (32-bit+; Integer)
327 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zve32f: "zve32f";
328 /// "Zve32f" Vector Extension for Embedded Processors (32-bit+; with Single-Precision Floating-Point)
329 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zve64x: "zve64x";
330 /// "Zve64x" Vector Extension for Embedded Processors (64-bit+; Integer)
331 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zve64f: "zve64f";
332 /// "Zve64f" Vector Extension for Embedded Processors (64-bit+; with Single-Precision Floating-Point)
333 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zve64d: "zve64d";
334 /// "Zve64d" Vector Extension for Embedded Processors (64-bit+; with Double-Precision Floating-Point)
335 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvfh: "zvfh";
336 /// "Zvfh" Vector Extension for Half-Precision Floating-Point
337 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvfhmin: "zvfhmin";
338 /// "Zvfhmin" Vector Extension for Minimal Half-Precision Floating-Point
339 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvfbfmin: "zvfbfmin";
340 /// "Zvfbfmin" Vector Extension for BF16 Converts
341 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvfbfwma: "zvfbfwma";
342 /// "Zvfbfwma" Vector Extension for BF16 Widening Multiply-Add
343
344 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvbb: "zvbb";
345 /// "Zvbb" Extension for Vector Basic Bit-Manipulation
346 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvbc: "zvbc";
347 /// "Zvbc" Extension for Vector Carryless Multiplication
348 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvkb: "zvkb";
349 /// "Zvkb" Extension for Vector Cryptography Bit-Manipulation
350 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvkg: "zvkg";
351 /// "Zvkg" Cryptography Extension for Vector GCM/GMAC
352 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvkned: "zvkned";
353 /// "Zvkned" Cryptography Extension for NIST Suite: Vector AES Block Cipher
354 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvknha: "zvknha";
355 /// "Zvknha" Cryptography Extension for Vector SHA-2 Secure Hash (SHA-256)
356 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvknhb: "zvknhb";
357 /// "Zvknhb" Cryptography Extension for Vector SHA-2 Secure Hash (SHA-256/512)
358 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvksed: "zvksed";
359 /// "Zvksed" Cryptography Extension for ShangMi Suite: Vector SM4 Block Cipher
360 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvksh: "zvksh";
361 /// "Zvksh" Cryptography Extension for ShangMi Suite: Vector SM3 Secure Hash
362 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvkn: "zvkn";
363 /// "Zvkn" Cryptography Extension for NIST Algorithm Suite
364 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvknc: "zvknc";
365 /// "Zvknc" Cryptography Extension for NIST Algorithm Suite with Carryless Multiply
366 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvkng: "zvkng";
367 /// "Zvkng" Cryptography Extension for NIST Algorithm Suite with GCM
368 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvks: "zvks";
369 /// "Zvks" Cryptography Extension for ShangMi Algorithm Suite
370 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvksc: "zvksc";
371 /// "Zvksc" Cryptography Extension for ShangMi Algorithm Suite with Carryless Multiply
372 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvksg: "zvksg";
373 /// "Zvksg" Cryptography Extension for ShangMi Algorithm Suite with GCM
374 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvkt: "zvkt";
375 /// "Zvkt" Extension for Vector Data-Independent Execution Latency
376
377 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] j: "j";
378 without cfg check: true;
379 /// "J" Extension for Dynamically Translated Languages
380 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] p: "p";
381 without cfg check: true;
382 /// "P" Extension for Packed-SIMD Instructions
383}