core/stdarch/crates/core_arch/src/hexagon/
v128.rs

1// This code is automatically generated. DO NOT MODIFY.
2//! Hexagon HVX 128-byte vector mode intrinsics
3//!
4//! This module provides intrinsics for the Hexagon Vector Extensions (HVX)
5//! in 128-byte vector mode (1024-bit vectors).
6//!
7//! HVX is a wide vector extension designed for high-performance signal processing.
8//! [Hexagon HVX Programmer's Reference Manual](https://docs.qualcomm.com/doc/80-N2040-61)
9//!
10//! ## Vector Types
11//!
12//! In 128-byte mode:
13//! - `HvxVector` is 1024 bits (128 bytes) containing 32 x 32-bit values
14//! - `HvxVectorPair` is 2048 bits (256 bytes)
15//! - `HvxVectorPred` is 1024 bits (128 bytes) for predicate operations
16//!
17//! To use this module, compile with `-C target-feature=+hvx-length128b`.
18//!
19//! ## Naming Convention
20//!
21//! Function names preserve the original Q6 naming case because the convention
22//! uses case to distinguish register types:
23//! - `W` (uppercase) = vector pair (`HvxVectorPair`)
24//! - `V` (uppercase) = vector (`HvxVector`)
25//! - `Q` (uppercase) = predicate (`HvxVectorPred`)
26//! - `R` = scalar register (`i32`)
27//!
28//! For example, `Q6_W_vcombine_VV` operates on a vector pair while
29//! `Q6_V_hi_W` extracts a vector from a pair.
30//!
31//! ## Architecture Versions
32//!
33//! Different intrinsics require different HVX architecture versions. Use the
34//! appropriate target feature to enable the required version:
35//! - HVX v60: `-C target-feature=+hvxv60` (basic HVX operations)
36//! - HVX v62: `-C target-feature=+hvxv62`
37//! - HVX v65: `-C target-feature=+hvxv65` (includes floating-point support)
38//! - HVX v66: `-C target-feature=+hvxv66`
39//! - HVX v68: `-C target-feature=+hvxv68`
40//! - HVX v69: `-C target-feature=+hvxv69`
41//! - HVX v73: `-C target-feature=+hvxv73`
42//! - HVX v79: `-C target-feature=+hvxv79`
43//!
44//! Each version includes all features from previous versions.
45
46#![allow(non_camel_case_types)]
47#![allow(non_snake_case)]
48
49#[cfg(test)]
50use stdarch_test::assert_instr;
51
52use crate::intrinsics::simd::{simd_add, simd_and, simd_or, simd_sub, simd_xor};
53
54// HVX type definitions for 128-byte vector mode
55types! {
56    #![unstable(feature = "stdarch_hexagon", issue = "151523")]
57
58    /// HVX vector type (1024 bits / 128 bytes)
59    ///
60    /// This type represents a single HVX vector register containing 32 x 32-bit values.
61    pub struct HvxVector(32 x i32);
62
63    /// HVX vector pair type (2048 bits / 256 bytes)
64    ///
65    /// This type represents a pair of HVX vector registers, often used for
66    /// operations that produce double-width results.
67    pub struct HvxVectorPair(64 x i32);
68
69    /// HVX vector predicate type (1024 bits / 128 bytes)
70    ///
71    /// This type represents a predicate vector used for conditional operations.
72    /// Each bit corresponds to a lane in the vector.
73    pub struct HvxVectorPred(32 x i32);
74}
75
76// LLVM intrinsic declarations for 128-byte vector mode
77#[allow(improper_ctypes)]
78unsafe extern "unadjusted" {
79    #[link_name = "llvm.hexagon.V6.extractw.128B"]
80    fn extractw(_: HvxVector, _: i32) -> i32;
81    #[link_name = "llvm.hexagon.V6.get.qfext.128B"]
82    fn get_qfext(_: HvxVector, _: i32) -> HvxVector;
83    #[link_name = "llvm.hexagon.V6.hi.128B"]
84    fn hi(_: HvxVectorPair) -> HvxVector;
85    #[link_name = "llvm.hexagon.V6.lo.128B"]
86    fn lo(_: HvxVectorPair) -> HvxVector;
87    #[link_name = "llvm.hexagon.V6.lvsplatb.128B"]
88    fn lvsplatb(_: i32) -> HvxVector;
89    #[link_name = "llvm.hexagon.V6.lvsplath.128B"]
90    fn lvsplath(_: i32) -> HvxVector;
91    #[link_name = "llvm.hexagon.V6.lvsplatw.128B"]
92    fn lvsplatw(_: i32) -> HvxVector;
93    #[link_name = "llvm.hexagon.V6.pred.and.128B"]
94    fn pred_and(_: HvxVector, _: HvxVector) -> HvxVector;
95    #[link_name = "llvm.hexagon.V6.pred.and.n.128B"]
96    fn pred_and_n(_: HvxVector, _: HvxVector) -> HvxVector;
97    #[link_name = "llvm.hexagon.V6.pred.not.128B"]
98    fn pred_not(_: HvxVector) -> HvxVector;
99    #[link_name = "llvm.hexagon.V6.pred.or.128B"]
100    fn pred_or(_: HvxVector, _: HvxVector) -> HvxVector;
101    #[link_name = "llvm.hexagon.V6.pred.or.n.128B"]
102    fn pred_or_n(_: HvxVector, _: HvxVector) -> HvxVector;
103    #[link_name = "llvm.hexagon.V6.pred.scalar2.128B"]
104    fn pred_scalar2(_: i32) -> HvxVector;
105    #[link_name = "llvm.hexagon.V6.pred.scalar2v2.128B"]
106    fn pred_scalar2v2(_: i32) -> HvxVector;
107    #[link_name = "llvm.hexagon.V6.pred.xor.128B"]
108    fn pred_xor(_: HvxVector, _: HvxVector) -> HvxVector;
109    #[link_name = "llvm.hexagon.V6.set.qfext.128B"]
110    fn set_qfext(_: HvxVector, _: i32) -> HvxVector;
111    #[link_name = "llvm.hexagon.V6.shuffeqh.128B"]
112    fn shuffeqh(_: HvxVector, _: HvxVector) -> HvxVector;
113    #[link_name = "llvm.hexagon.V6.shuffeqw.128B"]
114    fn shuffeqw(_: HvxVector, _: HvxVector) -> HvxVector;
115    #[link_name = "llvm.hexagon.V6.v6mpyhubs10.128B"]
116    fn v6mpyhubs10(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
117    #[link_name = "llvm.hexagon.V6.v6mpyhubs10.vxx.128B"]
118    fn v6mpyhubs10_vxx(
119        _: HvxVectorPair,
120        _: HvxVectorPair,
121        _: HvxVectorPair,
122        _: i32,
123    ) -> HvxVectorPair;
124    #[link_name = "llvm.hexagon.V6.v6mpyvubs10.128B"]
125    fn v6mpyvubs10(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
126    #[link_name = "llvm.hexagon.V6.v6mpyvubs10.vxx.128B"]
127    fn v6mpyvubs10_vxx(
128        _: HvxVectorPair,
129        _: HvxVectorPair,
130        _: HvxVectorPair,
131        _: i32,
132    ) -> HvxVectorPair;
133    #[link_name = "llvm.hexagon.V6.vS32b.nqpred.ai.128B"]
134    fn vS32b_nqpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> ();
135    #[link_name = "llvm.hexagon.V6.vS32b.nt.nqpred.ai.128B"]
136    fn vS32b_nt_nqpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> ();
137    #[link_name = "llvm.hexagon.V6.vS32b.nt.qpred.ai.128B"]
138    fn vS32b_nt_qpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> ();
139    #[link_name = "llvm.hexagon.V6.vS32b.qpred.ai.128B"]
140    fn vS32b_qpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> ();
141    #[link_name = "llvm.hexagon.V6.vabs.f8.128B"]
142    fn vabs_f8(_: HvxVector) -> HvxVector;
143    #[link_name = "llvm.hexagon.V6.vabs.hf.128B"]
144    fn vabs_hf(_: HvxVector) -> HvxVector;
145    #[link_name = "llvm.hexagon.V6.vabs.sf.128B"]
146    fn vabs_sf(_: HvxVector) -> HvxVector;
147    #[link_name = "llvm.hexagon.V6.vabsb.128B"]
148    fn vabsb(_: HvxVector) -> HvxVector;
149    #[link_name = "llvm.hexagon.V6.vabsb.sat.128B"]
150    fn vabsb_sat(_: HvxVector) -> HvxVector;
151    #[link_name = "llvm.hexagon.V6.vabsdiffh.128B"]
152    fn vabsdiffh(_: HvxVector, _: HvxVector) -> HvxVector;
153    #[link_name = "llvm.hexagon.V6.vabsdiffub.128B"]
154    fn vabsdiffub(_: HvxVector, _: HvxVector) -> HvxVector;
155    #[link_name = "llvm.hexagon.V6.vabsdiffuh.128B"]
156    fn vabsdiffuh(_: HvxVector, _: HvxVector) -> HvxVector;
157    #[link_name = "llvm.hexagon.V6.vabsdiffw.128B"]
158    fn vabsdiffw(_: HvxVector, _: HvxVector) -> HvxVector;
159    #[link_name = "llvm.hexagon.V6.vabsh.128B"]
160    fn vabsh(_: HvxVector) -> HvxVector;
161    #[link_name = "llvm.hexagon.V6.vabsh.sat.128B"]
162    fn vabsh_sat(_: HvxVector) -> HvxVector;
163    #[link_name = "llvm.hexagon.V6.vabsw.128B"]
164    fn vabsw(_: HvxVector) -> HvxVector;
165    #[link_name = "llvm.hexagon.V6.vabsw.sat.128B"]
166    fn vabsw_sat(_: HvxVector) -> HvxVector;
167    #[link_name = "llvm.hexagon.V6.vadd.hf.128B"]
168    fn vadd_hf(_: HvxVector, _: HvxVector) -> HvxVector;
169    #[link_name = "llvm.hexagon.V6.vadd.hf.hf.128B"]
170    fn vadd_hf_hf(_: HvxVector, _: HvxVector) -> HvxVector;
171    #[link_name = "llvm.hexagon.V6.vadd.qf16.128B"]
172    fn vadd_qf16(_: HvxVector, _: HvxVector) -> HvxVector;
173    #[link_name = "llvm.hexagon.V6.vadd.qf16.mix.128B"]
174    fn vadd_qf16_mix(_: HvxVector, _: HvxVector) -> HvxVector;
175    #[link_name = "llvm.hexagon.V6.vadd.qf32.128B"]
176    fn vadd_qf32(_: HvxVector, _: HvxVector) -> HvxVector;
177    #[link_name = "llvm.hexagon.V6.vadd.qf32.mix.128B"]
178    fn vadd_qf32_mix(_: HvxVector, _: HvxVector) -> HvxVector;
179    #[link_name = "llvm.hexagon.V6.vadd.sf.128B"]
180    fn vadd_sf(_: HvxVector, _: HvxVector) -> HvxVector;
181    #[link_name = "llvm.hexagon.V6.vadd.sf.hf.128B"]
182    fn vadd_sf_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair;
183    #[link_name = "llvm.hexagon.V6.vadd.sf.sf.128B"]
184    fn vadd_sf_sf(_: HvxVector, _: HvxVector) -> HvxVector;
185    #[link_name = "llvm.hexagon.V6.vaddb.128B"]
186    fn vaddb(_: HvxVector, _: HvxVector) -> HvxVector;
187    #[link_name = "llvm.hexagon.V6.vaddb.dv.128B"]
188    fn vaddb_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
189    #[link_name = "llvm.hexagon.V6.vaddbnq.128B"]
190    fn vaddbnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
191    #[link_name = "llvm.hexagon.V6.vaddbq.128B"]
192    fn vaddbq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
193    #[link_name = "llvm.hexagon.V6.vaddbsat.128B"]
194    fn vaddbsat(_: HvxVector, _: HvxVector) -> HvxVector;
195    #[link_name = "llvm.hexagon.V6.vaddbsat.dv.128B"]
196    fn vaddbsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
197    #[link_name = "llvm.hexagon.V6.vaddcarrysat.128B"]
198    fn vaddcarrysat(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
199    #[link_name = "llvm.hexagon.V6.vaddclbh.128B"]
200    fn vaddclbh(_: HvxVector, _: HvxVector) -> HvxVector;
201    #[link_name = "llvm.hexagon.V6.vaddclbw.128B"]
202    fn vaddclbw(_: HvxVector, _: HvxVector) -> HvxVector;
203    #[link_name = "llvm.hexagon.V6.vaddh.128B"]
204    fn vaddh(_: HvxVector, _: HvxVector) -> HvxVector;
205    #[link_name = "llvm.hexagon.V6.vaddh.dv.128B"]
206    fn vaddh_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
207    #[link_name = "llvm.hexagon.V6.vaddhnq.128B"]
208    fn vaddhnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
209    #[link_name = "llvm.hexagon.V6.vaddhq.128B"]
210    fn vaddhq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
211    #[link_name = "llvm.hexagon.V6.vaddhsat.128B"]
212    fn vaddhsat(_: HvxVector, _: HvxVector) -> HvxVector;
213    #[link_name = "llvm.hexagon.V6.vaddhsat.dv.128B"]
214    fn vaddhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
215    #[link_name = "llvm.hexagon.V6.vaddhw.128B"]
216    fn vaddhw(_: HvxVector, _: HvxVector) -> HvxVectorPair;
217    #[link_name = "llvm.hexagon.V6.vaddhw.acc.128B"]
218    fn vaddhw_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
219    #[link_name = "llvm.hexagon.V6.vaddubh.128B"]
220    fn vaddubh(_: HvxVector, _: HvxVector) -> HvxVectorPair;
221    #[link_name = "llvm.hexagon.V6.vaddubh.acc.128B"]
222    fn vaddubh_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
223    #[link_name = "llvm.hexagon.V6.vaddubsat.128B"]
224    fn vaddubsat(_: HvxVector, _: HvxVector) -> HvxVector;
225    #[link_name = "llvm.hexagon.V6.vaddubsat.dv.128B"]
226    fn vaddubsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
227    #[link_name = "llvm.hexagon.V6.vaddububb.sat.128B"]
228    fn vaddububb_sat(_: HvxVector, _: HvxVector) -> HvxVector;
229    #[link_name = "llvm.hexagon.V6.vadduhsat.128B"]
230    fn vadduhsat(_: HvxVector, _: HvxVector) -> HvxVector;
231    #[link_name = "llvm.hexagon.V6.vadduhsat.dv.128B"]
232    fn vadduhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
233    #[link_name = "llvm.hexagon.V6.vadduhw.128B"]
234    fn vadduhw(_: HvxVector, _: HvxVector) -> HvxVectorPair;
235    #[link_name = "llvm.hexagon.V6.vadduhw.acc.128B"]
236    fn vadduhw_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
237    #[link_name = "llvm.hexagon.V6.vadduwsat.128B"]
238    fn vadduwsat(_: HvxVector, _: HvxVector) -> HvxVector;
239    #[link_name = "llvm.hexagon.V6.vadduwsat.dv.128B"]
240    fn vadduwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
241    #[link_name = "llvm.hexagon.V6.vaddw.128B"]
242    fn vaddw(_: HvxVector, _: HvxVector) -> HvxVector;
243    #[link_name = "llvm.hexagon.V6.vaddw.dv.128B"]
244    fn vaddw_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
245    #[link_name = "llvm.hexagon.V6.vaddwnq.128B"]
246    fn vaddwnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
247    #[link_name = "llvm.hexagon.V6.vaddwq.128B"]
248    fn vaddwq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
249    #[link_name = "llvm.hexagon.V6.vaddwsat.128B"]
250    fn vaddwsat(_: HvxVector, _: HvxVector) -> HvxVector;
251    #[link_name = "llvm.hexagon.V6.vaddwsat.dv.128B"]
252    fn vaddwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
253    #[link_name = "llvm.hexagon.V6.valignb.128B"]
254    fn valignb(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
255    #[link_name = "llvm.hexagon.V6.valignbi.128B"]
256    fn valignbi(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
257    #[link_name = "llvm.hexagon.V6.vand.128B"]
258    fn vand(_: HvxVector, _: HvxVector) -> HvxVector;
259    #[link_name = "llvm.hexagon.V6.vandnqrt.128B"]
260    fn vandnqrt(_: HvxVector, _: i32) -> HvxVector;
261    #[link_name = "llvm.hexagon.V6.vandnqrt.acc.128B"]
262    fn vandnqrt_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
263    #[link_name = "llvm.hexagon.V6.vandqrt.128B"]
264    fn vandqrt(_: HvxVector, _: i32) -> HvxVector;
265    #[link_name = "llvm.hexagon.V6.vandqrt.acc.128B"]
266    fn vandqrt_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
267    #[link_name = "llvm.hexagon.V6.vandvnqv.128B"]
268    fn vandvnqv(_: HvxVector, _: HvxVector) -> HvxVector;
269    #[link_name = "llvm.hexagon.V6.vandvqv.128B"]
270    fn vandvqv(_: HvxVector, _: HvxVector) -> HvxVector;
271    #[link_name = "llvm.hexagon.V6.vandvrt.128B"]
272    fn vandvrt(_: HvxVector, _: i32) -> HvxVector;
273    #[link_name = "llvm.hexagon.V6.vandvrt.acc.128B"]
274    fn vandvrt_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
275    #[link_name = "llvm.hexagon.V6.vaslh.128B"]
276    fn vaslh(_: HvxVector, _: i32) -> HvxVector;
277    #[link_name = "llvm.hexagon.V6.vaslh.acc.128B"]
278    fn vaslh_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
279    #[link_name = "llvm.hexagon.V6.vaslhv.128B"]
280    fn vaslhv(_: HvxVector, _: HvxVector) -> HvxVector;
281    #[link_name = "llvm.hexagon.V6.vaslw.128B"]
282    fn vaslw(_: HvxVector, _: i32) -> HvxVector;
283    #[link_name = "llvm.hexagon.V6.vaslw.acc.128B"]
284    fn vaslw_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
285    #[link_name = "llvm.hexagon.V6.vaslwv.128B"]
286    fn vaslwv(_: HvxVector, _: HvxVector) -> HvxVector;
287    #[link_name = "llvm.hexagon.V6.vasr.into.128B"]
288    fn vasr_into(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
289    #[link_name = "llvm.hexagon.V6.vasrh.128B"]
290    fn vasrh(_: HvxVector, _: i32) -> HvxVector;
291    #[link_name = "llvm.hexagon.V6.vasrh.acc.128B"]
292    fn vasrh_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
293    #[link_name = "llvm.hexagon.V6.vasrhbrndsat.128B"]
294    fn vasrhbrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
295    #[link_name = "llvm.hexagon.V6.vasrhbsat.128B"]
296    fn vasrhbsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
297    #[link_name = "llvm.hexagon.V6.vasrhubrndsat.128B"]
298    fn vasrhubrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
299    #[link_name = "llvm.hexagon.V6.vasrhubsat.128B"]
300    fn vasrhubsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
301    #[link_name = "llvm.hexagon.V6.vasrhv.128B"]
302    fn vasrhv(_: HvxVector, _: HvxVector) -> HvxVector;
303    #[link_name = "llvm.hexagon.V6.vasruhubrndsat.128B"]
304    fn vasruhubrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
305    #[link_name = "llvm.hexagon.V6.vasruhubsat.128B"]
306    fn vasruhubsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
307    #[link_name = "llvm.hexagon.V6.vasruwuhrndsat.128B"]
308    fn vasruwuhrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
309    #[link_name = "llvm.hexagon.V6.vasruwuhsat.128B"]
310    fn vasruwuhsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
311    #[link_name = "llvm.hexagon.V6.vasrvuhubrndsat.128B"]
312    fn vasrvuhubrndsat(_: HvxVectorPair, _: HvxVector) -> HvxVector;
313    #[link_name = "llvm.hexagon.V6.vasrvuhubsat.128B"]
314    fn vasrvuhubsat(_: HvxVectorPair, _: HvxVector) -> HvxVector;
315    #[link_name = "llvm.hexagon.V6.vasrvwuhrndsat.128B"]
316    fn vasrvwuhrndsat(_: HvxVectorPair, _: HvxVector) -> HvxVector;
317    #[link_name = "llvm.hexagon.V6.vasrvwuhsat.128B"]
318    fn vasrvwuhsat(_: HvxVectorPair, _: HvxVector) -> HvxVector;
319    #[link_name = "llvm.hexagon.V6.vasrw.128B"]
320    fn vasrw(_: HvxVector, _: i32) -> HvxVector;
321    #[link_name = "llvm.hexagon.V6.vasrw.acc.128B"]
322    fn vasrw_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
323    #[link_name = "llvm.hexagon.V6.vasrwh.128B"]
324    fn vasrwh(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
325    #[link_name = "llvm.hexagon.V6.vasrwhrndsat.128B"]
326    fn vasrwhrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
327    #[link_name = "llvm.hexagon.V6.vasrwhsat.128B"]
328    fn vasrwhsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
329    #[link_name = "llvm.hexagon.V6.vasrwuhrndsat.128B"]
330    fn vasrwuhrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
331    #[link_name = "llvm.hexagon.V6.vasrwuhsat.128B"]
332    fn vasrwuhsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
333    #[link_name = "llvm.hexagon.V6.vasrwv.128B"]
334    fn vasrwv(_: HvxVector, _: HvxVector) -> HvxVector;
335    #[link_name = "llvm.hexagon.V6.vassign.128B"]
336    fn vassign(_: HvxVector) -> HvxVector;
337    #[link_name = "llvm.hexagon.V6.vassign.fp.128B"]
338    fn vassign_fp(_: HvxVector) -> HvxVector;
339    #[link_name = "llvm.hexagon.V6.vassignp.128B"]
340    fn vassignp(_: HvxVectorPair) -> HvxVectorPair;
341    #[link_name = "llvm.hexagon.V6.vavgb.128B"]
342    fn vavgb(_: HvxVector, _: HvxVector) -> HvxVector;
343    #[link_name = "llvm.hexagon.V6.vavgbrnd.128B"]
344    fn vavgbrnd(_: HvxVector, _: HvxVector) -> HvxVector;
345    #[link_name = "llvm.hexagon.V6.vavgh.128B"]
346    fn vavgh(_: HvxVector, _: HvxVector) -> HvxVector;
347    #[link_name = "llvm.hexagon.V6.vavghrnd.128B"]
348    fn vavghrnd(_: HvxVector, _: HvxVector) -> HvxVector;
349    #[link_name = "llvm.hexagon.V6.vavgub.128B"]
350    fn vavgub(_: HvxVector, _: HvxVector) -> HvxVector;
351    #[link_name = "llvm.hexagon.V6.vavgubrnd.128B"]
352    fn vavgubrnd(_: HvxVector, _: HvxVector) -> HvxVector;
353    #[link_name = "llvm.hexagon.V6.vavguh.128B"]
354    fn vavguh(_: HvxVector, _: HvxVector) -> HvxVector;
355    #[link_name = "llvm.hexagon.V6.vavguhrnd.128B"]
356    fn vavguhrnd(_: HvxVector, _: HvxVector) -> HvxVector;
357    #[link_name = "llvm.hexagon.V6.vavguw.128B"]
358    fn vavguw(_: HvxVector, _: HvxVector) -> HvxVector;
359    #[link_name = "llvm.hexagon.V6.vavguwrnd.128B"]
360    fn vavguwrnd(_: HvxVector, _: HvxVector) -> HvxVector;
361    #[link_name = "llvm.hexagon.V6.vavgw.128B"]
362    fn vavgw(_: HvxVector, _: HvxVector) -> HvxVector;
363    #[link_name = "llvm.hexagon.V6.vavgwrnd.128B"]
364    fn vavgwrnd(_: HvxVector, _: HvxVector) -> HvxVector;
365    #[link_name = "llvm.hexagon.V6.vcl0h.128B"]
366    fn vcl0h(_: HvxVector) -> HvxVector;
367    #[link_name = "llvm.hexagon.V6.vcl0w.128B"]
368    fn vcl0w(_: HvxVector) -> HvxVector;
369    #[link_name = "llvm.hexagon.V6.vcombine.128B"]
370    fn vcombine(_: HvxVector, _: HvxVector) -> HvxVectorPair;
371    #[link_name = "llvm.hexagon.V6.vconv.h.hf.128B"]
372    fn vconv_h_hf(_: HvxVector) -> HvxVector;
373    #[link_name = "llvm.hexagon.V6.vconv.hf.h.128B"]
374    fn vconv_hf_h(_: HvxVector) -> HvxVector;
375    #[link_name = "llvm.hexagon.V6.vconv.hf.qf16.128B"]
376    fn vconv_hf_qf16(_: HvxVector) -> HvxVector;
377    #[link_name = "llvm.hexagon.V6.vconv.hf.qf32.128B"]
378    fn vconv_hf_qf32(_: HvxVectorPair) -> HvxVector;
379    #[link_name = "llvm.hexagon.V6.vconv.sf.qf32.128B"]
380    fn vconv_sf_qf32(_: HvxVector) -> HvxVector;
381    #[link_name = "llvm.hexagon.V6.vconv.sf.w.128B"]
382    fn vconv_sf_w(_: HvxVector) -> HvxVector;
383    #[link_name = "llvm.hexagon.V6.vconv.w.sf.128B"]
384    fn vconv_w_sf(_: HvxVector) -> HvxVector;
385    #[link_name = "llvm.hexagon.V6.vcvt2.hf.b.128B"]
386    fn vcvt2_hf_b(_: HvxVector) -> HvxVectorPair;
387    #[link_name = "llvm.hexagon.V6.vcvt2.hf.ub.128B"]
388    fn vcvt2_hf_ub(_: HvxVector) -> HvxVectorPair;
389    #[link_name = "llvm.hexagon.V6.vcvt.b.hf.128B"]
390    fn vcvt_b_hf(_: HvxVector, _: HvxVector) -> HvxVector;
391    #[link_name = "llvm.hexagon.V6.vcvt.h.hf.128B"]
392    fn vcvt_h_hf(_: HvxVector) -> HvxVector;
393    #[link_name = "llvm.hexagon.V6.vcvt.hf.b.128B"]
394    fn vcvt_hf_b(_: HvxVector) -> HvxVectorPair;
395    #[link_name = "llvm.hexagon.V6.vcvt.hf.f8.128B"]
396    fn vcvt_hf_f8(_: HvxVector) -> HvxVectorPair;
397    #[link_name = "llvm.hexagon.V6.vcvt.hf.h.128B"]
398    fn vcvt_hf_h(_: HvxVector) -> HvxVector;
399    #[link_name = "llvm.hexagon.V6.vcvt.hf.sf.128B"]
400    fn vcvt_hf_sf(_: HvxVector, _: HvxVector) -> HvxVector;
401    #[link_name = "llvm.hexagon.V6.vcvt.hf.ub.128B"]
402    fn vcvt_hf_ub(_: HvxVector) -> HvxVectorPair;
403    #[link_name = "llvm.hexagon.V6.vcvt.hf.uh.128B"]
404    fn vcvt_hf_uh(_: HvxVector) -> HvxVector;
405    #[link_name = "llvm.hexagon.V6.vcvt.sf.hf.128B"]
406    fn vcvt_sf_hf(_: HvxVector) -> HvxVectorPair;
407    #[link_name = "llvm.hexagon.V6.vcvt.ub.hf.128B"]
408    fn vcvt_ub_hf(_: HvxVector, _: HvxVector) -> HvxVector;
409    #[link_name = "llvm.hexagon.V6.vcvt.uh.hf.128B"]
410    fn vcvt_uh_hf(_: HvxVector) -> HvxVector;
411    #[link_name = "llvm.hexagon.V6.vd0.128B"]
412    fn vd0() -> HvxVector;
413    #[link_name = "llvm.hexagon.V6.vdd0.128B"]
414    fn vdd0() -> HvxVectorPair;
415    #[link_name = "llvm.hexagon.V6.vdealb.128B"]
416    fn vdealb(_: HvxVector) -> HvxVector;
417    #[link_name = "llvm.hexagon.V6.vdealb4w.128B"]
418    fn vdealb4w(_: HvxVector, _: HvxVector) -> HvxVector;
419    #[link_name = "llvm.hexagon.V6.vdealh.128B"]
420    fn vdealh(_: HvxVector) -> HvxVector;
421    #[link_name = "llvm.hexagon.V6.vdealvdd.128B"]
422    fn vdealvdd(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair;
423    #[link_name = "llvm.hexagon.V6.vdelta.128B"]
424    fn vdelta(_: HvxVector, _: HvxVector) -> HvxVector;
425    #[link_name = "llvm.hexagon.V6.vdmpy.sf.hf.128B"]
426    fn vdmpy_sf_hf(_: HvxVector, _: HvxVector) -> HvxVector;
427    #[link_name = "llvm.hexagon.V6.vdmpy.sf.hf.acc.128B"]
428    fn vdmpy_sf_hf_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
429    #[link_name = "llvm.hexagon.V6.vdmpybus.128B"]
430    fn vdmpybus(_: HvxVector, _: i32) -> HvxVector;
431    #[link_name = "llvm.hexagon.V6.vdmpybus.acc.128B"]
432    fn vdmpybus_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
433    #[link_name = "llvm.hexagon.V6.vdmpybus.dv.128B"]
434    fn vdmpybus_dv(_: HvxVectorPair, _: i32) -> HvxVectorPair;
435    #[link_name = "llvm.hexagon.V6.vdmpybus.dv.acc.128B"]
436    fn vdmpybus_dv_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
437    #[link_name = "llvm.hexagon.V6.vdmpyhb.128B"]
438    fn vdmpyhb(_: HvxVector, _: i32) -> HvxVector;
439    #[link_name = "llvm.hexagon.V6.vdmpyhb.acc.128B"]
440    fn vdmpyhb_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
441    #[link_name = "llvm.hexagon.V6.vdmpyhb.dv.128B"]
442    fn vdmpyhb_dv(_: HvxVectorPair, _: i32) -> HvxVectorPair;
443    #[link_name = "llvm.hexagon.V6.vdmpyhb.dv.acc.128B"]
444    fn vdmpyhb_dv_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
445    #[link_name = "llvm.hexagon.V6.vdmpyhisat.128B"]
446    fn vdmpyhisat(_: HvxVectorPair, _: i32) -> HvxVector;
447    #[link_name = "llvm.hexagon.V6.vdmpyhisat.acc.128B"]
448    fn vdmpyhisat_acc(_: HvxVector, _: HvxVectorPair, _: i32) -> HvxVector;
449    #[link_name = "llvm.hexagon.V6.vdmpyhsat.128B"]
450    fn vdmpyhsat(_: HvxVector, _: i32) -> HvxVector;
451    #[link_name = "llvm.hexagon.V6.vdmpyhsat.acc.128B"]
452    fn vdmpyhsat_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
453    #[link_name = "llvm.hexagon.V6.vdmpyhsuisat.128B"]
454    fn vdmpyhsuisat(_: HvxVectorPair, _: i32) -> HvxVector;
455    #[link_name = "llvm.hexagon.V6.vdmpyhsuisat.acc.128B"]
456    fn vdmpyhsuisat_acc(_: HvxVector, _: HvxVectorPair, _: i32) -> HvxVector;
457    #[link_name = "llvm.hexagon.V6.vdmpyhsusat.128B"]
458    fn vdmpyhsusat(_: HvxVector, _: i32) -> HvxVector;
459    #[link_name = "llvm.hexagon.V6.vdmpyhsusat.acc.128B"]
460    fn vdmpyhsusat_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
461    #[link_name = "llvm.hexagon.V6.vdmpyhvsat.128B"]
462    fn vdmpyhvsat(_: HvxVector, _: HvxVector) -> HvxVector;
463    #[link_name = "llvm.hexagon.V6.vdmpyhvsat.acc.128B"]
464    fn vdmpyhvsat_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
465    #[link_name = "llvm.hexagon.V6.vdsaduh.128B"]
466    fn vdsaduh(_: HvxVectorPair, _: i32) -> HvxVectorPair;
467    #[link_name = "llvm.hexagon.V6.vdsaduh.acc.128B"]
468    fn vdsaduh_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
469    #[link_name = "llvm.hexagon.V6.veqb.128B"]
470    fn veqb(_: HvxVector, _: HvxVector) -> HvxVector;
471    #[link_name = "llvm.hexagon.V6.veqb.and.128B"]
472    fn veqb_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
473    #[link_name = "llvm.hexagon.V6.veqb.or.128B"]
474    fn veqb_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
475    #[link_name = "llvm.hexagon.V6.veqb.xor.128B"]
476    fn veqb_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
477    #[link_name = "llvm.hexagon.V6.veqh.128B"]
478    fn veqh(_: HvxVector, _: HvxVector) -> HvxVector;
479    #[link_name = "llvm.hexagon.V6.veqh.and.128B"]
480    fn veqh_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
481    #[link_name = "llvm.hexagon.V6.veqh.or.128B"]
482    fn veqh_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
483    #[link_name = "llvm.hexagon.V6.veqh.xor.128B"]
484    fn veqh_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
485    #[link_name = "llvm.hexagon.V6.veqw.128B"]
486    fn veqw(_: HvxVector, _: HvxVector) -> HvxVector;
487    #[link_name = "llvm.hexagon.V6.veqw.and.128B"]
488    fn veqw_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
489    #[link_name = "llvm.hexagon.V6.veqw.or.128B"]
490    fn veqw_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
491    #[link_name = "llvm.hexagon.V6.veqw.xor.128B"]
492    fn veqw_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
493    #[link_name = "llvm.hexagon.V6.vfmax.f8.128B"]
494    fn vfmax_f8(_: HvxVector, _: HvxVector) -> HvxVector;
495    #[link_name = "llvm.hexagon.V6.vfmax.hf.128B"]
496    fn vfmax_hf(_: HvxVector, _: HvxVector) -> HvxVector;
497    #[link_name = "llvm.hexagon.V6.vfmax.sf.128B"]
498    fn vfmax_sf(_: HvxVector, _: HvxVector) -> HvxVector;
499    #[link_name = "llvm.hexagon.V6.vfmin.f8.128B"]
500    fn vfmin_f8(_: HvxVector, _: HvxVector) -> HvxVector;
501    #[link_name = "llvm.hexagon.V6.vfmin.hf.128B"]
502    fn vfmin_hf(_: HvxVector, _: HvxVector) -> HvxVector;
503    #[link_name = "llvm.hexagon.V6.vfmin.sf.128B"]
504    fn vfmin_sf(_: HvxVector, _: HvxVector) -> HvxVector;
505    #[link_name = "llvm.hexagon.V6.vfneg.f8.128B"]
506    fn vfneg_f8(_: HvxVector) -> HvxVector;
507    #[link_name = "llvm.hexagon.V6.vfneg.hf.128B"]
508    fn vfneg_hf(_: HvxVector) -> HvxVector;
509    #[link_name = "llvm.hexagon.V6.vfneg.sf.128B"]
510    fn vfneg_sf(_: HvxVector) -> HvxVector;
511    #[link_name = "llvm.hexagon.V6.vgathermh.128B"]
512    fn vgathermh(_: *mut HvxVector, _: i32, _: i32, _: HvxVector) -> ();
513    #[link_name = "llvm.hexagon.V6.vgathermhq.128B"]
514    fn vgathermhq(_: *mut HvxVector, _: HvxVector, _: i32, _: i32, _: HvxVector) -> ();
515    #[link_name = "llvm.hexagon.V6.vgathermhw.128B"]
516    fn vgathermhw(_: *mut HvxVector, _: i32, _: i32, _: HvxVectorPair) -> ();
517    #[link_name = "llvm.hexagon.V6.vgathermhwq.128B"]
518    fn vgathermhwq(_: *mut HvxVector, _: HvxVector, _: i32, _: i32, _: HvxVectorPair) -> ();
519    #[link_name = "llvm.hexagon.V6.vgathermw.128B"]
520    fn vgathermw(_: *mut HvxVector, _: i32, _: i32, _: HvxVector) -> ();
521    #[link_name = "llvm.hexagon.V6.vgathermwq.128B"]
522    fn vgathermwq(_: *mut HvxVector, _: HvxVector, _: i32, _: i32, _: HvxVector) -> ();
523    #[link_name = "llvm.hexagon.V6.vgtb.128B"]
524    fn vgtb(_: HvxVector, _: HvxVector) -> HvxVector;
525    #[link_name = "llvm.hexagon.V6.vgtb.and.128B"]
526    fn vgtb_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
527    #[link_name = "llvm.hexagon.V6.vgtb.or.128B"]
528    fn vgtb_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
529    #[link_name = "llvm.hexagon.V6.vgtb.xor.128B"]
530    fn vgtb_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
531    #[link_name = "llvm.hexagon.V6.vgth.128B"]
532    fn vgth(_: HvxVector, _: HvxVector) -> HvxVector;
533    #[link_name = "llvm.hexagon.V6.vgth.and.128B"]
534    fn vgth_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
535    #[link_name = "llvm.hexagon.V6.vgth.or.128B"]
536    fn vgth_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
537    #[link_name = "llvm.hexagon.V6.vgth.xor.128B"]
538    fn vgth_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
539    #[link_name = "llvm.hexagon.V6.vgthf.128B"]
540    fn vgthf(_: HvxVector, _: HvxVector) -> HvxVector;
541    #[link_name = "llvm.hexagon.V6.vgthf.and.128B"]
542    fn vgthf_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
543    #[link_name = "llvm.hexagon.V6.vgthf.or.128B"]
544    fn vgthf_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
545    #[link_name = "llvm.hexagon.V6.vgthf.xor.128B"]
546    fn vgthf_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
547    #[link_name = "llvm.hexagon.V6.vgtsf.128B"]
548    fn vgtsf(_: HvxVector, _: HvxVector) -> HvxVector;
549    #[link_name = "llvm.hexagon.V6.vgtsf.and.128B"]
550    fn vgtsf_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
551    #[link_name = "llvm.hexagon.V6.vgtsf.or.128B"]
552    fn vgtsf_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
553    #[link_name = "llvm.hexagon.V6.vgtsf.xor.128B"]
554    fn vgtsf_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
555    #[link_name = "llvm.hexagon.V6.vgtub.128B"]
556    fn vgtub(_: HvxVector, _: HvxVector) -> HvxVector;
557    #[link_name = "llvm.hexagon.V6.vgtub.and.128B"]
558    fn vgtub_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
559    #[link_name = "llvm.hexagon.V6.vgtub.or.128B"]
560    fn vgtub_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
561    #[link_name = "llvm.hexagon.V6.vgtub.xor.128B"]
562    fn vgtub_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
563    #[link_name = "llvm.hexagon.V6.vgtuh.128B"]
564    fn vgtuh(_: HvxVector, _: HvxVector) -> HvxVector;
565    #[link_name = "llvm.hexagon.V6.vgtuh.and.128B"]
566    fn vgtuh_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
567    #[link_name = "llvm.hexagon.V6.vgtuh.or.128B"]
568    fn vgtuh_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
569    #[link_name = "llvm.hexagon.V6.vgtuh.xor.128B"]
570    fn vgtuh_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
571    #[link_name = "llvm.hexagon.V6.vgtuw.128B"]
572    fn vgtuw(_: HvxVector, _: HvxVector) -> HvxVector;
573    #[link_name = "llvm.hexagon.V6.vgtuw.and.128B"]
574    fn vgtuw_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
575    #[link_name = "llvm.hexagon.V6.vgtuw.or.128B"]
576    fn vgtuw_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
577    #[link_name = "llvm.hexagon.V6.vgtuw.xor.128B"]
578    fn vgtuw_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
579    #[link_name = "llvm.hexagon.V6.vgtw.128B"]
580    fn vgtw(_: HvxVector, _: HvxVector) -> HvxVector;
581    #[link_name = "llvm.hexagon.V6.vgtw.and.128B"]
582    fn vgtw_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
583    #[link_name = "llvm.hexagon.V6.vgtw.or.128B"]
584    fn vgtw_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
585    #[link_name = "llvm.hexagon.V6.vgtw.xor.128B"]
586    fn vgtw_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
587    #[link_name = "llvm.hexagon.V6.vinsertwr.128B"]
588    fn vinsertwr(_: HvxVector, _: i32) -> HvxVector;
589    #[link_name = "llvm.hexagon.V6.vlalignb.128B"]
590    fn vlalignb(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
591    #[link_name = "llvm.hexagon.V6.vlalignbi.128B"]
592    fn vlalignbi(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
593    #[link_name = "llvm.hexagon.V6.vlsrb.128B"]
594    fn vlsrb(_: HvxVector, _: i32) -> HvxVector;
595    #[link_name = "llvm.hexagon.V6.vlsrh.128B"]
596    fn vlsrh(_: HvxVector, _: i32) -> HvxVector;
597    #[link_name = "llvm.hexagon.V6.vlsrhv.128B"]
598    fn vlsrhv(_: HvxVector, _: HvxVector) -> HvxVector;
599    #[link_name = "llvm.hexagon.V6.vlsrw.128B"]
600    fn vlsrw(_: HvxVector, _: i32) -> HvxVector;
601    #[link_name = "llvm.hexagon.V6.vlsrwv.128B"]
602    fn vlsrwv(_: HvxVector, _: HvxVector) -> HvxVector;
603    #[link_name = "llvm.hexagon.V6.vlutvvb.128B"]
604    fn vlutvvb(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
605    #[link_name = "llvm.hexagon.V6.vlutvvb.nm.128B"]
606    fn vlutvvb_nm(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
607    #[link_name = "llvm.hexagon.V6.vlutvvb.oracc.128B"]
608    fn vlutvvb_oracc(_: HvxVector, _: HvxVector, _: HvxVector, _: i32) -> HvxVector;
609    #[link_name = "llvm.hexagon.V6.vlutvvb.oracci.128B"]
610    fn vlutvvb_oracci(_: HvxVector, _: HvxVector, _: HvxVector, _: i32) -> HvxVector;
611    #[link_name = "llvm.hexagon.V6.vlutvvbi.128B"]
612    fn vlutvvbi(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
613    #[link_name = "llvm.hexagon.V6.vlutvwh.128B"]
614    fn vlutvwh(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair;
615    #[link_name = "llvm.hexagon.V6.vlutvwh.nm.128B"]
616    fn vlutvwh_nm(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair;
617    #[link_name = "llvm.hexagon.V6.vlutvwh.oracc.128B"]
618    fn vlutvwh_oracc(_: HvxVectorPair, _: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair;
619    #[link_name = "llvm.hexagon.V6.vlutvwh.oracci.128B"]
620    fn vlutvwh_oracci(_: HvxVectorPair, _: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair;
621    #[link_name = "llvm.hexagon.V6.vlutvwhi.128B"]
622    fn vlutvwhi(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair;
623    #[link_name = "llvm.hexagon.V6.vmax.hf.128B"]
624    fn vmax_hf(_: HvxVector, _: HvxVector) -> HvxVector;
625    #[link_name = "llvm.hexagon.V6.vmax.sf.128B"]
626    fn vmax_sf(_: HvxVector, _: HvxVector) -> HvxVector;
627    #[link_name = "llvm.hexagon.V6.vmaxb.128B"]
628    fn vmaxb(_: HvxVector, _: HvxVector) -> HvxVector;
629    #[link_name = "llvm.hexagon.V6.vmaxh.128B"]
630    fn vmaxh(_: HvxVector, _: HvxVector) -> HvxVector;
631    #[link_name = "llvm.hexagon.V6.vmaxub.128B"]
632    fn vmaxub(_: HvxVector, _: HvxVector) -> HvxVector;
633    #[link_name = "llvm.hexagon.V6.vmaxuh.128B"]
634    fn vmaxuh(_: HvxVector, _: HvxVector) -> HvxVector;
635    #[link_name = "llvm.hexagon.V6.vmaxw.128B"]
636    fn vmaxw(_: HvxVector, _: HvxVector) -> HvxVector;
637    #[link_name = "llvm.hexagon.V6.vmin.hf.128B"]
638    fn vmin_hf(_: HvxVector, _: HvxVector) -> HvxVector;
639    #[link_name = "llvm.hexagon.V6.vmin.sf.128B"]
640    fn vmin_sf(_: HvxVector, _: HvxVector) -> HvxVector;
641    #[link_name = "llvm.hexagon.V6.vminb.128B"]
642    fn vminb(_: HvxVector, _: HvxVector) -> HvxVector;
643    #[link_name = "llvm.hexagon.V6.vminh.128B"]
644    fn vminh(_: HvxVector, _: HvxVector) -> HvxVector;
645    #[link_name = "llvm.hexagon.V6.vminub.128B"]
646    fn vminub(_: HvxVector, _: HvxVector) -> HvxVector;
647    #[link_name = "llvm.hexagon.V6.vminuh.128B"]
648    fn vminuh(_: HvxVector, _: HvxVector) -> HvxVector;
649    #[link_name = "llvm.hexagon.V6.vminw.128B"]
650    fn vminw(_: HvxVector, _: HvxVector) -> HvxVector;
651    #[link_name = "llvm.hexagon.V6.vmpabus.128B"]
652    fn vmpabus(_: HvxVectorPair, _: i32) -> HvxVectorPair;
653    #[link_name = "llvm.hexagon.V6.vmpabus.acc.128B"]
654    fn vmpabus_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
655    #[link_name = "llvm.hexagon.V6.vmpabusv.128B"]
656    fn vmpabusv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
657    #[link_name = "llvm.hexagon.V6.vmpabuu.128B"]
658    fn vmpabuu(_: HvxVectorPair, _: i32) -> HvxVectorPair;
659    #[link_name = "llvm.hexagon.V6.vmpabuu.acc.128B"]
660    fn vmpabuu_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
661    #[link_name = "llvm.hexagon.V6.vmpabuuv.128B"]
662    fn vmpabuuv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
663    #[link_name = "llvm.hexagon.V6.vmpahb.128B"]
664    fn vmpahb(_: HvxVectorPair, _: i32) -> HvxVectorPair;
665    #[link_name = "llvm.hexagon.V6.vmpahb.acc.128B"]
666    fn vmpahb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
667    #[link_name = "llvm.hexagon.V6.vmpauhb.128B"]
668    fn vmpauhb(_: HvxVectorPair, _: i32) -> HvxVectorPair;
669    #[link_name = "llvm.hexagon.V6.vmpauhb.acc.128B"]
670    fn vmpauhb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
671    #[link_name = "llvm.hexagon.V6.vmpy.hf.hf.128B"]
672    fn vmpy_hf_hf(_: HvxVector, _: HvxVector) -> HvxVector;
673    #[link_name = "llvm.hexagon.V6.vmpy.hf.hf.acc.128B"]
674    fn vmpy_hf_hf_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
675    #[link_name = "llvm.hexagon.V6.vmpy.qf16.128B"]
676    fn vmpy_qf16(_: HvxVector, _: HvxVector) -> HvxVector;
677    #[link_name = "llvm.hexagon.V6.vmpy.qf16.hf.128B"]
678    fn vmpy_qf16_hf(_: HvxVector, _: HvxVector) -> HvxVector;
679    #[link_name = "llvm.hexagon.V6.vmpy.qf16.mix.hf.128B"]
680    fn vmpy_qf16_mix_hf(_: HvxVector, _: HvxVector) -> HvxVector;
681    #[link_name = "llvm.hexagon.V6.vmpy.qf32.128B"]
682    fn vmpy_qf32(_: HvxVector, _: HvxVector) -> HvxVector;
683    #[link_name = "llvm.hexagon.V6.vmpy.qf32.hf.128B"]
684    fn vmpy_qf32_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair;
685    #[link_name = "llvm.hexagon.V6.vmpy.qf32.mix.hf.128B"]
686    fn vmpy_qf32_mix_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair;
687    #[link_name = "llvm.hexagon.V6.vmpy.qf32.qf16.128B"]
688    fn vmpy_qf32_qf16(_: HvxVector, _: HvxVector) -> HvxVectorPair;
689    #[link_name = "llvm.hexagon.V6.vmpy.qf32.sf.128B"]
690    fn vmpy_qf32_sf(_: HvxVector, _: HvxVector) -> HvxVector;
691    #[link_name = "llvm.hexagon.V6.vmpy.sf.hf.128B"]
692    fn vmpy_sf_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair;
693    #[link_name = "llvm.hexagon.V6.vmpy.sf.hf.acc.128B"]
694    fn vmpy_sf_hf_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
695    #[link_name = "llvm.hexagon.V6.vmpy.sf.sf.128B"]
696    fn vmpy_sf_sf(_: HvxVector, _: HvxVector) -> HvxVector;
697    #[link_name = "llvm.hexagon.V6.vmpybus.128B"]
698    fn vmpybus(_: HvxVector, _: i32) -> HvxVectorPair;
699    #[link_name = "llvm.hexagon.V6.vmpybus.acc.128B"]
700    fn vmpybus_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair;
701    #[link_name = "llvm.hexagon.V6.vmpybusv.128B"]
702    fn vmpybusv(_: HvxVector, _: HvxVector) -> HvxVectorPair;
703    #[link_name = "llvm.hexagon.V6.vmpybusv.acc.128B"]
704    fn vmpybusv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
705    #[link_name = "llvm.hexagon.V6.vmpybv.128B"]
706    fn vmpybv(_: HvxVector, _: HvxVector) -> HvxVectorPair;
707    #[link_name = "llvm.hexagon.V6.vmpybv.acc.128B"]
708    fn vmpybv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
709    #[link_name = "llvm.hexagon.V6.vmpyewuh.128B"]
710    fn vmpyewuh(_: HvxVector, _: HvxVector) -> HvxVector;
711    #[link_name = "llvm.hexagon.V6.vmpyewuh.64.128B"]
712    fn vmpyewuh_64(_: HvxVector, _: HvxVector) -> HvxVectorPair;
713    #[link_name = "llvm.hexagon.V6.vmpyh.128B"]
714    fn vmpyh(_: HvxVector, _: i32) -> HvxVectorPair;
715    #[link_name = "llvm.hexagon.V6.vmpyh.acc.128B"]
716    fn vmpyh_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair;
717    #[link_name = "llvm.hexagon.V6.vmpyhsat.acc.128B"]
718    fn vmpyhsat_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair;
719    #[link_name = "llvm.hexagon.V6.vmpyhsrs.128B"]
720    fn vmpyhsrs(_: HvxVector, _: i32) -> HvxVector;
721    #[link_name = "llvm.hexagon.V6.vmpyhss.128B"]
722    fn vmpyhss(_: HvxVector, _: i32) -> HvxVector;
723    #[link_name = "llvm.hexagon.V6.vmpyhus.128B"]
724    fn vmpyhus(_: HvxVector, _: HvxVector) -> HvxVectorPair;
725    #[link_name = "llvm.hexagon.V6.vmpyhus.acc.128B"]
726    fn vmpyhus_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
727    #[link_name = "llvm.hexagon.V6.vmpyhv.128B"]
728    fn vmpyhv(_: HvxVector, _: HvxVector) -> HvxVectorPair;
729    #[link_name = "llvm.hexagon.V6.vmpyhv.acc.128B"]
730    fn vmpyhv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
731    #[link_name = "llvm.hexagon.V6.vmpyhvsrs.128B"]
732    fn vmpyhvsrs(_: HvxVector, _: HvxVector) -> HvxVector;
733    #[link_name = "llvm.hexagon.V6.vmpyieoh.128B"]
734    fn vmpyieoh(_: HvxVector, _: HvxVector) -> HvxVector;
735    #[link_name = "llvm.hexagon.V6.vmpyiewh.acc.128B"]
736    fn vmpyiewh_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
737    #[link_name = "llvm.hexagon.V6.vmpyiewuh.128B"]
738    fn vmpyiewuh(_: HvxVector, _: HvxVector) -> HvxVector;
739    #[link_name = "llvm.hexagon.V6.vmpyiewuh.acc.128B"]
740    fn vmpyiewuh_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
741    #[link_name = "llvm.hexagon.V6.vmpyih.128B"]
742    fn vmpyih(_: HvxVector, _: HvxVector) -> HvxVector;
743    #[link_name = "llvm.hexagon.V6.vmpyih.acc.128B"]
744    fn vmpyih_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
745    #[link_name = "llvm.hexagon.V6.vmpyihb.128B"]
746    fn vmpyihb(_: HvxVector, _: i32) -> HvxVector;
747    #[link_name = "llvm.hexagon.V6.vmpyihb.acc.128B"]
748    fn vmpyihb_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
749    #[link_name = "llvm.hexagon.V6.vmpyiowh.128B"]
750    fn vmpyiowh(_: HvxVector, _: HvxVector) -> HvxVector;
751    #[link_name = "llvm.hexagon.V6.vmpyiwb.128B"]
752    fn vmpyiwb(_: HvxVector, _: i32) -> HvxVector;
753    #[link_name = "llvm.hexagon.V6.vmpyiwb.acc.128B"]
754    fn vmpyiwb_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
755    #[link_name = "llvm.hexagon.V6.vmpyiwh.128B"]
756    fn vmpyiwh(_: HvxVector, _: i32) -> HvxVector;
757    #[link_name = "llvm.hexagon.V6.vmpyiwh.acc.128B"]
758    fn vmpyiwh_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
759    #[link_name = "llvm.hexagon.V6.vmpyiwub.128B"]
760    fn vmpyiwub(_: HvxVector, _: i32) -> HvxVector;
761    #[link_name = "llvm.hexagon.V6.vmpyiwub.acc.128B"]
762    fn vmpyiwub_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
763    #[link_name = "llvm.hexagon.V6.vmpyowh.128B"]
764    fn vmpyowh(_: HvxVector, _: HvxVector) -> HvxVector;
765    #[link_name = "llvm.hexagon.V6.vmpyowh.64.acc.128B"]
766    fn vmpyowh_64_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
767    #[link_name = "llvm.hexagon.V6.vmpyowh.rnd.128B"]
768    fn vmpyowh_rnd(_: HvxVector, _: HvxVector) -> HvxVector;
769    #[link_name = "llvm.hexagon.V6.vmpyowh.rnd.sacc.128B"]
770    fn vmpyowh_rnd_sacc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
771    #[link_name = "llvm.hexagon.V6.vmpyowh.sacc.128B"]
772    fn vmpyowh_sacc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
773    #[link_name = "llvm.hexagon.V6.vmpyub.128B"]
774    fn vmpyub(_: HvxVector, _: i32) -> HvxVectorPair;
775    #[link_name = "llvm.hexagon.V6.vmpyub.acc.128B"]
776    fn vmpyub_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair;
777    #[link_name = "llvm.hexagon.V6.vmpyubv.128B"]
778    fn vmpyubv(_: HvxVector, _: HvxVector) -> HvxVectorPair;
779    #[link_name = "llvm.hexagon.V6.vmpyubv.acc.128B"]
780    fn vmpyubv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
781    #[link_name = "llvm.hexagon.V6.vmpyuh.128B"]
782    fn vmpyuh(_: HvxVector, _: i32) -> HvxVectorPair;
783    #[link_name = "llvm.hexagon.V6.vmpyuh.acc.128B"]
784    fn vmpyuh_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair;
785    #[link_name = "llvm.hexagon.V6.vmpyuhe.128B"]
786    fn vmpyuhe(_: HvxVector, _: i32) -> HvxVector;
787    #[link_name = "llvm.hexagon.V6.vmpyuhe.acc.128B"]
788    fn vmpyuhe_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
789    #[link_name = "llvm.hexagon.V6.vmpyuhv.128B"]
790    fn vmpyuhv(_: HvxVector, _: HvxVector) -> HvxVectorPair;
791    #[link_name = "llvm.hexagon.V6.vmpyuhv.acc.128B"]
792    fn vmpyuhv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
793    #[link_name = "llvm.hexagon.V6.vmpyuhvs.128B"]
794    fn vmpyuhvs(_: HvxVector, _: HvxVector) -> HvxVector;
795    #[link_name = "llvm.hexagon.V6.vmux.128B"]
796    fn vmux(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
797    #[link_name = "llvm.hexagon.V6.vnavgb.128B"]
798    fn vnavgb(_: HvxVector, _: HvxVector) -> HvxVector;
799    #[link_name = "llvm.hexagon.V6.vnavgh.128B"]
800    fn vnavgh(_: HvxVector, _: HvxVector) -> HvxVector;
801    #[link_name = "llvm.hexagon.V6.vnavgub.128B"]
802    fn vnavgub(_: HvxVector, _: HvxVector) -> HvxVector;
803    #[link_name = "llvm.hexagon.V6.vnavgw.128B"]
804    fn vnavgw(_: HvxVector, _: HvxVector) -> HvxVector;
805    #[link_name = "llvm.hexagon.V6.vnormamth.128B"]
806    fn vnormamth(_: HvxVector) -> HvxVector;
807    #[link_name = "llvm.hexagon.V6.vnormamtw.128B"]
808    fn vnormamtw(_: HvxVector) -> HvxVector;
809    #[link_name = "llvm.hexagon.V6.vnot.128B"]
810    fn vnot(_: HvxVector) -> HvxVector;
811    #[link_name = "llvm.hexagon.V6.vor.128B"]
812    fn vor(_: HvxVector, _: HvxVector) -> HvxVector;
813    #[link_name = "llvm.hexagon.V6.vpackeb.128B"]
814    fn vpackeb(_: HvxVector, _: HvxVector) -> HvxVector;
815    #[link_name = "llvm.hexagon.V6.vpackeh.128B"]
816    fn vpackeh(_: HvxVector, _: HvxVector) -> HvxVector;
817    #[link_name = "llvm.hexagon.V6.vpackhb.sat.128B"]
818    fn vpackhb_sat(_: HvxVector, _: HvxVector) -> HvxVector;
819    #[link_name = "llvm.hexagon.V6.vpackhub.sat.128B"]
820    fn vpackhub_sat(_: HvxVector, _: HvxVector) -> HvxVector;
821    #[link_name = "llvm.hexagon.V6.vpackob.128B"]
822    fn vpackob(_: HvxVector, _: HvxVector) -> HvxVector;
823    #[link_name = "llvm.hexagon.V6.vpackoh.128B"]
824    fn vpackoh(_: HvxVector, _: HvxVector) -> HvxVector;
825    #[link_name = "llvm.hexagon.V6.vpackwh.sat.128B"]
826    fn vpackwh_sat(_: HvxVector, _: HvxVector) -> HvxVector;
827    #[link_name = "llvm.hexagon.V6.vpackwuh.sat.128B"]
828    fn vpackwuh_sat(_: HvxVector, _: HvxVector) -> HvxVector;
829    #[link_name = "llvm.hexagon.V6.vpopcounth.128B"]
830    fn vpopcounth(_: HvxVector) -> HvxVector;
831    #[link_name = "llvm.hexagon.V6.vprefixqb.128B"]
832    fn vprefixqb(_: HvxVector) -> HvxVector;
833    #[link_name = "llvm.hexagon.V6.vprefixqh.128B"]
834    fn vprefixqh(_: HvxVector) -> HvxVector;
835    #[link_name = "llvm.hexagon.V6.vprefixqw.128B"]
836    fn vprefixqw(_: HvxVector) -> HvxVector;
837    #[link_name = "llvm.hexagon.V6.vrdelta.128B"]
838    fn vrdelta(_: HvxVector, _: HvxVector) -> HvxVector;
839    #[link_name = "llvm.hexagon.V6.vrmpybus.128B"]
840    fn vrmpybus(_: HvxVector, _: i32) -> HvxVector;
841    #[link_name = "llvm.hexagon.V6.vrmpybus.acc.128B"]
842    fn vrmpybus_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
843    #[link_name = "llvm.hexagon.V6.vrmpybusi.128B"]
844    fn vrmpybusi(_: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair;
845    #[link_name = "llvm.hexagon.V6.vrmpybusi.acc.128B"]
846    fn vrmpybusi_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair;
847    #[link_name = "llvm.hexagon.V6.vrmpybusv.128B"]
848    fn vrmpybusv(_: HvxVector, _: HvxVector) -> HvxVector;
849    #[link_name = "llvm.hexagon.V6.vrmpybusv.acc.128B"]
850    fn vrmpybusv_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
851    #[link_name = "llvm.hexagon.V6.vrmpybv.128B"]
852    fn vrmpybv(_: HvxVector, _: HvxVector) -> HvxVector;
853    #[link_name = "llvm.hexagon.V6.vrmpybv.acc.128B"]
854    fn vrmpybv_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
855    #[link_name = "llvm.hexagon.V6.vrmpyub.128B"]
856    fn vrmpyub(_: HvxVector, _: i32) -> HvxVector;
857    #[link_name = "llvm.hexagon.V6.vrmpyub.acc.128B"]
858    fn vrmpyub_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
859    #[link_name = "llvm.hexagon.V6.vrmpyubi.128B"]
860    fn vrmpyubi(_: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair;
861    #[link_name = "llvm.hexagon.V6.vrmpyubi.acc.128B"]
862    fn vrmpyubi_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair;
863    #[link_name = "llvm.hexagon.V6.vrmpyubv.128B"]
864    fn vrmpyubv(_: HvxVector, _: HvxVector) -> HvxVector;
865    #[link_name = "llvm.hexagon.V6.vrmpyubv.acc.128B"]
866    fn vrmpyubv_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
867    #[link_name = "llvm.hexagon.V6.vror.128B"]
868    fn vror(_: HvxVector, _: i32) -> HvxVector;
869    #[link_name = "llvm.hexagon.V6.vrotr.128B"]
870    fn vrotr(_: HvxVector, _: HvxVector) -> HvxVector;
871    #[link_name = "llvm.hexagon.V6.vroundhb.128B"]
872    fn vroundhb(_: HvxVector, _: HvxVector) -> HvxVector;
873    #[link_name = "llvm.hexagon.V6.vroundhub.128B"]
874    fn vroundhub(_: HvxVector, _: HvxVector) -> HvxVector;
875    #[link_name = "llvm.hexagon.V6.vrounduhub.128B"]
876    fn vrounduhub(_: HvxVector, _: HvxVector) -> HvxVector;
877    #[link_name = "llvm.hexagon.V6.vrounduwuh.128B"]
878    fn vrounduwuh(_: HvxVector, _: HvxVector) -> HvxVector;
879    #[link_name = "llvm.hexagon.V6.vroundwh.128B"]
880    fn vroundwh(_: HvxVector, _: HvxVector) -> HvxVector;
881    #[link_name = "llvm.hexagon.V6.vroundwuh.128B"]
882    fn vroundwuh(_: HvxVector, _: HvxVector) -> HvxVector;
883    #[link_name = "llvm.hexagon.V6.vrsadubi.128B"]
884    fn vrsadubi(_: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair;
885    #[link_name = "llvm.hexagon.V6.vrsadubi.acc.128B"]
886    fn vrsadubi_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair;
887    #[link_name = "llvm.hexagon.V6.vsatdw.128B"]
888    fn vsatdw(_: HvxVector, _: HvxVector) -> HvxVector;
889    #[link_name = "llvm.hexagon.V6.vsathub.128B"]
890    fn vsathub(_: HvxVector, _: HvxVector) -> HvxVector;
891    #[link_name = "llvm.hexagon.V6.vsatuwuh.128B"]
892    fn vsatuwuh(_: HvxVector, _: HvxVector) -> HvxVector;
893    #[link_name = "llvm.hexagon.V6.vsatwh.128B"]
894    fn vsatwh(_: HvxVector, _: HvxVector) -> HvxVector;
895    #[link_name = "llvm.hexagon.V6.vsb.128B"]
896    fn vsb(_: HvxVector) -> HvxVectorPair;
897    #[link_name = "llvm.hexagon.V6.vscattermh.128B"]
898    fn vscattermh(_: i32, _: i32, _: HvxVector, _: HvxVector) -> ();
899    #[link_name = "llvm.hexagon.V6.vscattermh.add.128B"]
900    fn vscattermh_add(_: i32, _: i32, _: HvxVector, _: HvxVector) -> ();
901    #[link_name = "llvm.hexagon.V6.vscattermhq.128B"]
902    fn vscattermhq(_: HvxVector, _: i32, _: i32, _: HvxVector, _: HvxVector) -> ();
903    #[link_name = "llvm.hexagon.V6.vscattermhw.128B"]
904    fn vscattermhw(_: i32, _: i32, _: HvxVectorPair, _: HvxVector) -> ();
905    #[link_name = "llvm.hexagon.V6.vscattermhw.add.128B"]
906    fn vscattermhw_add(_: i32, _: i32, _: HvxVectorPair, _: HvxVector) -> ();
907    #[link_name = "llvm.hexagon.V6.vscattermhwq.128B"]
908    fn vscattermhwq(_: HvxVector, _: i32, _: i32, _: HvxVectorPair, _: HvxVector) -> ();
909    #[link_name = "llvm.hexagon.V6.vscattermw.128B"]
910    fn vscattermw(_: i32, _: i32, _: HvxVector, _: HvxVector) -> ();
911    #[link_name = "llvm.hexagon.V6.vscattermw.add.128B"]
912    fn vscattermw_add(_: i32, _: i32, _: HvxVector, _: HvxVector) -> ();
913    #[link_name = "llvm.hexagon.V6.vscattermwq.128B"]
914    fn vscattermwq(_: HvxVector, _: i32, _: i32, _: HvxVector, _: HvxVector) -> ();
915    #[link_name = "llvm.hexagon.V6.vsh.128B"]
916    fn vsh(_: HvxVector) -> HvxVectorPair;
917    #[link_name = "llvm.hexagon.V6.vshufeh.128B"]
918    fn vshufeh(_: HvxVector, _: HvxVector) -> HvxVector;
919    #[link_name = "llvm.hexagon.V6.vshuffb.128B"]
920    fn vshuffb(_: HvxVector) -> HvxVector;
921    #[link_name = "llvm.hexagon.V6.vshuffeb.128B"]
922    fn vshuffeb(_: HvxVector, _: HvxVector) -> HvxVector;
923    #[link_name = "llvm.hexagon.V6.vshuffh.128B"]
924    fn vshuffh(_: HvxVector) -> HvxVector;
925    #[link_name = "llvm.hexagon.V6.vshuffob.128B"]
926    fn vshuffob(_: HvxVector, _: HvxVector) -> HvxVector;
927    #[link_name = "llvm.hexagon.V6.vshuffvdd.128B"]
928    fn vshuffvdd(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair;
929    #[link_name = "llvm.hexagon.V6.vshufoeb.128B"]
930    fn vshufoeb(_: HvxVector, _: HvxVector) -> HvxVectorPair;
931    #[link_name = "llvm.hexagon.V6.vshufoeh.128B"]
932    fn vshufoeh(_: HvxVector, _: HvxVector) -> HvxVectorPair;
933    #[link_name = "llvm.hexagon.V6.vshufoh.128B"]
934    fn vshufoh(_: HvxVector, _: HvxVector) -> HvxVector;
935    #[link_name = "llvm.hexagon.V6.vsub.hf.128B"]
936    fn vsub_hf(_: HvxVector, _: HvxVector) -> HvxVector;
937    #[link_name = "llvm.hexagon.V6.vsub.hf.hf.128B"]
938    fn vsub_hf_hf(_: HvxVector, _: HvxVector) -> HvxVector;
939    #[link_name = "llvm.hexagon.V6.vsub.qf16.128B"]
940    fn vsub_qf16(_: HvxVector, _: HvxVector) -> HvxVector;
941    #[link_name = "llvm.hexagon.V6.vsub.qf16.mix.128B"]
942    fn vsub_qf16_mix(_: HvxVector, _: HvxVector) -> HvxVector;
943    #[link_name = "llvm.hexagon.V6.vsub.qf32.128B"]
944    fn vsub_qf32(_: HvxVector, _: HvxVector) -> HvxVector;
945    #[link_name = "llvm.hexagon.V6.vsub.qf32.mix.128B"]
946    fn vsub_qf32_mix(_: HvxVector, _: HvxVector) -> HvxVector;
947    #[link_name = "llvm.hexagon.V6.vsub.sf.128B"]
948    fn vsub_sf(_: HvxVector, _: HvxVector) -> HvxVector;
949    #[link_name = "llvm.hexagon.V6.vsub.sf.hf.128B"]
950    fn vsub_sf_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair;
951    #[link_name = "llvm.hexagon.V6.vsub.sf.sf.128B"]
952    fn vsub_sf_sf(_: HvxVector, _: HvxVector) -> HvxVector;
953    #[link_name = "llvm.hexagon.V6.vsubb.128B"]
954    fn vsubb(_: HvxVector, _: HvxVector) -> HvxVector;
955    #[link_name = "llvm.hexagon.V6.vsubb.dv.128B"]
956    fn vsubb_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
957    #[link_name = "llvm.hexagon.V6.vsubbnq.128B"]
958    fn vsubbnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
959    #[link_name = "llvm.hexagon.V6.vsubbq.128B"]
960    fn vsubbq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
961    #[link_name = "llvm.hexagon.V6.vsubbsat.128B"]
962    fn vsubbsat(_: HvxVector, _: HvxVector) -> HvxVector;
963    #[link_name = "llvm.hexagon.V6.vsubbsat.dv.128B"]
964    fn vsubbsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
965    #[link_name = "llvm.hexagon.V6.vsubh.128B"]
966    fn vsubh(_: HvxVector, _: HvxVector) -> HvxVector;
967    #[link_name = "llvm.hexagon.V6.vsubh.dv.128B"]
968    fn vsubh_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
969    #[link_name = "llvm.hexagon.V6.vsubhnq.128B"]
970    fn vsubhnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
971    #[link_name = "llvm.hexagon.V6.vsubhq.128B"]
972    fn vsubhq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
973    #[link_name = "llvm.hexagon.V6.vsubhsat.128B"]
974    fn vsubhsat(_: HvxVector, _: HvxVector) -> HvxVector;
975    #[link_name = "llvm.hexagon.V6.vsubhsat.dv.128B"]
976    fn vsubhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
977    #[link_name = "llvm.hexagon.V6.vsubhw.128B"]
978    fn vsubhw(_: HvxVector, _: HvxVector) -> HvxVectorPair;
979    #[link_name = "llvm.hexagon.V6.vsububh.128B"]
980    fn vsububh(_: HvxVector, _: HvxVector) -> HvxVectorPair;
981    #[link_name = "llvm.hexagon.V6.vsububsat.128B"]
982    fn vsububsat(_: HvxVector, _: HvxVector) -> HvxVector;
983    #[link_name = "llvm.hexagon.V6.vsububsat.dv.128B"]
984    fn vsububsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
985    #[link_name = "llvm.hexagon.V6.vsubububb.sat.128B"]
986    fn vsubububb_sat(_: HvxVector, _: HvxVector) -> HvxVector;
987    #[link_name = "llvm.hexagon.V6.vsubuhsat.128B"]
988    fn vsubuhsat(_: HvxVector, _: HvxVector) -> HvxVector;
989    #[link_name = "llvm.hexagon.V6.vsubuhsat.dv.128B"]
990    fn vsubuhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
991    #[link_name = "llvm.hexagon.V6.vsubuhw.128B"]
992    fn vsubuhw(_: HvxVector, _: HvxVector) -> HvxVectorPair;
993    #[link_name = "llvm.hexagon.V6.vsubuwsat.128B"]
994    fn vsubuwsat(_: HvxVector, _: HvxVector) -> HvxVector;
995    #[link_name = "llvm.hexagon.V6.vsubuwsat.dv.128B"]
996    fn vsubuwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
997    #[link_name = "llvm.hexagon.V6.vsubw.128B"]
998    fn vsubw(_: HvxVector, _: HvxVector) -> HvxVector;
999    #[link_name = "llvm.hexagon.V6.vsubw.dv.128B"]
1000    fn vsubw_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
1001    #[link_name = "llvm.hexagon.V6.vsubwnq.128B"]
1002    fn vsubwnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
1003    #[link_name = "llvm.hexagon.V6.vsubwq.128B"]
1004    fn vsubwq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
1005    #[link_name = "llvm.hexagon.V6.vsubwsat.128B"]
1006    fn vsubwsat(_: HvxVector, _: HvxVector) -> HvxVector;
1007    #[link_name = "llvm.hexagon.V6.vsubwsat.dv.128B"]
1008    fn vsubwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
1009    #[link_name = "llvm.hexagon.V6.vswap.128B"]
1010    fn vswap(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVectorPair;
1011    #[link_name = "llvm.hexagon.V6.vtmpyb.128B"]
1012    fn vtmpyb(_: HvxVectorPair, _: i32) -> HvxVectorPair;
1013    #[link_name = "llvm.hexagon.V6.vtmpyb.acc.128B"]
1014    fn vtmpyb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
1015    #[link_name = "llvm.hexagon.V6.vtmpybus.128B"]
1016    fn vtmpybus(_: HvxVectorPair, _: i32) -> HvxVectorPair;
1017    #[link_name = "llvm.hexagon.V6.vtmpybus.acc.128B"]
1018    fn vtmpybus_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
1019    #[link_name = "llvm.hexagon.V6.vtmpyhb.128B"]
1020    fn vtmpyhb(_: HvxVectorPair, _: i32) -> HvxVectorPair;
1021    #[link_name = "llvm.hexagon.V6.vtmpyhb.acc.128B"]
1022    fn vtmpyhb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
1023    #[link_name = "llvm.hexagon.V6.vunpackb.128B"]
1024    fn vunpackb(_: HvxVector) -> HvxVectorPair;
1025    #[link_name = "llvm.hexagon.V6.vunpackh.128B"]
1026    fn vunpackh(_: HvxVector) -> HvxVectorPair;
1027    #[link_name = "llvm.hexagon.V6.vunpackob.128B"]
1028    fn vunpackob(_: HvxVectorPair, _: HvxVector) -> HvxVectorPair;
1029    #[link_name = "llvm.hexagon.V6.vunpackoh.128B"]
1030    fn vunpackoh(_: HvxVectorPair, _: HvxVector) -> HvxVectorPair;
1031    #[link_name = "llvm.hexagon.V6.vunpackub.128B"]
1032    fn vunpackub(_: HvxVector) -> HvxVectorPair;
1033    #[link_name = "llvm.hexagon.V6.vunpackuh.128B"]
1034    fn vunpackuh(_: HvxVector) -> HvxVectorPair;
1035    #[link_name = "llvm.hexagon.V6.vxor.128B"]
1036    fn vxor(_: HvxVector, _: HvxVector) -> HvxVector;
1037    #[link_name = "llvm.hexagon.V6.vzb.128B"]
1038    fn vzb(_: HvxVector) -> HvxVectorPair;
1039    #[link_name = "llvm.hexagon.V6.vzh.128B"]
1040    fn vzh(_: HvxVector) -> HvxVectorPair;
1041}
1042
1043/// `Rd32=vextract(Vu32,Rs32)`
1044///
1045/// Instruction Type: LD
1046/// Execution Slots: SLOT0
1047#[inline]
1048#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1049#[cfg_attr(test, assert_instr(extractw))]
1050#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1051pub unsafe fn Q6_R_vextract_VR(vu: HvxVector, rs: i32) -> i32 {
1052    extractw(vu, rs)
1053}
1054
1055/// `Vd32=hi(Vss32)`
1056///
1057/// Instruction Type: CVI_VA
1058/// Execution Slots: SLOT0123
1059#[inline]
1060#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1061#[cfg_attr(test, assert_instr(hi))]
1062#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1063pub unsafe fn Q6_V_hi_W(vss: HvxVectorPair) -> HvxVector {
1064    hi(vss)
1065}
1066
1067/// `Vd32=lo(Vss32)`
1068///
1069/// Instruction Type: CVI_VA
1070/// Execution Slots: SLOT0123
1071#[inline]
1072#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1073#[cfg_attr(test, assert_instr(lo))]
1074#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1075pub unsafe fn Q6_V_lo_W(vss: HvxVectorPair) -> HvxVector {
1076    lo(vss)
1077}
1078
1079/// `Vd32=vsplat(Rt32)`
1080///
1081/// Instruction Type: CVI_VX_LATE
1082/// Execution Slots: SLOT23
1083#[inline]
1084#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1085#[cfg_attr(test, assert_instr(lvsplatw))]
1086#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1087pub unsafe fn Q6_V_vsplat_R(rt: i32) -> HvxVector {
1088    lvsplatw(rt)
1089}
1090
1091/// `Vd32.uh=vabsdiff(Vu32.h,Vv32.h)`
1092///
1093/// Instruction Type: CVI_VX
1094/// Execution Slots: SLOT23
1095#[inline]
1096#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1097#[cfg_attr(test, assert_instr(vabsdiffh))]
1098#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1099pub unsafe fn Q6_Vuh_vabsdiff_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
1100    vabsdiffh(vu, vv)
1101}
1102
1103/// `Vd32.ub=vabsdiff(Vu32.ub,Vv32.ub)`
1104///
1105/// Instruction Type: CVI_VX
1106/// Execution Slots: SLOT23
1107#[inline]
1108#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1109#[cfg_attr(test, assert_instr(vabsdiffub))]
1110#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1111pub unsafe fn Q6_Vub_vabsdiff_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector {
1112    vabsdiffub(vu, vv)
1113}
1114
1115/// `Vd32.uh=vabsdiff(Vu32.uh,Vv32.uh)`
1116///
1117/// Instruction Type: CVI_VX
1118/// Execution Slots: SLOT23
1119#[inline]
1120#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1121#[cfg_attr(test, assert_instr(vabsdiffuh))]
1122#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1123pub unsafe fn Q6_Vuh_vabsdiff_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
1124    vabsdiffuh(vu, vv)
1125}
1126
1127/// `Vd32.uw=vabsdiff(Vu32.w,Vv32.w)`
1128///
1129/// Instruction Type: CVI_VX
1130/// Execution Slots: SLOT23
1131#[inline]
1132#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1133#[cfg_attr(test, assert_instr(vabsdiffw))]
1134#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1135pub unsafe fn Q6_Vuw_vabsdiff_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
1136    vabsdiffw(vu, vv)
1137}
1138
1139/// `Vd32.h=vabs(Vu32.h)`
1140///
1141/// Instruction Type: CVI_VA
1142/// Execution Slots: SLOT0123
1143#[inline]
1144#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1145#[cfg_attr(test, assert_instr(vabsh))]
1146#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1147pub unsafe fn Q6_Vh_vabs_Vh(vu: HvxVector) -> HvxVector {
1148    vabsh(vu)
1149}
1150
1151/// `Vd32.h=vabs(Vu32.h):sat`
1152///
1153/// Instruction Type: CVI_VA
1154/// Execution Slots: SLOT0123
1155#[inline]
1156#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1157#[cfg_attr(test, assert_instr(vabsh_sat))]
1158#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1159pub unsafe fn Q6_Vh_vabs_Vh_sat(vu: HvxVector) -> HvxVector {
1160    vabsh_sat(vu)
1161}
1162
1163/// `Vd32.w=vabs(Vu32.w)`
1164///
1165/// Instruction Type: CVI_VA
1166/// Execution Slots: SLOT0123
1167#[inline]
1168#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1169#[cfg_attr(test, assert_instr(vabsw))]
1170#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1171pub unsafe fn Q6_Vw_vabs_Vw(vu: HvxVector) -> HvxVector {
1172    vabsw(vu)
1173}
1174
1175/// `Vd32.w=vabs(Vu32.w):sat`
1176///
1177/// Instruction Type: CVI_VA
1178/// Execution Slots: SLOT0123
1179#[inline]
1180#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1181#[cfg_attr(test, assert_instr(vabsw_sat))]
1182#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1183pub unsafe fn Q6_Vw_vabs_Vw_sat(vu: HvxVector) -> HvxVector {
1184    vabsw_sat(vu)
1185}
1186
1187/// `Vd32.b=vadd(Vu32.b,Vv32.b)`
1188///
1189/// Instruction Type: CVI_VA
1190/// Execution Slots: SLOT0123
1191#[inline]
1192#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1193#[cfg_attr(test, assert_instr(vaddb))]
1194#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1195pub unsafe fn Q6_Vb_vadd_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
1196    vaddb(vu, vv)
1197}
1198
1199/// `Vdd32.b=vadd(Vuu32.b,Vvv32.b)`
1200///
1201/// Instruction Type: CVI_VA_DV
1202/// Execution Slots: SLOT0123
1203#[inline]
1204#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1205#[cfg_attr(test, assert_instr(vaddb_dv))]
1206#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1207pub unsafe fn Q6_Wb_vadd_WbWb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
1208    vaddb_dv(vuu, vvv)
1209}
1210
1211/// `Vd32.h=vadd(Vu32.h,Vv32.h)`
1212///
1213/// Instruction Type: CVI_VA
1214/// Execution Slots: SLOT0123
1215#[inline]
1216#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1217#[cfg_attr(test, assert_instr(vaddh))]
1218#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1219pub unsafe fn Q6_Vh_vadd_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
1220    vaddh(vu, vv)
1221}
1222
1223/// `Vdd32.h=vadd(Vuu32.h,Vvv32.h)`
1224///
1225/// Instruction Type: CVI_VA_DV
1226/// Execution Slots: SLOT0123
1227#[inline]
1228#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1229#[cfg_attr(test, assert_instr(vaddh_dv))]
1230#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1231pub unsafe fn Q6_Wh_vadd_WhWh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
1232    vaddh_dv(vuu, vvv)
1233}
1234
1235/// `Vd32.h=vadd(Vu32.h,Vv32.h):sat`
1236///
1237/// Instruction Type: CVI_VA
1238/// Execution Slots: SLOT0123
1239#[inline]
1240#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1241#[cfg_attr(test, assert_instr(vaddhsat))]
1242#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1243pub unsafe fn Q6_Vh_vadd_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
1244    vaddhsat(vu, vv)
1245}
1246
1247/// `Vdd32.h=vadd(Vuu32.h,Vvv32.h):sat`
1248///
1249/// Instruction Type: CVI_VA_DV
1250/// Execution Slots: SLOT0123
1251#[inline]
1252#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1253#[cfg_attr(test, assert_instr(vaddhsat_dv))]
1254#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1255pub unsafe fn Q6_Wh_vadd_WhWh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
1256    vaddhsat_dv(vuu, vvv)
1257}
1258
1259/// `Vdd32.w=vadd(Vu32.h,Vv32.h)`
1260///
1261/// Instruction Type: CVI_VX_DV
1262/// Execution Slots: SLOT23
1263#[inline]
1264#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1265#[cfg_attr(test, assert_instr(vaddhw))]
1266#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1267pub unsafe fn Q6_Ww_vadd_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
1268    vaddhw(vu, vv)
1269}
1270
1271/// `Vdd32.h=vadd(Vu32.ub,Vv32.ub)`
1272///
1273/// Instruction Type: CVI_VX_DV
1274/// Execution Slots: SLOT23
1275#[inline]
1276#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1277#[cfg_attr(test, assert_instr(vaddubh))]
1278#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1279pub unsafe fn Q6_Wh_vadd_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
1280    vaddubh(vu, vv)
1281}
1282
1283/// `Vd32.ub=vadd(Vu32.ub,Vv32.ub):sat`
1284///
1285/// Instruction Type: CVI_VA
1286/// Execution Slots: SLOT0123
1287#[inline]
1288#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1289#[cfg_attr(test, assert_instr(vaddubsat))]
1290#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1291pub unsafe fn Q6_Vub_vadd_VubVub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
1292    vaddubsat(vu, vv)
1293}
1294
1295/// `Vdd32.ub=vadd(Vuu32.ub,Vvv32.ub):sat`
1296///
1297/// Instruction Type: CVI_VA_DV
1298/// Execution Slots: SLOT0123
1299#[inline]
1300#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1301#[cfg_attr(test, assert_instr(vaddubsat_dv))]
1302#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1303pub unsafe fn Q6_Wub_vadd_WubWub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
1304    vaddubsat_dv(vuu, vvv)
1305}
1306
1307/// `Vd32.uh=vadd(Vu32.uh,Vv32.uh):sat`
1308///
1309/// Instruction Type: CVI_VA
1310/// Execution Slots: SLOT0123
1311#[inline]
1312#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1313#[cfg_attr(test, assert_instr(vadduhsat))]
1314#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1315pub unsafe fn Q6_Vuh_vadd_VuhVuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
1316    vadduhsat(vu, vv)
1317}
1318
1319/// `Vdd32.uh=vadd(Vuu32.uh,Vvv32.uh):sat`
1320///
1321/// Instruction Type: CVI_VA_DV
1322/// Execution Slots: SLOT0123
1323#[inline]
1324#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1325#[cfg_attr(test, assert_instr(vadduhsat_dv))]
1326#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1327pub unsafe fn Q6_Wuh_vadd_WuhWuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
1328    vadduhsat_dv(vuu, vvv)
1329}
1330
1331/// `Vdd32.w=vadd(Vu32.uh,Vv32.uh)`
1332///
1333/// Instruction Type: CVI_VX_DV
1334/// Execution Slots: SLOT23
1335#[inline]
1336#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1337#[cfg_attr(test, assert_instr(vadduhw))]
1338#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1339pub unsafe fn Q6_Ww_vadd_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
1340    vadduhw(vu, vv)
1341}
1342
1343/// `Vd32.w=vadd(Vu32.w,Vv32.w)`
1344///
1345/// Instruction Type: CVI_VA
1346/// Execution Slots: SLOT0123
1347#[inline]
1348#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1349#[cfg_attr(test, assert_instr(vaddw))]
1350#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1351pub unsafe fn Q6_Vw_vadd_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
1352    simd_add(vu, vv)
1353}
1354
1355/// `Vdd32.w=vadd(Vuu32.w,Vvv32.w)`
1356///
1357/// Instruction Type: CVI_VA_DV
1358/// Execution Slots: SLOT0123
1359#[inline]
1360#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1361#[cfg_attr(test, assert_instr(vaddw_dv))]
1362#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1363pub unsafe fn Q6_Ww_vadd_WwWw(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
1364    vaddw_dv(vuu, vvv)
1365}
1366
1367/// `Vd32.w=vadd(Vu32.w,Vv32.w):sat`
1368///
1369/// Instruction Type: CVI_VA
1370/// Execution Slots: SLOT0123
1371#[inline]
1372#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1373#[cfg_attr(test, assert_instr(vaddwsat))]
1374#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1375pub unsafe fn Q6_Vw_vadd_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
1376    vaddwsat(vu, vv)
1377}
1378
1379/// `Vdd32.w=vadd(Vuu32.w,Vvv32.w):sat`
1380///
1381/// Instruction Type: CVI_VA_DV
1382/// Execution Slots: SLOT0123
1383#[inline]
1384#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1385#[cfg_attr(test, assert_instr(vaddwsat_dv))]
1386#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1387pub unsafe fn Q6_Ww_vadd_WwWw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
1388    vaddwsat_dv(vuu, vvv)
1389}
1390
1391/// `Vd32=valign(Vu32,Vv32,Rt8)`
1392///
1393/// Instruction Type: CVI_VP
1394/// Execution Slots: SLOT0123
1395#[inline]
1396#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1397#[cfg_attr(test, assert_instr(valignb))]
1398#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1399pub unsafe fn Q6_V_valign_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
1400    valignb(vu, vv, rt)
1401}
1402
1403/// `Vd32=valign(Vu32,Vv32,#u3)`
1404///
1405/// Instruction Type: CVI_VP
1406/// Execution Slots: SLOT0123
1407#[inline]
1408#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1409#[cfg_attr(test, assert_instr(valignbi))]
1410#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1411pub unsafe fn Q6_V_valign_VVI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector {
1412    valignbi(vu, vv, iu3)
1413}
1414
1415/// `Vd32=vand(Vu32,Vv32)`
1416///
1417/// Instruction Type: CVI_VA
1418/// Execution Slots: SLOT0123
1419#[inline]
1420#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1421#[cfg_attr(test, assert_instr(vand))]
1422#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1423pub unsafe fn Q6_V_vand_VV(vu: HvxVector, vv: HvxVector) -> HvxVector {
1424    simd_and(vu, vv)
1425}
1426
1427/// `Vd32.h=vasl(Vu32.h,Rt32)`
1428///
1429/// Instruction Type: CVI_VS
1430/// Execution Slots: SLOT0123
1431#[inline]
1432#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1433#[cfg_attr(test, assert_instr(vaslh))]
1434#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1435pub unsafe fn Q6_Vh_vasl_VhR(vu: HvxVector, rt: i32) -> HvxVector {
1436    vaslh(vu, rt)
1437}
1438
1439/// `Vd32.h=vasl(Vu32.h,Vv32.h)`
1440///
1441/// Instruction Type: CVI_VS
1442/// Execution Slots: SLOT0123
1443#[inline]
1444#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1445#[cfg_attr(test, assert_instr(vaslhv))]
1446#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1447pub unsafe fn Q6_Vh_vasl_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
1448    vaslhv(vu, vv)
1449}
1450
1451/// `Vd32.w=vasl(Vu32.w,Rt32)`
1452///
1453/// Instruction Type: CVI_VS
1454/// Execution Slots: SLOT0123
1455#[inline]
1456#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1457#[cfg_attr(test, assert_instr(vaslw))]
1458#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1459pub unsafe fn Q6_Vw_vasl_VwR(vu: HvxVector, rt: i32) -> HvxVector {
1460    vaslw(vu, rt)
1461}
1462
1463/// `Vx32.w+=vasl(Vu32.w,Rt32)`
1464///
1465/// Instruction Type: CVI_VS
1466/// Execution Slots: SLOT0123
1467#[inline]
1468#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1469#[cfg_attr(test, assert_instr(vaslw_acc))]
1470#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1471pub unsafe fn Q6_Vw_vaslacc_VwVwR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
1472    vaslw_acc(vx, vu, rt)
1473}
1474
1475/// `Vd32.w=vasl(Vu32.w,Vv32.w)`
1476///
1477/// Instruction Type: CVI_VS
1478/// Execution Slots: SLOT0123
1479#[inline]
1480#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1481#[cfg_attr(test, assert_instr(vaslwv))]
1482#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1483pub unsafe fn Q6_Vw_vasl_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
1484    vaslwv(vu, vv)
1485}
1486
1487/// `Vd32.h=vasr(Vu32.h,Rt32)`
1488///
1489/// Instruction Type: CVI_VS
1490/// Execution Slots: SLOT0123
1491#[inline]
1492#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1493#[cfg_attr(test, assert_instr(vasrh))]
1494#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1495pub unsafe fn Q6_Vh_vasr_VhR(vu: HvxVector, rt: i32) -> HvxVector {
1496    vasrh(vu, rt)
1497}
1498
1499/// `Vd32.b=vasr(Vu32.h,Vv32.h,Rt8):rnd:sat`
1500///
1501/// Instruction Type: CVI_VS
1502/// Execution Slots: SLOT0123
1503#[inline]
1504#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1505#[cfg_attr(test, assert_instr(vasrhbrndsat))]
1506#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1507pub unsafe fn Q6_Vb_vasr_VhVhR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
1508    vasrhbrndsat(vu, vv, rt)
1509}
1510
1511/// `Vd32.ub=vasr(Vu32.h,Vv32.h,Rt8):rnd:sat`
1512///
1513/// Instruction Type: CVI_VS
1514/// Execution Slots: SLOT0123
1515#[inline]
1516#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1517#[cfg_attr(test, assert_instr(vasrhubrndsat))]
1518#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1519pub unsafe fn Q6_Vub_vasr_VhVhR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
1520    vasrhubrndsat(vu, vv, rt)
1521}
1522
1523/// `Vd32.ub=vasr(Vu32.h,Vv32.h,Rt8):sat`
1524///
1525/// Instruction Type: CVI_VS
1526/// Execution Slots: SLOT0123
1527#[inline]
1528#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1529#[cfg_attr(test, assert_instr(vasrhubsat))]
1530#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1531pub unsafe fn Q6_Vub_vasr_VhVhR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
1532    vasrhubsat(vu, vv, rt)
1533}
1534
1535/// `Vd32.h=vasr(Vu32.h,Vv32.h)`
1536///
1537/// Instruction Type: CVI_VS
1538/// Execution Slots: SLOT0123
1539#[inline]
1540#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1541#[cfg_attr(test, assert_instr(vasrhv))]
1542#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1543pub unsafe fn Q6_Vh_vasr_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
1544    vasrhv(vu, vv)
1545}
1546
1547/// `Vd32.w=vasr(Vu32.w,Rt32)`
1548///
1549/// Instruction Type: CVI_VS
1550/// Execution Slots: SLOT0123
1551#[inline]
1552#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1553#[cfg_attr(test, assert_instr(vasrw))]
1554#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1555pub unsafe fn Q6_Vw_vasr_VwR(vu: HvxVector, rt: i32) -> HvxVector {
1556    vasrw(vu, rt)
1557}
1558
1559/// `Vx32.w+=vasr(Vu32.w,Rt32)`
1560///
1561/// Instruction Type: CVI_VS
1562/// Execution Slots: SLOT0123
1563#[inline]
1564#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1565#[cfg_attr(test, assert_instr(vasrw_acc))]
1566#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1567pub unsafe fn Q6_Vw_vasracc_VwVwR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
1568    vasrw_acc(vx, vu, rt)
1569}
1570
1571/// `Vd32.h=vasr(Vu32.w,Vv32.w,Rt8)`
1572///
1573/// Instruction Type: CVI_VS
1574/// Execution Slots: SLOT0123
1575#[inline]
1576#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1577#[cfg_attr(test, assert_instr(vasrwh))]
1578#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1579pub unsafe fn Q6_Vh_vasr_VwVwR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
1580    vasrwh(vu, vv, rt)
1581}
1582
1583/// `Vd32.h=vasr(Vu32.w,Vv32.w,Rt8):rnd:sat`
1584///
1585/// Instruction Type: CVI_VS
1586/// Execution Slots: SLOT0123
1587#[inline]
1588#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1589#[cfg_attr(test, assert_instr(vasrwhrndsat))]
1590#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1591pub unsafe fn Q6_Vh_vasr_VwVwR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
1592    vasrwhrndsat(vu, vv, rt)
1593}
1594
1595/// `Vd32.h=vasr(Vu32.w,Vv32.w,Rt8):sat`
1596///
1597/// Instruction Type: CVI_VS
1598/// Execution Slots: SLOT0123
1599#[inline]
1600#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1601#[cfg_attr(test, assert_instr(vasrwhsat))]
1602#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1603pub unsafe fn Q6_Vh_vasr_VwVwR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
1604    vasrwhsat(vu, vv, rt)
1605}
1606
1607/// `Vd32.uh=vasr(Vu32.w,Vv32.w,Rt8):sat`
1608///
1609/// Instruction Type: CVI_VS
1610/// Execution Slots: SLOT0123
1611#[inline]
1612#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1613#[cfg_attr(test, assert_instr(vasrwuhsat))]
1614#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1615pub unsafe fn Q6_Vuh_vasr_VwVwR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
1616    vasrwuhsat(vu, vv, rt)
1617}
1618
1619/// `Vd32.w=vasr(Vu32.w,Vv32.w)`
1620///
1621/// Instruction Type: CVI_VS
1622/// Execution Slots: SLOT0123
1623#[inline]
1624#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1625#[cfg_attr(test, assert_instr(vasrwv))]
1626#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1627pub unsafe fn Q6_Vw_vasr_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
1628    vasrwv(vu, vv)
1629}
1630
1631/// `Vd32=Vu32`
1632///
1633/// Instruction Type: CVI_VA
1634/// Execution Slots: SLOT0123
1635#[inline]
1636#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1637#[cfg_attr(test, assert_instr(vassign))]
1638#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1639pub unsafe fn Q6_V_equals_V(vu: HvxVector) -> HvxVector {
1640    vassign(vu)
1641}
1642
1643/// `Vdd32=Vuu32`
1644///
1645/// Instruction Type: CVI_VA_DV
1646/// Execution Slots: SLOT0123
1647#[inline]
1648#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1649#[cfg_attr(test, assert_instr(vassignp))]
1650#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1651pub unsafe fn Q6_W_equals_W(vuu: HvxVectorPair) -> HvxVectorPair {
1652    vassignp(vuu)
1653}
1654
1655/// `Vd32.h=vavg(Vu32.h,Vv32.h)`
1656///
1657/// Instruction Type: CVI_VA
1658/// Execution Slots: SLOT0123
1659#[inline]
1660#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1661#[cfg_attr(test, assert_instr(vavgh))]
1662#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1663pub unsafe fn Q6_Vh_vavg_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
1664    vavgh(vu, vv)
1665}
1666
1667/// `Vd32.h=vavg(Vu32.h,Vv32.h):rnd`
1668///
1669/// Instruction Type: CVI_VA
1670/// Execution Slots: SLOT0123
1671#[inline]
1672#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1673#[cfg_attr(test, assert_instr(vavghrnd))]
1674#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1675pub unsafe fn Q6_Vh_vavg_VhVh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
1676    vavghrnd(vu, vv)
1677}
1678
1679/// `Vd32.ub=vavg(Vu32.ub,Vv32.ub)`
1680///
1681/// Instruction Type: CVI_VA
1682/// Execution Slots: SLOT0123
1683#[inline]
1684#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1685#[cfg_attr(test, assert_instr(vavgub))]
1686#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1687pub unsafe fn Q6_Vub_vavg_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector {
1688    vavgub(vu, vv)
1689}
1690
1691/// `Vd32.ub=vavg(Vu32.ub,Vv32.ub):rnd`
1692///
1693/// Instruction Type: CVI_VA
1694/// Execution Slots: SLOT0123
1695#[inline]
1696#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1697#[cfg_attr(test, assert_instr(vavgubrnd))]
1698#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1699pub unsafe fn Q6_Vub_vavg_VubVub_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
1700    vavgubrnd(vu, vv)
1701}
1702
1703/// `Vd32.uh=vavg(Vu32.uh,Vv32.uh)`
1704///
1705/// Instruction Type: CVI_VA
1706/// Execution Slots: SLOT0123
1707#[inline]
1708#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1709#[cfg_attr(test, assert_instr(vavguh))]
1710#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1711pub unsafe fn Q6_Vuh_vavg_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
1712    vavguh(vu, vv)
1713}
1714
1715/// `Vd32.uh=vavg(Vu32.uh,Vv32.uh):rnd`
1716///
1717/// Instruction Type: CVI_VA
1718/// Execution Slots: SLOT0123
1719#[inline]
1720#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1721#[cfg_attr(test, assert_instr(vavguhrnd))]
1722#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1723pub unsafe fn Q6_Vuh_vavg_VuhVuh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
1724    vavguhrnd(vu, vv)
1725}
1726
1727/// `Vd32.w=vavg(Vu32.w,Vv32.w)`
1728///
1729/// Instruction Type: CVI_VA
1730/// Execution Slots: SLOT0123
1731#[inline]
1732#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1733#[cfg_attr(test, assert_instr(vavgw))]
1734#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1735pub unsafe fn Q6_Vw_vavg_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
1736    vavgw(vu, vv)
1737}
1738
1739/// `Vd32.w=vavg(Vu32.w,Vv32.w):rnd`
1740///
1741/// Instruction Type: CVI_VA
1742/// Execution Slots: SLOT0123
1743#[inline]
1744#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1745#[cfg_attr(test, assert_instr(vavgwrnd))]
1746#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1747pub unsafe fn Q6_Vw_vavg_VwVw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
1748    vavgwrnd(vu, vv)
1749}
1750
1751/// `Vd32.uh=vcl0(Vu32.uh)`
1752///
1753/// Instruction Type: CVI_VS
1754/// Execution Slots: SLOT0123
1755#[inline]
1756#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1757#[cfg_attr(test, assert_instr(vcl0h))]
1758#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1759pub unsafe fn Q6_Vuh_vcl0_Vuh(vu: HvxVector) -> HvxVector {
1760    vcl0h(vu)
1761}
1762
1763/// `Vd32.uw=vcl0(Vu32.uw)`
1764///
1765/// Instruction Type: CVI_VS
1766/// Execution Slots: SLOT0123
1767#[inline]
1768#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1769#[cfg_attr(test, assert_instr(vcl0w))]
1770#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1771pub unsafe fn Q6_Vuw_vcl0_Vuw(vu: HvxVector) -> HvxVector {
1772    vcl0w(vu)
1773}
1774
1775/// `Vdd32=vcombine(Vu32,Vv32)`
1776///
1777/// Instruction Type: CVI_VA_DV
1778/// Execution Slots: SLOT0123
1779#[inline]
1780#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1781#[cfg_attr(test, assert_instr(vcombine))]
1782#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1783pub unsafe fn Q6_W_vcombine_VV(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
1784    vcombine(vu, vv)
1785}
1786
1787/// `Vd32=#0`
1788///
1789/// Instruction Type: CVI_VA
1790/// Execution Slots: SLOT0123
1791#[inline]
1792#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1793#[cfg_attr(test, assert_instr(vd0))]
1794#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1795pub unsafe fn Q6_V_vzero() -> HvxVector {
1796    vd0()
1797}
1798
1799/// `Vd32.b=vdeal(Vu32.b)`
1800///
1801/// Instruction Type: CVI_VP
1802/// Execution Slots: SLOT0123
1803#[inline]
1804#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1805#[cfg_attr(test, assert_instr(vdealb))]
1806#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1807pub unsafe fn Q6_Vb_vdeal_Vb(vu: HvxVector) -> HvxVector {
1808    vdealb(vu)
1809}
1810
1811/// `Vd32.b=vdeale(Vu32.b,Vv32.b)`
1812///
1813/// Instruction Type: CVI_VP
1814/// Execution Slots: SLOT0123
1815#[inline]
1816#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1817#[cfg_attr(test, assert_instr(vdealb4w))]
1818#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1819pub unsafe fn Q6_Vb_vdeale_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
1820    vdealb4w(vu, vv)
1821}
1822
1823/// `Vd32.h=vdeal(Vu32.h)`
1824///
1825/// Instruction Type: CVI_VP
1826/// Execution Slots: SLOT0123
1827#[inline]
1828#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1829#[cfg_attr(test, assert_instr(vdealh))]
1830#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1831pub unsafe fn Q6_Vh_vdeal_Vh(vu: HvxVector) -> HvxVector {
1832    vdealh(vu)
1833}
1834
1835/// `Vdd32=vdeal(Vu32,Vv32,Rt8)`
1836///
1837/// Instruction Type: CVI_VP_VS
1838/// Execution Slots: SLOT0123
1839#[inline]
1840#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1841#[cfg_attr(test, assert_instr(vdealvdd))]
1842#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1843pub unsafe fn Q6_W_vdeal_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair {
1844    vdealvdd(vu, vv, rt)
1845}
1846
1847/// `Vd32=vdelta(Vu32,Vv32)`
1848///
1849/// Instruction Type: CVI_VP
1850/// Execution Slots: SLOT0123
1851#[inline]
1852#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1853#[cfg_attr(test, assert_instr(vdelta))]
1854#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1855pub unsafe fn Q6_V_vdelta_VV(vu: HvxVector, vv: HvxVector) -> HvxVector {
1856    vdelta(vu, vv)
1857}
1858
1859/// `Vd32.h=vdmpy(Vu32.ub,Rt32.b)`
1860///
1861/// Instruction Type: CVI_VX
1862/// Execution Slots: SLOT23
1863#[inline]
1864#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1865#[cfg_attr(test, assert_instr(vdmpybus))]
1866#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1867pub unsafe fn Q6_Vh_vdmpy_VubRb(vu: HvxVector, rt: i32) -> HvxVector {
1868    vdmpybus(vu, rt)
1869}
1870
1871/// `Vx32.h+=vdmpy(Vu32.ub,Rt32.b)`
1872///
1873/// Instruction Type: CVI_VX
1874/// Execution Slots: SLOT23
1875#[inline]
1876#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1877#[cfg_attr(test, assert_instr(vdmpybus_acc))]
1878#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1879pub unsafe fn Q6_Vh_vdmpyacc_VhVubRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
1880    vdmpybus_acc(vx, vu, rt)
1881}
1882
1883/// `Vdd32.h=vdmpy(Vuu32.ub,Rt32.b)`
1884///
1885/// Instruction Type: CVI_VX_DV
1886/// Execution Slots: SLOT23
1887#[inline]
1888#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1889#[cfg_attr(test, assert_instr(vdmpybus_dv))]
1890#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1891pub unsafe fn Q6_Wh_vdmpy_WubRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
1892    vdmpybus_dv(vuu, rt)
1893}
1894
1895/// `Vxx32.h+=vdmpy(Vuu32.ub,Rt32.b)`
1896///
1897/// Instruction Type: CVI_VX_DV
1898/// Execution Slots: SLOT23
1899#[inline]
1900#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1901#[cfg_attr(test, assert_instr(vdmpybus_dv_acc))]
1902#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1903pub unsafe fn Q6_Wh_vdmpyacc_WhWubRb(
1904    vxx: HvxVectorPair,
1905    vuu: HvxVectorPair,
1906    rt: i32,
1907) -> HvxVectorPair {
1908    vdmpybus_dv_acc(vxx, vuu, rt)
1909}
1910
1911/// `Vd32.w=vdmpy(Vu32.h,Rt32.b)`
1912///
1913/// Instruction Type: CVI_VX
1914/// Execution Slots: SLOT23
1915#[inline]
1916#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1917#[cfg_attr(test, assert_instr(vdmpyhb))]
1918#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1919pub unsafe fn Q6_Vw_vdmpy_VhRb(vu: HvxVector, rt: i32) -> HvxVector {
1920    vdmpyhb(vu, rt)
1921}
1922
1923/// `Vx32.w+=vdmpy(Vu32.h,Rt32.b)`
1924///
1925/// Instruction Type: CVI_VX
1926/// Execution Slots: SLOT23
1927#[inline]
1928#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1929#[cfg_attr(test, assert_instr(vdmpyhb_acc))]
1930#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1931pub unsafe fn Q6_Vw_vdmpyacc_VwVhRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
1932    vdmpyhb_acc(vx, vu, rt)
1933}
1934
1935/// `Vdd32.w=vdmpy(Vuu32.h,Rt32.b)`
1936///
1937/// Instruction Type: CVI_VX_DV
1938/// Execution Slots: SLOT23
1939#[inline]
1940#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1941#[cfg_attr(test, assert_instr(vdmpyhb_dv))]
1942#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1943pub unsafe fn Q6_Ww_vdmpy_WhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
1944    vdmpyhb_dv(vuu, rt)
1945}
1946
1947/// `Vxx32.w+=vdmpy(Vuu32.h,Rt32.b)`
1948///
1949/// Instruction Type: CVI_VX_DV
1950/// Execution Slots: SLOT23
1951#[inline]
1952#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1953#[cfg_attr(test, assert_instr(vdmpyhb_dv_acc))]
1954#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1955pub unsafe fn Q6_Ww_vdmpyacc_WwWhRb(
1956    vxx: HvxVectorPair,
1957    vuu: HvxVectorPair,
1958    rt: i32,
1959) -> HvxVectorPair {
1960    vdmpyhb_dv_acc(vxx, vuu, rt)
1961}
1962
1963/// `Vd32.w=vdmpy(Vuu32.h,Rt32.h):sat`
1964///
1965/// Instruction Type: CVI_VX_DV
1966/// Execution Slots: SLOT23
1967#[inline]
1968#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1969#[cfg_attr(test, assert_instr(vdmpyhisat))]
1970#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1971pub unsafe fn Q6_Vw_vdmpy_WhRh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector {
1972    vdmpyhisat(vuu, rt)
1973}
1974
1975/// `Vx32.w+=vdmpy(Vuu32.h,Rt32.h):sat`
1976///
1977/// Instruction Type: CVI_VX_DV
1978/// Execution Slots: SLOT23
1979#[inline]
1980#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1981#[cfg_attr(test, assert_instr(vdmpyhisat_acc))]
1982#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1983pub unsafe fn Q6_Vw_vdmpyacc_VwWhRh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i32) -> HvxVector {
1984    vdmpyhisat_acc(vx, vuu, rt)
1985}
1986
1987/// `Vd32.w=vdmpy(Vu32.h,Rt32.h):sat`
1988///
1989/// Instruction Type: CVI_VX
1990/// Execution Slots: SLOT23
1991#[inline]
1992#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
1993#[cfg_attr(test, assert_instr(vdmpyhsat))]
1994#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1995pub unsafe fn Q6_Vw_vdmpy_VhRh_sat(vu: HvxVector, rt: i32) -> HvxVector {
1996    vdmpyhsat(vu, rt)
1997}
1998
1999/// `Vx32.w+=vdmpy(Vu32.h,Rt32.h):sat`
2000///
2001/// Instruction Type: CVI_VX
2002/// Execution Slots: SLOT23
2003#[inline]
2004#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2005#[cfg_attr(test, assert_instr(vdmpyhsat_acc))]
2006#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2007pub unsafe fn Q6_Vw_vdmpyacc_VwVhRh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
2008    vdmpyhsat_acc(vx, vu, rt)
2009}
2010
2011/// `Vd32.w=vdmpy(Vuu32.h,Rt32.uh,#1):sat`
2012///
2013/// Instruction Type: CVI_VX_DV
2014/// Execution Slots: SLOT23
2015#[inline]
2016#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2017#[cfg_attr(test, assert_instr(vdmpyhsuisat))]
2018#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2019pub unsafe fn Q6_Vw_vdmpy_WhRuh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector {
2020    vdmpyhsuisat(vuu, rt)
2021}
2022
2023/// `Vx32.w+=vdmpy(Vuu32.h,Rt32.uh,#1):sat`
2024///
2025/// Instruction Type: CVI_VX_DV
2026/// Execution Slots: SLOT23
2027#[inline]
2028#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2029#[cfg_attr(test, assert_instr(vdmpyhsuisat_acc))]
2030#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2031pub unsafe fn Q6_Vw_vdmpyacc_VwWhRuh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i32) -> HvxVector {
2032    vdmpyhsuisat_acc(vx, vuu, rt)
2033}
2034
2035/// `Vd32.w=vdmpy(Vu32.h,Rt32.uh):sat`
2036///
2037/// Instruction Type: CVI_VX
2038/// Execution Slots: SLOT23
2039#[inline]
2040#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2041#[cfg_attr(test, assert_instr(vdmpyhsusat))]
2042#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2043pub unsafe fn Q6_Vw_vdmpy_VhRuh_sat(vu: HvxVector, rt: i32) -> HvxVector {
2044    vdmpyhsusat(vu, rt)
2045}
2046
2047/// `Vx32.w+=vdmpy(Vu32.h,Rt32.uh):sat`
2048///
2049/// Instruction Type: CVI_VX
2050/// Execution Slots: SLOT23
2051#[inline]
2052#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2053#[cfg_attr(test, assert_instr(vdmpyhsusat_acc))]
2054#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2055pub unsafe fn Q6_Vw_vdmpyacc_VwVhRuh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
2056    vdmpyhsusat_acc(vx, vu, rt)
2057}
2058
2059/// `Vd32.w=vdmpy(Vu32.h,Vv32.h):sat`
2060///
2061/// Instruction Type: CVI_VX
2062/// Execution Slots: SLOT23
2063#[inline]
2064#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2065#[cfg_attr(test, assert_instr(vdmpyhvsat))]
2066#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2067pub unsafe fn Q6_Vw_vdmpy_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
2068    vdmpyhvsat(vu, vv)
2069}
2070
2071/// `Vx32.w+=vdmpy(Vu32.h,Vv32.h):sat`
2072///
2073/// Instruction Type: CVI_VX_DV
2074/// Execution Slots: SLOT23
2075#[inline]
2076#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2077#[cfg_attr(test, assert_instr(vdmpyhvsat_acc))]
2078#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2079pub unsafe fn Q6_Vw_vdmpyacc_VwVhVh_sat(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
2080    vdmpyhvsat_acc(vx, vu, vv)
2081}
2082
2083/// `Vdd32.uw=vdsad(Vuu32.uh,Rt32.uh)`
2084///
2085/// Instruction Type: CVI_VX_DV
2086/// Execution Slots: SLOT23
2087#[inline]
2088#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2089#[cfg_attr(test, assert_instr(vdsaduh))]
2090#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2091pub unsafe fn Q6_Wuw_vdsad_WuhRuh(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
2092    vdsaduh(vuu, rt)
2093}
2094
2095/// `Vxx32.uw+=vdsad(Vuu32.uh,Rt32.uh)`
2096///
2097/// Instruction Type: CVI_VX_DV
2098/// Execution Slots: SLOT23
2099#[inline]
2100#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2101#[cfg_attr(test, assert_instr(vdsaduh_acc))]
2102#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2103pub unsafe fn Q6_Wuw_vdsadacc_WuwWuhRuh(
2104    vxx: HvxVectorPair,
2105    vuu: HvxVectorPair,
2106    rt: i32,
2107) -> HvxVectorPair {
2108    vdsaduh_acc(vxx, vuu, rt)
2109}
2110
2111/// `Vx32.w=vinsert(Rt32)`
2112///
2113/// Instruction Type: CVI_VX_LATE
2114/// Execution Slots: SLOT23
2115#[inline]
2116#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2117#[cfg_attr(test, assert_instr(vinsertwr))]
2118#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2119pub unsafe fn Q6_Vw_vinsert_VwR(vx: HvxVector, rt: i32) -> HvxVector {
2120    vinsertwr(vx, rt)
2121}
2122
2123/// `Vd32=vlalign(Vu32,Vv32,Rt8)`
2124///
2125/// Instruction Type: CVI_VP
2126/// Execution Slots: SLOT0123
2127#[inline]
2128#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2129#[cfg_attr(test, assert_instr(vlalignb))]
2130#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2131pub unsafe fn Q6_V_vlalign_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
2132    vlalignb(vu, vv, rt)
2133}
2134
2135/// `Vd32=vlalign(Vu32,Vv32,#u3)`
2136///
2137/// Instruction Type: CVI_VP
2138/// Execution Slots: SLOT0123
2139#[inline]
2140#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2141#[cfg_attr(test, assert_instr(vlalignbi))]
2142#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2143pub unsafe fn Q6_V_vlalign_VVI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector {
2144    vlalignbi(vu, vv, iu3)
2145}
2146
2147/// `Vd32.uh=vlsr(Vu32.uh,Rt32)`
2148///
2149/// Instruction Type: CVI_VS
2150/// Execution Slots: SLOT0123
2151#[inline]
2152#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2153#[cfg_attr(test, assert_instr(vlsrh))]
2154#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2155pub unsafe fn Q6_Vuh_vlsr_VuhR(vu: HvxVector, rt: i32) -> HvxVector {
2156    vlsrh(vu, rt)
2157}
2158
2159/// `Vd32.h=vlsr(Vu32.h,Vv32.h)`
2160///
2161/// Instruction Type: CVI_VS
2162/// Execution Slots: SLOT0123
2163#[inline]
2164#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2165#[cfg_attr(test, assert_instr(vlsrhv))]
2166#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2167pub unsafe fn Q6_Vh_vlsr_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
2168    vlsrhv(vu, vv)
2169}
2170
2171/// `Vd32.uw=vlsr(Vu32.uw,Rt32)`
2172///
2173/// Instruction Type: CVI_VS
2174/// Execution Slots: SLOT0123
2175#[inline]
2176#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2177#[cfg_attr(test, assert_instr(vlsrw))]
2178#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2179pub unsafe fn Q6_Vuw_vlsr_VuwR(vu: HvxVector, rt: i32) -> HvxVector {
2180    vlsrw(vu, rt)
2181}
2182
2183/// `Vd32.w=vlsr(Vu32.w,Vv32.w)`
2184///
2185/// Instruction Type: CVI_VS
2186/// Execution Slots: SLOT0123
2187#[inline]
2188#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2189#[cfg_attr(test, assert_instr(vlsrwv))]
2190#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2191pub unsafe fn Q6_Vw_vlsr_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
2192    vlsrwv(vu, vv)
2193}
2194
2195/// `Vd32.b=vlut32(Vu32.b,Vv32.b,Rt8)`
2196///
2197/// Instruction Type: CVI_VP
2198/// Execution Slots: SLOT0123
2199#[inline]
2200#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2201#[cfg_attr(test, assert_instr(vlutvvb))]
2202#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2203pub unsafe fn Q6_Vb_vlut32_VbVbR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
2204    vlutvvb(vu, vv, rt)
2205}
2206
2207/// `Vx32.b|=vlut32(Vu32.b,Vv32.b,Rt8)`
2208///
2209/// Instruction Type: CVI_VP_VS
2210/// Execution Slots: SLOT0123
2211#[inline]
2212#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2213#[cfg_attr(test, assert_instr(vlutvvb_oracc))]
2214#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2215pub unsafe fn Q6_Vb_vlut32or_VbVbVbR(
2216    vx: HvxVector,
2217    vu: HvxVector,
2218    vv: HvxVector,
2219    rt: i32,
2220) -> HvxVector {
2221    vlutvvb_oracc(vx, vu, vv, rt)
2222}
2223
2224/// `Vdd32.h=vlut16(Vu32.b,Vv32.h,Rt8)`
2225///
2226/// Instruction Type: CVI_VP_VS
2227/// Execution Slots: SLOT0123
2228#[inline]
2229#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2230#[cfg_attr(test, assert_instr(vlutvwh))]
2231#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2232pub unsafe fn Q6_Wh_vlut16_VbVhR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair {
2233    vlutvwh(vu, vv, rt)
2234}
2235
2236/// `Vxx32.h|=vlut16(Vu32.b,Vv32.h,Rt8)`
2237///
2238/// Instruction Type: CVI_VP_VS
2239/// Execution Slots: SLOT0123
2240#[inline]
2241#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2242#[cfg_attr(test, assert_instr(vlutvwh_oracc))]
2243#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2244pub unsafe fn Q6_Wh_vlut16or_WhVbVhR(
2245    vxx: HvxVectorPair,
2246    vu: HvxVector,
2247    vv: HvxVector,
2248    rt: i32,
2249) -> HvxVectorPair {
2250    vlutvwh_oracc(vxx, vu, vv, rt)
2251}
2252
2253/// `Vd32.h=vmax(Vu32.h,Vv32.h)`
2254///
2255/// Instruction Type: CVI_VA
2256/// Execution Slots: SLOT0123
2257#[inline]
2258#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2259#[cfg_attr(test, assert_instr(vmaxh))]
2260#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2261pub unsafe fn Q6_Vh_vmax_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
2262    vmaxh(vu, vv)
2263}
2264
2265/// `Vd32.ub=vmax(Vu32.ub,Vv32.ub)`
2266///
2267/// Instruction Type: CVI_VA
2268/// Execution Slots: SLOT0123
2269#[inline]
2270#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2271#[cfg_attr(test, assert_instr(vmaxub))]
2272#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2273pub unsafe fn Q6_Vub_vmax_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector {
2274    vmaxub(vu, vv)
2275}
2276
2277/// `Vd32.uh=vmax(Vu32.uh,Vv32.uh)`
2278///
2279/// Instruction Type: CVI_VA
2280/// Execution Slots: SLOT0123
2281#[inline]
2282#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2283#[cfg_attr(test, assert_instr(vmaxuh))]
2284#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2285pub unsafe fn Q6_Vuh_vmax_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
2286    vmaxuh(vu, vv)
2287}
2288
2289/// `Vd32.w=vmax(Vu32.w,Vv32.w)`
2290///
2291/// Instruction Type: CVI_VA
2292/// Execution Slots: SLOT0123
2293#[inline]
2294#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2295#[cfg_attr(test, assert_instr(vmaxw))]
2296#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2297pub unsafe fn Q6_Vw_vmax_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
2298    vmaxw(vu, vv)
2299}
2300
2301/// `Vd32.h=vmin(Vu32.h,Vv32.h)`
2302///
2303/// Instruction Type: CVI_VA
2304/// Execution Slots: SLOT0123
2305#[inline]
2306#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2307#[cfg_attr(test, assert_instr(vminh))]
2308#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2309pub unsafe fn Q6_Vh_vmin_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
2310    vminh(vu, vv)
2311}
2312
2313/// `Vd32.ub=vmin(Vu32.ub,Vv32.ub)`
2314///
2315/// Instruction Type: CVI_VA
2316/// Execution Slots: SLOT0123
2317#[inline]
2318#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2319#[cfg_attr(test, assert_instr(vminub))]
2320#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2321pub unsafe fn Q6_Vub_vmin_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector {
2322    vminub(vu, vv)
2323}
2324
2325/// `Vd32.uh=vmin(Vu32.uh,Vv32.uh)`
2326///
2327/// Instruction Type: CVI_VA
2328/// Execution Slots: SLOT0123
2329#[inline]
2330#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2331#[cfg_attr(test, assert_instr(vminuh))]
2332#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2333pub unsafe fn Q6_Vuh_vmin_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
2334    vminuh(vu, vv)
2335}
2336
2337/// `Vd32.w=vmin(Vu32.w,Vv32.w)`
2338///
2339/// Instruction Type: CVI_VA
2340/// Execution Slots: SLOT0123
2341#[inline]
2342#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2343#[cfg_attr(test, assert_instr(vminw))]
2344#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2345pub unsafe fn Q6_Vw_vmin_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
2346    vminw(vu, vv)
2347}
2348
2349/// `Vdd32.h=vmpa(Vuu32.ub,Rt32.b)`
2350///
2351/// Instruction Type: CVI_VX_DV
2352/// Execution Slots: SLOT23
2353#[inline]
2354#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2355#[cfg_attr(test, assert_instr(vmpabus))]
2356#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2357pub unsafe fn Q6_Wh_vmpa_WubRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
2358    vmpabus(vuu, rt)
2359}
2360
2361/// `Vxx32.h+=vmpa(Vuu32.ub,Rt32.b)`
2362///
2363/// Instruction Type: CVI_VX_DV
2364/// Execution Slots: SLOT23
2365#[inline]
2366#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2367#[cfg_attr(test, assert_instr(vmpabus_acc))]
2368#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2369pub unsafe fn Q6_Wh_vmpaacc_WhWubRb(
2370    vxx: HvxVectorPair,
2371    vuu: HvxVectorPair,
2372    rt: i32,
2373) -> HvxVectorPair {
2374    vmpabus_acc(vxx, vuu, rt)
2375}
2376
2377/// `Vdd32.h=vmpa(Vuu32.ub,Vvv32.b)`
2378///
2379/// Instruction Type: CVI_VX_DV
2380/// Execution Slots: SLOT23
2381#[inline]
2382#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2383#[cfg_attr(test, assert_instr(vmpabusv))]
2384#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2385pub unsafe fn Q6_Wh_vmpa_WubWb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
2386    vmpabusv(vuu, vvv)
2387}
2388
2389/// `Vdd32.h=vmpa(Vuu32.ub,Vvv32.ub)`
2390///
2391/// Instruction Type: CVI_VX_DV
2392/// Execution Slots: SLOT23
2393#[inline]
2394#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2395#[cfg_attr(test, assert_instr(vmpabuuv))]
2396#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2397pub unsafe fn Q6_Wh_vmpa_WubWub(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
2398    vmpabuuv(vuu, vvv)
2399}
2400
2401/// `Vdd32.w=vmpa(Vuu32.h,Rt32.b)`
2402///
2403/// Instruction Type: CVI_VX_DV
2404/// Execution Slots: SLOT23
2405#[inline]
2406#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2407#[cfg_attr(test, assert_instr(vmpahb))]
2408#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2409pub unsafe fn Q6_Ww_vmpa_WhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
2410    vmpahb(vuu, rt)
2411}
2412
2413/// `Vxx32.w+=vmpa(Vuu32.h,Rt32.b)`
2414///
2415/// Instruction Type: CVI_VX_DV
2416/// Execution Slots: SLOT23
2417#[inline]
2418#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2419#[cfg_attr(test, assert_instr(vmpahb_acc))]
2420#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2421pub unsafe fn Q6_Ww_vmpaacc_WwWhRb(
2422    vxx: HvxVectorPair,
2423    vuu: HvxVectorPair,
2424    rt: i32,
2425) -> HvxVectorPair {
2426    vmpahb_acc(vxx, vuu, rt)
2427}
2428
2429/// `Vdd32.h=vmpy(Vu32.ub,Rt32.b)`
2430///
2431/// Instruction Type: CVI_VX_DV
2432/// Execution Slots: SLOT23
2433#[inline]
2434#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2435#[cfg_attr(test, assert_instr(vmpybus))]
2436#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2437pub unsafe fn Q6_Wh_vmpy_VubRb(vu: HvxVector, rt: i32) -> HvxVectorPair {
2438    vmpybus(vu, rt)
2439}
2440
2441/// `Vxx32.h+=vmpy(Vu32.ub,Rt32.b)`
2442///
2443/// Instruction Type: CVI_VX_DV
2444/// Execution Slots: SLOT23
2445#[inline]
2446#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2447#[cfg_attr(test, assert_instr(vmpybus_acc))]
2448#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2449pub unsafe fn Q6_Wh_vmpyacc_WhVubRb(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -> HvxVectorPair {
2450    vmpybus_acc(vxx, vu, rt)
2451}
2452
2453/// `Vdd32.h=vmpy(Vu32.ub,Vv32.b)`
2454///
2455/// Instruction Type: CVI_VX_DV
2456/// Execution Slots: SLOT23
2457#[inline]
2458#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2459#[cfg_attr(test, assert_instr(vmpybusv))]
2460#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2461pub unsafe fn Q6_Wh_vmpy_VubVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
2462    vmpybusv(vu, vv)
2463}
2464
2465/// `Vxx32.h+=vmpy(Vu32.ub,Vv32.b)`
2466///
2467/// Instruction Type: CVI_VX_DV
2468/// Execution Slots: SLOT23
2469#[inline]
2470#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2471#[cfg_attr(test, assert_instr(vmpybusv_acc))]
2472#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2473pub unsafe fn Q6_Wh_vmpyacc_WhVubVb(
2474    vxx: HvxVectorPair,
2475    vu: HvxVector,
2476    vv: HvxVector,
2477) -> HvxVectorPair {
2478    vmpybusv_acc(vxx, vu, vv)
2479}
2480
2481/// `Vdd32.h=vmpy(Vu32.b,Vv32.b)`
2482///
2483/// Instruction Type: CVI_VX_DV
2484/// Execution Slots: SLOT23
2485#[inline]
2486#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2487#[cfg_attr(test, assert_instr(vmpybv))]
2488#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2489pub unsafe fn Q6_Wh_vmpy_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
2490    vmpybv(vu, vv)
2491}
2492
2493/// `Vxx32.h+=vmpy(Vu32.b,Vv32.b)`
2494///
2495/// Instruction Type: CVI_VX_DV
2496/// Execution Slots: SLOT23
2497#[inline]
2498#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2499#[cfg_attr(test, assert_instr(vmpybv_acc))]
2500#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2501pub unsafe fn Q6_Wh_vmpyacc_WhVbVb(
2502    vxx: HvxVectorPair,
2503    vu: HvxVector,
2504    vv: HvxVector,
2505) -> HvxVectorPair {
2506    vmpybv_acc(vxx, vu, vv)
2507}
2508
2509/// `Vd32.w=vmpye(Vu32.w,Vv32.uh)`
2510///
2511/// Instruction Type: CVI_VX_DV
2512/// Execution Slots: SLOT23
2513#[inline]
2514#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2515#[cfg_attr(test, assert_instr(vmpyewuh))]
2516#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2517pub unsafe fn Q6_Vw_vmpye_VwVuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
2518    vmpyewuh(vu, vv)
2519}
2520
2521/// `Vdd32.w=vmpy(Vu32.h,Rt32.h)`
2522///
2523/// Instruction Type: CVI_VX_DV
2524/// Execution Slots: SLOT23
2525#[inline]
2526#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2527#[cfg_attr(test, assert_instr(vmpyh))]
2528#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2529pub unsafe fn Q6_Ww_vmpy_VhRh(vu: HvxVector, rt: i32) -> HvxVectorPair {
2530    vmpyh(vu, rt)
2531}
2532
2533/// `Vxx32.w+=vmpy(Vu32.h,Rt32.h):sat`
2534///
2535/// Instruction Type: CVI_VX_DV
2536/// Execution Slots: SLOT23
2537#[inline]
2538#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2539#[cfg_attr(test, assert_instr(vmpyhsat_acc))]
2540#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2541pub unsafe fn Q6_Ww_vmpyacc_WwVhRh_sat(
2542    vxx: HvxVectorPair,
2543    vu: HvxVector,
2544    rt: i32,
2545) -> HvxVectorPair {
2546    vmpyhsat_acc(vxx, vu, rt)
2547}
2548
2549/// `Vd32.h=vmpy(Vu32.h,Rt32.h):<<1:rnd:sat`
2550///
2551/// Instruction Type: CVI_VX
2552/// Execution Slots: SLOT23
2553#[inline]
2554#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2555#[cfg_attr(test, assert_instr(vmpyhsrs))]
2556#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2557pub unsafe fn Q6_Vh_vmpy_VhRh_s1_rnd_sat(vu: HvxVector, rt: i32) -> HvxVector {
2558    vmpyhsrs(vu, rt)
2559}
2560
2561/// `Vd32.h=vmpy(Vu32.h,Rt32.h):<<1:sat`
2562///
2563/// Instruction Type: CVI_VX
2564/// Execution Slots: SLOT23
2565#[inline]
2566#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2567#[cfg_attr(test, assert_instr(vmpyhss))]
2568#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2569pub unsafe fn Q6_Vh_vmpy_VhRh_s1_sat(vu: HvxVector, rt: i32) -> HvxVector {
2570    vmpyhss(vu, rt)
2571}
2572
2573/// `Vdd32.w=vmpy(Vu32.h,Vv32.uh)`
2574///
2575/// Instruction Type: CVI_VX_DV
2576/// Execution Slots: SLOT23
2577#[inline]
2578#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2579#[cfg_attr(test, assert_instr(vmpyhus))]
2580#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2581pub unsafe fn Q6_Ww_vmpy_VhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
2582    vmpyhus(vu, vv)
2583}
2584
2585/// `Vxx32.w+=vmpy(Vu32.h,Vv32.uh)`
2586///
2587/// Instruction Type: CVI_VX_DV
2588/// Execution Slots: SLOT23
2589#[inline]
2590#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2591#[cfg_attr(test, assert_instr(vmpyhus_acc))]
2592#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2593pub unsafe fn Q6_Ww_vmpyacc_WwVhVuh(
2594    vxx: HvxVectorPair,
2595    vu: HvxVector,
2596    vv: HvxVector,
2597) -> HvxVectorPair {
2598    vmpyhus_acc(vxx, vu, vv)
2599}
2600
2601/// `Vdd32.w=vmpy(Vu32.h,Vv32.h)`
2602///
2603/// Instruction Type: CVI_VX_DV
2604/// Execution Slots: SLOT23
2605#[inline]
2606#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2607#[cfg_attr(test, assert_instr(vmpyhv))]
2608#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2609pub unsafe fn Q6_Ww_vmpy_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
2610    vmpyhv(vu, vv)
2611}
2612
2613/// `Vxx32.w+=vmpy(Vu32.h,Vv32.h)`
2614///
2615/// Instruction Type: CVI_VX_DV
2616/// Execution Slots: SLOT23
2617#[inline]
2618#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2619#[cfg_attr(test, assert_instr(vmpyhv_acc))]
2620#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2621pub unsafe fn Q6_Ww_vmpyacc_WwVhVh(
2622    vxx: HvxVectorPair,
2623    vu: HvxVector,
2624    vv: HvxVector,
2625) -> HvxVectorPair {
2626    vmpyhv_acc(vxx, vu, vv)
2627}
2628
2629/// `Vd32.h=vmpy(Vu32.h,Vv32.h):<<1:rnd:sat`
2630///
2631/// Instruction Type: CVI_VX
2632/// Execution Slots: SLOT23
2633#[inline]
2634#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2635#[cfg_attr(test, assert_instr(vmpyhvsrs))]
2636#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2637pub unsafe fn Q6_Vh_vmpy_VhVh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
2638    vmpyhvsrs(vu, vv)
2639}
2640
2641/// `Vd32.w=vmpyieo(Vu32.h,Vv32.h)`
2642///
2643/// Instruction Type: CVI_VX
2644/// Execution Slots: SLOT23
2645#[inline]
2646#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2647#[cfg_attr(test, assert_instr(vmpyieoh))]
2648#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2649pub unsafe fn Q6_Vw_vmpyieo_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
2650    vmpyieoh(vu, vv)
2651}
2652
2653/// `Vx32.w+=vmpyie(Vu32.w,Vv32.h)`
2654///
2655/// Instruction Type: CVI_VX_DV
2656/// Execution Slots: SLOT23
2657#[inline]
2658#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2659#[cfg_attr(test, assert_instr(vmpyiewh_acc))]
2660#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2661pub unsafe fn Q6_Vw_vmpyieacc_VwVwVh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
2662    vmpyiewh_acc(vx, vu, vv)
2663}
2664
2665/// `Vd32.w=vmpyie(Vu32.w,Vv32.uh)`
2666///
2667/// Instruction Type: CVI_VX_DV
2668/// Execution Slots: SLOT23
2669#[inline]
2670#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2671#[cfg_attr(test, assert_instr(vmpyiewuh))]
2672#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2673pub unsafe fn Q6_Vw_vmpyie_VwVuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
2674    vmpyiewuh(vu, vv)
2675}
2676
2677/// `Vx32.w+=vmpyie(Vu32.w,Vv32.uh)`
2678///
2679/// Instruction Type: CVI_VX_DV
2680/// Execution Slots: SLOT23
2681#[inline]
2682#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2683#[cfg_attr(test, assert_instr(vmpyiewuh_acc))]
2684#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2685pub unsafe fn Q6_Vw_vmpyieacc_VwVwVuh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
2686    vmpyiewuh_acc(vx, vu, vv)
2687}
2688
2689/// `Vd32.h=vmpyi(Vu32.h,Vv32.h)`
2690///
2691/// Instruction Type: CVI_VX_DV
2692/// Execution Slots: SLOT23
2693#[inline]
2694#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2695#[cfg_attr(test, assert_instr(vmpyih))]
2696#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2697pub unsafe fn Q6_Vh_vmpyi_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
2698    vmpyih(vu, vv)
2699}
2700
2701/// `Vx32.h+=vmpyi(Vu32.h,Vv32.h)`
2702///
2703/// Instruction Type: CVI_VX_DV
2704/// Execution Slots: SLOT23
2705#[inline]
2706#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2707#[cfg_attr(test, assert_instr(vmpyih_acc))]
2708#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2709pub unsafe fn Q6_Vh_vmpyiacc_VhVhVh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
2710    vmpyih_acc(vx, vu, vv)
2711}
2712
2713/// `Vd32.h=vmpyi(Vu32.h,Rt32.b)`
2714///
2715/// Instruction Type: CVI_VX
2716/// Execution Slots: SLOT23
2717#[inline]
2718#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2719#[cfg_attr(test, assert_instr(vmpyihb))]
2720#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2721pub unsafe fn Q6_Vh_vmpyi_VhRb(vu: HvxVector, rt: i32) -> HvxVector {
2722    vmpyihb(vu, rt)
2723}
2724
2725/// `Vx32.h+=vmpyi(Vu32.h,Rt32.b)`
2726///
2727/// Instruction Type: CVI_VX
2728/// Execution Slots: SLOT23
2729#[inline]
2730#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2731#[cfg_attr(test, assert_instr(vmpyihb_acc))]
2732#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2733pub unsafe fn Q6_Vh_vmpyiacc_VhVhRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
2734    vmpyihb_acc(vx, vu, rt)
2735}
2736
2737/// `Vd32.w=vmpyio(Vu32.w,Vv32.h)`
2738///
2739/// Instruction Type: CVI_VX_DV
2740/// Execution Slots: SLOT23
2741#[inline]
2742#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2743#[cfg_attr(test, assert_instr(vmpyiowh))]
2744#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2745pub unsafe fn Q6_Vw_vmpyio_VwVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
2746    vmpyiowh(vu, vv)
2747}
2748
2749/// `Vd32.w=vmpyi(Vu32.w,Rt32.b)`
2750///
2751/// Instruction Type: CVI_VX
2752/// Execution Slots: SLOT23
2753#[inline]
2754#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2755#[cfg_attr(test, assert_instr(vmpyiwb))]
2756#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2757pub unsafe fn Q6_Vw_vmpyi_VwRb(vu: HvxVector, rt: i32) -> HvxVector {
2758    vmpyiwb(vu, rt)
2759}
2760
2761/// `Vx32.w+=vmpyi(Vu32.w,Rt32.b)`
2762///
2763/// Instruction Type: CVI_VX
2764/// Execution Slots: SLOT23
2765#[inline]
2766#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2767#[cfg_attr(test, assert_instr(vmpyiwb_acc))]
2768#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2769pub unsafe fn Q6_Vw_vmpyiacc_VwVwRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
2770    vmpyiwb_acc(vx, vu, rt)
2771}
2772
2773/// `Vd32.w=vmpyi(Vu32.w,Rt32.h)`
2774///
2775/// Instruction Type: CVI_VX_DV
2776/// Execution Slots: SLOT23
2777#[inline]
2778#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2779#[cfg_attr(test, assert_instr(vmpyiwh))]
2780#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2781pub unsafe fn Q6_Vw_vmpyi_VwRh(vu: HvxVector, rt: i32) -> HvxVector {
2782    vmpyiwh(vu, rt)
2783}
2784
2785/// `Vx32.w+=vmpyi(Vu32.w,Rt32.h)`
2786///
2787/// Instruction Type: CVI_VX_DV
2788/// Execution Slots: SLOT23
2789#[inline]
2790#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2791#[cfg_attr(test, assert_instr(vmpyiwh_acc))]
2792#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2793pub unsafe fn Q6_Vw_vmpyiacc_VwVwRh(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
2794    vmpyiwh_acc(vx, vu, rt)
2795}
2796
2797/// `Vd32.w=vmpyo(Vu32.w,Vv32.h):<<1:sat`
2798///
2799/// Instruction Type: CVI_VX_DV
2800/// Execution Slots: SLOT23
2801#[inline]
2802#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2803#[cfg_attr(test, assert_instr(vmpyowh))]
2804#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2805pub unsafe fn Q6_Vw_vmpyo_VwVh_s1_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
2806    vmpyowh(vu, vv)
2807}
2808
2809/// `Vd32.w=vmpyo(Vu32.w,Vv32.h):<<1:rnd:sat`
2810///
2811/// Instruction Type: CVI_VX_DV
2812/// Execution Slots: SLOT23
2813#[inline]
2814#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2815#[cfg_attr(test, assert_instr(vmpyowh_rnd))]
2816#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2817pub unsafe fn Q6_Vw_vmpyo_VwVh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
2818    vmpyowh_rnd(vu, vv)
2819}
2820
2821/// `Vx32.w+=vmpyo(Vu32.w,Vv32.h):<<1:rnd:sat:shift`
2822///
2823/// Instruction Type: CVI_VX_DV
2824/// Execution Slots: SLOT23
2825#[inline]
2826#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2827#[cfg_attr(test, assert_instr(vmpyowh_rnd_sacc))]
2828#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2829pub unsafe fn Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shift(
2830    vx: HvxVector,
2831    vu: HvxVector,
2832    vv: HvxVector,
2833) -> HvxVector {
2834    vmpyowh_rnd_sacc(vx, vu, vv)
2835}
2836
2837/// `Vx32.w+=vmpyo(Vu32.w,Vv32.h):<<1:sat:shift`
2838///
2839/// Instruction Type: CVI_VX_DV
2840/// Execution Slots: SLOT23
2841#[inline]
2842#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2843#[cfg_attr(test, assert_instr(vmpyowh_sacc))]
2844#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2845pub unsafe fn Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shift(
2846    vx: HvxVector,
2847    vu: HvxVector,
2848    vv: HvxVector,
2849) -> HvxVector {
2850    vmpyowh_sacc(vx, vu, vv)
2851}
2852
2853/// `Vdd32.uh=vmpy(Vu32.ub,Rt32.ub)`
2854///
2855/// Instruction Type: CVI_VX_DV
2856/// Execution Slots: SLOT23
2857#[inline]
2858#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2859#[cfg_attr(test, assert_instr(vmpyub))]
2860#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2861pub unsafe fn Q6_Wuh_vmpy_VubRub(vu: HvxVector, rt: i32) -> HvxVectorPair {
2862    vmpyub(vu, rt)
2863}
2864
2865/// `Vxx32.uh+=vmpy(Vu32.ub,Rt32.ub)`
2866///
2867/// Instruction Type: CVI_VX_DV
2868/// Execution Slots: SLOT23
2869#[inline]
2870#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2871#[cfg_attr(test, assert_instr(vmpyub_acc))]
2872#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2873pub unsafe fn Q6_Wuh_vmpyacc_WuhVubRub(
2874    vxx: HvxVectorPair,
2875    vu: HvxVector,
2876    rt: i32,
2877) -> HvxVectorPair {
2878    vmpyub_acc(vxx, vu, rt)
2879}
2880
2881/// `Vdd32.uh=vmpy(Vu32.ub,Vv32.ub)`
2882///
2883/// Instruction Type: CVI_VX_DV
2884/// Execution Slots: SLOT23
2885#[inline]
2886#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2887#[cfg_attr(test, assert_instr(vmpyubv))]
2888#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2889pub unsafe fn Q6_Wuh_vmpy_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
2890    vmpyubv(vu, vv)
2891}
2892
2893/// `Vxx32.uh+=vmpy(Vu32.ub,Vv32.ub)`
2894///
2895/// Instruction Type: CVI_VX_DV
2896/// Execution Slots: SLOT23
2897#[inline]
2898#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2899#[cfg_attr(test, assert_instr(vmpyubv_acc))]
2900#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2901pub unsafe fn Q6_Wuh_vmpyacc_WuhVubVub(
2902    vxx: HvxVectorPair,
2903    vu: HvxVector,
2904    vv: HvxVector,
2905) -> HvxVectorPair {
2906    vmpyubv_acc(vxx, vu, vv)
2907}
2908
2909/// `Vdd32.uw=vmpy(Vu32.uh,Rt32.uh)`
2910///
2911/// Instruction Type: CVI_VX_DV
2912/// Execution Slots: SLOT23
2913#[inline]
2914#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2915#[cfg_attr(test, assert_instr(vmpyuh))]
2916#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2917pub unsafe fn Q6_Wuw_vmpy_VuhRuh(vu: HvxVector, rt: i32) -> HvxVectorPair {
2918    vmpyuh(vu, rt)
2919}
2920
2921/// `Vxx32.uw+=vmpy(Vu32.uh,Rt32.uh)`
2922///
2923/// Instruction Type: CVI_VX_DV
2924/// Execution Slots: SLOT23
2925#[inline]
2926#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2927#[cfg_attr(test, assert_instr(vmpyuh_acc))]
2928#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2929pub unsafe fn Q6_Wuw_vmpyacc_WuwVuhRuh(
2930    vxx: HvxVectorPair,
2931    vu: HvxVector,
2932    rt: i32,
2933) -> HvxVectorPair {
2934    vmpyuh_acc(vxx, vu, rt)
2935}
2936
2937/// `Vdd32.uw=vmpy(Vu32.uh,Vv32.uh)`
2938///
2939/// Instruction Type: CVI_VX_DV
2940/// Execution Slots: SLOT23
2941#[inline]
2942#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2943#[cfg_attr(test, assert_instr(vmpyuhv))]
2944#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2945pub unsafe fn Q6_Wuw_vmpy_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
2946    vmpyuhv(vu, vv)
2947}
2948
2949/// `Vxx32.uw+=vmpy(Vu32.uh,Vv32.uh)`
2950///
2951/// Instruction Type: CVI_VX_DV
2952/// Execution Slots: SLOT23
2953#[inline]
2954#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2955#[cfg_attr(test, assert_instr(vmpyuhv_acc))]
2956#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2957pub unsafe fn Q6_Wuw_vmpyacc_WuwVuhVuh(
2958    vxx: HvxVectorPair,
2959    vu: HvxVector,
2960    vv: HvxVector,
2961) -> HvxVectorPair {
2962    vmpyuhv_acc(vxx, vu, vv)
2963}
2964
2965/// `Vd32.h=vnavg(Vu32.h,Vv32.h)`
2966///
2967/// Instruction Type: CVI_VA
2968/// Execution Slots: SLOT0123
2969#[inline]
2970#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2971#[cfg_attr(test, assert_instr(vnavgh))]
2972#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2973pub unsafe fn Q6_Vh_vnavg_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
2974    vnavgh(vu, vv)
2975}
2976
2977/// `Vd32.b=vnavg(Vu32.ub,Vv32.ub)`
2978///
2979/// Instruction Type: CVI_VA
2980/// Execution Slots: SLOT0123
2981#[inline]
2982#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2983#[cfg_attr(test, assert_instr(vnavgub))]
2984#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2985pub unsafe fn Q6_Vb_vnavg_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector {
2986    vnavgub(vu, vv)
2987}
2988
2989/// `Vd32.w=vnavg(Vu32.w,Vv32.w)`
2990///
2991/// Instruction Type: CVI_VA
2992/// Execution Slots: SLOT0123
2993#[inline]
2994#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
2995#[cfg_attr(test, assert_instr(vnavgw))]
2996#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2997pub unsafe fn Q6_Vw_vnavg_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
2998    vnavgw(vu, vv)
2999}
3000
3001/// `Vd32.h=vnormamt(Vu32.h)`
3002///
3003/// Instruction Type: CVI_VS
3004/// Execution Slots: SLOT0123
3005#[inline]
3006#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3007#[cfg_attr(test, assert_instr(vnormamth))]
3008#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3009pub unsafe fn Q6_Vh_vnormamt_Vh(vu: HvxVector) -> HvxVector {
3010    vnormamth(vu)
3011}
3012
3013/// `Vd32.w=vnormamt(Vu32.w)`
3014///
3015/// Instruction Type: CVI_VS
3016/// Execution Slots: SLOT0123
3017#[inline]
3018#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3019#[cfg_attr(test, assert_instr(vnormamtw))]
3020#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3021pub unsafe fn Q6_Vw_vnormamt_Vw(vu: HvxVector) -> HvxVector {
3022    vnormamtw(vu)
3023}
3024
3025/// `Vd32=vnot(Vu32)`
3026///
3027/// Instruction Type: CVI_VA
3028/// Execution Slots: SLOT0123
3029#[inline]
3030#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3031#[cfg_attr(test, assert_instr(vnot))]
3032#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3033pub unsafe fn Q6_V_vnot_V(vu: HvxVector) -> HvxVector {
3034    vnot(vu)
3035}
3036
3037/// `Vd32=vor(Vu32,Vv32)`
3038///
3039/// Instruction Type: CVI_VA
3040/// Execution Slots: SLOT0123
3041#[inline]
3042#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3043#[cfg_attr(test, assert_instr(vor))]
3044#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3045pub unsafe fn Q6_V_vor_VV(vu: HvxVector, vv: HvxVector) -> HvxVector {
3046    simd_or(vu, vv)
3047}
3048
3049/// `Vd32.b=vpacke(Vu32.h,Vv32.h)`
3050///
3051/// Instruction Type: CVI_VP
3052/// Execution Slots: SLOT0123
3053#[inline]
3054#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3055#[cfg_attr(test, assert_instr(vpackeb))]
3056#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3057pub unsafe fn Q6_Vb_vpacke_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
3058    vpackeb(vu, vv)
3059}
3060
3061/// `Vd32.h=vpacke(Vu32.w,Vv32.w)`
3062///
3063/// Instruction Type: CVI_VP
3064/// Execution Slots: SLOT0123
3065#[inline]
3066#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3067#[cfg_attr(test, assert_instr(vpackeh))]
3068#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3069pub unsafe fn Q6_Vh_vpacke_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
3070    vpackeh(vu, vv)
3071}
3072
3073/// `Vd32.b=vpack(Vu32.h,Vv32.h):sat`
3074///
3075/// Instruction Type: CVI_VP
3076/// Execution Slots: SLOT0123
3077#[inline]
3078#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3079#[cfg_attr(test, assert_instr(vpackhb_sat))]
3080#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3081pub unsafe fn Q6_Vb_vpack_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
3082    vpackhb_sat(vu, vv)
3083}
3084
3085/// `Vd32.ub=vpack(Vu32.h,Vv32.h):sat`
3086///
3087/// Instruction Type: CVI_VP
3088/// Execution Slots: SLOT0123
3089#[inline]
3090#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3091#[cfg_attr(test, assert_instr(vpackhub_sat))]
3092#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3093pub unsafe fn Q6_Vub_vpack_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
3094    vpackhub_sat(vu, vv)
3095}
3096
3097/// `Vd32.b=vpacko(Vu32.h,Vv32.h)`
3098///
3099/// Instruction Type: CVI_VP
3100/// Execution Slots: SLOT0123
3101#[inline]
3102#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3103#[cfg_attr(test, assert_instr(vpackob))]
3104#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3105pub unsafe fn Q6_Vb_vpacko_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
3106    vpackob(vu, vv)
3107}
3108
3109/// `Vd32.h=vpacko(Vu32.w,Vv32.w)`
3110///
3111/// Instruction Type: CVI_VP
3112/// Execution Slots: SLOT0123
3113#[inline]
3114#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3115#[cfg_attr(test, assert_instr(vpackoh))]
3116#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3117pub unsafe fn Q6_Vh_vpacko_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
3118    vpackoh(vu, vv)
3119}
3120
3121/// `Vd32.h=vpack(Vu32.w,Vv32.w):sat`
3122///
3123/// Instruction Type: CVI_VP
3124/// Execution Slots: SLOT0123
3125#[inline]
3126#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3127#[cfg_attr(test, assert_instr(vpackwh_sat))]
3128#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3129pub unsafe fn Q6_Vh_vpack_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
3130    vpackwh_sat(vu, vv)
3131}
3132
3133/// `Vd32.uh=vpack(Vu32.w,Vv32.w):sat`
3134///
3135/// Instruction Type: CVI_VP
3136/// Execution Slots: SLOT0123
3137#[inline]
3138#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3139#[cfg_attr(test, assert_instr(vpackwuh_sat))]
3140#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3141pub unsafe fn Q6_Vuh_vpack_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
3142    vpackwuh_sat(vu, vv)
3143}
3144
3145/// `Vd32.h=vpopcount(Vu32.h)`
3146///
3147/// Instruction Type: CVI_VS
3148/// Execution Slots: SLOT0123
3149#[inline]
3150#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3151#[cfg_attr(test, assert_instr(vpopcounth))]
3152#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3153pub unsafe fn Q6_Vh_vpopcount_Vh(vu: HvxVector) -> HvxVector {
3154    vpopcounth(vu)
3155}
3156
3157/// `Vd32=vrdelta(Vu32,Vv32)`
3158///
3159/// Instruction Type: CVI_VP
3160/// Execution Slots: SLOT0123
3161#[inline]
3162#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3163#[cfg_attr(test, assert_instr(vrdelta))]
3164#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3165pub unsafe fn Q6_V_vrdelta_VV(vu: HvxVector, vv: HvxVector) -> HvxVector {
3166    vrdelta(vu, vv)
3167}
3168
3169/// `Vd32.w=vrmpy(Vu32.ub,Rt32.b)`
3170///
3171/// Instruction Type: CVI_VX
3172/// Execution Slots: SLOT23
3173#[inline]
3174#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3175#[cfg_attr(test, assert_instr(vrmpybus))]
3176#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3177pub unsafe fn Q6_Vw_vrmpy_VubRb(vu: HvxVector, rt: i32) -> HvxVector {
3178    vrmpybus(vu, rt)
3179}
3180
3181/// `Vx32.w+=vrmpy(Vu32.ub,Rt32.b)`
3182///
3183/// Instruction Type: CVI_VX
3184/// Execution Slots: SLOT23
3185#[inline]
3186#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3187#[cfg_attr(test, assert_instr(vrmpybus_acc))]
3188#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3189pub unsafe fn Q6_Vw_vrmpyacc_VwVubRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
3190    vrmpybus_acc(vx, vu, rt)
3191}
3192
3193/// `Vdd32.w=vrmpy(Vuu32.ub,Rt32.b,#u1)`
3194///
3195/// Instruction Type: CVI_VX_DV
3196/// Execution Slots: SLOT23
3197#[inline]
3198#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3199#[cfg_attr(test, assert_instr(vrmpybusi))]
3200#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3201pub unsafe fn Q6_Ww_vrmpy_WubRbI(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair {
3202    vrmpybusi(vuu, rt, iu1)
3203}
3204
3205/// `Vxx32.w+=vrmpy(Vuu32.ub,Rt32.b,#u1)`
3206///
3207/// Instruction Type: CVI_VX_DV
3208/// Execution Slots: SLOT23
3209#[inline]
3210#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3211#[cfg_attr(test, assert_instr(vrmpybusi_acc))]
3212#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3213pub unsafe fn Q6_Ww_vrmpyacc_WwWubRbI(
3214    vxx: HvxVectorPair,
3215    vuu: HvxVectorPair,
3216    rt: i32,
3217    iu1: i32,
3218) -> HvxVectorPair {
3219    vrmpybusi_acc(vxx, vuu, rt, iu1)
3220}
3221
3222/// `Vd32.w=vrmpy(Vu32.ub,Vv32.b)`
3223///
3224/// Instruction Type: CVI_VX
3225/// Execution Slots: SLOT23
3226#[inline]
3227#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3228#[cfg_attr(test, assert_instr(vrmpybusv))]
3229#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3230pub unsafe fn Q6_Vw_vrmpy_VubVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
3231    vrmpybusv(vu, vv)
3232}
3233
3234/// `Vx32.w+=vrmpy(Vu32.ub,Vv32.b)`
3235///
3236/// Instruction Type: CVI_VX
3237/// Execution Slots: SLOT23
3238#[inline]
3239#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3240#[cfg_attr(test, assert_instr(vrmpybusv_acc))]
3241#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3242pub unsafe fn Q6_Vw_vrmpyacc_VwVubVb(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
3243    vrmpybusv_acc(vx, vu, vv)
3244}
3245
3246/// `Vd32.w=vrmpy(Vu32.b,Vv32.b)`
3247///
3248/// Instruction Type: CVI_VX
3249/// Execution Slots: SLOT23
3250#[inline]
3251#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3252#[cfg_attr(test, assert_instr(vrmpybv))]
3253#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3254pub unsafe fn Q6_Vw_vrmpy_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
3255    vrmpybv(vu, vv)
3256}
3257
3258/// `Vx32.w+=vrmpy(Vu32.b,Vv32.b)`
3259///
3260/// Instruction Type: CVI_VX
3261/// Execution Slots: SLOT23
3262#[inline]
3263#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3264#[cfg_attr(test, assert_instr(vrmpybv_acc))]
3265#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3266pub unsafe fn Q6_Vw_vrmpyacc_VwVbVb(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
3267    vrmpybv_acc(vx, vu, vv)
3268}
3269
3270/// `Vd32.uw=vrmpy(Vu32.ub,Rt32.ub)`
3271///
3272/// Instruction Type: CVI_VX
3273/// Execution Slots: SLOT23
3274#[inline]
3275#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3276#[cfg_attr(test, assert_instr(vrmpyub))]
3277#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3278pub unsafe fn Q6_Vuw_vrmpy_VubRub(vu: HvxVector, rt: i32) -> HvxVector {
3279    vrmpyub(vu, rt)
3280}
3281
3282/// `Vx32.uw+=vrmpy(Vu32.ub,Rt32.ub)`
3283///
3284/// Instruction Type: CVI_VX
3285/// Execution Slots: SLOT23
3286#[inline]
3287#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3288#[cfg_attr(test, assert_instr(vrmpyub_acc))]
3289#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3290pub unsafe fn Q6_Vuw_vrmpyacc_VuwVubRub(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
3291    vrmpyub_acc(vx, vu, rt)
3292}
3293
3294/// `Vdd32.uw=vrmpy(Vuu32.ub,Rt32.ub,#u1)`
3295///
3296/// Instruction Type: CVI_VX_DV
3297/// Execution Slots: SLOT23
3298#[inline]
3299#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3300#[cfg_attr(test, assert_instr(vrmpyubi))]
3301#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3302pub unsafe fn Q6_Wuw_vrmpy_WubRubI(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair {
3303    vrmpyubi(vuu, rt, iu1)
3304}
3305
3306/// `Vxx32.uw+=vrmpy(Vuu32.ub,Rt32.ub,#u1)`
3307///
3308/// Instruction Type: CVI_VX_DV
3309/// Execution Slots: SLOT23
3310#[inline]
3311#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3312#[cfg_attr(test, assert_instr(vrmpyubi_acc))]
3313#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3314pub unsafe fn Q6_Wuw_vrmpyacc_WuwWubRubI(
3315    vxx: HvxVectorPair,
3316    vuu: HvxVectorPair,
3317    rt: i32,
3318    iu1: i32,
3319) -> HvxVectorPair {
3320    vrmpyubi_acc(vxx, vuu, rt, iu1)
3321}
3322
3323/// `Vd32.uw=vrmpy(Vu32.ub,Vv32.ub)`
3324///
3325/// Instruction Type: CVI_VX
3326/// Execution Slots: SLOT23
3327#[inline]
3328#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3329#[cfg_attr(test, assert_instr(vrmpyubv))]
3330#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3331pub unsafe fn Q6_Vuw_vrmpy_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector {
3332    vrmpyubv(vu, vv)
3333}
3334
3335/// `Vx32.uw+=vrmpy(Vu32.ub,Vv32.ub)`
3336///
3337/// Instruction Type: CVI_VX
3338/// Execution Slots: SLOT23
3339#[inline]
3340#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3341#[cfg_attr(test, assert_instr(vrmpyubv_acc))]
3342#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3343pub unsafe fn Q6_Vuw_vrmpyacc_VuwVubVub(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
3344    vrmpyubv_acc(vx, vu, vv)
3345}
3346
3347/// `Vd32=vror(Vu32,Rt32)`
3348///
3349/// Instruction Type: CVI_VP
3350/// Execution Slots: SLOT0123
3351#[inline]
3352#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3353#[cfg_attr(test, assert_instr(vror))]
3354#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3355pub unsafe fn Q6_V_vror_VR(vu: HvxVector, rt: i32) -> HvxVector {
3356    vror(vu, rt)
3357}
3358
3359/// `Vd32.b=vround(Vu32.h,Vv32.h):sat`
3360///
3361/// Instruction Type: CVI_VS
3362/// Execution Slots: SLOT0123
3363#[inline]
3364#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3365#[cfg_attr(test, assert_instr(vroundhb))]
3366#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3367pub unsafe fn Q6_Vb_vround_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
3368    vroundhb(vu, vv)
3369}
3370
3371/// `Vd32.ub=vround(Vu32.h,Vv32.h):sat`
3372///
3373/// Instruction Type: CVI_VS
3374/// Execution Slots: SLOT0123
3375#[inline]
3376#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3377#[cfg_attr(test, assert_instr(vroundhub))]
3378#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3379pub unsafe fn Q6_Vub_vround_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
3380    vroundhub(vu, vv)
3381}
3382
3383/// `Vd32.h=vround(Vu32.w,Vv32.w):sat`
3384///
3385/// Instruction Type: CVI_VS
3386/// Execution Slots: SLOT0123
3387#[inline]
3388#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3389#[cfg_attr(test, assert_instr(vroundwh))]
3390#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3391pub unsafe fn Q6_Vh_vround_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
3392    vroundwh(vu, vv)
3393}
3394
3395/// `Vd32.uh=vround(Vu32.w,Vv32.w):sat`
3396///
3397/// Instruction Type: CVI_VS
3398/// Execution Slots: SLOT0123
3399#[inline]
3400#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3401#[cfg_attr(test, assert_instr(vroundwuh))]
3402#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3403pub unsafe fn Q6_Vuh_vround_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
3404    vroundwuh(vu, vv)
3405}
3406
3407/// `Vdd32.uw=vrsad(Vuu32.ub,Rt32.ub,#u1)`
3408///
3409/// Instruction Type: CVI_VX_DV
3410/// Execution Slots: SLOT23
3411#[inline]
3412#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3413#[cfg_attr(test, assert_instr(vrsadubi))]
3414#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3415pub unsafe fn Q6_Wuw_vrsad_WubRubI(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair {
3416    vrsadubi(vuu, rt, iu1)
3417}
3418
3419/// `Vxx32.uw+=vrsad(Vuu32.ub,Rt32.ub,#u1)`
3420///
3421/// Instruction Type: CVI_VX_DV
3422/// Execution Slots: SLOT23
3423#[inline]
3424#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3425#[cfg_attr(test, assert_instr(vrsadubi_acc))]
3426#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3427pub unsafe fn Q6_Wuw_vrsadacc_WuwWubRubI(
3428    vxx: HvxVectorPair,
3429    vuu: HvxVectorPair,
3430    rt: i32,
3431    iu1: i32,
3432) -> HvxVectorPair {
3433    vrsadubi_acc(vxx, vuu, rt, iu1)
3434}
3435
3436/// `Vd32.ub=vsat(Vu32.h,Vv32.h)`
3437///
3438/// Instruction Type: CVI_VA
3439/// Execution Slots: SLOT0123
3440#[inline]
3441#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3442#[cfg_attr(test, assert_instr(vsathub))]
3443#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3444pub unsafe fn Q6_Vub_vsat_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
3445    vsathub(vu, vv)
3446}
3447
3448/// `Vd32.h=vsat(Vu32.w,Vv32.w)`
3449///
3450/// Instruction Type: CVI_VA
3451/// Execution Slots: SLOT0123
3452#[inline]
3453#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3454#[cfg_attr(test, assert_instr(vsatwh))]
3455#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3456pub unsafe fn Q6_Vh_vsat_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
3457    vsatwh(vu, vv)
3458}
3459
3460/// `Vdd32.h=vsxt(Vu32.b)`
3461///
3462/// Instruction Type: CVI_VA_DV
3463/// Execution Slots: SLOT0123
3464#[inline]
3465#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3466#[cfg_attr(test, assert_instr(vsb))]
3467#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3468pub unsafe fn Q6_Wh_vsxt_Vb(vu: HvxVector) -> HvxVectorPair {
3469    vsb(vu)
3470}
3471
3472/// `Vdd32.w=vsxt(Vu32.h)`
3473///
3474/// Instruction Type: CVI_VA_DV
3475/// Execution Slots: SLOT0123
3476#[inline]
3477#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3478#[cfg_attr(test, assert_instr(vsh))]
3479#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3480pub unsafe fn Q6_Ww_vsxt_Vh(vu: HvxVector) -> HvxVectorPair {
3481    vsh(vu)
3482}
3483
3484/// `Vd32.h=vshuffe(Vu32.h,Vv32.h)`
3485///
3486/// Instruction Type: CVI_VA
3487/// Execution Slots: SLOT0123
3488#[inline]
3489#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3490#[cfg_attr(test, assert_instr(vshufeh))]
3491#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3492pub unsafe fn Q6_Vh_vshuffe_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
3493    vshufeh(vu, vv)
3494}
3495
3496/// `Vd32.b=vshuff(Vu32.b)`
3497///
3498/// Instruction Type: CVI_VP
3499/// Execution Slots: SLOT0123
3500#[inline]
3501#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3502#[cfg_attr(test, assert_instr(vshuffb))]
3503#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3504pub unsafe fn Q6_Vb_vshuff_Vb(vu: HvxVector) -> HvxVector {
3505    vshuffb(vu)
3506}
3507
3508/// `Vd32.b=vshuffe(Vu32.b,Vv32.b)`
3509///
3510/// Instruction Type: CVI_VA
3511/// Execution Slots: SLOT0123
3512#[inline]
3513#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3514#[cfg_attr(test, assert_instr(vshuffeb))]
3515#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3516pub unsafe fn Q6_Vb_vshuffe_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
3517    vshuffeb(vu, vv)
3518}
3519
3520/// `Vd32.h=vshuff(Vu32.h)`
3521///
3522/// Instruction Type: CVI_VP
3523/// Execution Slots: SLOT0123
3524#[inline]
3525#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3526#[cfg_attr(test, assert_instr(vshuffh))]
3527#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3528pub unsafe fn Q6_Vh_vshuff_Vh(vu: HvxVector) -> HvxVector {
3529    vshuffh(vu)
3530}
3531
3532/// `Vd32.b=vshuffo(Vu32.b,Vv32.b)`
3533///
3534/// Instruction Type: CVI_VA
3535/// Execution Slots: SLOT0123
3536#[inline]
3537#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3538#[cfg_attr(test, assert_instr(vshuffob))]
3539#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3540pub unsafe fn Q6_Vb_vshuffo_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
3541    vshuffob(vu, vv)
3542}
3543
3544/// `Vdd32=vshuff(Vu32,Vv32,Rt8)`
3545///
3546/// Instruction Type: CVI_VP_VS
3547/// Execution Slots: SLOT0123
3548#[inline]
3549#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3550#[cfg_attr(test, assert_instr(vshuffvdd))]
3551#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3552pub unsafe fn Q6_W_vshuff_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair {
3553    vshuffvdd(vu, vv, rt)
3554}
3555
3556/// `Vdd32.b=vshuffoe(Vu32.b,Vv32.b)`
3557///
3558/// Instruction Type: CVI_VA_DV
3559/// Execution Slots: SLOT0123
3560#[inline]
3561#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3562#[cfg_attr(test, assert_instr(vshufoeb))]
3563#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3564pub unsafe fn Q6_Wb_vshuffoe_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
3565    vshufoeb(vu, vv)
3566}
3567
3568/// `Vdd32.h=vshuffoe(Vu32.h,Vv32.h)`
3569///
3570/// Instruction Type: CVI_VA_DV
3571/// Execution Slots: SLOT0123
3572#[inline]
3573#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3574#[cfg_attr(test, assert_instr(vshufoeh))]
3575#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3576pub unsafe fn Q6_Wh_vshuffoe_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
3577    vshufoeh(vu, vv)
3578}
3579
3580/// `Vd32.h=vshuffo(Vu32.h,Vv32.h)`
3581///
3582/// Instruction Type: CVI_VA
3583/// Execution Slots: SLOT0123
3584#[inline]
3585#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3586#[cfg_attr(test, assert_instr(vshufoh))]
3587#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3588pub unsafe fn Q6_Vh_vshuffo_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
3589    vshufoh(vu, vv)
3590}
3591
3592/// `Vd32.b=vsub(Vu32.b,Vv32.b)`
3593///
3594/// Instruction Type: CVI_VA
3595/// Execution Slots: SLOT0123
3596#[inline]
3597#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3598#[cfg_attr(test, assert_instr(vsubb))]
3599#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3600pub unsafe fn Q6_Vb_vsub_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
3601    vsubb(vu, vv)
3602}
3603
3604/// `Vdd32.b=vsub(Vuu32.b,Vvv32.b)`
3605///
3606/// Instruction Type: CVI_VA_DV
3607/// Execution Slots: SLOT0123
3608#[inline]
3609#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3610#[cfg_attr(test, assert_instr(vsubb_dv))]
3611#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3612pub unsafe fn Q6_Wb_vsub_WbWb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
3613    vsubb_dv(vuu, vvv)
3614}
3615
3616/// `Vd32.h=vsub(Vu32.h,Vv32.h)`
3617///
3618/// Instruction Type: CVI_VA
3619/// Execution Slots: SLOT0123
3620#[inline]
3621#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3622#[cfg_attr(test, assert_instr(vsubh))]
3623#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3624pub unsafe fn Q6_Vh_vsub_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
3625    vsubh(vu, vv)
3626}
3627
3628/// `Vdd32.h=vsub(Vuu32.h,Vvv32.h)`
3629///
3630/// Instruction Type: CVI_VA_DV
3631/// Execution Slots: SLOT0123
3632#[inline]
3633#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3634#[cfg_attr(test, assert_instr(vsubh_dv))]
3635#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3636pub unsafe fn Q6_Wh_vsub_WhWh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
3637    vsubh_dv(vuu, vvv)
3638}
3639
3640/// `Vd32.h=vsub(Vu32.h,Vv32.h):sat`
3641///
3642/// Instruction Type: CVI_VA
3643/// Execution Slots: SLOT0123
3644#[inline]
3645#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3646#[cfg_attr(test, assert_instr(vsubhsat))]
3647#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3648pub unsafe fn Q6_Vh_vsub_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
3649    vsubhsat(vu, vv)
3650}
3651
3652/// `Vdd32.h=vsub(Vuu32.h,Vvv32.h):sat`
3653///
3654/// Instruction Type: CVI_VA_DV
3655/// Execution Slots: SLOT0123
3656#[inline]
3657#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3658#[cfg_attr(test, assert_instr(vsubhsat_dv))]
3659#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3660pub unsafe fn Q6_Wh_vsub_WhWh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
3661    vsubhsat_dv(vuu, vvv)
3662}
3663
3664/// `Vdd32.w=vsub(Vu32.h,Vv32.h)`
3665///
3666/// Instruction Type: CVI_VX_DV
3667/// Execution Slots: SLOT23
3668#[inline]
3669#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3670#[cfg_attr(test, assert_instr(vsubhw))]
3671#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3672pub unsafe fn Q6_Ww_vsub_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
3673    vsubhw(vu, vv)
3674}
3675
3676/// `Vdd32.h=vsub(Vu32.ub,Vv32.ub)`
3677///
3678/// Instruction Type: CVI_VX_DV
3679/// Execution Slots: SLOT23
3680#[inline]
3681#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3682#[cfg_attr(test, assert_instr(vsububh))]
3683#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3684pub unsafe fn Q6_Wh_vsub_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
3685    vsububh(vu, vv)
3686}
3687
3688/// `Vd32.ub=vsub(Vu32.ub,Vv32.ub):sat`
3689///
3690/// Instruction Type: CVI_VA
3691/// Execution Slots: SLOT0123
3692#[inline]
3693#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3694#[cfg_attr(test, assert_instr(vsububsat))]
3695#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3696pub unsafe fn Q6_Vub_vsub_VubVub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
3697    vsububsat(vu, vv)
3698}
3699
3700/// `Vdd32.ub=vsub(Vuu32.ub,Vvv32.ub):sat`
3701///
3702/// Instruction Type: CVI_VA_DV
3703/// Execution Slots: SLOT0123
3704#[inline]
3705#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3706#[cfg_attr(test, assert_instr(vsububsat_dv))]
3707#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3708pub unsafe fn Q6_Wub_vsub_WubWub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
3709    vsububsat_dv(vuu, vvv)
3710}
3711
3712/// `Vd32.uh=vsub(Vu32.uh,Vv32.uh):sat`
3713///
3714/// Instruction Type: CVI_VA
3715/// Execution Slots: SLOT0123
3716#[inline]
3717#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3718#[cfg_attr(test, assert_instr(vsubuhsat))]
3719#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3720pub unsafe fn Q6_Vuh_vsub_VuhVuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
3721    vsubuhsat(vu, vv)
3722}
3723
3724/// `Vdd32.uh=vsub(Vuu32.uh,Vvv32.uh):sat`
3725///
3726/// Instruction Type: CVI_VA_DV
3727/// Execution Slots: SLOT0123
3728#[inline]
3729#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3730#[cfg_attr(test, assert_instr(vsubuhsat_dv))]
3731#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3732pub unsafe fn Q6_Wuh_vsub_WuhWuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
3733    vsubuhsat_dv(vuu, vvv)
3734}
3735
3736/// `Vdd32.w=vsub(Vu32.uh,Vv32.uh)`
3737///
3738/// Instruction Type: CVI_VX_DV
3739/// Execution Slots: SLOT23
3740#[inline]
3741#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3742#[cfg_attr(test, assert_instr(vsubuhw))]
3743#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3744pub unsafe fn Q6_Ww_vsub_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
3745    vsubuhw(vu, vv)
3746}
3747
3748/// `Vd32.w=vsub(Vu32.w,Vv32.w)`
3749///
3750/// Instruction Type: CVI_VA
3751/// Execution Slots: SLOT0123
3752#[inline]
3753#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3754#[cfg_attr(test, assert_instr(vsubw))]
3755#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3756pub unsafe fn Q6_Vw_vsub_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
3757    simd_sub(vu, vv)
3758}
3759
3760/// `Vdd32.w=vsub(Vuu32.w,Vvv32.w)`
3761///
3762/// Instruction Type: CVI_VA_DV
3763/// Execution Slots: SLOT0123
3764#[inline]
3765#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3766#[cfg_attr(test, assert_instr(vsubw_dv))]
3767#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3768pub unsafe fn Q6_Ww_vsub_WwWw(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
3769    vsubw_dv(vuu, vvv)
3770}
3771
3772/// `Vd32.w=vsub(Vu32.w,Vv32.w):sat`
3773///
3774/// Instruction Type: CVI_VA
3775/// Execution Slots: SLOT0123
3776#[inline]
3777#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3778#[cfg_attr(test, assert_instr(vsubwsat))]
3779#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3780pub unsafe fn Q6_Vw_vsub_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
3781    vsubwsat(vu, vv)
3782}
3783
3784/// `Vdd32.w=vsub(Vuu32.w,Vvv32.w):sat`
3785///
3786/// Instruction Type: CVI_VA_DV
3787/// Execution Slots: SLOT0123
3788#[inline]
3789#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3790#[cfg_attr(test, assert_instr(vsubwsat_dv))]
3791#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3792pub unsafe fn Q6_Ww_vsub_WwWw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
3793    vsubwsat_dv(vuu, vvv)
3794}
3795
3796/// `Vdd32.h=vtmpy(Vuu32.b,Rt32.b)`
3797///
3798/// Instruction Type: CVI_VX_DV
3799/// Execution Slots: SLOT23
3800#[inline]
3801#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3802#[cfg_attr(test, assert_instr(vtmpyb))]
3803#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3804pub unsafe fn Q6_Wh_vtmpy_WbRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
3805    vtmpyb(vuu, rt)
3806}
3807
3808/// `Vxx32.h+=vtmpy(Vuu32.b,Rt32.b)`
3809///
3810/// Instruction Type: CVI_VX_DV
3811/// Execution Slots: SLOT23
3812#[inline]
3813#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3814#[cfg_attr(test, assert_instr(vtmpyb_acc))]
3815#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3816pub unsafe fn Q6_Wh_vtmpyacc_WhWbRb(
3817    vxx: HvxVectorPair,
3818    vuu: HvxVectorPair,
3819    rt: i32,
3820) -> HvxVectorPair {
3821    vtmpyb_acc(vxx, vuu, rt)
3822}
3823
3824/// `Vdd32.h=vtmpy(Vuu32.ub,Rt32.b)`
3825///
3826/// Instruction Type: CVI_VX_DV
3827/// Execution Slots: SLOT23
3828#[inline]
3829#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3830#[cfg_attr(test, assert_instr(vtmpybus))]
3831#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3832pub unsafe fn Q6_Wh_vtmpy_WubRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
3833    vtmpybus(vuu, rt)
3834}
3835
3836/// `Vxx32.h+=vtmpy(Vuu32.ub,Rt32.b)`
3837///
3838/// Instruction Type: CVI_VX_DV
3839/// Execution Slots: SLOT23
3840#[inline]
3841#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3842#[cfg_attr(test, assert_instr(vtmpybus_acc))]
3843#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3844pub unsafe fn Q6_Wh_vtmpyacc_WhWubRb(
3845    vxx: HvxVectorPair,
3846    vuu: HvxVectorPair,
3847    rt: i32,
3848) -> HvxVectorPair {
3849    vtmpybus_acc(vxx, vuu, rt)
3850}
3851
3852/// `Vdd32.w=vtmpy(Vuu32.h,Rt32.b)`
3853///
3854/// Instruction Type: CVI_VX_DV
3855/// Execution Slots: SLOT23
3856#[inline]
3857#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3858#[cfg_attr(test, assert_instr(vtmpyhb))]
3859#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3860pub unsafe fn Q6_Ww_vtmpy_WhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
3861    vtmpyhb(vuu, rt)
3862}
3863
3864/// `Vxx32.w+=vtmpy(Vuu32.h,Rt32.b)`
3865///
3866/// Instruction Type: CVI_VX_DV
3867/// Execution Slots: SLOT23
3868#[inline]
3869#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3870#[cfg_attr(test, assert_instr(vtmpyhb_acc))]
3871#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3872pub unsafe fn Q6_Ww_vtmpyacc_WwWhRb(
3873    vxx: HvxVectorPair,
3874    vuu: HvxVectorPair,
3875    rt: i32,
3876) -> HvxVectorPair {
3877    vtmpyhb_acc(vxx, vuu, rt)
3878}
3879
3880/// `Vdd32.h=vunpack(Vu32.b)`
3881///
3882/// Instruction Type: CVI_VP_VS
3883/// Execution Slots: SLOT0123
3884#[inline]
3885#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3886#[cfg_attr(test, assert_instr(vunpackb))]
3887#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3888pub unsafe fn Q6_Wh_vunpack_Vb(vu: HvxVector) -> HvxVectorPair {
3889    vunpackb(vu)
3890}
3891
3892/// `Vdd32.w=vunpack(Vu32.h)`
3893///
3894/// Instruction Type: CVI_VP_VS
3895/// Execution Slots: SLOT0123
3896#[inline]
3897#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3898#[cfg_attr(test, assert_instr(vunpackh))]
3899#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3900pub unsafe fn Q6_Ww_vunpack_Vh(vu: HvxVector) -> HvxVectorPair {
3901    vunpackh(vu)
3902}
3903
3904/// `Vxx32.h|=vunpacko(Vu32.b)`
3905///
3906/// Instruction Type: CVI_VP_VS
3907/// Execution Slots: SLOT0123
3908#[inline]
3909#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3910#[cfg_attr(test, assert_instr(vunpackob))]
3911#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3912pub unsafe fn Q6_Wh_vunpackoor_WhVb(vxx: HvxVectorPair, vu: HvxVector) -> HvxVectorPair {
3913    vunpackob(vxx, vu)
3914}
3915
3916/// `Vxx32.w|=vunpacko(Vu32.h)`
3917///
3918/// Instruction Type: CVI_VP_VS
3919/// Execution Slots: SLOT0123
3920#[inline]
3921#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3922#[cfg_attr(test, assert_instr(vunpackoh))]
3923#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3924pub unsafe fn Q6_Ww_vunpackoor_WwVh(vxx: HvxVectorPair, vu: HvxVector) -> HvxVectorPair {
3925    vunpackoh(vxx, vu)
3926}
3927
3928/// `Vdd32.uh=vunpack(Vu32.ub)`
3929///
3930/// Instruction Type: CVI_VP_VS
3931/// Execution Slots: SLOT0123
3932#[inline]
3933#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3934#[cfg_attr(test, assert_instr(vunpackub))]
3935#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3936pub unsafe fn Q6_Wuh_vunpack_Vub(vu: HvxVector) -> HvxVectorPair {
3937    vunpackub(vu)
3938}
3939
3940/// `Vdd32.uw=vunpack(Vu32.uh)`
3941///
3942/// Instruction Type: CVI_VP_VS
3943/// Execution Slots: SLOT0123
3944#[inline]
3945#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3946#[cfg_attr(test, assert_instr(vunpackuh))]
3947#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3948pub unsafe fn Q6_Wuw_vunpack_Vuh(vu: HvxVector) -> HvxVectorPair {
3949    vunpackuh(vu)
3950}
3951
3952/// `Vd32=vxor(Vu32,Vv32)`
3953///
3954/// Instruction Type: CVI_VA
3955/// Execution Slots: SLOT0123
3956#[inline]
3957#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3958#[cfg_attr(test, assert_instr(vxor))]
3959#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3960pub unsafe fn Q6_V_vxor_VV(vu: HvxVector, vv: HvxVector) -> HvxVector {
3961    simd_xor(vu, vv)
3962}
3963
3964/// `Vdd32.uh=vzxt(Vu32.ub)`
3965///
3966/// Instruction Type: CVI_VA_DV
3967/// Execution Slots: SLOT0123
3968#[inline]
3969#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3970#[cfg_attr(test, assert_instr(vzb))]
3971#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3972pub unsafe fn Q6_Wuh_vzxt_Vub(vu: HvxVector) -> HvxVectorPair {
3973    vzb(vu)
3974}
3975
3976/// `Vdd32.uw=vzxt(Vu32.uh)`
3977///
3978/// Instruction Type: CVI_VA_DV
3979/// Execution Slots: SLOT0123
3980#[inline]
3981#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
3982#[cfg_attr(test, assert_instr(vzh))]
3983#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3984pub unsafe fn Q6_Wuw_vzxt_Vuh(vu: HvxVector) -> HvxVectorPair {
3985    vzh(vu)
3986}
3987
3988/// `Vd32.b=vsplat(Rt32)`
3989///
3990/// Instruction Type: CVI_VX_LATE
3991/// Execution Slots: SLOT23
3992#[inline]
3993#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
3994#[cfg_attr(test, assert_instr(lvsplatb))]
3995#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3996pub unsafe fn Q6_Vb_vsplat_R(rt: i32) -> HvxVector {
3997    lvsplatb(rt)
3998}
3999
4000/// `Vd32.h=vsplat(Rt32)`
4001///
4002/// Instruction Type: CVI_VX_LATE
4003/// Execution Slots: SLOT23
4004#[inline]
4005#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
4006#[cfg_attr(test, assert_instr(lvsplath))]
4007#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4008pub unsafe fn Q6_Vh_vsplat_R(rt: i32) -> HvxVector {
4009    lvsplath(rt)
4010}
4011
4012/// `Vd32.b=vadd(Vu32.b,Vv32.b):sat`
4013///
4014/// Instruction Type: CVI_VA
4015/// Execution Slots: SLOT0123
4016#[inline]
4017#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
4018#[cfg_attr(test, assert_instr(vaddbsat))]
4019#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4020pub unsafe fn Q6_Vb_vadd_VbVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
4021    vaddbsat(vu, vv)
4022}
4023
4024/// `Vdd32.b=vadd(Vuu32.b,Vvv32.b):sat`
4025///
4026/// Instruction Type: CVI_VA_DV
4027/// Execution Slots: SLOT0123
4028#[inline]
4029#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
4030#[cfg_attr(test, assert_instr(vaddbsat_dv))]
4031#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4032pub unsafe fn Q6_Wb_vadd_WbWb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
4033    vaddbsat_dv(vuu, vvv)
4034}
4035
4036/// `Vd32.h=vadd(vclb(Vu32.h),Vv32.h)`
4037///
4038/// Instruction Type: CVI_VS
4039/// Execution Slots: SLOT0123
4040#[inline]
4041#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
4042#[cfg_attr(test, assert_instr(vaddclbh))]
4043#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4044pub unsafe fn Q6_Vh_vadd_vclb_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
4045    vaddclbh(vu, vv)
4046}
4047
4048/// `Vd32.w=vadd(vclb(Vu32.w),Vv32.w)`
4049///
4050/// Instruction Type: CVI_VS
4051/// Execution Slots: SLOT0123
4052#[inline]
4053#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
4054#[cfg_attr(test, assert_instr(vaddclbw))]
4055#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4056pub unsafe fn Q6_Vw_vadd_vclb_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
4057    vaddclbw(vu, vv)
4058}
4059
4060/// `Vxx32.w+=vadd(Vu32.h,Vv32.h)`
4061///
4062/// Instruction Type: CVI_VX_DV
4063/// Execution Slots: SLOT23
4064#[inline]
4065#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
4066#[cfg_attr(test, assert_instr(vaddhw_acc))]
4067#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4068pub unsafe fn Q6_Ww_vaddacc_WwVhVh(
4069    vxx: HvxVectorPair,
4070    vu: HvxVector,
4071    vv: HvxVector,
4072) -> HvxVectorPair {
4073    vaddhw_acc(vxx, vu, vv)
4074}
4075
4076/// `Vxx32.h+=vadd(Vu32.ub,Vv32.ub)`
4077///
4078/// Instruction Type: CVI_VX_DV
4079/// Execution Slots: SLOT23
4080#[inline]
4081#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
4082#[cfg_attr(test, assert_instr(vaddubh_acc))]
4083#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4084pub unsafe fn Q6_Wh_vaddacc_WhVubVub(
4085    vxx: HvxVectorPair,
4086    vu: HvxVector,
4087    vv: HvxVector,
4088) -> HvxVectorPair {
4089    vaddubh_acc(vxx, vu, vv)
4090}
4091
4092/// `Vd32.ub=vadd(Vu32.ub,Vv32.b):sat`
4093///
4094/// Instruction Type: CVI_VA
4095/// Execution Slots: SLOT0123
4096#[inline]
4097#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
4098#[cfg_attr(test, assert_instr(vaddububb_sat))]
4099#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4100pub unsafe fn Q6_Vub_vadd_VubVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
4101    vaddububb_sat(vu, vv)
4102}
4103
4104/// `Vxx32.w+=vadd(Vu32.uh,Vv32.uh)`
4105///
4106/// Instruction Type: CVI_VX_DV
4107/// Execution Slots: SLOT23
4108#[inline]
4109#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
4110#[cfg_attr(test, assert_instr(vadduhw_acc))]
4111#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4112pub unsafe fn Q6_Ww_vaddacc_WwVuhVuh(
4113    vxx: HvxVectorPair,
4114    vu: HvxVector,
4115    vv: HvxVector,
4116) -> HvxVectorPair {
4117    vadduhw_acc(vxx, vu, vv)
4118}
4119
4120/// `Vd32.uw=vadd(Vu32.uw,Vv32.uw):sat`
4121///
4122/// Instruction Type: CVI_VA
4123/// Execution Slots: SLOT0123
4124#[inline]
4125#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
4126#[cfg_attr(test, assert_instr(vadduwsat))]
4127#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4128pub unsafe fn Q6_Vuw_vadd_VuwVuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
4129    vadduwsat(vu, vv)
4130}
4131
4132/// `Vdd32.uw=vadd(Vuu32.uw,Vvv32.uw):sat`
4133///
4134/// Instruction Type: CVI_VA_DV
4135/// Execution Slots: SLOT0123
4136#[inline]
4137#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
4138#[cfg_attr(test, assert_instr(vadduwsat_dv))]
4139#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4140pub unsafe fn Q6_Wuw_vadd_WuwWuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
4141    vadduwsat_dv(vuu, vvv)
4142}
4143
4144/// `Vd32.b=vasr(Vu32.h,Vv32.h,Rt8):sat`
4145///
4146/// Instruction Type: CVI_VS
4147/// Execution Slots: SLOT0123
4148#[inline]
4149#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
4150#[cfg_attr(test, assert_instr(vasrhbsat))]
4151#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4152pub unsafe fn Q6_Vb_vasr_VhVhR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
4153    vasrhbsat(vu, vv, rt)
4154}
4155
4156/// `Vd32.uh=vasr(Vu32.uw,Vv32.uw,Rt8):rnd:sat`
4157///
4158/// Instruction Type: CVI_VS
4159/// Execution Slots: SLOT0123
4160#[inline]
4161#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
4162#[cfg_attr(test, assert_instr(vasruwuhrndsat))]
4163#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4164pub unsafe fn Q6_Vuh_vasr_VuwVuwR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
4165    vasruwuhrndsat(vu, vv, rt)
4166}
4167
4168/// `Vd32.uh=vasr(Vu32.w,Vv32.w,Rt8):rnd:sat`
4169///
4170/// Instruction Type: CVI_VS
4171/// Execution Slots: SLOT0123
4172#[inline]
4173#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
4174#[cfg_attr(test, assert_instr(vasrwuhrndsat))]
4175#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4176pub unsafe fn Q6_Vuh_vasr_VwVwR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
4177    vasrwuhrndsat(vu, vv, rt)
4178}
4179
4180/// `Vd32.ub=vlsr(Vu32.ub,Rt32)`
4181///
4182/// Instruction Type: CVI_VS
4183/// Execution Slots: SLOT0123
4184#[inline]
4185#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
4186#[cfg_attr(test, assert_instr(vlsrb))]
4187#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4188pub unsafe fn Q6_Vub_vlsr_VubR(vu: HvxVector, rt: i32) -> HvxVector {
4189    vlsrb(vu, rt)
4190}
4191
4192/// `Vd32.b=vlut32(Vu32.b,Vv32.b,Rt8):nomatch`
4193///
4194/// Instruction Type: CVI_VP
4195/// Execution Slots: SLOT0123
4196#[inline]
4197#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
4198#[cfg_attr(test, assert_instr(vlutvvb_nm))]
4199#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4200pub unsafe fn Q6_Vb_vlut32_VbVbR_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
4201    vlutvvb_nm(vu, vv, rt)
4202}
4203
4204/// `Vx32.b|=vlut32(Vu32.b,Vv32.b,#u3)`
4205///
4206/// Instruction Type: CVI_VP_VS
4207/// Execution Slots: SLOT0123
4208#[inline]
4209#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
4210#[cfg_attr(test, assert_instr(vlutvvb_oracci))]
4211#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4212pub unsafe fn Q6_Vb_vlut32or_VbVbVbI(
4213    vx: HvxVector,
4214    vu: HvxVector,
4215    vv: HvxVector,
4216    iu3: i32,
4217) -> HvxVector {
4218    vlutvvb_oracci(vx, vu, vv, iu3)
4219}
4220
4221/// `Vd32.b=vlut32(Vu32.b,Vv32.b,#u3)`
4222///
4223/// Instruction Type: CVI_VP
4224/// Execution Slots: SLOT0123
4225#[inline]
4226#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
4227#[cfg_attr(test, assert_instr(vlutvvbi))]
4228#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4229pub unsafe fn Q6_Vb_vlut32_VbVbI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector {
4230    vlutvvbi(vu, vv, iu3)
4231}
4232
4233/// `Vdd32.h=vlut16(Vu32.b,Vv32.h,Rt8):nomatch`
4234///
4235/// Instruction Type: CVI_VP_VS
4236/// Execution Slots: SLOT0123
4237#[inline]
4238#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
4239#[cfg_attr(test, assert_instr(vlutvwh_nm))]
4240#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4241pub unsafe fn Q6_Wh_vlut16_VbVhR_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair {
4242    vlutvwh_nm(vu, vv, rt)
4243}
4244
4245/// `Vxx32.h|=vlut16(Vu32.b,Vv32.h,#u3)`
4246///
4247/// Instruction Type: CVI_VP_VS
4248/// Execution Slots: SLOT0123
4249#[inline]
4250#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
4251#[cfg_attr(test, assert_instr(vlutvwh_oracci))]
4252#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4253pub unsafe fn Q6_Wh_vlut16or_WhVbVhI(
4254    vxx: HvxVectorPair,
4255    vu: HvxVector,
4256    vv: HvxVector,
4257    iu3: i32,
4258) -> HvxVectorPair {
4259    vlutvwh_oracci(vxx, vu, vv, iu3)
4260}
4261
4262/// `Vdd32.h=vlut16(Vu32.b,Vv32.h,#u3)`
4263///
4264/// Instruction Type: CVI_VP_VS
4265/// Execution Slots: SLOT0123
4266#[inline]
4267#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
4268#[cfg_attr(test, assert_instr(vlutvwhi))]
4269#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4270pub unsafe fn Q6_Wh_vlut16_VbVhI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVectorPair {
4271    vlutvwhi(vu, vv, iu3)
4272}
4273
4274/// `Vd32.b=vmax(Vu32.b,Vv32.b)`
4275///
4276/// Instruction Type: CVI_VA
4277/// Execution Slots: SLOT0123
4278#[inline]
4279#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
4280#[cfg_attr(test, assert_instr(vmaxb))]
4281#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4282pub unsafe fn Q6_Vb_vmax_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
4283    vmaxb(vu, vv)
4284}
4285
4286/// `Vd32.b=vmin(Vu32.b,Vv32.b)`
4287///
4288/// Instruction Type: CVI_VA
4289/// Execution Slots: SLOT0123
4290#[inline]
4291#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
4292#[cfg_attr(test, assert_instr(vminb))]
4293#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4294pub unsafe fn Q6_Vb_vmin_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
4295    vminb(vu, vv)
4296}
4297
4298/// `Vdd32.w=vmpa(Vuu32.uh,Rt32.b)`
4299///
4300/// Instruction Type: CVI_VX_DV
4301/// Execution Slots: SLOT23
4302#[inline]
4303#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
4304#[cfg_attr(test, assert_instr(vmpauhb))]
4305#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4306pub unsafe fn Q6_Ww_vmpa_WuhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
4307    vmpauhb(vuu, rt)
4308}
4309
4310/// `Vxx32.w+=vmpa(Vuu32.uh,Rt32.b)`
4311///
4312/// Instruction Type: CVI_VX_DV
4313/// Execution Slots: SLOT23
4314#[inline]
4315#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
4316#[cfg_attr(test, assert_instr(vmpauhb_acc))]
4317#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4318pub unsafe fn Q6_Ww_vmpaacc_WwWuhRb(
4319    vxx: HvxVectorPair,
4320    vuu: HvxVectorPair,
4321    rt: i32,
4322) -> HvxVectorPair {
4323    vmpauhb_acc(vxx, vuu, rt)
4324}
4325
4326/// `Vdd32=vmpye(Vu32.w,Vv32.uh)`
4327///
4328/// Instruction Type: CVI_VX_DV
4329/// Execution Slots: SLOT23
4330#[inline]
4331#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
4332#[cfg_attr(test, assert_instr(vmpyewuh_64))]
4333#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4334pub unsafe fn Q6_W_vmpye_VwVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
4335    vmpyewuh_64(vu, vv)
4336}
4337
4338/// `Vd32.w=vmpyi(Vu32.w,Rt32.ub)`
4339///
4340/// Instruction Type: CVI_VX
4341/// Execution Slots: SLOT23
4342#[inline]
4343#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
4344#[cfg_attr(test, assert_instr(vmpyiwub))]
4345#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4346pub unsafe fn Q6_Vw_vmpyi_VwRub(vu: HvxVector, rt: i32) -> HvxVector {
4347    vmpyiwub(vu, rt)
4348}
4349
4350/// `Vx32.w+=vmpyi(Vu32.w,Rt32.ub)`
4351///
4352/// Instruction Type: CVI_VX
4353/// Execution Slots: SLOT23
4354#[inline]
4355#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
4356#[cfg_attr(test, assert_instr(vmpyiwub_acc))]
4357#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4358pub unsafe fn Q6_Vw_vmpyiacc_VwVwRub(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
4359    vmpyiwub_acc(vx, vu, rt)
4360}
4361
4362/// `Vxx32+=vmpyo(Vu32.w,Vv32.h)`
4363///
4364/// Instruction Type: CVI_VX_DV
4365/// Execution Slots: SLOT23
4366#[inline]
4367#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
4368#[cfg_attr(test, assert_instr(vmpyowh_64_acc))]
4369#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4370pub unsafe fn Q6_W_vmpyoacc_WVwVh(
4371    vxx: HvxVectorPair,
4372    vu: HvxVector,
4373    vv: HvxVector,
4374) -> HvxVectorPair {
4375    vmpyowh_64_acc(vxx, vu, vv)
4376}
4377
4378/// `Vd32.ub=vround(Vu32.uh,Vv32.uh):sat`
4379///
4380/// Instruction Type: CVI_VS
4381/// Execution Slots: SLOT0123
4382#[inline]
4383#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
4384#[cfg_attr(test, assert_instr(vrounduhub))]
4385#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4386pub unsafe fn Q6_Vub_vround_VuhVuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
4387    vrounduhub(vu, vv)
4388}
4389
4390/// `Vd32.uh=vround(Vu32.uw,Vv32.uw):sat`
4391///
4392/// Instruction Type: CVI_VS
4393/// Execution Slots: SLOT0123
4394#[inline]
4395#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
4396#[cfg_attr(test, assert_instr(vrounduwuh))]
4397#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4398pub unsafe fn Q6_Vuh_vround_VuwVuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
4399    vrounduwuh(vu, vv)
4400}
4401
4402/// `Vd32.uh=vsat(Vu32.uw,Vv32.uw)`
4403///
4404/// Instruction Type: CVI_VA
4405/// Execution Slots: SLOT0123
4406#[inline]
4407#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
4408#[cfg_attr(test, assert_instr(vsatuwuh))]
4409#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4410pub unsafe fn Q6_Vuh_vsat_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVector {
4411    vsatuwuh(vu, vv)
4412}
4413
4414/// `Vd32.b=vsub(Vu32.b,Vv32.b):sat`
4415///
4416/// Instruction Type: CVI_VA
4417/// Execution Slots: SLOT0123
4418#[inline]
4419#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
4420#[cfg_attr(test, assert_instr(vsubbsat))]
4421#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4422pub unsafe fn Q6_Vb_vsub_VbVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
4423    vsubbsat(vu, vv)
4424}
4425
4426/// `Vdd32.b=vsub(Vuu32.b,Vvv32.b):sat`
4427///
4428/// Instruction Type: CVI_VA_DV
4429/// Execution Slots: SLOT0123
4430#[inline]
4431#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
4432#[cfg_attr(test, assert_instr(vsubbsat_dv))]
4433#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4434pub unsafe fn Q6_Wb_vsub_WbWb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
4435    vsubbsat_dv(vuu, vvv)
4436}
4437
4438/// `Vd32.ub=vsub(Vu32.ub,Vv32.b):sat`
4439///
4440/// Instruction Type: CVI_VA
4441/// Execution Slots: SLOT0123
4442#[inline]
4443#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
4444#[cfg_attr(test, assert_instr(vsubububb_sat))]
4445#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4446pub unsafe fn Q6_Vub_vsub_VubVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
4447    vsubububb_sat(vu, vv)
4448}
4449
4450/// `Vd32.uw=vsub(Vu32.uw,Vv32.uw):sat`
4451///
4452/// Instruction Type: CVI_VA
4453/// Execution Slots: SLOT0123
4454#[inline]
4455#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
4456#[cfg_attr(test, assert_instr(vsubuwsat))]
4457#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4458pub unsafe fn Q6_Vuw_vsub_VuwVuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
4459    vsubuwsat(vu, vv)
4460}
4461
4462/// `Vdd32.uw=vsub(Vuu32.uw,Vvv32.uw):sat`
4463///
4464/// Instruction Type: CVI_VA_DV
4465/// Execution Slots: SLOT0123
4466#[inline]
4467#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
4468#[cfg_attr(test, assert_instr(vsubuwsat_dv))]
4469#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4470pub unsafe fn Q6_Wuw_vsub_WuwWuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
4471    vsubuwsat_dv(vuu, vvv)
4472}
4473
4474/// `Vd32.b=vabs(Vu32.b)`
4475///
4476/// Instruction Type: CVI_VA
4477/// Execution Slots: SLOT0123
4478#[inline]
4479#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
4480#[cfg_attr(test, assert_instr(vabsb))]
4481#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4482pub unsafe fn Q6_Vb_vabs_Vb(vu: HvxVector) -> HvxVector {
4483    vabsb(vu)
4484}
4485
4486/// `Vd32.b=vabs(Vu32.b):sat`
4487///
4488/// Instruction Type: CVI_VA
4489/// Execution Slots: SLOT0123
4490#[inline]
4491#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
4492#[cfg_attr(test, assert_instr(vabsb_sat))]
4493#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4494pub unsafe fn Q6_Vb_vabs_Vb_sat(vu: HvxVector) -> HvxVector {
4495    vabsb_sat(vu)
4496}
4497
4498/// `Vx32.h+=vasl(Vu32.h,Rt32)`
4499///
4500/// Instruction Type: CVI_VS
4501/// Execution Slots: SLOT0123
4502#[inline]
4503#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
4504#[cfg_attr(test, assert_instr(vaslh_acc))]
4505#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4506pub unsafe fn Q6_Vh_vaslacc_VhVhR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
4507    vaslh_acc(vx, vu, rt)
4508}
4509
4510/// `Vx32.h+=vasr(Vu32.h,Rt32)`
4511///
4512/// Instruction Type: CVI_VS
4513/// Execution Slots: SLOT0123
4514#[inline]
4515#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
4516#[cfg_attr(test, assert_instr(vasrh_acc))]
4517#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4518pub unsafe fn Q6_Vh_vasracc_VhVhR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
4519    vasrh_acc(vx, vu, rt)
4520}
4521
4522/// `Vd32.ub=vasr(Vu32.uh,Vv32.uh,Rt8):rnd:sat`
4523///
4524/// Instruction Type: CVI_VS
4525/// Execution Slots: SLOT0123
4526#[inline]
4527#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
4528#[cfg_attr(test, assert_instr(vasruhubrndsat))]
4529#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4530pub unsafe fn Q6_Vub_vasr_VuhVuhR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
4531    vasruhubrndsat(vu, vv, rt)
4532}
4533
4534/// `Vd32.ub=vasr(Vu32.uh,Vv32.uh,Rt8):sat`
4535///
4536/// Instruction Type: CVI_VS
4537/// Execution Slots: SLOT0123
4538#[inline]
4539#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
4540#[cfg_attr(test, assert_instr(vasruhubsat))]
4541#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4542pub unsafe fn Q6_Vub_vasr_VuhVuhR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
4543    vasruhubsat(vu, vv, rt)
4544}
4545
4546/// `Vd32.uh=vasr(Vu32.uw,Vv32.uw,Rt8):sat`
4547///
4548/// Instruction Type: CVI_VS
4549/// Execution Slots: SLOT0123
4550#[inline]
4551#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
4552#[cfg_attr(test, assert_instr(vasruwuhsat))]
4553#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4554pub unsafe fn Q6_Vuh_vasr_VuwVuwR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
4555    vasruwuhsat(vu, vv, rt)
4556}
4557
4558/// `Vd32.b=vavg(Vu32.b,Vv32.b)`
4559///
4560/// Instruction Type: CVI_VA
4561/// Execution Slots: SLOT0123
4562#[inline]
4563#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
4564#[cfg_attr(test, assert_instr(vavgb))]
4565#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4566pub unsafe fn Q6_Vb_vavg_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
4567    vavgb(vu, vv)
4568}
4569
4570/// `Vd32.b=vavg(Vu32.b,Vv32.b):rnd`
4571///
4572/// Instruction Type: CVI_VA
4573/// Execution Slots: SLOT0123
4574#[inline]
4575#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
4576#[cfg_attr(test, assert_instr(vavgbrnd))]
4577#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4578pub unsafe fn Q6_Vb_vavg_VbVb_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
4579    vavgbrnd(vu, vv)
4580}
4581
4582/// `Vd32.uw=vavg(Vu32.uw,Vv32.uw)`
4583///
4584/// Instruction Type: CVI_VA
4585/// Execution Slots: SLOT0123
4586#[inline]
4587#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
4588#[cfg_attr(test, assert_instr(vavguw))]
4589#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4590pub unsafe fn Q6_Vuw_vavg_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVector {
4591    vavguw(vu, vv)
4592}
4593
4594/// `Vd32.uw=vavg(Vu32.uw,Vv32.uw):rnd`
4595///
4596/// Instruction Type: CVI_VA
4597/// Execution Slots: SLOT0123
4598#[inline]
4599#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
4600#[cfg_attr(test, assert_instr(vavguwrnd))]
4601#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4602pub unsafe fn Q6_Vuw_vavg_VuwVuw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
4603    vavguwrnd(vu, vv)
4604}
4605
4606/// `Vdd32=#0`
4607///
4608/// Instruction Type: MAPPING
4609/// Execution Slots: SLOT0123
4610#[inline]
4611#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
4612#[cfg_attr(test, assert_instr(vdd0))]
4613#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4614pub unsafe fn Q6_W_vzero() -> HvxVectorPair {
4615    vdd0()
4616}
4617
4618/// `vtmp.h=vgather(Rt32,Mu2,Vv32.h).h`
4619///
4620/// Instruction Type: CVI_GATHER
4621/// Execution Slots: SLOT01
4622#[inline]
4623#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
4624#[cfg_attr(test, assert_instr(vgathermh))]
4625#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4626pub unsafe fn Q6_vgather_ARMVh(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVector) {
4627    vgathermh(rs, rt, mu, vv)
4628}
4629
4630/// `vtmp.h=vgather(Rt32,Mu2,Vvv32.w).h`
4631///
4632/// Instruction Type: CVI_GATHER_DV
4633/// Execution Slots: SLOT01
4634#[inline]
4635#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
4636#[cfg_attr(test, assert_instr(vgathermhw))]
4637#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4638pub unsafe fn Q6_vgather_ARMWw(rs: *mut HvxVector, rt: i32, mu: i32, vvv: HvxVectorPair) {
4639    vgathermhw(rs, rt, mu, vvv)
4640}
4641
4642/// `vtmp.w=vgather(Rt32,Mu2,Vv32.w).w`
4643///
4644/// Instruction Type: CVI_GATHER
4645/// Execution Slots: SLOT01
4646#[inline]
4647#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
4648#[cfg_attr(test, assert_instr(vgathermw))]
4649#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4650pub unsafe fn Q6_vgather_ARMVw(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVector) {
4651    vgathermw(rs, rt, mu, vv)
4652}
4653
4654/// `Vdd32.h=vmpa(Vuu32.ub,Rt32.ub)`
4655///
4656/// Instruction Type: CVI_VX_DV
4657/// Execution Slots: SLOT23
4658#[inline]
4659#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
4660#[cfg_attr(test, assert_instr(vmpabuu))]
4661#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4662pub unsafe fn Q6_Wh_vmpa_WubRub(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
4663    vmpabuu(vuu, rt)
4664}
4665
4666/// `Vxx32.h+=vmpa(Vuu32.ub,Rt32.ub)`
4667///
4668/// Instruction Type: CVI_VX_DV
4669/// Execution Slots: SLOT23
4670#[inline]
4671#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
4672#[cfg_attr(test, assert_instr(vmpabuu_acc))]
4673#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4674pub unsafe fn Q6_Wh_vmpaacc_WhWubRub(
4675    vxx: HvxVectorPair,
4676    vuu: HvxVectorPair,
4677    rt: i32,
4678) -> HvxVectorPair {
4679    vmpabuu_acc(vxx, vuu, rt)
4680}
4681
4682/// `Vxx32.w+=vmpy(Vu32.h,Rt32.h)`
4683///
4684/// Instruction Type: CVI_VX_DV
4685/// Execution Slots: SLOT23
4686#[inline]
4687#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
4688#[cfg_attr(test, assert_instr(vmpyh_acc))]
4689#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4690pub unsafe fn Q6_Ww_vmpyacc_WwVhRh(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -> HvxVectorPair {
4691    vmpyh_acc(vxx, vu, rt)
4692}
4693
4694/// `Vd32.uw=vmpye(Vu32.uh,Rt32.uh)`
4695///
4696/// Instruction Type: CVI_VX
4697/// Execution Slots: SLOT23
4698#[inline]
4699#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
4700#[cfg_attr(test, assert_instr(vmpyuhe))]
4701#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4702pub unsafe fn Q6_Vuw_vmpye_VuhRuh(vu: HvxVector, rt: i32) -> HvxVector {
4703    vmpyuhe(vu, rt)
4704}
4705
4706/// `Vx32.uw+=vmpye(Vu32.uh,Rt32.uh)`
4707///
4708/// Instruction Type: CVI_VX
4709/// Execution Slots: SLOT23
4710#[inline]
4711#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
4712#[cfg_attr(test, assert_instr(vmpyuhe_acc))]
4713#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4714pub unsafe fn Q6_Vuw_vmpyeacc_VuwVuhRuh(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
4715    vmpyuhe_acc(vx, vu, rt)
4716}
4717
4718/// `Vd32.b=vnavg(Vu32.b,Vv32.b)`
4719///
4720/// Instruction Type: CVI_VA
4721/// Execution Slots: SLOT0123
4722#[inline]
4723#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
4724#[cfg_attr(test, assert_instr(vnavgb))]
4725#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4726pub unsafe fn Q6_Vb_vnavg_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
4727    vnavgb(vu, vv)
4728}
4729
4730/// `vscatter(Rt32,Mu2,Vv32.h).h=Vw32`
4731///
4732/// Instruction Type: CVI_SCATTER
4733/// Execution Slots: SLOT0
4734#[inline]
4735#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
4736#[cfg_attr(test, assert_instr(vscattermh))]
4737#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4738pub unsafe fn Q6_vscatter_RMVhV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) {
4739    vscattermh(rt, mu, vv, vw)
4740}
4741
4742/// `vscatter(Rt32,Mu2,Vv32.h).h+=Vw32`
4743///
4744/// Instruction Type: CVI_SCATTER
4745/// Execution Slots: SLOT0
4746#[inline]
4747#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
4748#[cfg_attr(test, assert_instr(vscattermh_add))]
4749#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4750pub unsafe fn Q6_vscatteracc_RMVhV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) {
4751    vscattermh_add(rt, mu, vv, vw)
4752}
4753
4754/// `vscatter(Rt32,Mu2,Vvv32.w).h=Vw32`
4755///
4756/// Instruction Type: CVI_SCATTER_DV
4757/// Execution Slots: SLOT0
4758#[inline]
4759#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
4760#[cfg_attr(test, assert_instr(vscattermhw))]
4761#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4762pub unsafe fn Q6_vscatter_RMWwV(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVector) {
4763    vscattermhw(rt, mu, vvv, vw)
4764}
4765
4766/// `vscatter(Rt32,Mu2,Vvv32.w).h+=Vw32`
4767///
4768/// Instruction Type: CVI_SCATTER_DV
4769/// Execution Slots: SLOT0
4770#[inline]
4771#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
4772#[cfg_attr(test, assert_instr(vscattermhw_add))]
4773#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4774pub unsafe fn Q6_vscatteracc_RMWwV(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVector) {
4775    vscattermhw_add(rt, mu, vvv, vw)
4776}
4777
4778/// `vscatter(Rt32,Mu2,Vv32.w).w=Vw32`
4779///
4780/// Instruction Type: CVI_SCATTER
4781/// Execution Slots: SLOT0
4782#[inline]
4783#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
4784#[cfg_attr(test, assert_instr(vscattermw))]
4785#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4786pub unsafe fn Q6_vscatter_RMVwV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) {
4787    vscattermw(rt, mu, vv, vw)
4788}
4789
4790/// `vscatter(Rt32,Mu2,Vv32.w).w+=Vw32`
4791///
4792/// Instruction Type: CVI_SCATTER
4793/// Execution Slots: SLOT0
4794#[inline]
4795#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
4796#[cfg_attr(test, assert_instr(vscattermw_add))]
4797#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4798pub unsafe fn Q6_vscatteracc_RMVwV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) {
4799    vscattermw_add(rt, mu, vv, vw)
4800}
4801
4802/// `Vxx32.w=vasrinto(Vu32.w,Vv32.w)`
4803///
4804/// Instruction Type: CVI_VP_VS
4805/// Execution Slots: SLOT0123
4806#[inline]
4807#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))]
4808#[cfg_attr(test, assert_instr(vasr_into))]
4809#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4810pub unsafe fn Q6_Ww_vasrinto_WwVwVw(
4811    vxx: HvxVectorPair,
4812    vu: HvxVector,
4813    vv: HvxVector,
4814) -> HvxVectorPair {
4815    vasr_into(vxx, vu, vv)
4816}
4817
4818/// `Vd32.uw=vrotr(Vu32.uw,Vv32.uw)`
4819///
4820/// Instruction Type: CVI_VS
4821/// Execution Slots: SLOT0123
4822#[inline]
4823#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))]
4824#[cfg_attr(test, assert_instr(vrotr))]
4825#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4826pub unsafe fn Q6_Vuw_vrotr_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVector {
4827    vrotr(vu, vv)
4828}
4829
4830/// `Vd32.w=vsatdw(Vu32.w,Vv32.w)`
4831///
4832/// Instruction Type: CVI_VA
4833/// Execution Slots: SLOT0123
4834#[inline]
4835#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))]
4836#[cfg_attr(test, assert_instr(vsatdw))]
4837#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4838pub unsafe fn Q6_Vw_vsatdw_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
4839    vsatdw(vu, vv)
4840}
4841
4842/// `Vdd32.w=v6mpy(Vuu32.ub,Vvv32.b,#u2):h`
4843///
4844/// Instruction Type: CVI_VX_DV
4845/// Execution Slots: SLOT23
4846#[inline]
4847#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
4848#[cfg_attr(test, assert_instr(v6mpyhubs10))]
4849#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4850pub unsafe fn Q6_Ww_v6mpy_WubWbI_h(
4851    vuu: HvxVectorPair,
4852    vvv: HvxVectorPair,
4853    iu2: i32,
4854) -> HvxVectorPair {
4855    v6mpyhubs10(vuu, vvv, iu2)
4856}
4857
4858/// `Vxx32.w+=v6mpy(Vuu32.ub,Vvv32.b,#u2):h`
4859///
4860/// Instruction Type: CVI_VX_DV
4861/// Execution Slots: SLOT23
4862#[inline]
4863#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
4864#[cfg_attr(test, assert_instr(v6mpyhubs10_vxx))]
4865#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4866pub unsafe fn Q6_Ww_v6mpyacc_WwWubWbI_h(
4867    vxx: HvxVectorPair,
4868    vuu: HvxVectorPair,
4869    vvv: HvxVectorPair,
4870    iu2: i32,
4871) -> HvxVectorPair {
4872    v6mpyhubs10_vxx(vxx, vuu, vvv, iu2)
4873}
4874
4875/// `Vdd32.w=v6mpy(Vuu32.ub,Vvv32.b,#u2):v`
4876///
4877/// Instruction Type: CVI_VX_DV
4878/// Execution Slots: SLOT23
4879#[inline]
4880#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
4881#[cfg_attr(test, assert_instr(v6mpyvubs10))]
4882#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4883pub unsafe fn Q6_Ww_v6mpy_WubWbI_v(
4884    vuu: HvxVectorPair,
4885    vvv: HvxVectorPair,
4886    iu2: i32,
4887) -> HvxVectorPair {
4888    v6mpyvubs10(vuu, vvv, iu2)
4889}
4890
4891/// `Vxx32.w+=v6mpy(Vuu32.ub,Vvv32.b,#u2):v`
4892///
4893/// Instruction Type: CVI_VX_DV
4894/// Execution Slots: SLOT23
4895#[inline]
4896#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
4897#[cfg_attr(test, assert_instr(v6mpyvubs10_vxx))]
4898#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4899pub unsafe fn Q6_Ww_v6mpyacc_WwWubWbI_v(
4900    vxx: HvxVectorPair,
4901    vuu: HvxVectorPair,
4902    vvv: HvxVectorPair,
4903    iu2: i32,
4904) -> HvxVectorPair {
4905    v6mpyvubs10_vxx(vxx, vuu, vvv, iu2)
4906}
4907
4908/// `Vd32.hf=vabs(Vu32.hf)`
4909///
4910/// Instruction Type: CVI_VX_LATE
4911/// Execution Slots: SLOT23
4912#[inline]
4913#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
4914#[cfg_attr(test, assert_instr(vabs_hf))]
4915#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4916pub unsafe fn Q6_Vhf_vabs_Vhf(vu: HvxVector) -> HvxVector {
4917    vabs_hf(vu)
4918}
4919
4920/// `Vd32.sf=vabs(Vu32.sf)`
4921///
4922/// Instruction Type: CVI_VX_LATE
4923/// Execution Slots: SLOT23
4924#[inline]
4925#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
4926#[cfg_attr(test, assert_instr(vabs_sf))]
4927#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4928pub unsafe fn Q6_Vsf_vabs_Vsf(vu: HvxVector) -> HvxVector {
4929    vabs_sf(vu)
4930}
4931
4932/// `Vd32.qf16=vadd(Vu32.hf,Vv32.hf)`
4933///
4934/// Instruction Type: CVI_VS
4935/// Execution Slots: SLOT0123
4936#[inline]
4937#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
4938#[cfg_attr(test, assert_instr(vadd_hf))]
4939#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4940pub unsafe fn Q6_Vqf16_vadd_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
4941    vadd_hf(vu, vv)
4942}
4943
4944/// `Vd32.hf=vadd(Vu32.hf,Vv32.hf)`
4945///
4946/// Instruction Type: CVI_VX
4947/// Execution Slots: SLOT23
4948#[inline]
4949#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
4950#[cfg_attr(test, assert_instr(vadd_hf_hf))]
4951#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4952pub unsafe fn Q6_Vhf_vadd_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
4953    vadd_hf_hf(vu, vv)
4954}
4955
4956/// `Vd32.qf16=vadd(Vu32.qf16,Vv32.qf16)`
4957///
4958/// Instruction Type: CVI_VS
4959/// Execution Slots: SLOT0123
4960#[inline]
4961#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
4962#[cfg_attr(test, assert_instr(vadd_qf16))]
4963#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4964pub unsafe fn Q6_Vqf16_vadd_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector {
4965    vadd_qf16(vu, vv)
4966}
4967
4968/// `Vd32.qf16=vadd(Vu32.qf16,Vv32.hf)`
4969///
4970/// Instruction Type: CVI_VS
4971/// Execution Slots: SLOT0123
4972#[inline]
4973#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
4974#[cfg_attr(test, assert_instr(vadd_qf16_mix))]
4975#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4976pub unsafe fn Q6_Vqf16_vadd_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
4977    vadd_qf16_mix(vu, vv)
4978}
4979
4980/// `Vd32.qf32=vadd(Vu32.qf32,Vv32.qf32)`
4981///
4982/// Instruction Type: CVI_VS
4983/// Execution Slots: SLOT0123
4984#[inline]
4985#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
4986#[cfg_attr(test, assert_instr(vadd_qf32))]
4987#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4988pub unsafe fn Q6_Vqf32_vadd_Vqf32Vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector {
4989    vadd_qf32(vu, vv)
4990}
4991
4992/// `Vd32.qf32=vadd(Vu32.qf32,Vv32.sf)`
4993///
4994/// Instruction Type: CVI_VS
4995/// Execution Slots: SLOT0123
4996#[inline]
4997#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
4998#[cfg_attr(test, assert_instr(vadd_qf32_mix))]
4999#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5000pub unsafe fn Q6_Vqf32_vadd_Vqf32Vsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
5001    vadd_qf32_mix(vu, vv)
5002}
5003
5004/// `Vd32.qf32=vadd(Vu32.sf,Vv32.sf)`
5005///
5006/// Instruction Type: CVI_VS
5007/// Execution Slots: SLOT0123
5008#[inline]
5009#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5010#[cfg_attr(test, assert_instr(vadd_sf))]
5011#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5012pub unsafe fn Q6_Vqf32_vadd_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
5013    vadd_sf(vu, vv)
5014}
5015
5016/// `Vdd32.sf=vadd(Vu32.hf,Vv32.hf)`
5017///
5018/// Instruction Type: CVI_VX_DV
5019/// Execution Slots: SLOT23
5020#[inline]
5021#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5022#[cfg_attr(test, assert_instr(vadd_sf_hf))]
5023#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5024pub unsafe fn Q6_Wsf_vadd_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
5025    vadd_sf_hf(vu, vv)
5026}
5027
5028/// `Vd32.sf=vadd(Vu32.sf,Vv32.sf)`
5029///
5030/// Instruction Type: CVI_VX
5031/// Execution Slots: SLOT23
5032#[inline]
5033#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5034#[cfg_attr(test, assert_instr(vadd_sf_sf))]
5035#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5036pub unsafe fn Q6_Vsf_vadd_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
5037    vadd_sf_sf(vu, vv)
5038}
5039
5040/// `Vd32.w=vfmv(Vu32.w)`
5041///
5042/// Instruction Type: CVI_VX_LATE
5043/// Execution Slots: SLOT23
5044#[inline]
5045#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5046#[cfg_attr(test, assert_instr(vassign_fp))]
5047#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5048pub unsafe fn Q6_Vw_vfmv_Vw(vu: HvxVector) -> HvxVector {
5049    vassign_fp(vu)
5050}
5051
5052/// `Vd32.hf=Vu32.qf16`
5053///
5054/// Instruction Type: CVI_VS
5055/// Execution Slots: SLOT0123
5056#[inline]
5057#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5058#[cfg_attr(test, assert_instr(vconv_hf_qf16))]
5059#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5060pub unsafe fn Q6_Vhf_equals_Vqf16(vu: HvxVector) -> HvxVector {
5061    vconv_hf_qf16(vu)
5062}
5063
5064/// `Vd32.hf=Vuu32.qf32`
5065///
5066/// Instruction Type: CVI_VS
5067/// Execution Slots: SLOT0123
5068#[inline]
5069#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5070#[cfg_attr(test, assert_instr(vconv_hf_qf32))]
5071#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5072pub unsafe fn Q6_Vhf_equals_Wqf32(vuu: HvxVectorPair) -> HvxVector {
5073    vconv_hf_qf32(vuu)
5074}
5075
5076/// `Vd32.sf=Vu32.qf32`
5077///
5078/// Instruction Type: CVI_VS
5079/// Execution Slots: SLOT0123
5080#[inline]
5081#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5082#[cfg_attr(test, assert_instr(vconv_sf_qf32))]
5083#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5084pub unsafe fn Q6_Vsf_equals_Vqf32(vu: HvxVector) -> HvxVector {
5085    vconv_sf_qf32(vu)
5086}
5087
5088/// `Vd32.b=vcvt(Vu32.hf,Vv32.hf)`
5089///
5090/// Instruction Type: CVI_VX
5091/// Execution Slots: SLOT23
5092#[inline]
5093#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5094#[cfg_attr(test, assert_instr(vcvt_b_hf))]
5095#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5096pub unsafe fn Q6_Vb_vcvt_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
5097    vcvt_b_hf(vu, vv)
5098}
5099
5100/// `Vd32.h=vcvt(Vu32.hf)`
5101///
5102/// Instruction Type: CVI_VX
5103/// Execution Slots: SLOT23
5104#[inline]
5105#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5106#[cfg_attr(test, assert_instr(vcvt_h_hf))]
5107#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5108pub unsafe fn Q6_Vh_vcvt_Vhf(vu: HvxVector) -> HvxVector {
5109    vcvt_h_hf(vu)
5110}
5111
5112/// `Vdd32.hf=vcvt(Vu32.b)`
5113///
5114/// Instruction Type: CVI_VX_DV
5115/// Execution Slots: SLOT23
5116#[inline]
5117#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5118#[cfg_attr(test, assert_instr(vcvt_hf_b))]
5119#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5120pub unsafe fn Q6_Whf_vcvt_Vb(vu: HvxVector) -> HvxVectorPair {
5121    vcvt_hf_b(vu)
5122}
5123
5124/// `Vd32.hf=vcvt(Vu32.h)`
5125///
5126/// Instruction Type: CVI_VX
5127/// Execution Slots: SLOT23
5128#[inline]
5129#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5130#[cfg_attr(test, assert_instr(vcvt_hf_h))]
5131#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5132pub unsafe fn Q6_Vhf_vcvt_Vh(vu: HvxVector) -> HvxVector {
5133    vcvt_hf_h(vu)
5134}
5135
5136/// `Vd32.hf=vcvt(Vu32.sf,Vv32.sf)`
5137///
5138/// Instruction Type: CVI_VX
5139/// Execution Slots: SLOT23
5140#[inline]
5141#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5142#[cfg_attr(test, assert_instr(vcvt_hf_sf))]
5143#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5144pub unsafe fn Q6_Vhf_vcvt_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
5145    vcvt_hf_sf(vu, vv)
5146}
5147
5148/// `Vdd32.hf=vcvt(Vu32.ub)`
5149///
5150/// Instruction Type: CVI_VX_DV
5151/// Execution Slots: SLOT23
5152#[inline]
5153#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5154#[cfg_attr(test, assert_instr(vcvt_hf_ub))]
5155#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5156pub unsafe fn Q6_Whf_vcvt_Vub(vu: HvxVector) -> HvxVectorPair {
5157    vcvt_hf_ub(vu)
5158}
5159
5160/// `Vd32.hf=vcvt(Vu32.uh)`
5161///
5162/// Instruction Type: CVI_VX
5163/// Execution Slots: SLOT23
5164#[inline]
5165#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5166#[cfg_attr(test, assert_instr(vcvt_hf_uh))]
5167#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5168pub unsafe fn Q6_Vhf_vcvt_Vuh(vu: HvxVector) -> HvxVector {
5169    vcvt_hf_uh(vu)
5170}
5171
5172/// `Vdd32.sf=vcvt(Vu32.hf)`
5173///
5174/// Instruction Type: CVI_VX_DV
5175/// Execution Slots: SLOT23
5176#[inline]
5177#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5178#[cfg_attr(test, assert_instr(vcvt_sf_hf))]
5179#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5180pub unsafe fn Q6_Wsf_vcvt_Vhf(vu: HvxVector) -> HvxVectorPair {
5181    vcvt_sf_hf(vu)
5182}
5183
5184/// `Vd32.ub=vcvt(Vu32.hf,Vv32.hf)`
5185///
5186/// Instruction Type: CVI_VX
5187/// Execution Slots: SLOT23
5188#[inline]
5189#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5190#[cfg_attr(test, assert_instr(vcvt_ub_hf))]
5191#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5192pub unsafe fn Q6_Vub_vcvt_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
5193    vcvt_ub_hf(vu, vv)
5194}
5195
5196/// `Vd32.uh=vcvt(Vu32.hf)`
5197///
5198/// Instruction Type: CVI_VX
5199/// Execution Slots: SLOT23
5200#[inline]
5201#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5202#[cfg_attr(test, assert_instr(vcvt_uh_hf))]
5203#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5204pub unsafe fn Q6_Vuh_vcvt_Vhf(vu: HvxVector) -> HvxVector {
5205    vcvt_uh_hf(vu)
5206}
5207
5208/// `Vd32.sf=vdmpy(Vu32.hf,Vv32.hf)`
5209///
5210/// Instruction Type: CVI_VX
5211/// Execution Slots: SLOT23
5212#[inline]
5213#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5214#[cfg_attr(test, assert_instr(vdmpy_sf_hf))]
5215#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5216pub unsafe fn Q6_Vsf_vdmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
5217    vdmpy_sf_hf(vu, vv)
5218}
5219
5220/// `Vx32.sf+=vdmpy(Vu32.hf,Vv32.hf)`
5221///
5222/// Instruction Type: CVI_VX
5223/// Execution Slots: SLOT23
5224#[inline]
5225#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5226#[cfg_attr(test, assert_instr(vdmpy_sf_hf_acc))]
5227#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5228pub unsafe fn Q6_Vsf_vdmpyacc_VsfVhfVhf(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
5229    vdmpy_sf_hf_acc(vx, vu, vv)
5230}
5231
5232/// `Vd32.hf=vfmax(Vu32.hf,Vv32.hf)`
5233///
5234/// Instruction Type: CVI_VX_LATE
5235/// Execution Slots: SLOT23
5236#[inline]
5237#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5238#[cfg_attr(test, assert_instr(vfmax_hf))]
5239#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5240pub unsafe fn Q6_Vhf_vfmax_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
5241    vfmax_hf(vu, vv)
5242}
5243
5244/// `Vd32.sf=vfmax(Vu32.sf,Vv32.sf)`
5245///
5246/// Instruction Type: CVI_VX_LATE
5247/// Execution Slots: SLOT23
5248#[inline]
5249#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5250#[cfg_attr(test, assert_instr(vfmax_sf))]
5251#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5252pub unsafe fn Q6_Vsf_vfmax_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
5253    vfmax_sf(vu, vv)
5254}
5255
5256/// `Vd32.hf=vfmin(Vu32.hf,Vv32.hf)`
5257///
5258/// Instruction Type: CVI_VX_LATE
5259/// Execution Slots: SLOT23
5260#[inline]
5261#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5262#[cfg_attr(test, assert_instr(vfmin_hf))]
5263#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5264pub unsafe fn Q6_Vhf_vfmin_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
5265    vfmin_hf(vu, vv)
5266}
5267
5268/// `Vd32.sf=vfmin(Vu32.sf,Vv32.sf)`
5269///
5270/// Instruction Type: CVI_VX_LATE
5271/// Execution Slots: SLOT23
5272#[inline]
5273#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5274#[cfg_attr(test, assert_instr(vfmin_sf))]
5275#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5276pub unsafe fn Q6_Vsf_vfmin_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
5277    vfmin_sf(vu, vv)
5278}
5279
5280/// `Vd32.hf=vfneg(Vu32.hf)`
5281///
5282/// Instruction Type: CVI_VX_LATE
5283/// Execution Slots: SLOT23
5284#[inline]
5285#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5286#[cfg_attr(test, assert_instr(vfneg_hf))]
5287#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5288pub unsafe fn Q6_Vhf_vfneg_Vhf(vu: HvxVector) -> HvxVector {
5289    vfneg_hf(vu)
5290}
5291
5292/// `Vd32.sf=vfneg(Vu32.sf)`
5293///
5294/// Instruction Type: CVI_VX_LATE
5295/// Execution Slots: SLOT23
5296#[inline]
5297#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5298#[cfg_attr(test, assert_instr(vfneg_sf))]
5299#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5300pub unsafe fn Q6_Vsf_vfneg_Vsf(vu: HvxVector) -> HvxVector {
5301    vfneg_sf(vu)
5302}
5303
5304/// `Vd32.hf=vmax(Vu32.hf,Vv32.hf)`
5305///
5306/// Instruction Type: CVI_VA
5307/// Execution Slots: SLOT0123
5308#[inline]
5309#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5310#[cfg_attr(test, assert_instr(vmax_hf))]
5311#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5312pub unsafe fn Q6_Vhf_vmax_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
5313    vmax_hf(vu, vv)
5314}
5315
5316/// `Vd32.sf=vmax(Vu32.sf,Vv32.sf)`
5317///
5318/// Instruction Type: CVI_VA
5319/// Execution Slots: SLOT0123
5320#[inline]
5321#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5322#[cfg_attr(test, assert_instr(vmax_sf))]
5323#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5324pub unsafe fn Q6_Vsf_vmax_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
5325    vmax_sf(vu, vv)
5326}
5327
5328/// `Vd32.hf=vmin(Vu32.hf,Vv32.hf)`
5329///
5330/// Instruction Type: CVI_VA
5331/// Execution Slots: SLOT0123
5332#[inline]
5333#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5334#[cfg_attr(test, assert_instr(vmin_hf))]
5335#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5336pub unsafe fn Q6_Vhf_vmin_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
5337    vmin_hf(vu, vv)
5338}
5339
5340/// `Vd32.sf=vmin(Vu32.sf,Vv32.sf)`
5341///
5342/// Instruction Type: CVI_VA
5343/// Execution Slots: SLOT0123
5344#[inline]
5345#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5346#[cfg_attr(test, assert_instr(vmin_sf))]
5347#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5348pub unsafe fn Q6_Vsf_vmin_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
5349    vmin_sf(vu, vv)
5350}
5351
5352/// `Vd32.hf=vmpy(Vu32.hf,Vv32.hf)`
5353///
5354/// Instruction Type: CVI_VX
5355/// Execution Slots: SLOT23
5356#[inline]
5357#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5358#[cfg_attr(test, assert_instr(vmpy_hf_hf))]
5359#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5360pub unsafe fn Q6_Vhf_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
5361    vmpy_hf_hf(vu, vv)
5362}
5363
5364/// `Vx32.hf+=vmpy(Vu32.hf,Vv32.hf)`
5365///
5366/// Instruction Type: CVI_VX
5367/// Execution Slots: SLOT23
5368#[inline]
5369#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5370#[cfg_attr(test, assert_instr(vmpy_hf_hf_acc))]
5371#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5372pub unsafe fn Q6_Vhf_vmpyacc_VhfVhfVhf(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
5373    vmpy_hf_hf_acc(vx, vu, vv)
5374}
5375
5376/// `Vd32.qf16=vmpy(Vu32.qf16,Vv32.qf16)`
5377///
5378/// Instruction Type: CVI_VX_DV
5379/// Execution Slots: SLOT23
5380#[inline]
5381#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5382#[cfg_attr(test, assert_instr(vmpy_qf16))]
5383#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5384pub unsafe fn Q6_Vqf16_vmpy_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector {
5385    vmpy_qf16(vu, vv)
5386}
5387
5388/// `Vd32.qf16=vmpy(Vu32.hf,Vv32.hf)`
5389///
5390/// Instruction Type: CVI_VX_DV
5391/// Execution Slots: SLOT23
5392#[inline]
5393#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5394#[cfg_attr(test, assert_instr(vmpy_qf16_hf))]
5395#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5396pub unsafe fn Q6_Vqf16_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
5397    vmpy_qf16_hf(vu, vv)
5398}
5399
5400/// `Vd32.qf16=vmpy(Vu32.qf16,Vv32.hf)`
5401///
5402/// Instruction Type: CVI_VX_DV
5403/// Execution Slots: SLOT23
5404#[inline]
5405#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5406#[cfg_attr(test, assert_instr(vmpy_qf16_mix_hf))]
5407#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5408pub unsafe fn Q6_Vqf16_vmpy_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
5409    vmpy_qf16_mix_hf(vu, vv)
5410}
5411
5412/// `Vd32.qf32=vmpy(Vu32.qf32,Vv32.qf32)`
5413///
5414/// Instruction Type: CVI_VX_DV
5415/// Execution Slots: SLOT23
5416#[inline]
5417#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5418#[cfg_attr(test, assert_instr(vmpy_qf32))]
5419#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5420pub unsafe fn Q6_Vqf32_vmpy_Vqf32Vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector {
5421    vmpy_qf32(vu, vv)
5422}
5423
5424/// `Vdd32.qf32=vmpy(Vu32.hf,Vv32.hf)`
5425///
5426/// Instruction Type: CVI_VX_DV
5427/// Execution Slots: SLOT23
5428#[inline]
5429#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5430#[cfg_attr(test, assert_instr(vmpy_qf32_hf))]
5431#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5432pub unsafe fn Q6_Wqf32_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
5433    vmpy_qf32_hf(vu, vv)
5434}
5435
5436/// `Vdd32.qf32=vmpy(Vu32.qf16,Vv32.hf)`
5437///
5438/// Instruction Type: CVI_VX_DV
5439/// Execution Slots: SLOT23
5440#[inline]
5441#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5442#[cfg_attr(test, assert_instr(vmpy_qf32_mix_hf))]
5443#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5444pub unsafe fn Q6_Wqf32_vmpy_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
5445    vmpy_qf32_mix_hf(vu, vv)
5446}
5447
5448/// `Vdd32.qf32=vmpy(Vu32.qf16,Vv32.qf16)`
5449///
5450/// Instruction Type: CVI_VX_DV
5451/// Execution Slots: SLOT23
5452#[inline]
5453#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5454#[cfg_attr(test, assert_instr(vmpy_qf32_qf16))]
5455#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5456pub unsafe fn Q6_Wqf32_vmpy_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
5457    vmpy_qf32_qf16(vu, vv)
5458}
5459
5460/// `Vd32.qf32=vmpy(Vu32.sf,Vv32.sf)`
5461///
5462/// Instruction Type: CVI_VX_DV
5463/// Execution Slots: SLOT23
5464#[inline]
5465#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5466#[cfg_attr(test, assert_instr(vmpy_qf32_sf))]
5467#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5468pub unsafe fn Q6_Vqf32_vmpy_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
5469    vmpy_qf32_sf(vu, vv)
5470}
5471
5472/// `Vdd32.sf=vmpy(Vu32.hf,Vv32.hf)`
5473///
5474/// Instruction Type: CVI_VX_DV
5475/// Execution Slots: SLOT23
5476#[inline]
5477#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5478#[cfg_attr(test, assert_instr(vmpy_sf_hf))]
5479#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5480pub unsafe fn Q6_Wsf_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
5481    vmpy_sf_hf(vu, vv)
5482}
5483
5484/// `Vxx32.sf+=vmpy(Vu32.hf,Vv32.hf)`
5485///
5486/// Instruction Type: CVI_VX_DV
5487/// Execution Slots: SLOT23
5488#[inline]
5489#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5490#[cfg_attr(test, assert_instr(vmpy_sf_hf_acc))]
5491#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5492pub unsafe fn Q6_Wsf_vmpyacc_WsfVhfVhf(
5493    vxx: HvxVectorPair,
5494    vu: HvxVector,
5495    vv: HvxVector,
5496) -> HvxVectorPair {
5497    vmpy_sf_hf_acc(vxx, vu, vv)
5498}
5499
5500/// `Vd32.sf=vmpy(Vu32.sf,Vv32.sf)`
5501///
5502/// Instruction Type: CVI_VX_DV
5503/// Execution Slots: SLOT23
5504#[inline]
5505#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5506#[cfg_attr(test, assert_instr(vmpy_sf_sf))]
5507#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5508pub unsafe fn Q6_Vsf_vmpy_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
5509    vmpy_sf_sf(vu, vv)
5510}
5511
5512/// `Vd32.qf16=vsub(Vu32.hf,Vv32.hf)`
5513///
5514/// Instruction Type: CVI_VS
5515/// Execution Slots: SLOT0123
5516#[inline]
5517#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5518#[cfg_attr(test, assert_instr(vsub_hf))]
5519#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5520pub unsafe fn Q6_Vqf16_vsub_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
5521    vsub_hf(vu, vv)
5522}
5523
5524/// `Vd32.hf=vsub(Vu32.hf,Vv32.hf)`
5525///
5526/// Instruction Type: CVI_VX
5527/// Execution Slots: SLOT23
5528#[inline]
5529#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5530#[cfg_attr(test, assert_instr(vsub_hf_hf))]
5531#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5532pub unsafe fn Q6_Vhf_vsub_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
5533    vsub_hf_hf(vu, vv)
5534}
5535
5536/// `Vd32.qf16=vsub(Vu32.qf16,Vv32.qf16)`
5537///
5538/// Instruction Type: CVI_VS
5539/// Execution Slots: SLOT0123
5540#[inline]
5541#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5542#[cfg_attr(test, assert_instr(vsub_qf16))]
5543#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5544pub unsafe fn Q6_Vqf16_vsub_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector {
5545    vsub_qf16(vu, vv)
5546}
5547
5548/// `Vd32.qf16=vsub(Vu32.qf16,Vv32.hf)`
5549///
5550/// Instruction Type: CVI_VS
5551/// Execution Slots: SLOT0123
5552#[inline]
5553#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5554#[cfg_attr(test, assert_instr(vsub_qf16_mix))]
5555#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5556pub unsafe fn Q6_Vqf16_vsub_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
5557    vsub_qf16_mix(vu, vv)
5558}
5559
5560/// `Vd32.qf32=vsub(Vu32.qf32,Vv32.qf32)`
5561///
5562/// Instruction Type: CVI_VS
5563/// Execution Slots: SLOT0123
5564#[inline]
5565#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5566#[cfg_attr(test, assert_instr(vsub_qf32))]
5567#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5568pub unsafe fn Q6_Vqf32_vsub_Vqf32Vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector {
5569    vsub_qf32(vu, vv)
5570}
5571
5572/// `Vd32.qf32=vsub(Vu32.qf32,Vv32.sf)`
5573///
5574/// Instruction Type: CVI_VS
5575/// Execution Slots: SLOT0123
5576#[inline]
5577#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5578#[cfg_attr(test, assert_instr(vsub_qf32_mix))]
5579#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5580pub unsafe fn Q6_Vqf32_vsub_Vqf32Vsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
5581    vsub_qf32_mix(vu, vv)
5582}
5583
5584/// `Vd32.qf32=vsub(Vu32.sf,Vv32.sf)`
5585///
5586/// Instruction Type: CVI_VS
5587/// Execution Slots: SLOT0123
5588#[inline]
5589#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5590#[cfg_attr(test, assert_instr(vsub_sf))]
5591#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5592pub unsafe fn Q6_Vqf32_vsub_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
5593    vsub_sf(vu, vv)
5594}
5595
5596/// `Vdd32.sf=vsub(Vu32.hf,Vv32.hf)`
5597///
5598/// Instruction Type: CVI_VX_DV
5599/// Execution Slots: SLOT23
5600#[inline]
5601#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5602#[cfg_attr(test, assert_instr(vsub_sf_hf))]
5603#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5604pub unsafe fn Q6_Wsf_vsub_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
5605    vsub_sf_hf(vu, vv)
5606}
5607
5608/// `Vd32.sf=vsub(Vu32.sf,Vv32.sf)`
5609///
5610/// Instruction Type: CVI_VX
5611/// Execution Slots: SLOT23
5612#[inline]
5613#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
5614#[cfg_attr(test, assert_instr(vsub_sf_sf))]
5615#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5616pub unsafe fn Q6_Vsf_vsub_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
5617    vsub_sf_sf(vu, vv)
5618}
5619
5620/// `Vd32.ub=vasr(Vuu32.uh,Vv32.ub):rnd:sat`
5621///
5622/// Instruction Type: CVI_VS
5623/// Execution Slots: SLOT0123
5624#[inline]
5625#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))]
5626#[cfg_attr(test, assert_instr(vasrvuhubrndsat))]
5627#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5628pub unsafe fn Q6_Vub_vasr_WuhVub_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector {
5629    vasrvuhubrndsat(vuu, vv)
5630}
5631
5632/// `Vd32.ub=vasr(Vuu32.uh,Vv32.ub):sat`
5633///
5634/// Instruction Type: CVI_VS
5635/// Execution Slots: SLOT0123
5636#[inline]
5637#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))]
5638#[cfg_attr(test, assert_instr(vasrvuhubsat))]
5639#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5640pub unsafe fn Q6_Vub_vasr_WuhVub_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector {
5641    vasrvuhubsat(vuu, vv)
5642}
5643
5644/// `Vd32.uh=vasr(Vuu32.w,Vv32.uh):rnd:sat`
5645///
5646/// Instruction Type: CVI_VS
5647/// Execution Slots: SLOT0123
5648#[inline]
5649#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))]
5650#[cfg_attr(test, assert_instr(vasrvwuhrndsat))]
5651#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5652pub unsafe fn Q6_Vuh_vasr_WwVuh_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector {
5653    vasrvwuhrndsat(vuu, vv)
5654}
5655
5656/// `Vd32.uh=vasr(Vuu32.w,Vv32.uh):sat`
5657///
5658/// Instruction Type: CVI_VS
5659/// Execution Slots: SLOT0123
5660#[inline]
5661#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))]
5662#[cfg_attr(test, assert_instr(vasrvwuhsat))]
5663#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5664pub unsafe fn Q6_Vuh_vasr_WwVuh_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector {
5665    vasrvwuhsat(vuu, vv)
5666}
5667
5668/// `Vd32.uh=vmpy(Vu32.uh,Vv32.uh):>>16`
5669///
5670/// Instruction Type: CVI_VX
5671/// Execution Slots: SLOT23
5672#[inline]
5673#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))]
5674#[cfg_attr(test, assert_instr(vmpyuhvs))]
5675#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5676pub unsafe fn Q6_Vuh_vmpy_VuhVuh_rs16(vu: HvxVector, vv: HvxVector) -> HvxVector {
5677    vmpyuhvs(vu, vv)
5678}
5679
5680/// `Vd32.h=Vu32.hf`
5681///
5682/// Instruction Type: CVI_VS
5683/// Execution Slots: SLOT0123
5684#[inline]
5685#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))]
5686#[cfg_attr(test, assert_instr(vconv_h_hf))]
5687#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5688pub unsafe fn Q6_Vh_equals_Vhf(vu: HvxVector) -> HvxVector {
5689    vconv_h_hf(vu)
5690}
5691
5692/// `Vd32.hf=Vu32.h`
5693///
5694/// Instruction Type: CVI_VS
5695/// Execution Slots: SLOT0123
5696#[inline]
5697#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))]
5698#[cfg_attr(test, assert_instr(vconv_hf_h))]
5699#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5700pub unsafe fn Q6_Vhf_equals_Vh(vu: HvxVector) -> HvxVector {
5701    vconv_hf_h(vu)
5702}
5703
5704/// `Vd32.sf=Vu32.w`
5705///
5706/// Instruction Type: CVI_VS
5707/// Execution Slots: SLOT0123
5708#[inline]
5709#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))]
5710#[cfg_attr(test, assert_instr(vconv_sf_w))]
5711#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5712pub unsafe fn Q6_Vsf_equals_Vw(vu: HvxVector) -> HvxVector {
5713    vconv_sf_w(vu)
5714}
5715
5716/// `Vd32.w=Vu32.sf`
5717///
5718/// Instruction Type: CVI_VS
5719/// Execution Slots: SLOT0123
5720#[inline]
5721#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))]
5722#[cfg_attr(test, assert_instr(vconv_w_sf))]
5723#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5724pub unsafe fn Q6_Vw_equals_Vsf(vu: HvxVector) -> HvxVector {
5725    vconv_w_sf(vu)
5726}
5727
5728/// `Vd32=vgetqfext(Vu32.x,Rt32)`
5729///
5730/// Instruction Type: CVI_VX
5731/// Execution Slots: SLOT23
5732#[inline]
5733#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
5734#[cfg_attr(test, assert_instr(get_qfext))]
5735#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5736pub unsafe fn Q6_V_vgetqfext_VR(vu: HvxVector, rt: i32) -> HvxVector {
5737    get_qfext(vu, rt)
5738}
5739
5740/// `Vd32.x=vsetqfext(Vu32,Rt32)`
5741///
5742/// Instruction Type: CVI_VX
5743/// Execution Slots: SLOT23
5744#[inline]
5745#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
5746#[cfg_attr(test, assert_instr(set_qfext))]
5747#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5748pub unsafe fn Q6_V_vsetqfext_VR(vu: HvxVector, rt: i32) -> HvxVector {
5749    set_qfext(vu, rt)
5750}
5751
5752/// `Vd32.f8=vabs(Vu32.f8)`
5753///
5754/// Instruction Type: CVI_VX_LATE
5755/// Execution Slots: SLOT23
5756#[inline]
5757#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
5758#[cfg_attr(test, assert_instr(vabs_f8))]
5759#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5760pub unsafe fn Q6_V_vabs_V(vu: HvxVector) -> HvxVector {
5761    vabs_f8(vu)
5762}
5763
5764/// `Vdd32.hf=vcvt2(Vu32.b)`
5765///
5766/// Instruction Type: CVI_VX_DV
5767/// Execution Slots: SLOT23
5768#[inline]
5769#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
5770#[cfg_attr(test, assert_instr(vcvt2_hf_b))]
5771#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5772pub unsafe fn Q6_Whf_vcvt2_Vb(vu: HvxVector) -> HvxVectorPair {
5773    vcvt2_hf_b(vu)
5774}
5775
5776/// `Vdd32.hf=vcvt2(Vu32.ub)`
5777///
5778/// Instruction Type: CVI_VX_DV
5779/// Execution Slots: SLOT23
5780#[inline]
5781#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
5782#[cfg_attr(test, assert_instr(vcvt2_hf_ub))]
5783#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5784pub unsafe fn Q6_Whf_vcvt2_Vub(vu: HvxVector) -> HvxVectorPair {
5785    vcvt2_hf_ub(vu)
5786}
5787
5788/// `Vdd32.hf=vcvt(Vu32.f8)`
5789///
5790/// Instruction Type: CVI_VX_DV
5791/// Execution Slots: SLOT23
5792#[inline]
5793#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
5794#[cfg_attr(test, assert_instr(vcvt_hf_f8))]
5795#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5796pub unsafe fn Q6_Whf_vcvt_V(vu: HvxVector) -> HvxVectorPair {
5797    vcvt_hf_f8(vu)
5798}
5799
5800/// `Vd32.f8=vfmax(Vu32.f8,Vv32.f8)`
5801///
5802/// Instruction Type: CVI_VX_LATE
5803/// Execution Slots: SLOT23
5804#[inline]
5805#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
5806#[cfg_attr(test, assert_instr(vfmax_f8))]
5807#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5808pub unsafe fn Q6_V_vfmax_VV(vu: HvxVector, vv: HvxVector) -> HvxVector {
5809    vfmax_f8(vu, vv)
5810}
5811
5812/// `Vd32.f8=vfmin(Vu32.f8,Vv32.f8)`
5813///
5814/// Instruction Type: CVI_VX_LATE
5815/// Execution Slots: SLOT23
5816#[inline]
5817#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
5818#[cfg_attr(test, assert_instr(vfmin_f8))]
5819#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5820pub unsafe fn Q6_V_vfmin_VV(vu: HvxVector, vv: HvxVector) -> HvxVector {
5821    vfmin_f8(vu, vv)
5822}
5823
5824/// `Vd32.f8=vfneg(Vu32.f8)`
5825///
5826/// Instruction Type: CVI_VX_LATE
5827/// Execution Slots: SLOT23
5828#[inline]
5829#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
5830#[cfg_attr(test, assert_instr(vfneg_f8))]
5831#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5832pub unsafe fn Q6_V_vfneg_V(vu: HvxVector) -> HvxVector {
5833    vfneg_f8(vu)
5834}
5835
5836/// `Qd4=and(Qs4,Qt4)`
5837///
5838/// This is a compound operation composed of multiple HVX instructions.
5839/// Instruction Type: CVI_VA_DV
5840/// Execution Slots: SLOT0123
5841#[inline]
5842#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
5843#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5844pub unsafe fn Q6_Q_and_QQ(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
5845    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
5846        pred_and(
5847            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
5848            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qt), -1),
5849        ),
5850        -1,
5851    ))
5852}
5853
5854/// `Qd4=and(Qs4,!Qt4)`
5855///
5856/// This is a compound operation composed of multiple HVX instructions.
5857/// Instruction Type: CVI_VA_DV
5858/// Execution Slots: SLOT0123
5859#[inline]
5860#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
5861#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5862pub unsafe fn Q6_Q_and_QQn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
5863    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
5864        pred_and_n(
5865            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
5866            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qt), -1),
5867        ),
5868        -1,
5869    ))
5870}
5871
5872/// `Qd4=not(Qs4)`
5873///
5874/// This is a compound operation composed of multiple HVX instructions.
5875/// Instruction Type: CVI_VA
5876/// Execution Slots: SLOT0123
5877#[inline]
5878#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
5879#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5880pub unsafe fn Q6_Q_not_Q(qs: HvxVectorPred) -> HvxVectorPred {
5881    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
5882        pred_not(vandvrt(
5883            core::mem::transmute::<HvxVectorPred, HvxVector>(qs),
5884            -1,
5885        )),
5886        -1,
5887    ))
5888}
5889
5890/// `Qd4=or(Qs4,Qt4)`
5891///
5892/// This is a compound operation composed of multiple HVX instructions.
5893/// Instruction Type: CVI_VA_DV
5894/// Execution Slots: SLOT0123
5895#[inline]
5896#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
5897#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5898pub unsafe fn Q6_Q_or_QQ(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
5899    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
5900        pred_or(
5901            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
5902            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qt), -1),
5903        ),
5904        -1,
5905    ))
5906}
5907
5908/// `Qd4=or(Qs4,!Qt4)`
5909///
5910/// This is a compound operation composed of multiple HVX instructions.
5911/// Instruction Type: CVI_VA_DV
5912/// Execution Slots: SLOT0123
5913#[inline]
5914#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
5915#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5916pub unsafe fn Q6_Q_or_QQn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
5917    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
5918        pred_or_n(
5919            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
5920            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qt), -1),
5921        ),
5922        -1,
5923    ))
5924}
5925
5926/// `Qd4=vsetq(Rt32)`
5927///
5928/// This is a compound operation composed of multiple HVX instructions.
5929/// Instruction Type: CVI_VP
5930/// Execution Slots: SLOT0123
5931#[inline]
5932#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
5933#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5934pub unsafe fn Q6_Q_vsetq_R(rt: i32) -> HvxVectorPred {
5935    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(pred_scalar2(rt), -1))
5936}
5937
5938/// `Qd4=xor(Qs4,Qt4)`
5939///
5940/// This is a compound operation composed of multiple HVX instructions.
5941/// Instruction Type: CVI_VA_DV
5942/// Execution Slots: SLOT0123
5943#[inline]
5944#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
5945#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5946pub unsafe fn Q6_Q_xor_QQ(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
5947    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
5948        pred_xor(
5949            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
5950            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qt), -1),
5951        ),
5952        -1,
5953    ))
5954}
5955
5956/// `if (!Qv4) vmem(Rt32+#s4)=Vs32`
5957///
5958/// This is a compound operation composed of multiple HVX instructions.
5959/// Instruction Type: CVI_VM_ST
5960/// Execution Slots: SLOT0
5961#[inline]
5962#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
5963#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5964pub unsafe fn Q6_vmem_QnRIV(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) {
5965    vS32b_nqpred_ai(
5966        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
5967        rt,
5968        vs,
5969    )
5970}
5971
5972/// `if (!Qv4) vmem(Rt32+#s4):nt=Vs32`
5973///
5974/// This is a compound operation composed of multiple HVX instructions.
5975/// Instruction Type: CVI_VM_ST
5976/// Execution Slots: SLOT0
5977#[inline]
5978#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
5979#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5980pub unsafe fn Q6_vmem_QnRIV_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) {
5981    vS32b_nt_nqpred_ai(
5982        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
5983        rt,
5984        vs,
5985    )
5986}
5987
5988/// `if (Qv4) vmem(Rt32+#s4):nt=Vs32`
5989///
5990/// This is a compound operation composed of multiple HVX instructions.
5991/// Instruction Type: CVI_VM_ST
5992/// Execution Slots: SLOT0
5993#[inline]
5994#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
5995#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5996pub unsafe fn Q6_vmem_QRIV_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) {
5997    vS32b_nt_qpred_ai(
5998        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
5999        rt,
6000        vs,
6001    )
6002}
6003
6004/// `if (Qv4) vmem(Rt32+#s4)=Vs32`
6005///
6006/// This is a compound operation composed of multiple HVX instructions.
6007/// Instruction Type: CVI_VM_ST
6008/// Execution Slots: SLOT0
6009#[inline]
6010#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6011#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6012pub unsafe fn Q6_vmem_QRIV(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) {
6013    vS32b_qpred_ai(
6014        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
6015        rt,
6016        vs,
6017    )
6018}
6019
6020/// `if (!Qv4) Vx32.b+=Vu32.b`
6021///
6022/// This is a compound operation composed of multiple HVX instructions.
6023/// Instruction Type: CVI_VA
6024/// Execution Slots: SLOT0123
6025#[inline]
6026#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6027#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6028pub unsafe fn Q6_Vb_condacc_QnVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
6029    vaddbnq(
6030        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
6031        vx,
6032        vu,
6033    )
6034}
6035
6036/// `if (Qv4) Vx32.b+=Vu32.b`
6037///
6038/// This is a compound operation composed of multiple HVX instructions.
6039/// Instruction Type: CVI_VA
6040/// Execution Slots: SLOT0123
6041#[inline]
6042#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6043#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6044pub unsafe fn Q6_Vb_condacc_QVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
6045    vaddbq(
6046        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
6047        vx,
6048        vu,
6049    )
6050}
6051
6052/// `if (!Qv4) Vx32.h+=Vu32.h`
6053///
6054/// This is a compound operation composed of multiple HVX instructions.
6055/// Instruction Type: CVI_VA
6056/// Execution Slots: SLOT0123
6057#[inline]
6058#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6059#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6060pub unsafe fn Q6_Vh_condacc_QnVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
6061    vaddhnq(
6062        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
6063        vx,
6064        vu,
6065    )
6066}
6067
6068/// `if (Qv4) Vx32.h+=Vu32.h`
6069///
6070/// This is a compound operation composed of multiple HVX instructions.
6071/// Instruction Type: CVI_VA
6072/// Execution Slots: SLOT0123
6073#[inline]
6074#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6075#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6076pub unsafe fn Q6_Vh_condacc_QVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
6077    vaddhq(
6078        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
6079        vx,
6080        vu,
6081    )
6082}
6083
6084/// `if (!Qv4) Vx32.w+=Vu32.w`
6085///
6086/// This is a compound operation composed of multiple HVX instructions.
6087/// Instruction Type: CVI_VA
6088/// Execution Slots: SLOT0123
6089#[inline]
6090#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6091#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6092pub unsafe fn Q6_Vw_condacc_QnVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
6093    vaddwnq(
6094        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
6095        vx,
6096        vu,
6097    )
6098}
6099
6100/// `if (Qv4) Vx32.w+=Vu32.w`
6101///
6102/// This is a compound operation composed of multiple HVX instructions.
6103/// Instruction Type: CVI_VA
6104/// Execution Slots: SLOT0123
6105#[inline]
6106#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6107#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6108pub unsafe fn Q6_Vw_condacc_QVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
6109    vaddwq(
6110        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
6111        vx,
6112        vu,
6113    )
6114}
6115
6116/// `Vd32=vand(Qu4,Rt32)`
6117///
6118/// This is a compound operation composed of multiple HVX instructions.
6119/// Instruction Type: CVI_VX_LATE
6120/// Execution Slots: SLOT23
6121#[inline]
6122#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6123#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6124pub unsafe fn Q6_V_vand_QR(qu: HvxVectorPred, rt: i32) -> HvxVector {
6125    vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qu), rt)
6126}
6127
6128/// `Vx32|=vand(Qu4,Rt32)`
6129///
6130/// This is a compound operation composed of multiple HVX instructions.
6131/// Instruction Type: CVI_VX_LATE
6132/// Execution Slots: SLOT23
6133#[inline]
6134#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6135#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6136pub unsafe fn Q6_V_vandor_VQR(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector {
6137    vandvrt_acc(vx, core::mem::transmute::<HvxVectorPred, HvxVector>(qu), rt)
6138}
6139
6140/// `Qd4=vand(Vu32,Rt32)`
6141///
6142/// This is a compound operation composed of multiple HVX instructions.
6143/// Instruction Type: CVI_VX_LATE
6144/// Execution Slots: SLOT23
6145#[inline]
6146#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6147#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6148pub unsafe fn Q6_Q_vand_VR(vu: HvxVector, rt: i32) -> HvxVectorPred {
6149    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vu, rt))
6150}
6151
6152/// `Qx4|=vand(Vu32,Rt32)`
6153///
6154/// This is a compound operation composed of multiple HVX instructions.
6155/// Instruction Type: CVI_VX_LATE
6156/// Execution Slots: SLOT23
6157#[inline]
6158#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6159#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6160pub unsafe fn Q6_Q_vandor_QVR(qx: HvxVectorPred, vu: HvxVector, rt: i32) -> HvxVectorPred {
6161    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt_acc(
6162        core::mem::transmute::<HvxVectorPred, HvxVector>(qx),
6163        vu,
6164        rt,
6165    ))
6166}
6167
6168/// `Qd4=vcmp.eq(Vu32.b,Vv32.b)`
6169///
6170/// This is a compound operation composed of multiple HVX instructions.
6171/// Instruction Type: CVI_VA
6172/// Execution Slots: SLOT0123
6173#[inline]
6174#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6175#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6176pub unsafe fn Q6_Q_vcmp_eq_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
6177    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(veqb(vu, vv), -1))
6178}
6179
6180/// `Qx4&=vcmp.eq(Vu32.b,Vv32.b)`
6181///
6182/// This is a compound operation composed of multiple HVX instructions.
6183/// Instruction Type: CVI_VA
6184/// Execution Slots: SLOT0123
6185#[inline]
6186#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6187#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6188pub unsafe fn Q6_Q_vcmp_eqand_QVbVb(
6189    qx: HvxVectorPred,
6190    vu: HvxVector,
6191    vv: HvxVector,
6192) -> HvxVectorPred {
6193    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
6194        veqb_and(
6195            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
6196            vu,
6197            vv,
6198        ),
6199        -1,
6200    ))
6201}
6202
6203/// `Qx4|=vcmp.eq(Vu32.b,Vv32.b)`
6204///
6205/// This is a compound operation composed of multiple HVX instructions.
6206/// Instruction Type: CVI_VA
6207/// Execution Slots: SLOT0123
6208#[inline]
6209#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6210#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6211pub unsafe fn Q6_Q_vcmp_eqor_QVbVb(
6212    qx: HvxVectorPred,
6213    vu: HvxVector,
6214    vv: HvxVector,
6215) -> HvxVectorPred {
6216    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
6217        veqb_or(
6218            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
6219            vu,
6220            vv,
6221        ),
6222        -1,
6223    ))
6224}
6225
6226/// `Qx4^=vcmp.eq(Vu32.b,Vv32.b)`
6227///
6228/// This is a compound operation composed of multiple HVX instructions.
6229/// Instruction Type: CVI_VA
6230/// Execution Slots: SLOT0123
6231#[inline]
6232#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6233#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6234pub unsafe fn Q6_Q_vcmp_eqxacc_QVbVb(
6235    qx: HvxVectorPred,
6236    vu: HvxVector,
6237    vv: HvxVector,
6238) -> HvxVectorPred {
6239    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
6240        veqb_xor(
6241            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
6242            vu,
6243            vv,
6244        ),
6245        -1,
6246    ))
6247}
6248
6249/// `Qd4=vcmp.eq(Vu32.h,Vv32.h)`
6250///
6251/// This is a compound operation composed of multiple HVX instructions.
6252/// Instruction Type: CVI_VA
6253/// Execution Slots: SLOT0123
6254#[inline]
6255#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6256#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6257pub unsafe fn Q6_Q_vcmp_eq_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
6258    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(veqh(vu, vv), -1))
6259}
6260
6261/// `Qx4&=vcmp.eq(Vu32.h,Vv32.h)`
6262///
6263/// This is a compound operation composed of multiple HVX instructions.
6264/// Instruction Type: CVI_VA
6265/// Execution Slots: SLOT0123
6266#[inline]
6267#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6268#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6269pub unsafe fn Q6_Q_vcmp_eqand_QVhVh(
6270    qx: HvxVectorPred,
6271    vu: HvxVector,
6272    vv: HvxVector,
6273) -> HvxVectorPred {
6274    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
6275        veqh_and(
6276            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
6277            vu,
6278            vv,
6279        ),
6280        -1,
6281    ))
6282}
6283
6284/// `Qx4|=vcmp.eq(Vu32.h,Vv32.h)`
6285///
6286/// This is a compound operation composed of multiple HVX instructions.
6287/// Instruction Type: CVI_VA
6288/// Execution Slots: SLOT0123
6289#[inline]
6290#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6291#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6292pub unsafe fn Q6_Q_vcmp_eqor_QVhVh(
6293    qx: HvxVectorPred,
6294    vu: HvxVector,
6295    vv: HvxVector,
6296) -> HvxVectorPred {
6297    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
6298        veqh_or(
6299            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
6300            vu,
6301            vv,
6302        ),
6303        -1,
6304    ))
6305}
6306
6307/// `Qx4^=vcmp.eq(Vu32.h,Vv32.h)`
6308///
6309/// This is a compound operation composed of multiple HVX instructions.
6310/// Instruction Type: CVI_VA
6311/// Execution Slots: SLOT0123
6312#[inline]
6313#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6314#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6315pub unsafe fn Q6_Q_vcmp_eqxacc_QVhVh(
6316    qx: HvxVectorPred,
6317    vu: HvxVector,
6318    vv: HvxVector,
6319) -> HvxVectorPred {
6320    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
6321        veqh_xor(
6322            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
6323            vu,
6324            vv,
6325        ),
6326        -1,
6327    ))
6328}
6329
6330/// `Qd4=vcmp.eq(Vu32.w,Vv32.w)`
6331///
6332/// This is a compound operation composed of multiple HVX instructions.
6333/// Instruction Type: CVI_VA
6334/// Execution Slots: SLOT0123
6335#[inline]
6336#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6337#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6338pub unsafe fn Q6_Q_vcmp_eq_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
6339    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(veqw(vu, vv), -1))
6340}
6341
6342/// `Qx4&=vcmp.eq(Vu32.w,Vv32.w)`
6343///
6344/// This is a compound operation composed of multiple HVX instructions.
6345/// Instruction Type: CVI_VA
6346/// Execution Slots: SLOT0123
6347#[inline]
6348#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6349#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6350pub unsafe fn Q6_Q_vcmp_eqand_QVwVw(
6351    qx: HvxVectorPred,
6352    vu: HvxVector,
6353    vv: HvxVector,
6354) -> HvxVectorPred {
6355    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
6356        veqw_and(
6357            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
6358            vu,
6359            vv,
6360        ),
6361        -1,
6362    ))
6363}
6364
6365/// `Qx4|=vcmp.eq(Vu32.w,Vv32.w)`
6366///
6367/// This is a compound operation composed of multiple HVX instructions.
6368/// Instruction Type: CVI_VA
6369/// Execution Slots: SLOT0123
6370#[inline]
6371#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6372#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6373pub unsafe fn Q6_Q_vcmp_eqor_QVwVw(
6374    qx: HvxVectorPred,
6375    vu: HvxVector,
6376    vv: HvxVector,
6377) -> HvxVectorPred {
6378    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
6379        veqw_or(
6380            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
6381            vu,
6382            vv,
6383        ),
6384        -1,
6385    ))
6386}
6387
6388/// `Qx4^=vcmp.eq(Vu32.w,Vv32.w)`
6389///
6390/// This is a compound operation composed of multiple HVX instructions.
6391/// Instruction Type: CVI_VA
6392/// Execution Slots: SLOT0123
6393#[inline]
6394#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6395#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6396pub unsafe fn Q6_Q_vcmp_eqxacc_QVwVw(
6397    qx: HvxVectorPred,
6398    vu: HvxVector,
6399    vv: HvxVector,
6400) -> HvxVectorPred {
6401    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
6402        veqw_xor(
6403            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
6404            vu,
6405            vv,
6406        ),
6407        -1,
6408    ))
6409}
6410
6411/// `Qd4=vcmp.gt(Vu32.b,Vv32.b)`
6412///
6413/// This is a compound operation composed of multiple HVX instructions.
6414/// Instruction Type: CVI_VA
6415/// Execution Slots: SLOT0123
6416#[inline]
6417#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6418#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6419pub unsafe fn Q6_Q_vcmp_gt_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
6420    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vgtb(vu, vv), -1))
6421}
6422
6423/// `Qx4&=vcmp.gt(Vu32.b,Vv32.b)`
6424///
6425/// This is a compound operation composed of multiple HVX instructions.
6426/// Instruction Type: CVI_VA
6427/// Execution Slots: SLOT0123
6428#[inline]
6429#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6430#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6431pub unsafe fn Q6_Q_vcmp_gtand_QVbVb(
6432    qx: HvxVectorPred,
6433    vu: HvxVector,
6434    vv: HvxVector,
6435) -> HvxVectorPred {
6436    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
6437        vgtb_and(
6438            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
6439            vu,
6440            vv,
6441        ),
6442        -1,
6443    ))
6444}
6445
6446/// `Qx4|=vcmp.gt(Vu32.b,Vv32.b)`
6447///
6448/// This is a compound operation composed of multiple HVX instructions.
6449/// Instruction Type: CVI_VA
6450/// Execution Slots: SLOT0123
6451#[inline]
6452#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6453#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6454pub unsafe fn Q6_Q_vcmp_gtor_QVbVb(
6455    qx: HvxVectorPred,
6456    vu: HvxVector,
6457    vv: HvxVector,
6458) -> HvxVectorPred {
6459    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
6460        vgtb_or(
6461            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
6462            vu,
6463            vv,
6464        ),
6465        -1,
6466    ))
6467}
6468
6469/// `Qx4^=vcmp.gt(Vu32.b,Vv32.b)`
6470///
6471/// This is a compound operation composed of multiple HVX instructions.
6472/// Instruction Type: CVI_VA
6473/// Execution Slots: SLOT0123
6474#[inline]
6475#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6476#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6477pub unsafe fn Q6_Q_vcmp_gtxacc_QVbVb(
6478    qx: HvxVectorPred,
6479    vu: HvxVector,
6480    vv: HvxVector,
6481) -> HvxVectorPred {
6482    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
6483        vgtb_xor(
6484            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
6485            vu,
6486            vv,
6487        ),
6488        -1,
6489    ))
6490}
6491
6492/// `Qd4=vcmp.gt(Vu32.h,Vv32.h)`
6493///
6494/// This is a compound operation composed of multiple HVX instructions.
6495/// Instruction Type: CVI_VA
6496/// Execution Slots: SLOT0123
6497#[inline]
6498#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6499#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6500pub unsafe fn Q6_Q_vcmp_gt_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
6501    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vgth(vu, vv), -1))
6502}
6503
6504/// `Qx4&=vcmp.gt(Vu32.h,Vv32.h)`
6505///
6506/// This is a compound operation composed of multiple HVX instructions.
6507/// Instruction Type: CVI_VA
6508/// Execution Slots: SLOT0123
6509#[inline]
6510#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6511#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6512pub unsafe fn Q6_Q_vcmp_gtand_QVhVh(
6513    qx: HvxVectorPred,
6514    vu: HvxVector,
6515    vv: HvxVector,
6516) -> HvxVectorPred {
6517    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
6518        vgth_and(
6519            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
6520            vu,
6521            vv,
6522        ),
6523        -1,
6524    ))
6525}
6526
6527/// `Qx4|=vcmp.gt(Vu32.h,Vv32.h)`
6528///
6529/// This is a compound operation composed of multiple HVX instructions.
6530/// Instruction Type: CVI_VA
6531/// Execution Slots: SLOT0123
6532#[inline]
6533#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6534#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6535pub unsafe fn Q6_Q_vcmp_gtor_QVhVh(
6536    qx: HvxVectorPred,
6537    vu: HvxVector,
6538    vv: HvxVector,
6539) -> HvxVectorPred {
6540    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
6541        vgth_or(
6542            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
6543            vu,
6544            vv,
6545        ),
6546        -1,
6547    ))
6548}
6549
6550/// `Qx4^=vcmp.gt(Vu32.h,Vv32.h)`
6551///
6552/// This is a compound operation composed of multiple HVX instructions.
6553/// Instruction Type: CVI_VA
6554/// Execution Slots: SLOT0123
6555#[inline]
6556#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6557#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6558pub unsafe fn Q6_Q_vcmp_gtxacc_QVhVh(
6559    qx: HvxVectorPred,
6560    vu: HvxVector,
6561    vv: HvxVector,
6562) -> HvxVectorPred {
6563    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
6564        vgth_xor(
6565            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
6566            vu,
6567            vv,
6568        ),
6569        -1,
6570    ))
6571}
6572
6573/// `Qd4=vcmp.gt(Vu32.ub,Vv32.ub)`
6574///
6575/// This is a compound operation composed of multiple HVX instructions.
6576/// Instruction Type: CVI_VA
6577/// Execution Slots: SLOT0123
6578#[inline]
6579#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6580#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6581pub unsafe fn Q6_Q_vcmp_gt_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
6582    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vgtub(vu, vv), -1))
6583}
6584
6585/// `Qx4&=vcmp.gt(Vu32.ub,Vv32.ub)`
6586///
6587/// This is a compound operation composed of multiple HVX instructions.
6588/// Instruction Type: CVI_VA
6589/// Execution Slots: SLOT0123
6590#[inline]
6591#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6592#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6593pub unsafe fn Q6_Q_vcmp_gtand_QVubVub(
6594    qx: HvxVectorPred,
6595    vu: HvxVector,
6596    vv: HvxVector,
6597) -> HvxVectorPred {
6598    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
6599        vgtub_and(
6600            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
6601            vu,
6602            vv,
6603        ),
6604        -1,
6605    ))
6606}
6607
6608/// `Qx4|=vcmp.gt(Vu32.ub,Vv32.ub)`
6609///
6610/// This is a compound operation composed of multiple HVX instructions.
6611/// Instruction Type: CVI_VA
6612/// Execution Slots: SLOT0123
6613#[inline]
6614#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6615#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6616pub unsafe fn Q6_Q_vcmp_gtor_QVubVub(
6617    qx: HvxVectorPred,
6618    vu: HvxVector,
6619    vv: HvxVector,
6620) -> HvxVectorPred {
6621    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
6622        vgtub_or(
6623            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
6624            vu,
6625            vv,
6626        ),
6627        -1,
6628    ))
6629}
6630
6631/// `Qx4^=vcmp.gt(Vu32.ub,Vv32.ub)`
6632///
6633/// This is a compound operation composed of multiple HVX instructions.
6634/// Instruction Type: CVI_VA
6635/// Execution Slots: SLOT0123
6636#[inline]
6637#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6638#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6639pub unsafe fn Q6_Q_vcmp_gtxacc_QVubVub(
6640    qx: HvxVectorPred,
6641    vu: HvxVector,
6642    vv: HvxVector,
6643) -> HvxVectorPred {
6644    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
6645        vgtub_xor(
6646            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
6647            vu,
6648            vv,
6649        ),
6650        -1,
6651    ))
6652}
6653
6654/// `Qd4=vcmp.gt(Vu32.uh,Vv32.uh)`
6655///
6656/// This is a compound operation composed of multiple HVX instructions.
6657/// Instruction Type: CVI_VA
6658/// Execution Slots: SLOT0123
6659#[inline]
6660#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6661#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6662pub unsafe fn Q6_Q_vcmp_gt_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
6663    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vgtuh(vu, vv), -1))
6664}
6665
6666/// `Qx4&=vcmp.gt(Vu32.uh,Vv32.uh)`
6667///
6668/// This is a compound operation composed of multiple HVX instructions.
6669/// Instruction Type: CVI_VA
6670/// Execution Slots: SLOT0123
6671#[inline]
6672#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6673#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6674pub unsafe fn Q6_Q_vcmp_gtand_QVuhVuh(
6675    qx: HvxVectorPred,
6676    vu: HvxVector,
6677    vv: HvxVector,
6678) -> HvxVectorPred {
6679    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
6680        vgtuh_and(
6681            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
6682            vu,
6683            vv,
6684        ),
6685        -1,
6686    ))
6687}
6688
6689/// `Qx4|=vcmp.gt(Vu32.uh,Vv32.uh)`
6690///
6691/// This is a compound operation composed of multiple HVX instructions.
6692/// Instruction Type: CVI_VA
6693/// Execution Slots: SLOT0123
6694#[inline]
6695#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6696#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6697pub unsafe fn Q6_Q_vcmp_gtor_QVuhVuh(
6698    qx: HvxVectorPred,
6699    vu: HvxVector,
6700    vv: HvxVector,
6701) -> HvxVectorPred {
6702    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
6703        vgtuh_or(
6704            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
6705            vu,
6706            vv,
6707        ),
6708        -1,
6709    ))
6710}
6711
6712/// `Qx4^=vcmp.gt(Vu32.uh,Vv32.uh)`
6713///
6714/// This is a compound operation composed of multiple HVX instructions.
6715/// Instruction Type: CVI_VA
6716/// Execution Slots: SLOT0123
6717#[inline]
6718#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6719#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6720pub unsafe fn Q6_Q_vcmp_gtxacc_QVuhVuh(
6721    qx: HvxVectorPred,
6722    vu: HvxVector,
6723    vv: HvxVector,
6724) -> HvxVectorPred {
6725    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
6726        vgtuh_xor(
6727            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
6728            vu,
6729            vv,
6730        ),
6731        -1,
6732    ))
6733}
6734
6735/// `Qd4=vcmp.gt(Vu32.uw,Vv32.uw)`
6736///
6737/// This is a compound operation composed of multiple HVX instructions.
6738/// Instruction Type: CVI_VA
6739/// Execution Slots: SLOT0123
6740#[inline]
6741#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6742#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6743pub unsafe fn Q6_Q_vcmp_gt_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
6744    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vgtuw(vu, vv), -1))
6745}
6746
6747/// `Qx4&=vcmp.gt(Vu32.uw,Vv32.uw)`
6748///
6749/// This is a compound operation composed of multiple HVX instructions.
6750/// Instruction Type: CVI_VA
6751/// Execution Slots: SLOT0123
6752#[inline]
6753#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6754#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6755pub unsafe fn Q6_Q_vcmp_gtand_QVuwVuw(
6756    qx: HvxVectorPred,
6757    vu: HvxVector,
6758    vv: HvxVector,
6759) -> HvxVectorPred {
6760    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
6761        vgtuw_and(
6762            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
6763            vu,
6764            vv,
6765        ),
6766        -1,
6767    ))
6768}
6769
6770/// `Qx4|=vcmp.gt(Vu32.uw,Vv32.uw)`
6771///
6772/// This is a compound operation composed of multiple HVX instructions.
6773/// Instruction Type: CVI_VA
6774/// Execution Slots: SLOT0123
6775#[inline]
6776#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6777#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6778pub unsafe fn Q6_Q_vcmp_gtor_QVuwVuw(
6779    qx: HvxVectorPred,
6780    vu: HvxVector,
6781    vv: HvxVector,
6782) -> HvxVectorPred {
6783    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
6784        vgtuw_or(
6785            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
6786            vu,
6787            vv,
6788        ),
6789        -1,
6790    ))
6791}
6792
6793/// `Qx4^=vcmp.gt(Vu32.uw,Vv32.uw)`
6794///
6795/// This is a compound operation composed of multiple HVX instructions.
6796/// Instruction Type: CVI_VA
6797/// Execution Slots: SLOT0123
6798#[inline]
6799#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6800#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6801pub unsafe fn Q6_Q_vcmp_gtxacc_QVuwVuw(
6802    qx: HvxVectorPred,
6803    vu: HvxVector,
6804    vv: HvxVector,
6805) -> HvxVectorPred {
6806    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
6807        vgtuw_xor(
6808            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
6809            vu,
6810            vv,
6811        ),
6812        -1,
6813    ))
6814}
6815
6816/// `Qd4=vcmp.gt(Vu32.w,Vv32.w)`
6817///
6818/// This is a compound operation composed of multiple HVX instructions.
6819/// Instruction Type: CVI_VA
6820/// Execution Slots: SLOT0123
6821#[inline]
6822#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6823#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6824pub unsafe fn Q6_Q_vcmp_gt_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
6825    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vgtw(vu, vv), -1))
6826}
6827
6828/// `Qx4&=vcmp.gt(Vu32.w,Vv32.w)`
6829///
6830/// This is a compound operation composed of multiple HVX instructions.
6831/// Instruction Type: CVI_VA
6832/// Execution Slots: SLOT0123
6833#[inline]
6834#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6835#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6836pub unsafe fn Q6_Q_vcmp_gtand_QVwVw(
6837    qx: HvxVectorPred,
6838    vu: HvxVector,
6839    vv: HvxVector,
6840) -> HvxVectorPred {
6841    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
6842        vgtw_and(
6843            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
6844            vu,
6845            vv,
6846        ),
6847        -1,
6848    ))
6849}
6850
6851/// `Qx4|=vcmp.gt(Vu32.w,Vv32.w)`
6852///
6853/// This is a compound operation composed of multiple HVX instructions.
6854/// Instruction Type: CVI_VA
6855/// Execution Slots: SLOT0123
6856#[inline]
6857#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6858#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6859pub unsafe fn Q6_Q_vcmp_gtor_QVwVw(
6860    qx: HvxVectorPred,
6861    vu: HvxVector,
6862    vv: HvxVector,
6863) -> HvxVectorPred {
6864    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
6865        vgtw_or(
6866            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
6867            vu,
6868            vv,
6869        ),
6870        -1,
6871    ))
6872}
6873
6874/// `Qx4^=vcmp.gt(Vu32.w,Vv32.w)`
6875///
6876/// This is a compound operation composed of multiple HVX instructions.
6877/// Instruction Type: CVI_VA
6878/// Execution Slots: SLOT0123
6879#[inline]
6880#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6881#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6882pub unsafe fn Q6_Q_vcmp_gtxacc_QVwVw(
6883    qx: HvxVectorPred,
6884    vu: HvxVector,
6885    vv: HvxVector,
6886) -> HvxVectorPred {
6887    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
6888        vgtw_xor(
6889            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
6890            vu,
6891            vv,
6892        ),
6893        -1,
6894    ))
6895}
6896
6897/// `Vd32=vmux(Qt4,Vu32,Vv32)`
6898///
6899/// This is a compound operation composed of multiple HVX instructions.
6900/// Instruction Type: CVI_VA
6901/// Execution Slots: SLOT0123
6902#[inline]
6903#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6904#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6905pub unsafe fn Q6_V_vmux_QVV(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVector {
6906    vmux(
6907        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qt), -1),
6908        vu,
6909        vv,
6910    )
6911}
6912
6913/// `if (!Qv4) Vx32.b-=Vu32.b`
6914///
6915/// This is a compound operation composed of multiple HVX instructions.
6916/// Instruction Type: CVI_VA
6917/// Execution Slots: SLOT0123
6918#[inline]
6919#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6920#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6921pub unsafe fn Q6_Vb_condnac_QnVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
6922    vsubbnq(
6923        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
6924        vx,
6925        vu,
6926    )
6927}
6928
6929/// `if (Qv4) Vx32.b-=Vu32.b`
6930///
6931/// This is a compound operation composed of multiple HVX instructions.
6932/// Instruction Type: CVI_VA
6933/// Execution Slots: SLOT0123
6934#[inline]
6935#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6936#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6937pub unsafe fn Q6_Vb_condnac_QVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
6938    vsubbq(
6939        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
6940        vx,
6941        vu,
6942    )
6943}
6944
6945/// `if (!Qv4) Vx32.h-=Vu32.h`
6946///
6947/// This is a compound operation composed of multiple HVX instructions.
6948/// Instruction Type: CVI_VA
6949/// Execution Slots: SLOT0123
6950#[inline]
6951#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6952#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6953pub unsafe fn Q6_Vh_condnac_QnVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
6954    vsubhnq(
6955        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
6956        vx,
6957        vu,
6958    )
6959}
6960
6961/// `if (Qv4) Vx32.h-=Vu32.h`
6962///
6963/// This is a compound operation composed of multiple HVX instructions.
6964/// Instruction Type: CVI_VA
6965/// Execution Slots: SLOT0123
6966#[inline]
6967#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6968#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6969pub unsafe fn Q6_Vh_condnac_QVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
6970    vsubhq(
6971        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
6972        vx,
6973        vu,
6974    )
6975}
6976
6977/// `if (!Qv4) Vx32.w-=Vu32.w`
6978///
6979/// This is a compound operation composed of multiple HVX instructions.
6980/// Instruction Type: CVI_VA
6981/// Execution Slots: SLOT0123
6982#[inline]
6983#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
6984#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6985pub unsafe fn Q6_Vw_condnac_QnVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
6986    vsubwnq(
6987        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
6988        vx,
6989        vu,
6990    )
6991}
6992
6993/// `if (Qv4) Vx32.w-=Vu32.w`
6994///
6995/// This is a compound operation composed of multiple HVX instructions.
6996/// Instruction Type: CVI_VA
6997/// Execution Slots: SLOT0123
6998#[inline]
6999#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
7000#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7001pub unsafe fn Q6_Vw_condnac_QVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
7002    vsubwq(
7003        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
7004        vx,
7005        vu,
7006    )
7007}
7008
7009/// `Vdd32=vswap(Qt4,Vu32,Vv32)`
7010///
7011/// This is a compound operation composed of multiple HVX instructions.
7012/// Instruction Type: CVI_VA_DV
7013/// Execution Slots: SLOT0123
7014#[inline]
7015#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
7016#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7017pub unsafe fn Q6_W_vswap_QVV(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
7018    vswap(
7019        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qt), -1),
7020        vu,
7021        vv,
7022    )
7023}
7024
7025/// `Qd4=vsetq2(Rt32)`
7026///
7027/// This is a compound operation composed of multiple HVX instructions.
7028/// Instruction Type: CVI_VP
7029/// Execution Slots: SLOT0123
7030#[inline]
7031#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
7032#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7033pub unsafe fn Q6_Q_vsetq2_R(rt: i32) -> HvxVectorPred {
7034    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(pred_scalar2v2(rt), -1))
7035}
7036
7037/// `Qd4.b=vshuffe(Qs4.h,Qt4.h)`
7038///
7039/// This is a compound operation composed of multiple HVX instructions.
7040/// Instruction Type: CVI_VA_DV
7041/// Execution Slots: SLOT0123
7042#[inline]
7043#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
7044#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7045pub unsafe fn Q6_Qb_vshuffe_QhQh(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
7046    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
7047        shuffeqh(
7048            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
7049            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qt), -1),
7050        ),
7051        -1,
7052    ))
7053}
7054
7055/// `Qd4.h=vshuffe(Qs4.w,Qt4.w)`
7056///
7057/// This is a compound operation composed of multiple HVX instructions.
7058/// Instruction Type: CVI_VA_DV
7059/// Execution Slots: SLOT0123
7060#[inline]
7061#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
7062#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7063pub unsafe fn Q6_Qh_vshuffe_QwQw(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
7064    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
7065        shuffeqw(
7066            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
7067            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qt), -1),
7068        ),
7069        -1,
7070    ))
7071}
7072
7073/// `Vd32=vand(!Qu4,Rt32)`
7074///
7075/// This is a compound operation composed of multiple HVX instructions.
7076/// Instruction Type: CVI_VX_LATE
7077/// Execution Slots: SLOT23
7078#[inline]
7079#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
7080#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7081pub unsafe fn Q6_V_vand_QnR(qu: HvxVectorPred, rt: i32) -> HvxVector {
7082    vandnqrt(
7083        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qu), -1),
7084        rt,
7085    )
7086}
7087
7088/// `Vx32|=vand(!Qu4,Rt32)`
7089///
7090/// This is a compound operation composed of multiple HVX instructions.
7091/// Instruction Type: CVI_VX_LATE
7092/// Execution Slots: SLOT23
7093#[inline]
7094#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
7095#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7096pub unsafe fn Q6_V_vandor_VQnR(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector {
7097    vandnqrt_acc(
7098        vx,
7099        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qu), -1),
7100        rt,
7101    )
7102}
7103
7104/// `Vd32=vand(!Qv4,Vu32)`
7105///
7106/// This is a compound operation composed of multiple HVX instructions.
7107/// Instruction Type: CVI_VA
7108/// Execution Slots: SLOT0123
7109#[inline]
7110#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
7111#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7112pub unsafe fn Q6_V_vand_QnV(qv: HvxVectorPred, vu: HvxVector) -> HvxVector {
7113    vandvnqv(
7114        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
7115        vu,
7116    )
7117}
7118
7119/// `Vd32=vand(Qv4,Vu32)`
7120///
7121/// This is a compound operation composed of multiple HVX instructions.
7122/// Instruction Type: CVI_VA
7123/// Execution Slots: SLOT0123
7124#[inline]
7125#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
7126#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7127pub unsafe fn Q6_V_vand_QV(qv: HvxVectorPred, vu: HvxVector) -> HvxVector {
7128    vandvqv(
7129        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
7130        vu,
7131    )
7132}
7133
7134/// `if (Qs4) vtmp.h=vgather(Rt32,Mu2,Vv32.h).h`
7135///
7136/// This is a compound operation composed of multiple HVX instructions.
7137/// Instruction Type: CVI_GATHER
7138/// Execution Slots: SLOT01
7139#[inline]
7140#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
7141#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7142pub unsafe fn Q6_vgather_AQRMVh(
7143    rs: *mut HvxVector,
7144    qs: HvxVectorPred,
7145    rt: i32,
7146    mu: i32,
7147    vv: HvxVector,
7148) {
7149    vgathermhq(
7150        rs,
7151        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
7152        rt,
7153        mu,
7154        vv,
7155    )
7156}
7157
7158/// `if (Qs4) vtmp.h=vgather(Rt32,Mu2,Vvv32.w).h`
7159///
7160/// This is a compound operation composed of multiple HVX instructions.
7161/// Instruction Type: CVI_GATHER_DV
7162/// Execution Slots: SLOT01
7163#[inline]
7164#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
7165#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7166pub unsafe fn Q6_vgather_AQRMWw(
7167    rs: *mut HvxVector,
7168    qs: HvxVectorPred,
7169    rt: i32,
7170    mu: i32,
7171    vvv: HvxVectorPair,
7172) {
7173    vgathermhwq(
7174        rs,
7175        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
7176        rt,
7177        mu,
7178        vvv,
7179    )
7180}
7181
7182/// `if (Qs4) vtmp.w=vgather(Rt32,Mu2,Vv32.w).w`
7183///
7184/// This is a compound operation composed of multiple HVX instructions.
7185/// Instruction Type: CVI_GATHER
7186/// Execution Slots: SLOT01
7187#[inline]
7188#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
7189#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7190pub unsafe fn Q6_vgather_AQRMVw(
7191    rs: *mut HvxVector,
7192    qs: HvxVectorPred,
7193    rt: i32,
7194    mu: i32,
7195    vv: HvxVector,
7196) {
7197    vgathermwq(
7198        rs,
7199        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
7200        rt,
7201        mu,
7202        vv,
7203    )
7204}
7205
7206/// `Vd32.b=prefixsum(Qv4)`
7207///
7208/// This is a compound operation composed of multiple HVX instructions.
7209/// Instruction Type: CVI_VS
7210/// Execution Slots: SLOT0123
7211#[inline]
7212#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
7213#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7214pub unsafe fn Q6_Vb_prefixsum_Q(qv: HvxVectorPred) -> HvxVector {
7215    vprefixqb(vandvrt(
7216        core::mem::transmute::<HvxVectorPred, HvxVector>(qv),
7217        -1,
7218    ))
7219}
7220
7221/// `Vd32.h=prefixsum(Qv4)`
7222///
7223/// This is a compound operation composed of multiple HVX instructions.
7224/// Instruction Type: CVI_VS
7225/// Execution Slots: SLOT0123
7226#[inline]
7227#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
7228#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7229pub unsafe fn Q6_Vh_prefixsum_Q(qv: HvxVectorPred) -> HvxVector {
7230    vprefixqh(vandvrt(
7231        core::mem::transmute::<HvxVectorPred, HvxVector>(qv),
7232        -1,
7233    ))
7234}
7235
7236/// `Vd32.w=prefixsum(Qv4)`
7237///
7238/// This is a compound operation composed of multiple HVX instructions.
7239/// Instruction Type: CVI_VS
7240/// Execution Slots: SLOT0123
7241#[inline]
7242#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
7243#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7244pub unsafe fn Q6_Vw_prefixsum_Q(qv: HvxVectorPred) -> HvxVector {
7245    vprefixqw(vandvrt(
7246        core::mem::transmute::<HvxVectorPred, HvxVector>(qv),
7247        -1,
7248    ))
7249}
7250
7251/// `if (Qs4) vscatter(Rt32,Mu2,Vv32.h).h=Vw32`
7252///
7253/// This is a compound operation composed of multiple HVX instructions.
7254/// Instruction Type: CVI_SCATTER
7255/// Execution Slots: SLOT0
7256#[inline]
7257#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
7258#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7259pub unsafe fn Q6_vscatter_QRMVhV(
7260    qs: HvxVectorPred,
7261    rt: i32,
7262    mu: i32,
7263    vv: HvxVector,
7264    vw: HvxVector,
7265) {
7266    vscattermhq(
7267        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
7268        rt,
7269        mu,
7270        vv,
7271        vw,
7272    )
7273}
7274
7275/// `if (Qs4) vscatter(Rt32,Mu2,Vvv32.w).h=Vw32`
7276///
7277/// This is a compound operation composed of multiple HVX instructions.
7278/// Instruction Type: CVI_SCATTER_DV
7279/// Execution Slots: SLOT0
7280#[inline]
7281#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
7282#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7283pub unsafe fn Q6_vscatter_QRMWwV(
7284    qs: HvxVectorPred,
7285    rt: i32,
7286    mu: i32,
7287    vvv: HvxVectorPair,
7288    vw: HvxVector,
7289) {
7290    vscattermhwq(
7291        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
7292        rt,
7293        mu,
7294        vvv,
7295        vw,
7296    )
7297}
7298
7299/// `if (Qs4) vscatter(Rt32,Mu2,Vv32.w).w=Vw32`
7300///
7301/// This is a compound operation composed of multiple HVX instructions.
7302/// Instruction Type: CVI_SCATTER
7303/// Execution Slots: SLOT0
7304#[inline]
7305#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
7306#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7307pub unsafe fn Q6_vscatter_QRMVwV(
7308    qs: HvxVectorPred,
7309    rt: i32,
7310    mu: i32,
7311    vv: HvxVector,
7312    vw: HvxVector,
7313) {
7314    vscattermwq(
7315        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
7316        rt,
7317        mu,
7318        vv,
7319        vw,
7320    )
7321}
7322
7323/// `Vd32.w=vadd(Vu32.w,Vv32.w,Qs4):carry:sat`
7324///
7325/// This is a compound operation composed of multiple HVX instructions.
7326/// Instruction Type: CVI_VA
7327/// Execution Slots: SLOT0123
7328#[inline]
7329#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))]
7330#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7331pub unsafe fn Q6_Vw_vadd_VwVwQ_carry_sat(
7332    vu: HvxVector,
7333    vv: HvxVector,
7334    qs: HvxVectorPred,
7335) -> HvxVector {
7336    vaddcarrysat(
7337        vu,
7338        vv,
7339        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
7340    )
7341}
7342
7343/// `Qd4=vcmp.gt(Vu32.hf,Vv32.hf)`
7344///
7345/// This is a compound operation composed of multiple HVX instructions.
7346/// Instruction Type: CVI_VA
7347/// Execution Slots: SLOT0123
7348#[inline]
7349#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
7350#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7351pub unsafe fn Q6_Q_vcmp_gt_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
7352    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vgthf(vu, vv), -1))
7353}
7354
7355/// `Qx4&=vcmp.gt(Vu32.hf,Vv32.hf)`
7356///
7357/// This is a compound operation composed of multiple HVX instructions.
7358/// Instruction Type: CVI_VA
7359/// Execution Slots: SLOT0123
7360#[inline]
7361#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
7362#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7363pub unsafe fn Q6_Q_vcmp_gtand_QVhfVhf(
7364    qx: HvxVectorPred,
7365    vu: HvxVector,
7366    vv: HvxVector,
7367) -> HvxVectorPred {
7368    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
7369        vgthf_and(
7370            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
7371            vu,
7372            vv,
7373        ),
7374        -1,
7375    ))
7376}
7377
7378/// `Qx4|=vcmp.gt(Vu32.hf,Vv32.hf)`
7379///
7380/// This is a compound operation composed of multiple HVX instructions.
7381/// Instruction Type: CVI_VA
7382/// Execution Slots: SLOT0123
7383#[inline]
7384#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
7385#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7386pub unsafe fn Q6_Q_vcmp_gtor_QVhfVhf(
7387    qx: HvxVectorPred,
7388    vu: HvxVector,
7389    vv: HvxVector,
7390) -> HvxVectorPred {
7391    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
7392        vgthf_or(
7393            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
7394            vu,
7395            vv,
7396        ),
7397        -1,
7398    ))
7399}
7400
7401/// `Qx4^=vcmp.gt(Vu32.hf,Vv32.hf)`
7402///
7403/// This is a compound operation composed of multiple HVX instructions.
7404/// Instruction Type: CVI_VA
7405/// Execution Slots: SLOT0123
7406#[inline]
7407#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
7408#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7409pub unsafe fn Q6_Q_vcmp_gtxacc_QVhfVhf(
7410    qx: HvxVectorPred,
7411    vu: HvxVector,
7412    vv: HvxVector,
7413) -> HvxVectorPred {
7414    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
7415        vgthf_xor(
7416            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
7417            vu,
7418            vv,
7419        ),
7420        -1,
7421    ))
7422}
7423
7424/// `Qd4=vcmp.gt(Vu32.sf,Vv32.sf)`
7425///
7426/// This is a compound operation composed of multiple HVX instructions.
7427/// Instruction Type: CVI_VA
7428/// Execution Slots: SLOT0123
7429#[inline]
7430#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
7431#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7432pub unsafe fn Q6_Q_vcmp_gt_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
7433    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vgtsf(vu, vv), -1))
7434}
7435
7436/// `Qx4&=vcmp.gt(Vu32.sf,Vv32.sf)`
7437///
7438/// This is a compound operation composed of multiple HVX instructions.
7439/// Instruction Type: CVI_VA
7440/// Execution Slots: SLOT0123
7441#[inline]
7442#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
7443#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7444pub unsafe fn Q6_Q_vcmp_gtand_QVsfVsf(
7445    qx: HvxVectorPred,
7446    vu: HvxVector,
7447    vv: HvxVector,
7448) -> HvxVectorPred {
7449    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
7450        vgtsf_and(
7451            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
7452            vu,
7453            vv,
7454        ),
7455        -1,
7456    ))
7457}
7458
7459/// `Qx4|=vcmp.gt(Vu32.sf,Vv32.sf)`
7460///
7461/// This is a compound operation composed of multiple HVX instructions.
7462/// Instruction Type: CVI_VA
7463/// Execution Slots: SLOT0123
7464#[inline]
7465#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
7466#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7467pub unsafe fn Q6_Q_vcmp_gtor_QVsfVsf(
7468    qx: HvxVectorPred,
7469    vu: HvxVector,
7470    vv: HvxVector,
7471) -> HvxVectorPred {
7472    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
7473        vgtsf_or(
7474            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
7475            vu,
7476            vv,
7477        ),
7478        -1,
7479    ))
7480}
7481
7482/// `Qx4^=vcmp.gt(Vu32.sf,Vv32.sf)`
7483///
7484/// This is a compound operation composed of multiple HVX instructions.
7485/// Instruction Type: CVI_VA
7486/// Execution Slots: SLOT0123
7487#[inline]
7488#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
7489#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7490pub unsafe fn Q6_Q_vcmp_gtxacc_QVsfVsf(
7491    qx: HvxVectorPred,
7492    vu: HvxVector,
7493    vv: HvxVector,
7494) -> HvxVectorPred {
7495    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
7496        vgtsf_xor(
7497            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
7498            vu,
7499            vv,
7500        ),
7501        -1,
7502    ))
7503}
core/stdarch/crates/core_arch/src/hexagon/v128.rs

core/stdarch/crates/core_arch/src/hexagon/
v128.rs
