core/stdarch/crates/core_arch/src/x86_64/
bmi.rs

1//! Bit Manipulation Instruction (BMI) Set 1.0.
2//!
3//! The reference is [Intel 64 and IA-32 Architectures Software Developer's
4//! Manual Volume 2: Instruction Set Reference, A-Z][intel64_ref].
5//!
6//! [Wikipedia][wikipedia_bmi] provides a quick overview of the instructions
7//! available.
8//!
9//! [intel64_ref]: https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
10//! [wikipedia_bmi]: https://en.wikipedia.org/wiki/Bit_Manipulation_Instruction_Sets#ABM_.28Advanced_Bit_Manipulation.29
11
12#[cfg(test)]
13use stdarch_test::assert_instr;
14
15/// Extracts bits in range [`start`, `start` + `length`) from `a` into
16/// the least significant bits of the result.
17///
18/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_bextr_u64)
19#[inline]
20#[target_feature(enable = "bmi1")]
21#[cfg_attr(test, assert_instr(bextr))]
22#[cfg(not(target_arch = "x86"))]
23#[stable(feature = "simd_x86", since = "1.27.0")]
24pub fn _bextr_u64(a: u64, start: u32, len: u32) -> u64 {
25    _bextr2_u64(a, ((start & 0xff) | ((len & 0xff) << 8)) as u64)
26}
27
28/// Extracts bits of `a` specified by `control` into
29/// the least significant bits of the result.
30///
31/// Bits `[7,0]` of `control` specify the index to the first bit in the range
32/// to be extracted, and bits `[15,8]` specify the length of the range.
33///
34/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_bextr2_u64)
35#[inline]
36#[target_feature(enable = "bmi1")]
37#[cfg_attr(test, assert_instr(bextr))]
38#[cfg(not(target_arch = "x86"))]
39#[stable(feature = "simd_x86", since = "1.27.0")]
40pub fn _bextr2_u64(a: u64, control: u64) -> u64 {
41    unsafe { x86_bmi_bextr_64(a, control) }
42}
43
44/// Bitwise logical `AND` of inverted `a` with `b`.
45///
46/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_andn_u64)
47#[inline]
48#[target_feature(enable = "bmi1")]
49#[cfg_attr(test, assert_instr(andn))]
50#[stable(feature = "simd_x86", since = "1.27.0")]
51#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
52pub const fn _andn_u64(a: u64, b: u64) -> u64 {
53    !a & b
54}
55
56/// Extracts lowest set isolated bit.
57///
58/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_blsi_u64)
59#[inline]
60#[target_feature(enable = "bmi1")]
61#[cfg_attr(test, assert_instr(blsi))]
62#[cfg(not(target_arch = "x86"))] // generates lots of instructions
63#[stable(feature = "simd_x86", since = "1.27.0")]
64#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
65pub const fn _blsi_u64(x: u64) -> u64 {
66    x & x.wrapping_neg()
67}
68
69/// Gets mask up to lowest set bit.
70///
71/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_blsmsk_u64)
72#[inline]
73#[target_feature(enable = "bmi1")]
74#[cfg_attr(test, assert_instr(blsmsk))]
75#[cfg(not(target_arch = "x86"))] // generates lots of instructions
76#[stable(feature = "simd_x86", since = "1.27.0")]
77#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
78pub const fn _blsmsk_u64(x: u64) -> u64 {
79    x ^ (x.wrapping_sub(1_u64))
80}
81
82/// Resets the lowest set bit of `x`.
83///
84/// If `x` is sets CF.
85///
86/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_blsr_u64)
87#[inline]
88#[target_feature(enable = "bmi1")]
89#[cfg_attr(test, assert_instr(blsr))]
90#[cfg(not(target_arch = "x86"))] // generates lots of instructions
91#[stable(feature = "simd_x86", since = "1.27.0")]
92#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
93pub const fn _blsr_u64(x: u64) -> u64 {
94    x & (x.wrapping_sub(1))
95}
96
97/// Counts the number of trailing least significant zero bits.
98///
99/// When the source operand is `0`, it returns its size in bits.
100///
101/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_tzcnt_u64)
102#[inline]
103#[target_feature(enable = "bmi1")]
104#[cfg_attr(test, assert_instr(tzcnt))]
105#[stable(feature = "simd_x86", since = "1.27.0")]
106#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
107pub const fn _tzcnt_u64(x: u64) -> u64 {
108    x.trailing_zeros() as u64
109}
110
111/// Counts the number of trailing least significant zero bits.
112///
113/// When the source operand is `0`, it returns its size in bits.
114///
115/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_tzcnt_64)
116#[inline]
117#[target_feature(enable = "bmi1")]
118#[cfg_attr(test, assert_instr(tzcnt))]
119#[stable(feature = "simd_x86", since = "1.27.0")]
120#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
121pub const fn _mm_tzcnt_64(x: u64) -> i64 {
122    x.trailing_zeros() as i64
123}
124
125unsafe extern "C" {
126    #[link_name = "llvm.x86.bmi.bextr.64"]
127    fn x86_bmi_bextr_64(x: u64, y: u64) -> u64;
128}
129
130#[cfg(test)]
131mod tests {
132    use crate::core_arch::assert_eq_const as assert_eq;
133    use stdarch_test::simd_test;
134
135    use crate::core_arch::{x86::*, x86_64::*};
136
137    #[simd_test(enable = "bmi1")]
138    fn test_bextr_u64() {
139        let r = _bextr_u64(0b0101_0000u64, 4, 4);
140        assert_eq!(r, 0b0000_0101u64);
141    }
142
143    #[simd_test(enable = "bmi1")]
144    const fn test_andn_u64() {
145        assert_eq!(_andn_u64(0, 0), 0);
146        assert_eq!(_andn_u64(0, 1), 1);
147        assert_eq!(_andn_u64(1, 0), 0);
148        assert_eq!(_andn_u64(1, 1), 0);
149
150        let r = _andn_u64(0b0000_0000u64, 0b0000_0000u64);
151        assert_eq!(r, 0b0000_0000u64);
152
153        let r = _andn_u64(0b0000_0000u64, 0b1111_1111u64);
154        assert_eq!(r, 0b1111_1111u64);
155
156        let r = _andn_u64(0b1111_1111u64, 0b0000_0000u64);
157        assert_eq!(r, 0b0000_0000u64);
158
159        let r = _andn_u64(0b1111_1111u64, 0b1111_1111u64);
160        assert_eq!(r, 0b0000_0000u64);
161
162        let r = _andn_u64(0b0100_0000u64, 0b0101_1101u64);
163        assert_eq!(r, 0b0001_1101u64);
164    }
165
166    #[simd_test(enable = "bmi1")]
167    const fn test_blsi_u64() {
168        assert_eq!(_blsi_u64(0b1101_0000u64), 0b0001_0000u64);
169    }
170
171    #[simd_test(enable = "bmi1")]
172    const fn test_blsmsk_u64() {
173        let r = _blsmsk_u64(0b0011_0000u64);
174        assert_eq!(r, 0b0001_1111u64);
175    }
176
177    #[simd_test(enable = "bmi1")]
178    const fn test_blsr_u64() {
179        // TODO: test the behavior when the input is `0`.
180        let r = _blsr_u64(0b0011_0000u64);
181        assert_eq!(r, 0b0010_0000u64);
182    }
183
184    #[simd_test(enable = "bmi1")]
185    const fn test_tzcnt_u64() {
186        assert_eq!(_tzcnt_u64(0b0000_0001u64), 0u64);
187        assert_eq!(_tzcnt_u64(0b0000_0000u64), 64u64);
188        assert_eq!(_tzcnt_u64(0b1001_0000u64), 4u64);
189    }
190}
core/stdarch/crates/core_arch/src/x86_64/bmi.rs

core/stdarch/crates/core_arch/src/x86_64/
bmi.rs
