core/stdarch/crates/core_arch/src/x86/
avx512fp16.rs

1use crate::arch::asm;
2use crate::core_arch::{simd::*, x86::*};
3use crate::intrinsics::{fmaf16, simd::*};
4use crate::ptr;
5
6/// Set packed half-precision (16-bit) floating-point elements in dst with the supplied values.
7///
8/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_set_ph)
9#[inline]
10#[target_feature(enable = "avx512fp16")]
11#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
12#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
13pub const fn _mm_set_ph(
14    e7: f16,
15    e6: f16,
16    e5: f16,
17    e4: f16,
18    e3: f16,
19    e2: f16,
20    e1: f16,
21    e0: f16,
22) -> __m128h {
23    __m128h([e0, e1, e2, e3, e4, e5, e6, e7])
24}
25
26/// Set packed half-precision (16-bit) floating-point elements in dst with the supplied values.
27///
28/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_set_ph)
29#[inline]
30#[target_feature(enable = "avx512fp16")]
31#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
32#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
33pub const fn _mm256_set_ph(
34    e15: f16,
35    e14: f16,
36    e13: f16,
37    e12: f16,
38    e11: f16,
39    e10: f16,
40    e9: f16,
41    e8: f16,
42    e7: f16,
43    e6: f16,
44    e5: f16,
45    e4: f16,
46    e3: f16,
47    e2: f16,
48    e1: f16,
49    e0: f16,
50) -> __m256h {
51    __m256h([
52        e0, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10, e11, e12, e13, e14, e15,
53    ])
54}
55
56/// Set packed half-precision (16-bit) floating-point elements in dst with the supplied values.
57///
58/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_set_ph)
59#[inline]
60#[target_feature(enable = "avx512fp16")]
61#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
62#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
63pub const fn _mm512_set_ph(
64    e31: f16,
65    e30: f16,
66    e29: f16,
67    e28: f16,
68    e27: f16,
69    e26: f16,
70    e25: f16,
71    e24: f16,
72    e23: f16,
73    e22: f16,
74    e21: f16,
75    e20: f16,
76    e19: f16,
77    e18: f16,
78    e17: f16,
79    e16: f16,
80    e15: f16,
81    e14: f16,
82    e13: f16,
83    e12: f16,
84    e11: f16,
85    e10: f16,
86    e9: f16,
87    e8: f16,
88    e7: f16,
89    e6: f16,
90    e5: f16,
91    e4: f16,
92    e3: f16,
93    e2: f16,
94    e1: f16,
95    e0: f16,
96) -> __m512h {
97    __m512h([
98        e0, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10, e11, e12, e13, e14, e15, e16, e17, e18, e19,
99        e20, e21, e22, e23, e24, e25, e26, e27, e28, e29, e30, e31,
100    ])
101}
102
103/// Copy half-precision (16-bit) floating-point elements from a to the lower element of dst and zero
104/// the upper 7 elements.
105///
106/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_set_sh)
107#[inline]
108#[target_feature(enable = "avx512fp16")]
109#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
110#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
111pub const fn _mm_set_sh(a: f16) -> __m128h {
112    __m128h([a, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0])
113}
114
115/// Broadcast the half-precision (16-bit) floating-point value a to all elements of dst.
116///
117/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_set1_ph)
118#[inline]
119#[target_feature(enable = "avx512fp16")]
120#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
121#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
122pub const fn _mm_set1_ph(a: f16) -> __m128h {
123    unsafe { transmute(f16x8::splat(a)) }
124}
125
126/// Broadcast the half-precision (16-bit) floating-point value a to all elements of dst.
127///
128/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_set1_ph)
129#[inline]
130#[target_feature(enable = "avx512fp16")]
131#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
132#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
133pub const fn _mm256_set1_ph(a: f16) -> __m256h {
134    unsafe { transmute(f16x16::splat(a)) }
135}
136
137/// Broadcast the half-precision (16-bit) floating-point value a to all elements of dst.
138///
139/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_set1_ph)
140#[inline]
141#[target_feature(enable = "avx512fp16")]
142#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
143#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
144pub const fn _mm512_set1_ph(a: f16) -> __m512h {
145    unsafe { transmute(f16x32::splat(a)) }
146}
147
148/// Set packed half-precision (16-bit) floating-point elements in dst with the supplied values in reverse order.
149///
150/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_setr_ph)
151#[inline]
152#[target_feature(enable = "avx512fp16")]
153#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
154#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
155pub const fn _mm_setr_ph(
156    e0: f16,
157    e1: f16,
158    e2: f16,
159    e3: f16,
160    e4: f16,
161    e5: f16,
162    e6: f16,
163    e7: f16,
164) -> __m128h {
165    __m128h([e0, e1, e2, e3, e4, e5, e6, e7])
166}
167
168/// Set packed half-precision (16-bit) floating-point elements in dst with the supplied values in reverse order.
169///
170/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_setr_ph)
171#[inline]
172#[target_feature(enable = "avx512fp16")]
173#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
174#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
175pub const fn _mm256_setr_ph(
176    e0: f16,
177    e1: f16,
178    e2: f16,
179    e3: f16,
180    e4: f16,
181    e5: f16,
182    e6: f16,
183    e7: f16,
184    e8: f16,
185    e9: f16,
186    e10: f16,
187    e11: f16,
188    e12: f16,
189    e13: f16,
190    e14: f16,
191    e15: f16,
192) -> __m256h {
193    __m256h([
194        e0, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10, e11, e12, e13, e14, e15,
195    ])
196}
197
198/// Set packed half-precision (16-bit) floating-point elements in dst with the supplied values in reverse order.
199///
200/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_setr_ph)
201#[inline]
202#[target_feature(enable = "avx512fp16")]
203#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
204#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
205pub const fn _mm512_setr_ph(
206    e0: f16,
207    e1: f16,
208    e2: f16,
209    e3: f16,
210    e4: f16,
211    e5: f16,
212    e6: f16,
213    e7: f16,
214    e8: f16,
215    e9: f16,
216    e10: f16,
217    e11: f16,
218    e12: f16,
219    e13: f16,
220    e14: f16,
221    e15: f16,
222    e16: f16,
223    e17: f16,
224    e18: f16,
225    e19: f16,
226    e20: f16,
227    e21: f16,
228    e22: f16,
229    e23: f16,
230    e24: f16,
231    e25: f16,
232    e26: f16,
233    e27: f16,
234    e28: f16,
235    e29: f16,
236    e30: f16,
237    e31: f16,
238) -> __m512h {
239    __m512h([
240        e0, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10, e11, e12, e13, e14, e15, e16, e17, e18, e19,
241        e20, e21, e22, e23, e24, e25, e26, e27, e28, e29, e30, e31,
242    ])
243}
244
245/// Return vector of type __m128h with all elements set to zero.
246///
247/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_setzero_ph)
248#[inline]
249#[target_feature(enable = "avx512fp16,avx512vl")]
250#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
251#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
252pub const fn _mm_setzero_ph() -> __m128h {
253    unsafe { transmute(f16x8::ZERO) }
254}
255
256/// Return vector of type __m256h with all elements set to zero.
257///
258/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_setzero_ph)
259#[inline]
260#[target_feature(enable = "avx512fp16,avx512vl")]
261#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
262#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
263pub const fn _mm256_setzero_ph() -> __m256h {
264    f16x16::ZERO.as_m256h()
265}
266
267/// Return vector of type __m512h with all elements set to zero.
268///
269/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_setzero_ph)
270#[inline]
271#[target_feature(enable = "avx512fp16")]
272#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
273#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
274pub const fn _mm512_setzero_ph() -> __m512h {
275    f16x32::ZERO.as_m512h()
276}
277
278/// Return vector of type `__m128h` with indetermination elements.
279/// Despite using the word "undefined" (following Intel's naming scheme), this non-deterministically
280/// picks some valid value and is not equivalent to [`mem::MaybeUninit`](crate::mem::MaybeUninit).
281/// In practice, this is typically equivalent to [`mem::zeroed`](crate::mem::zeroed).
282///
283/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_undefined_ph)
284#[inline]
285#[target_feature(enable = "avx512fp16,avx512vl")]
286#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
287#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
288pub const fn _mm_undefined_ph() -> __m128h {
289    f16x8::ZERO.as_m128h()
290}
291
292/// Return vector of type `__m256h` with indetermination elements.
293/// Despite using the word "undefined" (following Intel's naming scheme), this non-deterministically
294/// picks some valid value and is not equivalent to [`mem::MaybeUninit`](crate::mem::MaybeUninit).
295/// In practice, this is typically equivalent to [`mem::zeroed`](crate::mem::zeroed).
296///
297/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_undefined_ph)
298#[inline]
299#[target_feature(enable = "avx512fp16,avx512vl")]
300#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
301#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
302pub const fn _mm256_undefined_ph() -> __m256h {
303    f16x16::ZERO.as_m256h()
304}
305
306/// Return vector of type `__m512h` with indetermination elements.
307/// Despite using the word "undefined" (following Intel's naming scheme), this non-deterministically
308/// picks some valid value and is not equivalent to [`mem::MaybeUninit`](crate::mem::MaybeUninit).
309/// In practice, this is typically equivalent to [`mem::zeroed`](crate::mem::zeroed).
310///
311/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_undefined_ph)
312#[inline]
313#[target_feature(enable = "avx512fp16")]
314#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
315#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
316pub const fn _mm512_undefined_ph() -> __m512h {
317    f16x32::ZERO.as_m512h()
318}
319
320/// Cast vector of type `__m128d` to type `__m128h`. This intrinsic is only used for compilation and
321/// does not generate any instructions, thus it has zero latency.
322///
323/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castpd_ph)
324#[inline]
325#[target_feature(enable = "avx512fp16")]
326#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
327#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
328pub const fn _mm_castpd_ph(a: __m128d) -> __m128h {
329    unsafe { transmute(a) }
330}
331
332/// Cast vector of type `__m256d` to type `__m256h`. This intrinsic is only used for compilation and
333/// does not generate any instructions, thus it has zero latency.
334///
335/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castpd_ph)
336#[inline]
337#[target_feature(enable = "avx512fp16")]
338#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
339#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
340pub const fn _mm256_castpd_ph(a: __m256d) -> __m256h {
341    unsafe { transmute(a) }
342}
343
344/// Cast vector of type `__m512d` to type `__m512h`. This intrinsic is only used for compilation and
345/// does not generate any instructions, thus it has zero latency.
346///
347/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castpd_ph)
348#[inline]
349#[target_feature(enable = "avx512fp16")]
350#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
351#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
352pub const fn _mm512_castpd_ph(a: __m512d) -> __m512h {
353    unsafe { transmute(a) }
354}
355
356/// Cast vector of type `__m128h` to type `__m128d`. This intrinsic is only used for compilation and
357/// does not generate any instructions, thus it has zero latency.
358///
359/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castph_pd)
360#[inline]
361#[target_feature(enable = "avx512fp16")]
362#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
363#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
364pub const fn _mm_castph_pd(a: __m128h) -> __m128d {
365    unsafe { transmute(a) }
366}
367
368/// Cast vector of type `__m256h` to type `__m256d`. This intrinsic is only used for compilation and
369/// does not generate any instructions, thus it has zero latency.
370///
371/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castph_pd)
372#[inline]
373#[target_feature(enable = "avx512fp16")]
374#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
375#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
376pub const fn _mm256_castph_pd(a: __m256h) -> __m256d {
377    unsafe { transmute(a) }
378}
379
380/// Cast vector of type `__m512h` to type `__m512d`. This intrinsic is only used for compilation and
381/// does not generate any instructions, thus it has zero latency.
382///
383/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castph_pd)
384#[inline]
385#[target_feature(enable = "avx512fp16")]
386#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
387#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
388pub const fn _mm512_castph_pd(a: __m512h) -> __m512d {
389    unsafe { transmute(a) }
390}
391
392/// Cast vector of type `__m128` to type `__m128h`. This intrinsic is only used for compilation and
393/// does not generate any instructions, thus it has zero latency.
394///
395/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castps_ph)
396#[inline]
397#[target_feature(enable = "avx512fp16")]
398#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
399#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
400pub const fn _mm_castps_ph(a: __m128) -> __m128h {
401    unsafe { transmute(a) }
402}
403
404/// Cast vector of type `__m256` to type `__m256h`. This intrinsic is only used for compilation and
405/// does not generate any instructions, thus it has zero latency.
406///
407/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castps_ph)
408#[inline]
409#[target_feature(enable = "avx512fp16")]
410#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
411#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
412pub const fn _mm256_castps_ph(a: __m256) -> __m256h {
413    unsafe { transmute(a) }
414}
415
416/// Cast vector of type `__m512` to type `__m512h`. This intrinsic is only used for compilation and
417/// does not generate any instructions, thus it has zero latency.
418///
419/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castps_ph)
420#[inline]
421#[target_feature(enable = "avx512fp16")]
422#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
423#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
424pub const fn _mm512_castps_ph(a: __m512) -> __m512h {
425    unsafe { transmute(a) }
426}
427
428/// Cast vector of type `__m128h` to type `__m128`. This intrinsic is only used for compilation and
429/// does not generate any instructions, thus it has zero latency.
430///
431/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castph_ps)
432#[inline]
433#[target_feature(enable = "avx512fp16")]
434#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
435#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
436pub const fn _mm_castph_ps(a: __m128h) -> __m128 {
437    unsafe { transmute(a) }
438}
439
440/// Cast vector of type `__m256h` to type `__m256`. This intrinsic is only used for compilation and
441/// does not generate any instructions, thus it has zero latency.
442///
443/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castph_ps)
444#[inline]
445#[target_feature(enable = "avx512fp16")]
446#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
447#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
448pub const fn _mm256_castph_ps(a: __m256h) -> __m256 {
449    unsafe { transmute(a) }
450}
451
452/// Cast vector of type `__m512h` to type `__m512`. This intrinsic is only used for compilation and
453/// does not generate any instructions, thus it has zero latency.
454///
455/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castph_ps)
456#[inline]
457#[target_feature(enable = "avx512fp16")]
458#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
459#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
460pub const fn _mm512_castph_ps(a: __m512h) -> __m512 {
461    unsafe { transmute(a) }
462}
463
464/// Cast vector of type `__m128i` to type `__m128h`. This intrinsic is only used for compilation and
465/// does not generate any instructions, thus it has zero latency.
466///
467/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castsi128_ph)
468#[inline]
469#[target_feature(enable = "avx512fp16")]
470#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
471#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
472pub const fn _mm_castsi128_ph(a: __m128i) -> __m128h {
473    unsafe { transmute(a) }
474}
475
476/// Cast vector of type `__m256i` to type `__m256h`. This intrinsic is only used for compilation and
477/// does not generate any instructions, thus it has zero latency.
478///
479/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castsi256_ph)
480#[inline]
481#[target_feature(enable = "avx512fp16")]
482#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
483#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
484pub const fn _mm256_castsi256_ph(a: __m256i) -> __m256h {
485    unsafe { transmute(a) }
486}
487
488/// Cast vector of type `__m512i` to type `__m512h`. This intrinsic is only used for compilation and
489/// does not generate any instructions, thus it has zero latency.
490///
491/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castsi512_ph)
492#[inline]
493#[target_feature(enable = "avx512fp16")]
494#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
495#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
496pub const fn _mm512_castsi512_ph(a: __m512i) -> __m512h {
497    unsafe { transmute(a) }
498}
499
500/// Cast vector of type `__m128h` to type `__m128i`. This intrinsic is only used for compilation and
501/// does not generate any instructions, thus it has zero latency.
502///
503/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castph_si128)
504#[inline]
505#[target_feature(enable = "avx512fp16")]
506#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
507#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
508pub const fn _mm_castph_si128(a: __m128h) -> __m128i {
509    unsafe { transmute(a) }
510}
511
512/// Cast vector of type `__m256h` to type `__m256i`. This intrinsic is only used for compilation and
513/// does not generate any instructions, thus it has zero latency.
514///
515/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castph_si256)
516#[inline]
517#[target_feature(enable = "avx512fp16")]
518#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
519#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
520pub const fn _mm256_castph_si256(a: __m256h) -> __m256i {
521    unsafe { transmute(a) }
522}
523
524/// Cast vector of type `__m512h` to type `__m512i`. This intrinsic is only used for compilation and
525/// does not generate any instructions, thus it has zero latency.
526///
527/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castph_si512)
528#[inline]
529#[target_feature(enable = "avx512fp16")]
530#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
531#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
532pub const fn _mm512_castph_si512(a: __m512h) -> __m512i {
533    unsafe { transmute(a) }
534}
535
536/// Cast vector of type `__m256h` to type `__m128h`. This intrinsic is only used for compilation and
537/// does not generate any instructions, thus it has zero latency.
538///
539/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castph256_ph128)
540#[inline]
541#[target_feature(enable = "avx512fp16")]
542#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
543#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
544pub const fn _mm256_castph256_ph128(a: __m256h) -> __m128h {
545    unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) }
546}
547
548/// Cast vector of type `__m512h` to type `__m128h`. This intrinsic is only used for compilation and
549/// does not generate any instructions, thus it has zero latency.
550///
551/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castph512_ph128)
552#[inline]
553#[target_feature(enable = "avx512fp16")]
554#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
555#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
556pub const fn _mm512_castph512_ph128(a: __m512h) -> __m128h {
557    unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) }
558}
559
560/// Cast vector of type `__m512h` to type `__m256h`. This intrinsic is only used for compilation and
561/// does not generate any instructions, thus it has zero latency.
562///
563/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castph512_ph256)
564#[inline]
565#[target_feature(enable = "avx512fp16")]
566#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
567#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
568pub const fn _mm512_castph512_ph256(a: __m512h) -> __m256h {
569    unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }
570}
571
572/// Cast vector of type `__m128h` to type `__m256h`. The upper 8 elements of the result are undefined.
573/// In practice, the upper elements are zeroed. This intrinsic can generate the `vzeroupper` instruction,
574/// but most of the time it does not generate any instructions.
575///
576/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castph128_ph256)
577#[inline]
578#[target_feature(enable = "avx512fp16")]
579#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
580#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
581pub const fn _mm256_castph128_ph256(a: __m128h) -> __m256h {
582    unsafe {
583        simd_shuffle!(
584            a,
585            _mm_undefined_ph(),
586            [0, 1, 2, 3, 4, 5, 6, 7, 8, 8, 8, 8, 8, 8, 8, 8]
587        )
588    }
589}
590
591/// Cast vector of type `__m128h` to type `__m512h`. The upper 24 elements of the result are undefined.
592/// In practice, the upper elements are zeroed. This intrinsic can generate the `vzeroupper` instruction,
593/// but most of the time it does not generate any instructions.
594///
595/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castph128_ph512)
596#[inline]
597#[target_feature(enable = "avx512fp16")]
598#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
599#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
600pub const fn _mm512_castph128_ph512(a: __m128h) -> __m512h {
601    unsafe {
602        simd_shuffle!(
603            a,
604            _mm_undefined_ph(),
605            [
606                0, 1, 2, 3, 4, 5, 6, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
607                8, 8, 8, 8
608            ]
609        )
610    }
611}
612
613/// Cast vector of type `__m256h` to type `__m512h`. The upper 16 elements of the result are undefined.
614/// In practice, the upper elements are zeroed. This intrinsic can generate the `vzeroupper` instruction,
615/// but most of the time it does not generate any instructions.
616///
617/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castph256_ph512)
618#[inline]
619#[target_feature(enable = "avx512fp16")]
620#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
621#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
622pub const fn _mm512_castph256_ph512(a: __m256h) -> __m512h {
623    unsafe {
624        simd_shuffle!(
625            a,
626            _mm256_undefined_ph(),
627            [
628                0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16,
629                16, 16, 16, 16, 16, 16, 16, 16, 16
630            ]
631        )
632    }
633}
634
635/// Cast vector of type `__m256h` to type `__m128h`. The upper 8 elements of the result are zeroed.
636/// This intrinsic can generate the `vzeroupper` instruction, but most of the time it does not generate
637/// any instructions.
638///
639/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_zextph128_ph256)
640#[inline]
641#[target_feature(enable = "avx512fp16")]
642#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
643#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
644pub const fn _mm256_zextph128_ph256(a: __m128h) -> __m256h {
645    unsafe {
646        simd_shuffle!(
647            a,
648            _mm_setzero_ph(),
649            [0, 1, 2, 3, 4, 5, 6, 7, 8, 8, 8, 8, 8, 8, 8, 8]
650        )
651    }
652}
653
654/// Cast vector of type `__m256h` to type `__m512h`. The upper 16 elements of the result are zeroed.
655/// This intrinsic can generate the `vzeroupper` instruction, but most of the time it does not generate
656/// any instructions.
657///
658/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_zextph256_ph512)
659#[inline]
660#[target_feature(enable = "avx512fp16")]
661#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
662#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
663pub const fn _mm512_zextph256_ph512(a: __m256h) -> __m512h {
664    unsafe {
665        simd_shuffle!(
666            a,
667            _mm256_setzero_ph(),
668            [
669                0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16,
670                16, 16, 16, 16, 16, 16, 16, 16, 16
671            ]
672        )
673    }
674}
675
676/// Cast vector of type `__m128h` to type `__m512h`. The upper 24 elements of the result are zeroed.
677/// This intrinsic can generate the `vzeroupper` instruction, but most of the time it does not generate
678/// any instructions.
679///
680/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_zextph128_ph512)
681#[inline]
682#[target_feature(enable = "avx512fp16")]
683#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
684#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
685pub const fn _mm512_zextph128_ph512(a: __m128h) -> __m512h {
686    unsafe {
687        simd_shuffle!(
688            a,
689            _mm_setzero_ph(),
690            [
691                0, 1, 2, 3, 4, 5, 6, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
692                8, 8, 8, 8
693            ]
694        )
695    }
696}
697
698/// Compare packed half-precision (16-bit) floating-point elements in a and b based on the comparison
699/// operand specified by imm8, and store the results in mask vector k.
700///
701/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmp_ph_mask)
702#[inline]
703#[target_feature(enable = "avx512fp16,avx512vl")]
704#[rustc_legacy_const_generics(2)]
705#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
706pub fn _mm_cmp_ph_mask<const IMM5: i32>(a: __m128h, b: __m128h) -> __mmask8 {
707    _mm_mask_cmp_ph_mask::<IMM5>(!0, a, b)
708}
709
710/// Compare packed half-precision (16-bit) floating-point elements in a and b based on the comparison
711/// operand specified by imm8, and store the results in mask vector k using zeromask k (elements are
712/// zeroed out when the corresponding mask bit is not set).
713///
714/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cmp_ph_mask)
715#[inline]
716#[target_feature(enable = "avx512fp16,avx512vl")]
717#[rustc_legacy_const_generics(3)]
718#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
719pub fn _mm_mask_cmp_ph_mask<const IMM5: i32>(k1: __mmask8, a: __m128h, b: __m128h) -> __mmask8 {
720    unsafe {
721        static_assert_uimm_bits!(IMM5, 5);
722        vcmpph_128(a, b, IMM5, k1)
723    }
724}
725
726/// Compare packed half-precision (16-bit) floating-point elements in a and b based on the comparison
727/// operand specified by imm8, and store the results in mask vector k.
728///
729/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cmp_ph_mask)
730#[inline]
731#[target_feature(enable = "avx512fp16,avx512vl")]
732#[rustc_legacy_const_generics(2)]
733#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
734pub fn _mm256_cmp_ph_mask<const IMM5: i32>(a: __m256h, b: __m256h) -> __mmask16 {
735    _mm256_mask_cmp_ph_mask::<IMM5>(!0, a, b)
736}
737
738/// Compare packed half-precision (16-bit) floating-point elements in a and b based on the comparison
739/// operand specified by imm8, and store the results in mask vector k using zeromask k (elements are
740/// zeroed out when the corresponding mask bit is not set).
741///
742/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_cmp_ph_mask)
743#[inline]
744#[target_feature(enable = "avx512fp16,avx512vl")]
745#[rustc_legacy_const_generics(3)]
746#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
747pub fn _mm256_mask_cmp_ph_mask<const IMM5: i32>(
748    k1: __mmask16,
749    a: __m256h,
750    b: __m256h,
751) -> __mmask16 {
752    unsafe {
753        static_assert_uimm_bits!(IMM5, 5);
754        vcmpph_256(a, b, IMM5, k1)
755    }
756}
757
758/// Compare packed half-precision (16-bit) floating-point elements in a and b based on the comparison
759/// operand specified by imm8, and store the results in mask vector k.
760///
761/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmp_ph_mask)
762#[inline]
763#[target_feature(enable = "avx512fp16")]
764#[rustc_legacy_const_generics(2)]
765#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
766pub fn _mm512_cmp_ph_mask<const IMM5: i32>(a: __m512h, b: __m512h) -> __mmask32 {
767    _mm512_mask_cmp_ph_mask::<IMM5>(!0, a, b)
768}
769
770/// Compare packed half-precision (16-bit) floating-point elements in a and b based on the comparison
771/// operand specified by imm8, and store the results in mask vector k using zeromask k (elements are
772/// zeroed out when the corresponding mask bit is not set).
773///
774/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmp_ph_mask)
775#[inline]
776#[target_feature(enable = "avx512fp16")]
777#[rustc_legacy_const_generics(3)]
778#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
779pub fn _mm512_mask_cmp_ph_mask<const IMM5: i32>(
780    k1: __mmask32,
781    a: __m512h,
782    b: __m512h,
783) -> __mmask32 {
784    _mm512_mask_cmp_round_ph_mask::<IMM5, _MM_FROUND_CUR_DIRECTION>(k1, a, b)
785}
786
787/// Compare packed half-precision (16-bit) floating-point elements in a and b based on the comparison
788/// operand specified by imm8, and store the results in mask vector k.
789///
790/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter
791///
792/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmp_round_ph_mask)
793#[inline]
794#[target_feature(enable = "avx512fp16")]
795#[rustc_legacy_const_generics(2, 3)]
796#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
797pub fn _mm512_cmp_round_ph_mask<const IMM5: i32, const SAE: i32>(
798    a: __m512h,
799    b: __m512h,
800) -> __mmask32 {
801    _mm512_mask_cmp_round_ph_mask::<IMM5, SAE>(!0, a, b)
802}
803
804/// Compare packed half-precision (16-bit) floating-point elements in a and b based on the comparison
805/// operand specified by imm8, and store the results in mask vector k using zeromask k (elements are
806/// zeroed out when the corresponding mask bit is not set).
807///
808/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter
809///
810/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmp_round_ph_mask)
811#[inline]
812#[target_feature(enable = "avx512fp16")]
813#[rustc_legacy_const_generics(3, 4)]
814#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
815pub fn _mm512_mask_cmp_round_ph_mask<const IMM5: i32, const SAE: i32>(
816    k1: __mmask32,
817    a: __m512h,
818    b: __m512h,
819) -> __mmask32 {
820    unsafe {
821        static_assert_uimm_bits!(IMM5, 5);
822        static_assert_sae!(SAE);
823        vcmpph_512(a, b, IMM5, k1, SAE)
824    }
825}
826
827/// Compare the lower half-precision (16-bit) floating-point elements in a and b based on the comparison
828/// operand specified by imm8, and store the result in mask vector k. Exceptions can be suppressed by
829/// passing _MM_FROUND_NO_EXC in the sae parameter.
830///
831/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmp_round_sh_mask)
832#[inline]
833#[target_feature(enable = "avx512fp16")]
834#[rustc_legacy_const_generics(2, 3)]
835#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
836pub fn _mm_cmp_round_sh_mask<const IMM5: i32, const SAE: i32>(a: __m128h, b: __m128h) -> __mmask8 {
837    static_assert_uimm_bits!(IMM5, 5);
838    static_assert_sae!(SAE);
839    _mm_mask_cmp_round_sh_mask::<IMM5, SAE>(0xff, a, b)
840}
841
842/// Compare the lower half-precision (16-bit) floating-point elements in a and b based on the comparison
843/// operand specified by imm8, and store the result in mask vector k using zeromask k1. Exceptions can be
844/// suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
845///
846/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cmp_round_sh_mask)
847#[inline]
848#[target_feature(enable = "avx512fp16")]
849#[rustc_legacy_const_generics(3, 4)]
850#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
851pub fn _mm_mask_cmp_round_sh_mask<const IMM5: i32, const SAE: i32>(
852    k1: __mmask8,
853    a: __m128h,
854    b: __m128h,
855) -> __mmask8 {
856    unsafe {
857        static_assert_uimm_bits!(IMM5, 5);
858        static_assert_sae!(SAE);
859        vcmpsh(a, b, IMM5, k1, SAE)
860    }
861}
862
863/// Compare the lower half-precision (16-bit) floating-point elements in a and b based on the comparison
864/// operand specified by imm8, and store the result in mask vector k.
865///
866/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmp_sh_mask)
867#[inline]
868#[target_feature(enable = "avx512fp16")]
869#[rustc_legacy_const_generics(2)]
870#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
871pub fn _mm_cmp_sh_mask<const IMM5: i32>(a: __m128h, b: __m128h) -> __mmask8 {
872    static_assert_uimm_bits!(IMM5, 5);
873    _mm_cmp_round_sh_mask::<IMM5, _MM_FROUND_CUR_DIRECTION>(a, b)
874}
875
876/// Compare the lower half-precision (16-bit) floating-point elements in a and b based on the comparison
877/// operand specified by imm8, and store the result in mask vector k using zeromask k1.
878///
879/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cmp_sh_mask)
880#[inline]
881#[target_feature(enable = "avx512fp16")]
882#[rustc_legacy_const_generics(3)]
883#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
884pub fn _mm_mask_cmp_sh_mask<const IMM5: i32>(k1: __mmask8, a: __m128h, b: __m128h) -> __mmask8 {
885    static_assert_uimm_bits!(IMM5, 5);
886    _mm_mask_cmp_round_sh_mask::<IMM5, _MM_FROUND_CUR_DIRECTION>(k1, a, b)
887}
888
889/// Compare the lower half-precision (16-bit) floating-point elements in a and b based on the comparison
890/// operand specified by imm8, and return the boolean result (0 or 1).
891/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
892///
893/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comi_round_sh)
894#[inline]
895#[target_feature(enable = "avx512fp16")]
896#[rustc_legacy_const_generics(2, 3)]
897#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
898pub fn _mm_comi_round_sh<const IMM5: i32, const SAE: i32>(a: __m128h, b: __m128h) -> i32 {
899    unsafe {
900        static_assert_uimm_bits!(IMM5, 5);
901        static_assert_sae!(SAE);
902        vcomish(a, b, IMM5, SAE)
903    }
904}
905
906/// Compare the lower half-precision (16-bit) floating-point elements in a and b based on the comparison
907/// operand specified by imm8, and return the boolean result (0 or 1).
908///
909/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comi_sh)
910#[inline]
911#[target_feature(enable = "avx512fp16")]
912#[rustc_legacy_const_generics(2)]
913#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
914pub fn _mm_comi_sh<const IMM5: i32>(a: __m128h, b: __m128h) -> i32 {
915    static_assert_uimm_bits!(IMM5, 5);
916    _mm_comi_round_sh::<IMM5, _MM_FROUND_CUR_DIRECTION>(a, b)
917}
918
919/// Compare the lower half-precision (16-bit) floating-point elements in a and b for equality, and return
920/// the boolean result (0 or 1).
921///
922/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comieq_sh)
923#[inline]
924#[target_feature(enable = "avx512fp16")]
925#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
926pub fn _mm_comieq_sh(a: __m128h, b: __m128h) -> i32 {
927    _mm_comi_sh::<_CMP_EQ_OS>(a, b)
928}
929
930/// Compare the lower half-precision (16-bit) floating-point elements in a and b for greater-than-or-equal,
931/// and return the boolean result (0 or 1).
932///
933/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comige_sh)
934#[inline]
935#[target_feature(enable = "avx512fp16")]
936#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
937pub fn _mm_comige_sh(a: __m128h, b: __m128h) -> i32 {
938    _mm_comi_sh::<_CMP_GE_OS>(a, b)
939}
940
941/// Compare the lower half-precision (16-bit) floating-point elements in a and b for greater-than, and return
942/// the boolean result (0 or 1).
943///
944/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comigt_sh)
945#[inline]
946#[target_feature(enable = "avx512fp16")]
947#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
948pub fn _mm_comigt_sh(a: __m128h, b: __m128h) -> i32 {
949    _mm_comi_sh::<_CMP_GT_OS>(a, b)
950}
951
952/// Compare the lower half-precision (16-bit) floating-point elements in a and b for less-than-or-equal, and
953/// return the boolean result (0 or 1).
954///
955/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comile_sh)
956#[inline]
957#[target_feature(enable = "avx512fp16")]
958#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
959pub fn _mm_comile_sh(a: __m128h, b: __m128h) -> i32 {
960    _mm_comi_sh::<_CMP_LE_OS>(a, b)
961}
962
963/// Compare the lower half-precision (16-bit) floating-point elements in a and b for less-than, and return
964/// the boolean result (0 or 1).
965///
966/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comilt_sh)
967#[inline]
968#[target_feature(enable = "avx512fp16")]
969#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
970pub fn _mm_comilt_sh(a: __m128h, b: __m128h) -> i32 {
971    _mm_comi_sh::<_CMP_LT_OS>(a, b)
972}
973
974/// Compare the lower half-precision (16-bit) floating-point elements in a and b for not-equal, and return
975/// the boolean result (0 or 1).
976///
977/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comineq_sh)
978#[inline]
979#[target_feature(enable = "avx512fp16")]
980#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
981pub fn _mm_comineq_sh(a: __m128h, b: __m128h) -> i32 {
982    _mm_comi_sh::<_CMP_NEQ_US>(a, b)
983}
984
985/// Compare the lower half-precision (16-bit) floating-point elements in a and b for equality, and
986/// return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.
987///
988/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomieq_sh)
989#[inline]
990#[target_feature(enable = "avx512fp16")]
991#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
992pub fn _mm_ucomieq_sh(a: __m128h, b: __m128h) -> i32 {
993    _mm_comi_sh::<_CMP_EQ_OQ>(a, b)
994}
995
996/// Compare the lower half-precision (16-bit) floating-point elements in a and b for greater-than-or-equal,
997/// and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.
998///
999/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomige_sh)
1000#[inline]
1001#[target_feature(enable = "avx512fp16")]
1002#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1003pub fn _mm_ucomige_sh(a: __m128h, b: __m128h) -> i32 {
1004    _mm_comi_sh::<_CMP_GE_OQ>(a, b)
1005}
1006
1007/// Compare the lower half-precision (16-bit) floating-point elements in a and b for greater-than, and return
1008/// the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.
1009///
1010/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomigt_sh)
1011#[inline]
1012#[target_feature(enable = "avx512fp16")]
1013#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1014pub fn _mm_ucomigt_sh(a: __m128h, b: __m128h) -> i32 {
1015    _mm_comi_sh::<_CMP_GT_OQ>(a, b)
1016}
1017
1018/// Compare the lower half-precision (16-bit) floating-point elements in a and b for less-than-or-equal, and
1019/// return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.
1020///
1021/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomile_sh)
1022#[inline]
1023#[target_feature(enable = "avx512fp16")]
1024#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1025pub fn _mm_ucomile_sh(a: __m128h, b: __m128h) -> i32 {
1026    _mm_comi_sh::<_CMP_LE_OQ>(a, b)
1027}
1028
1029/// Compare the lower half-precision (16-bit) floating-point elements in a and b for less-than, and return
1030/// the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.
1031///
1032/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomilt_sh)
1033#[inline]
1034#[target_feature(enable = "avx512fp16")]
1035#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1036pub fn _mm_ucomilt_sh(a: __m128h, b: __m128h) -> i32 {
1037    _mm_comi_sh::<_CMP_LT_OQ>(a, b)
1038}
1039
1040/// Compare the lower half-precision (16-bit) floating-point elements in a and b for not-equal, and return
1041/// the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.
1042///
1043/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomineq_sh)
1044#[inline]
1045#[target_feature(enable = "avx512fp16")]
1046#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1047pub fn _mm_ucomineq_sh(a: __m128h, b: __m128h) -> i32 {
1048    _mm_comi_sh::<_CMP_NEQ_UQ>(a, b)
1049}
1050
1051/// Load 128-bits (composed of 8 packed half-precision (16-bit) floating-point elements) from memory into
1052/// a new vector. The address must be aligned to 16 bytes or a general-protection exception may be generated.
1053///
1054/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_load_ph)
1055#[inline]
1056#[target_feature(enable = "avx512fp16,avx512vl")]
1057#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
1058#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
1059pub const unsafe fn _mm_load_ph(mem_addr: *const f16) -> __m128h {
1060    *mem_addr.cast()
1061}
1062
1063/// Load 256-bits (composed of 16 packed half-precision (16-bit) floating-point elements) from memory into
1064/// a new vector. The address must be aligned to 32 bytes or a general-protection exception may be generated.
1065///
1066/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_load_ph)
1067#[inline]
1068#[target_feature(enable = "avx512fp16,avx512vl")]
1069#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
1070#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
1071pub const unsafe fn _mm256_load_ph(mem_addr: *const f16) -> __m256h {
1072    *mem_addr.cast()
1073}
1074
1075/// Load 512-bits (composed of 32 packed half-precision (16-bit) floating-point elements) from memory into
1076/// a new vector. The address must be aligned to 64 bytes or a general-protection exception may be generated.
1077///
1078/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_load_ph)
1079#[inline]
1080#[target_feature(enable = "avx512fp16")]
1081#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
1082#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
1083pub const unsafe fn _mm512_load_ph(mem_addr: *const f16) -> __m512h {
1084    *mem_addr.cast()
1085}
1086
1087/// Load a half-precision (16-bit) floating-point element from memory into the lower element of a new vector,
1088/// and zero the upper elements
1089///
1090/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_load_sh)
1091#[inline]
1092#[target_feature(enable = "avx512fp16")]
1093#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
1094#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
1095pub const unsafe fn _mm_load_sh(mem_addr: *const f16) -> __m128h {
1096    _mm_set_sh(*mem_addr)
1097}
1098
1099/// Load a half-precision (16-bit) floating-point element from memory into the lower element of a new vector
1100/// using writemask k (the element is copied from src when mask bit 0 is not set), and zero the upper elements.
1101///
1102/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_load_sh)
1103#[inline]
1104#[target_feature(enable = "avx512fp16")]
1105#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
1106pub unsafe fn _mm_mask_load_sh(src: __m128h, k: __mmask8, mem_addr: *const f16) -> __m128h {
1107    let mut dst = src;
1108    asm!(
1109        vpl!("vmovsh {dst}{{{k}}}"),
1110        dst = inout(xmm_reg) dst,
1111        k = in(kreg) k,
1112        p = in(reg) mem_addr,
1113        options(pure, readonly, nostack, preserves_flags)
1114    );
1115    dst
1116}
1117
1118/// Load a half-precision (16-bit) floating-point element from memory into the lower element of a new vector
1119/// using zeromask k (the element is zeroed out when mask bit 0 is not set), and zero the upper elements.
1120///
1121/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_load_sh)
1122#[inline]
1123#[target_feature(enable = "avx512fp16")]
1124#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
1125pub unsafe fn _mm_maskz_load_sh(k: __mmask8, mem_addr: *const f16) -> __m128h {
1126    let mut dst: __m128h;
1127    asm!(
1128        vpl!("vmovsh {dst}{{{k}}}{{z}}"),
1129        dst = out(xmm_reg) dst,
1130        k = in(kreg) k,
1131        p = in(reg) mem_addr,
1132        options(pure, readonly, nostack, preserves_flags)
1133    );
1134    dst
1135}
1136
1137/// Load 128-bits (composed of 8 packed half-precision (16-bit) floating-point elements) from memory into
1138/// a new vector. The address does not need to be aligned to any particular boundary.
1139///
1140/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_loadu_ph)
1141#[inline]
1142#[target_feature(enable = "avx512fp16,avx512vl")]
1143#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
1144#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
1145pub const unsafe fn _mm_loadu_ph(mem_addr: *const f16) -> __m128h {
1146    ptr::read_unaligned(mem_addr.cast())
1147}
1148
1149/// Load 256-bits (composed of 16 packed half-precision (16-bit) floating-point elements) from memory into
1150/// a new vector. The address does not need to be aligned to any particular boundary.
1151///
1152/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_loadu_ph)
1153#[inline]
1154#[target_feature(enable = "avx512fp16,avx512vl")]
1155#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
1156#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
1157pub const unsafe fn _mm256_loadu_ph(mem_addr: *const f16) -> __m256h {
1158    ptr::read_unaligned(mem_addr.cast())
1159}
1160
1161/// Load 512-bits (composed of 32 packed half-precision (16-bit) floating-point elements) from memory into
1162/// a new vector. The address does not need to be aligned to any particular boundary.
1163///
1164/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_loadu_ph)
1165#[inline]
1166#[target_feature(enable = "avx512fp16")]
1167#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
1168#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
1169pub const unsafe fn _mm512_loadu_ph(mem_addr: *const f16) -> __m512h {
1170    ptr::read_unaligned(mem_addr.cast())
1171}
1172
1173/// Move the lower half-precision (16-bit) floating-point element from b to the lower element of dst
1174/// using writemask k (the element is copied from src when mask bit 0 is not set), and copy the upper
1175/// 7 packed elements from a to the upper elements of dst.
1176///
1177/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_move_sh)
1178#[inline]
1179#[target_feature(enable = "avx512fp16")]
1180#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1181#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
1182pub const fn _mm_mask_move_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
1183    unsafe {
1184        let mut mov: f16 = simd_extract!(src, 0);
1185        if (k & 1) != 0 {
1186            mov = simd_extract!(b, 0);
1187        }
1188        simd_insert!(a, 0, mov)
1189    }
1190}
1191
1192/// Move the lower half-precision (16-bit) floating-point element from b to the lower element of dst
1193/// using zeromask k (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed
1194/// elements from a to the upper elements of dst.
1195///
1196/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_move_sh)
1197#[inline]
1198#[target_feature(enable = "avx512fp16")]
1199#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1200#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
1201pub const fn _mm_maskz_move_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
1202    unsafe {
1203        let mut mov: f16 = 0.;
1204        if (k & 1) != 0 {
1205            mov = simd_extract!(b, 0);
1206        }
1207        simd_insert!(a, 0, mov)
1208    }
1209}
1210
1211/// Move the lower half-precision (16-bit) floating-point element from b to the lower element of dst,
1212/// and copy the upper 7 packed elements from a to the upper elements of dst.
1213///
1214/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_move_sh)
1215#[inline]
1216#[target_feature(enable = "avx512fp16")]
1217#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1218#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
1219pub const fn _mm_move_sh(a: __m128h, b: __m128h) -> __m128h {
1220    unsafe {
1221        let mov: f16 = simd_extract!(b, 0);
1222        simd_insert!(a, 0, mov)
1223    }
1224}
1225
1226/// Store 128-bits (composed of 8 packed half-precision (16-bit) floating-point elements) from a into memory.
1227/// The address must be aligned to 16 bytes or a general-protection exception may be generated.
1228///
1229/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_store_ph)
1230#[inline]
1231#[target_feature(enable = "avx512fp16,avx512vl")]
1232#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
1233#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
1234pub const unsafe fn _mm_store_ph(mem_addr: *mut f16, a: __m128h) {
1235    *mem_addr.cast() = a;
1236}
1237
1238/// Store 256-bits (composed of 16 packed half-precision (16-bit) floating-point elements) from a into memory.
1239/// The address must be aligned to 32 bytes or a general-protection exception may be generated.
1240///
1241/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_store_ph)
1242#[inline]
1243#[target_feature(enable = "avx512fp16,avx512vl")]
1244#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
1245#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
1246pub const unsafe fn _mm256_store_ph(mem_addr: *mut f16, a: __m256h) {
1247    *mem_addr.cast() = a;
1248}
1249
1250/// Store 512-bits (composed of 32 packed half-precision (16-bit) floating-point elements) from a into memory.
1251/// The address must be aligned to 64 bytes or a general-protection exception may be generated.
1252///
1253/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_store_ph)
1254#[inline]
1255#[target_feature(enable = "avx512fp16")]
1256#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
1257#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
1258pub const unsafe fn _mm512_store_ph(mem_addr: *mut f16, a: __m512h) {
1259    *mem_addr.cast() = a;
1260}
1261
1262/// Store the lower half-precision (16-bit) floating-point element from a into memory.
1263///
1264/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_store_sh)
1265#[inline]
1266#[target_feature(enable = "avx512fp16")]
1267#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
1268#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
1269pub const unsafe fn _mm_store_sh(mem_addr: *mut f16, a: __m128h) {
1270    *mem_addr = simd_extract!(a, 0);
1271}
1272
1273/// Store the lower half-precision (16-bit) floating-point element from a into memory using writemask k
1274///
1275/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_store_sh)
1276#[inline]
1277#[target_feature(enable = "avx512fp16")]
1278#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
1279pub unsafe fn _mm_mask_store_sh(mem_addr: *mut f16, k: __mmask8, a: __m128h) {
1280    asm!(
1281        vps!("vmovdqu16", "{{{k}}}, {src}"),
1282        p = in(reg) mem_addr,
1283        k = in(kreg) k,
1284        src = in(xmm_reg) a,
1285        options(nostack, preserves_flags)
1286    );
1287}
1288
1289/// Store 128-bits (composed of 8 packed half-precision (16-bit) floating-point elements) from a into memory.
1290/// The address does not need to be aligned to any particular boundary.
1291///
1292/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_storeu_ph)
1293#[inline]
1294#[target_feature(enable = "avx512fp16,avx512vl")]
1295#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
1296#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
1297pub const unsafe fn _mm_storeu_ph(mem_addr: *mut f16, a: __m128h) {
1298    ptr::write_unaligned(mem_addr.cast(), a);
1299}
1300
1301/// Store 256-bits (composed of 16 packed half-precision (16-bit) floating-point elements) from a into memory.
1302/// The address does not need to be aligned to any particular boundary.
1303///
1304/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_storeu_ph)
1305#[inline]
1306#[target_feature(enable = "avx512fp16,avx512vl")]
1307#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
1308#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
1309pub const unsafe fn _mm256_storeu_ph(mem_addr: *mut f16, a: __m256h) {
1310    ptr::write_unaligned(mem_addr.cast(), a);
1311}
1312
1313/// Store 512-bits (composed of 32 packed half-precision (16-bit) floating-point elements) from a into memory.
1314/// The address does not need to be aligned to any particular boundary.
1315///
1316/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_storeu_ph)
1317#[inline]
1318#[target_feature(enable = "avx512fp16")]
1319#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
1320#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
1321pub const unsafe fn _mm512_storeu_ph(mem_addr: *mut f16, a: __m512h) {
1322    ptr::write_unaligned(mem_addr.cast(), a);
1323}
1324
1325/// Add packed half-precision (16-bit) floating-point elements in a and b, and store the results in dst.
1326///
1327/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_add_ph)
1328#[inline]
1329#[target_feature(enable = "avx512fp16,avx512vl")]
1330#[cfg_attr(test, assert_instr(vaddph))]
1331#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1332#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
1333pub const fn _mm_add_ph(a: __m128h, b: __m128h) -> __m128h {
1334    unsafe { simd_add(a, b) }
1335}
1336
1337/// Add packed half-precision (16-bit) floating-point elements in a and b, and store the results in dst using
1338/// writemask k (elements are copied from src when the corresponding mask bit is not set).
1339///
1340/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_add_ph)
1341#[inline]
1342#[target_feature(enable = "avx512fp16,avx512vl")]
1343#[cfg_attr(test, assert_instr(vaddph))]
1344#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1345#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
1346pub const fn _mm_mask_add_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
1347    unsafe {
1348        let r = _mm_add_ph(a, b);
1349        simd_select_bitmask(k, r, src)
1350    }
1351}
1352
1353/// Add packed half-precision (16-bit) floating-point elements in a and b, and store the results in dst using
1354/// zeromask k (elements are zeroed out when the corresponding mask bit is not set).
1355///
1356/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_add_ph)
1357#[inline]
1358#[target_feature(enable = "avx512fp16,avx512vl")]
1359#[cfg_attr(test, assert_instr(vaddph))]
1360#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1361#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
1362pub const fn _mm_maskz_add_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
1363    unsafe {
1364        let r = _mm_add_ph(a, b);
1365        simd_select_bitmask(k, r, _mm_setzero_ph())
1366    }
1367}
1368
1369/// Add packed half-precision (16-bit) floating-point elements in a and b, and store the results in dst.
1370///
1371/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_add_ph)
1372#[inline]
1373#[target_feature(enable = "avx512fp16,avx512vl")]
1374#[cfg_attr(test, assert_instr(vaddph))]
1375#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1376#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
1377pub const fn _mm256_add_ph(a: __m256h, b: __m256h) -> __m256h {
1378    unsafe { simd_add(a, b) }
1379}
1380
1381/// Add packed half-precision (16-bit) floating-point elements in a and b, and store the results in dst using
1382/// writemask k (elements are copied from src when the corresponding mask bit is not set).
1383///
1384/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_add_ph)
1385#[inline]
1386#[target_feature(enable = "avx512fp16,avx512vl")]
1387#[cfg_attr(test, assert_instr(vaddph))]
1388#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1389#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
1390pub const fn _mm256_mask_add_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
1391    unsafe {
1392        let r = _mm256_add_ph(a, b);
1393        simd_select_bitmask(k, r, src)
1394    }
1395}
1396
1397/// Add packed half-precision (16-bit) floating-point elements in a and b, and store the results in dst using
1398/// zeromask k (elements are zeroed out when the corresponding mask bit is not set).
1399///
1400/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_add_ph)
1401#[inline]
1402#[target_feature(enable = "avx512fp16,avx512vl")]
1403#[cfg_attr(test, assert_instr(vaddph))]
1404#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1405#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
1406pub const fn _mm256_maskz_add_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
1407    unsafe {
1408        let r = _mm256_add_ph(a, b);
1409        simd_select_bitmask(k, r, _mm256_setzero_ph())
1410    }
1411}
1412
1413/// Add packed half-precision (16-bit) floating-point elements in a and b, and store the results in dst.
1414///
1415/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_add_ph)
1416#[inline]
1417#[target_feature(enable = "avx512fp16")]
1418#[cfg_attr(test, assert_instr(vaddph))]
1419#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1420#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
1421pub const fn _mm512_add_ph(a: __m512h, b: __m512h) -> __m512h {
1422    unsafe { simd_add(a, b) }
1423}
1424
1425/// Add packed half-precision (16-bit) floating-point elements in a and b, and store the results in dst using
1426/// writemask k (elements are copied from src when the corresponding mask bit is not set).
1427///
1428/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_add_ph)
1429#[inline]
1430#[target_feature(enable = "avx512fp16")]
1431#[cfg_attr(test, assert_instr(vaddph))]
1432#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1433#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
1434pub const fn _mm512_mask_add_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
1435    unsafe {
1436        let r = _mm512_add_ph(a, b);
1437        simd_select_bitmask(k, r, src)
1438    }
1439}
1440
1441/// Add packed half-precision (16-bit) floating-point elements in a and b, and store the results in dst using
1442/// zeromask k (elements are zeroed out when the corresponding mask bit is not set).
1443///
1444/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_add_ph)
1445#[inline]
1446#[target_feature(enable = "avx512fp16")]
1447#[cfg_attr(test, assert_instr(vaddph))]
1448#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1449#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
1450pub const fn _mm512_maskz_add_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
1451    unsafe {
1452        let r = _mm512_add_ph(a, b);
1453        simd_select_bitmask(k, r, _mm512_setzero_ph())
1454    }
1455}
1456
1457/// Add packed half-precision (16-bit) floating-point elements in a and b, and store the results in dst.
1458/// Rounding is done according to the rounding parameter, which can be one of:
1459///
1460/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
1461/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
1462/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
1463/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
1464/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
1465///
1466/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_add_round_ph)
1467#[inline]
1468#[target_feature(enable = "avx512fp16")]
1469#[cfg_attr(test, assert_instr(vaddph, ROUNDING = 8))]
1470#[rustc_legacy_const_generics(2)]
1471#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1472pub fn _mm512_add_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __m512h {
1473    unsafe {
1474        static_assert_rounding!(ROUNDING);
1475        vaddph(a, b, ROUNDING)
1476    }
1477}
1478
1479/// Add packed half-precision (16-bit) floating-point elements in a and b, and store the results in dst using
1480/// writemask k (elements are copied from src when the corresponding mask bit is not set).
1481/// Rounding is done according to the rounding parameter, which can be one of:
1482///
1483/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
1484/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
1485/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
1486/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
1487/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
1488///
1489/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_add_round_ph)
1490#[inline]
1491#[target_feature(enable = "avx512fp16")]
1492#[cfg_attr(test, assert_instr(vaddph, ROUNDING = 8))]
1493#[rustc_legacy_const_generics(4)]
1494#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1495pub fn _mm512_mask_add_round_ph<const ROUNDING: i32>(
1496    src: __m512h,
1497    k: __mmask32,
1498    a: __m512h,
1499    b: __m512h,
1500) -> __m512h {
1501    unsafe {
1502        static_assert_rounding!(ROUNDING);
1503        let r = _mm512_add_round_ph::<ROUNDING>(a, b);
1504        simd_select_bitmask(k, r, src)
1505    }
1506}
1507
1508/// Add packed half-precision (16-bit) floating-point elements in a and b, and store the results in dst using
1509/// zeromask k (elements are zeroed out when the corresponding mask bit is not set).
1510/// Rounding is done according to the rounding parameter, which can be one of:
1511///
1512/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
1513/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
1514/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
1515/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
1516///
1517/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_add_round_ph)
1518#[inline]
1519#[target_feature(enable = "avx512fp16")]
1520#[cfg_attr(test, assert_instr(vaddph, ROUNDING = 8))]
1521#[rustc_legacy_const_generics(3)]
1522#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1523pub fn _mm512_maskz_add_round_ph<const ROUNDING: i32>(
1524    k: __mmask32,
1525    a: __m512h,
1526    b: __m512h,
1527) -> __m512h {
1528    unsafe {
1529        static_assert_rounding!(ROUNDING);
1530        let r = _mm512_add_round_ph::<ROUNDING>(a, b);
1531        simd_select_bitmask(k, r, _mm512_setzero_ph())
1532    }
1533}
1534
1535/// Add the lower half-precision (16-bit) floating-point elements in a and b, store the result in the
1536/// lower element of dst, and copy the upper 7 packed elements from a to the upper elements of dst.
1537/// Rounding is done according to the rounding parameter, which can be one of:
1538///
1539/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
1540/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
1541/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
1542/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
1543/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
1544///
1545/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_add_round_sh)
1546#[inline]
1547#[target_feature(enable = "avx512fp16")]
1548#[cfg_attr(test, assert_instr(vaddsh, ROUNDING = 8))]
1549#[rustc_legacy_const_generics(2)]
1550#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1551pub fn _mm_add_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128h {
1552    static_assert_rounding!(ROUNDING);
1553    _mm_mask_add_round_sh::<ROUNDING>(f16x8::ZERO.as_m128h(), 0xff, a, b)
1554}
1555
1556/// Add the lower half-precision (16-bit) floating-point elements in a and b, store the result in the
1557/// lower element of dst, and copy the upper 7 packed elements from a to the upper elements of dst using
1558/// writemask k (the element is copied from src when mask bit 0 is not set).
1559/// Rounding is done according to the rounding parameter, which can be one of:
1560///
1561/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
1562/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
1563/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
1564/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
1565/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
1566///
1567/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_add_round_sh)
1568#[inline]
1569#[target_feature(enable = "avx512fp16")]
1570#[cfg_attr(test, assert_instr(vaddsh, ROUNDING = 8))]
1571#[rustc_legacy_const_generics(4)]
1572#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1573pub fn _mm_mask_add_round_sh<const ROUNDING: i32>(
1574    src: __m128h,
1575    k: __mmask8,
1576    a: __m128h,
1577    b: __m128h,
1578) -> __m128h {
1579    unsafe {
1580        static_assert_rounding!(ROUNDING);
1581        vaddsh(a, b, src, k, ROUNDING)
1582    }
1583}
1584
1585/// Add the lower half-precision (16-bit) floating-point elements in a and b, store the result in the
1586/// lower element of dst, and copy the upper 7 packed elements from a to the upper elements of dst using
1587/// zeromask k (the element is zeroed out when mask bit 0 is not set).
1588/// Rounding is done according to the rounding parameter, which can be one of:
1589///
1590/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
1591/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
1592/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
1593/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
1594/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
1595///
1596/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_add_round_sh)
1597#[inline]
1598#[target_feature(enable = "avx512fp16")]
1599#[cfg_attr(test, assert_instr(vaddsh, ROUNDING = 8))]
1600#[rustc_legacy_const_generics(3)]
1601#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1602pub fn _mm_maskz_add_round_sh<const ROUNDING: i32>(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
1603    static_assert_rounding!(ROUNDING);
1604    _mm_mask_add_round_sh::<ROUNDING>(f16x8::ZERO.as_m128h(), k, a, b)
1605}
1606
1607/// Add the lower half-precision (16-bit) floating-point elements in a and b, store the result in the
1608/// lower element of dst, and copy the upper 7 packed elements from a to the upper elements of dst.
1609///
1610/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_add_sh)
1611#[inline]
1612#[target_feature(enable = "avx512fp16")]
1613#[cfg_attr(test, assert_instr(vaddsh))]
1614#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1615#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
1616pub const fn _mm_add_sh(a: __m128h, b: __m128h) -> __m128h {
1617    unsafe { simd_insert!(a, 0, _mm_cvtsh_h(a) + _mm_cvtsh_h(b)) }
1618}
1619
1620/// Add the lower half-precision (16-bit) floating-point elements in a and b, store the result in the
1621/// lower element of dst, and copy the upper 7 packed elements from a to the upper elements of dst using
1622/// writemask k (the element is copied from src when mask bit 0 is not set).
1623///
1624/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_add_sh)
1625#[inline]
1626#[target_feature(enable = "avx512fp16")]
1627#[cfg_attr(test, assert_instr(vaddsh))]
1628#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1629#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
1630pub const fn _mm_mask_add_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
1631    unsafe {
1632        let extractsrc: f16 = simd_extract!(src, 0);
1633        let mut add: f16 = extractsrc;
1634        if (k & 0b00000001) != 0 {
1635            let extracta: f16 = simd_extract!(a, 0);
1636            let extractb: f16 = simd_extract!(b, 0);
1637            add = extracta + extractb;
1638        }
1639        simd_insert!(a, 0, add)
1640    }
1641}
1642
1643/// Add the lower half-precision (16-bit) floating-point elements in a and b, store the result in the
1644/// lower element of dst, and copy the upper 7 packed elements from a to the upper elements of dst using
1645/// zeromask k (the element is zeroed out when mask bit 0 is not set).
1646///
1647/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_add_sh)
1648#[inline]
1649#[target_feature(enable = "avx512fp16")]
1650#[cfg_attr(test, assert_instr(vaddsh))]
1651#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1652#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
1653pub const fn _mm_maskz_add_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
1654    unsafe {
1655        let mut add: f16 = 0.;
1656        if (k & 0b00000001) != 0 {
1657            let extracta: f16 = simd_extract!(a, 0);
1658            let extractb: f16 = simd_extract!(b, 0);
1659            add = extracta + extractb;
1660        }
1661        simd_insert!(a, 0, add)
1662    }
1663}
1664
1665/// Subtract packed half-precision (16-bit) floating-point elements in b from a, and store the results in dst.
1666///
1667/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sub_ph)
1668#[inline]
1669#[target_feature(enable = "avx512fp16,avx512vl")]
1670#[cfg_attr(test, assert_instr(vsubph))]
1671#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1672#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
1673pub const fn _mm_sub_ph(a: __m128h, b: __m128h) -> __m128h {
1674    unsafe { simd_sub(a, b) }
1675}
1676
1677/// Subtract packed half-precision (16-bit) floating-point elements in b from a, and store the results in dst using
1678/// writemask k (elements are copied from src when the corresponding mask bit is not set).
1679///
1680/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_sub_ph)
1681#[inline]
1682#[target_feature(enable = "avx512fp16,avx512vl")]
1683#[cfg_attr(test, assert_instr(vsubph))]
1684#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1685#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
1686pub const fn _mm_mask_sub_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
1687    unsafe {
1688        let r = _mm_sub_ph(a, b);
1689        simd_select_bitmask(k, r, src)
1690    }
1691}
1692
1693/// Subtract packed half-precision (16-bit) floating-point elements in b from a, and store the results in dst using
1694/// zeromask k (elements are zeroed out when the corresponding mask bit is not set).
1695///
1696/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_sub_ph)
1697#[inline]
1698#[target_feature(enable = "avx512fp16,avx512vl")]
1699#[cfg_attr(test, assert_instr(vsubph))]
1700#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1701#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
1702pub const fn _mm_maskz_sub_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
1703    unsafe {
1704        let r = _mm_sub_ph(a, b);
1705        simd_select_bitmask(k, r, _mm_setzero_ph())
1706    }
1707}
1708
1709/// Subtract packed half-precision (16-bit) floating-point elements in b from a, and store the results in dst.
1710///
1711/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_sub_ph)
1712#[inline]
1713#[target_feature(enable = "avx512fp16,avx512vl")]
1714#[cfg_attr(test, assert_instr(vsubph))]
1715#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1716#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
1717pub const fn _mm256_sub_ph(a: __m256h, b: __m256h) -> __m256h {
1718    unsafe { simd_sub(a, b) }
1719}
1720
1721/// Subtract packed half-precision (16-bit) floating-point elements in b from a, and store the results in dst using
1722/// writemask k (elements are copied from src when the corresponding mask bit is not set).
1723///
1724/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_sub_ph)
1725#[inline]
1726#[target_feature(enable = "avx512fp16,avx512vl")]
1727#[cfg_attr(test, assert_instr(vsubph))]
1728#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1729#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
1730pub const fn _mm256_mask_sub_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
1731    unsafe {
1732        let r = _mm256_sub_ph(a, b);
1733        simd_select_bitmask(k, r, src)
1734    }
1735}
1736
1737/// Subtract packed half-precision (16-bit) floating-point elements in b from a, and store the results in dst using
1738/// zeromask k (elements are zeroed out when the corresponding mask bit is not set).
1739///
1740/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_sub_ph)
1741#[inline]
1742#[target_feature(enable = "avx512fp16,avx512vl")]
1743#[cfg_attr(test, assert_instr(vsubph))]
1744#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1745#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
1746pub const fn _mm256_maskz_sub_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
1747    unsafe {
1748        let r = _mm256_sub_ph(a, b);
1749        simd_select_bitmask(k, r, _mm256_setzero_ph())
1750    }
1751}
1752
1753/// Subtract packed half-precision (16-bit) floating-point elements in b from a, and store the results in dst.
1754///
1755/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_sub_ph)
1756#[inline]
1757#[target_feature(enable = "avx512fp16")]
1758#[cfg_attr(test, assert_instr(vsubph))]
1759#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1760#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
1761pub const fn _mm512_sub_ph(a: __m512h, b: __m512h) -> __m512h {
1762    unsafe { simd_sub(a, b) }
1763}
1764
1765/// Subtract packed half-precision (16-bit) floating-point elements in b from a, and store the results in dst using
1766/// writemask k (elements are copied from src when the corresponding mask bit is not set).
1767///
1768/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_sub_ph)
1769#[inline]
1770#[target_feature(enable = "avx512fp16")]
1771#[cfg_attr(test, assert_instr(vsubph))]
1772#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1773#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
1774pub const fn _mm512_mask_sub_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
1775    unsafe {
1776        let r = _mm512_sub_ph(a, b);
1777        simd_select_bitmask(k, r, src)
1778    }
1779}
1780
1781/// Subtract packed half-precision (16-bit) floating-point elements in b from a, and store the results in dst using
1782/// zeromask k (elements are zeroed out when the corresponding mask bit is not set).
1783///
1784/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_sub_ph)
1785#[inline]
1786#[target_feature(enable = "avx512fp16")]
1787#[cfg_attr(test, assert_instr(vsubph))]
1788#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1789#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
1790pub const fn _mm512_maskz_sub_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
1791    unsafe {
1792        let r = _mm512_sub_ph(a, b);
1793        simd_select_bitmask(k, r, _mm512_setzero_ph())
1794    }
1795}
1796
1797/// Subtract packed half-precision (16-bit) floating-point elements in b from a, and store the results in dst.
1798/// Rounding is done according to the rounding parameter, which can be one of:
1799///
1800/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
1801/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
1802/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
1803/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
1804/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
1805///
1806/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_sub_round_ph)
1807#[inline]
1808#[target_feature(enable = "avx512fp16")]
1809#[cfg_attr(test, assert_instr(vsubph, ROUNDING = 8))]
1810#[rustc_legacy_const_generics(2)]
1811#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1812pub fn _mm512_sub_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __m512h {
1813    unsafe {
1814        static_assert_rounding!(ROUNDING);
1815        vsubph(a, b, ROUNDING)
1816    }
1817}
1818
1819/// Subtract packed half-precision (16-bit) floating-point elements in b from a, and store the results in dst using
1820/// writemask k (elements are copied from src when the corresponding mask bit is not set).
1821/// Rounding is done according to the rounding parameter, which can be one of:
1822///
1823/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
1824/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
1825/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
1826/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
1827/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
1828///
1829/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_sub_round_ph)
1830#[inline]
1831#[target_feature(enable = "avx512fp16")]
1832#[cfg_attr(test, assert_instr(vsubph, ROUNDING = 8))]
1833#[rustc_legacy_const_generics(4)]
1834#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1835pub fn _mm512_mask_sub_round_ph<const ROUNDING: i32>(
1836    src: __m512h,
1837    k: __mmask32,
1838    a: __m512h,
1839    b: __m512h,
1840) -> __m512h {
1841    unsafe {
1842        static_assert_rounding!(ROUNDING);
1843        let r = _mm512_sub_round_ph::<ROUNDING>(a, b);
1844        simd_select_bitmask(k, r, src)
1845    }
1846}
1847
1848/// Subtract packed half-precision (16-bit) floating-point elements in b from a, and store the results in dst using
1849/// zeromask k (elements are zeroed out when the corresponding mask bit is not set).
1850/// Rounding is done according to the rounding parameter, which can be one of:
1851///
1852/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
1853/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
1854/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
1855/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
1856/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
1857///
1858/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_sub_round_ph)
1859#[inline]
1860#[target_feature(enable = "avx512fp16")]
1861#[cfg_attr(test, assert_instr(vsubph, ROUNDING = 8))]
1862#[rustc_legacy_const_generics(3)]
1863#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1864pub fn _mm512_maskz_sub_round_ph<const ROUNDING: i32>(
1865    k: __mmask32,
1866    a: __m512h,
1867    b: __m512h,
1868) -> __m512h {
1869    unsafe {
1870        static_assert_rounding!(ROUNDING);
1871        let r = _mm512_sub_round_ph::<ROUNDING>(a, b);
1872        simd_select_bitmask(k, r, _mm512_setzero_ph())
1873    }
1874}
1875
1876/// Subtract the lower half-precision (16-bit) floating-point elements in b from a, store the result in the
1877/// lower element of dst, and copy the upper 7 packed elements from a to the upper elements of dst.
1878/// Rounding is done according to the rounding parameter, which can be one of:
1879///
1880/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
1881/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
1882/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
1883/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
1884/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
1885///
1886/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sub_round_sh)
1887#[inline]
1888#[target_feature(enable = "avx512fp16")]
1889#[cfg_attr(test, assert_instr(vsubsh, ROUNDING = 8))]
1890#[rustc_legacy_const_generics(2)]
1891#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1892pub fn _mm_sub_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128h {
1893    static_assert_rounding!(ROUNDING);
1894    _mm_mask_sub_round_sh::<ROUNDING>(f16x8::ZERO.as_m128h(), 0xff, a, b)
1895}
1896
1897/// Subtract the lower half-precision (16-bit) floating-point elements in b from a, store the result in the
1898/// lower element of dst, and copy the upper 7 packed elements from a to the upper elements of dst using
1899/// writemask k (the element is copied from src when mask bit 0 is not set).
1900/// Rounding is done according to the rounding parameter, which can be one of:
1901///
1902/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
1903/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
1904/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
1905/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
1906/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
1907///
1908/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_sub_round_sh)
1909#[inline]
1910#[target_feature(enable = "avx512fp16")]
1911#[cfg_attr(test, assert_instr(vsubsh, ROUNDING = 8))]
1912#[rustc_legacy_const_generics(4)]
1913#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1914pub fn _mm_mask_sub_round_sh<const ROUNDING: i32>(
1915    src: __m128h,
1916    k: __mmask8,
1917    a: __m128h,
1918    b: __m128h,
1919) -> __m128h {
1920    unsafe {
1921        static_assert_rounding!(ROUNDING);
1922        vsubsh(a, b, src, k, ROUNDING)
1923    }
1924}
1925
1926/// Subtract the lower half-precision (16-bit) floating-point elements in b from a, store the result in the
1927/// lower element of dst, and copy the upper 7 packed elements from a to the upper elements of dst using
1928/// zeromask k (the element is zeroed out when mask bit 0 is not set).
1929/// Rounding is done according to the rounding parameter, which can be one of:
1930///
1931/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
1932/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
1933/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
1934/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
1935/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
1936///
1937/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_sub_round_sh)
1938#[inline]
1939#[target_feature(enable = "avx512fp16")]
1940#[cfg_attr(test, assert_instr(vsubsh, ROUNDING = 8))]
1941#[rustc_legacy_const_generics(3)]
1942#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1943pub fn _mm_maskz_sub_round_sh<const ROUNDING: i32>(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
1944    static_assert_rounding!(ROUNDING);
1945    _mm_mask_sub_round_sh::<ROUNDING>(f16x8::ZERO.as_m128h(), k, a, b)
1946}
1947
1948/// Subtract the lower half-precision (16-bit) floating-point elements in b from a, store the result in the
1949/// lower element of dst, and copy the upper 7 packed elements from a to the upper elements of dst.
1950///
1951/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sub_sh)
1952#[inline]
1953#[target_feature(enable = "avx512fp16")]
1954#[cfg_attr(test, assert_instr(vsubsh))]
1955#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1956#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
1957pub const fn _mm_sub_sh(a: __m128h, b: __m128h) -> __m128h {
1958    unsafe { simd_insert!(a, 0, _mm_cvtsh_h(a) - _mm_cvtsh_h(b)) }
1959}
1960
1961/// Subtract the lower half-precision (16-bit) floating-point elements in b from a, store the result in the
1962/// lower element of dst, and copy the upper 7 packed elements from a to the upper elements of dst using
1963/// writemask k (the element is copied from src when mask bit 0 is not set).
1964///
1965/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_sub_sh)
1966#[inline]
1967#[target_feature(enable = "avx512fp16")]
1968#[cfg_attr(test, assert_instr(vsubsh))]
1969#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1970#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
1971pub const fn _mm_mask_sub_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
1972    unsafe {
1973        let extractsrc: f16 = simd_extract!(src, 0);
1974        let mut add: f16 = extractsrc;
1975        if (k & 0b00000001) != 0 {
1976            let extracta: f16 = simd_extract!(a, 0);
1977            let extractb: f16 = simd_extract!(b, 0);
1978            add = extracta - extractb;
1979        }
1980        simd_insert!(a, 0, add)
1981    }
1982}
1983
1984/// Subtract the lower half-precision (16-bit) floating-point elements in b from a, store the result in the
1985/// lower element of dst, and copy the upper 7 packed elements from a to the upper elements of dst using
1986/// zeromask k (the element is zeroed out when mask bit 0 is not set).
1987///
1988/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_sub_sh)
1989#[inline]
1990#[target_feature(enable = "avx512fp16")]
1991#[cfg_attr(test, assert_instr(vsubsh))]
1992#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
1993#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
1994pub const fn _mm_maskz_sub_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
1995    unsafe {
1996        let mut add: f16 = 0.;
1997        if (k & 0b00000001) != 0 {
1998            let extracta: f16 = simd_extract!(a, 0);
1999            let extractb: f16 = simd_extract!(b, 0);
2000            add = extracta - extractb;
2001        }
2002        simd_insert!(a, 0, add)
2003    }
2004}
2005
2006/// Multiply packed half-precision (16-bit) floating-point elements in a and b, and store the results in dst.
2007///
2008/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mul_ph)
2009#[inline]
2010#[target_feature(enable = "avx512fp16,avx512vl")]
2011#[cfg_attr(test, assert_instr(vmulph))]
2012#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2013#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
2014pub const fn _mm_mul_ph(a: __m128h, b: __m128h) -> __m128h {
2015    unsafe { simd_mul(a, b) }
2016}
2017
2018/// Multiply packed half-precision (16-bit) floating-point elements in a and b, and store the results in dst using
2019/// writemask k (elements are copied from src when the corresponding mask bit is not set).
2020///
2021/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_mul_ph)
2022#[inline]
2023#[target_feature(enable = "avx512fp16,avx512vl")]
2024#[cfg_attr(test, assert_instr(vmulph))]
2025#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2026#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
2027pub const fn _mm_mask_mul_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
2028    unsafe {
2029        let r = _mm_mul_ph(a, b);
2030        simd_select_bitmask(k, r, src)
2031    }
2032}
2033
2034/// Multiply packed half-precision (16-bit) floating-point elements in a and b, and store the results in dst using
2035/// zeromask k (elements are zeroed out when the corresponding mask bit is not set).
2036///
2037/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_mul_ph)
2038#[inline]
2039#[target_feature(enable = "avx512fp16,avx512vl")]
2040#[cfg_attr(test, assert_instr(vmulph))]
2041#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2042#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
2043pub const fn _mm_maskz_mul_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
2044    unsafe {
2045        let r = _mm_mul_ph(a, b);
2046        simd_select_bitmask(k, r, _mm_setzero_ph())
2047    }
2048}
2049
2050/// Multiply packed half-precision (16-bit) floating-point elements in a and b, and store the results in dst.
2051///
2052/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mul_ph)
2053#[inline]
2054#[target_feature(enable = "avx512fp16,avx512vl")]
2055#[cfg_attr(test, assert_instr(vmulph))]
2056#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2057#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
2058pub const fn _mm256_mul_ph(a: __m256h, b: __m256h) -> __m256h {
2059    unsafe { simd_mul(a, b) }
2060}
2061
2062/// Multiply packed half-precision (16-bit) floating-point elements in a and b, and store the results in dst using
2063/// writemask k (elements are copied from src when the corresponding mask bit is not set).
2064///
2065/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_mul_ph)
2066#[inline]
2067#[target_feature(enable = "avx512fp16,avx512vl")]
2068#[cfg_attr(test, assert_instr(vmulph))]
2069#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2070#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
2071pub const fn _mm256_mask_mul_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
2072    unsafe {
2073        let r = _mm256_mul_ph(a, b);
2074        simd_select_bitmask(k, r, src)
2075    }
2076}
2077
2078/// Multiply packed half-precision (16-bit) floating-point elements in a and b, and store the results in dst using
2079/// zeromask k (elements are zeroed out when the corresponding mask bit is not set).
2080///
2081/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_mul_ph)
2082#[inline]
2083#[target_feature(enable = "avx512fp16,avx512vl")]
2084#[cfg_attr(test, assert_instr(vmulph))]
2085#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2086#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
2087pub const fn _mm256_maskz_mul_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
2088    unsafe {
2089        let r = _mm256_mul_ph(a, b);
2090        simd_select_bitmask(k, r, _mm256_setzero_ph())
2091    }
2092}
2093
2094/// Multiply packed half-precision (16-bit) floating-point elements in a and b, and store the results in dst.
2095///
2096/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mul_ph)
2097#[inline]
2098#[target_feature(enable = "avx512fp16")]
2099#[cfg_attr(test, assert_instr(vmulph))]
2100#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2101#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
2102pub const fn _mm512_mul_ph(a: __m512h, b: __m512h) -> __m512h {
2103    unsafe { simd_mul(a, b) }
2104}
2105
2106/// Multiply packed half-precision (16-bit) floating-point elements in a and b, and store the results in dst using
2107/// writemask k (elements are copied from src when the corresponding mask bit is not set).
2108///
2109/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_mul_ph)
2110#[inline]
2111#[target_feature(enable = "avx512fp16")]
2112#[cfg_attr(test, assert_instr(vmulph))]
2113#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2114#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
2115pub const fn _mm512_mask_mul_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
2116    unsafe {
2117        let r = _mm512_mul_ph(a, b);
2118        simd_select_bitmask(k, r, src)
2119    }
2120}
2121
2122/// Multiply packed half-precision (16-bit) floating-point elements in a and b, and store the results in dst using
2123/// zeromask k (elements are zeroed out when the corresponding mask bit is not set).
2124///
2125/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_mul_ph)
2126#[inline]
2127#[target_feature(enable = "avx512fp16")]
2128#[cfg_attr(test, assert_instr(vmulph))]
2129#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2130#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
2131pub const fn _mm512_maskz_mul_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
2132    unsafe {
2133        let r = _mm512_mul_ph(a, b);
2134        simd_select_bitmask(k, r, _mm512_setzero_ph())
2135    }
2136}
2137
2138/// Multiply packed half-precision (16-bit) floating-point elements in a and b, and store the results in dst.
2139/// Rounding is done according to the rounding parameter, which can be one of:
2140///
2141/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
2142/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
2143/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
2144/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
2145/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
2146///
2147/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mul_round_ph)
2148#[inline]
2149#[target_feature(enable = "avx512fp16")]
2150#[cfg_attr(test, assert_instr(vmulph, ROUNDING = 8))]
2151#[rustc_legacy_const_generics(2)]
2152#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2153pub fn _mm512_mul_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __m512h {
2154    unsafe {
2155        static_assert_rounding!(ROUNDING);
2156        vmulph(a, b, ROUNDING)
2157    }
2158}
2159
2160/// Multiply packed half-precision (16-bit) floating-point elements in a and b, and store the results in dst using
2161/// writemask k (elements are copied from src when the corresponding mask bit is not set).
2162/// Rounding is done according to the rounding parameter, which can be one of:
2163///
2164/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
2165/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
2166/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
2167/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
2168/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
2169///
2170/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_mul_round_ph)
2171#[inline]
2172#[target_feature(enable = "avx512fp16")]
2173#[cfg_attr(test, assert_instr(vmulph, ROUNDING = 8))]
2174#[rustc_legacy_const_generics(4)]
2175#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2176pub fn _mm512_mask_mul_round_ph<const ROUNDING: i32>(
2177    src: __m512h,
2178    k: __mmask32,
2179    a: __m512h,
2180    b: __m512h,
2181) -> __m512h {
2182    unsafe {
2183        static_assert_rounding!(ROUNDING);
2184        let r = _mm512_mul_round_ph::<ROUNDING>(a, b);
2185        simd_select_bitmask(k, r, src)
2186    }
2187}
2188
2189/// Multiply packed half-precision (16-bit) floating-point elements in a and b, and store the results in dst using
2190/// zeromask k (elements are zeroed out when the corresponding mask bit is not set).
2191/// Rounding is done according to the rounding parameter, which can be one of:
2192///
2193/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
2194/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
2195/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
2196/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
2197/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
2198///
2199/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_mul_round_ph)
2200#[inline]
2201#[target_feature(enable = "avx512fp16")]
2202#[cfg_attr(test, assert_instr(vmulph, ROUNDING = 8))]
2203#[rustc_legacy_const_generics(3)]
2204#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2205pub fn _mm512_maskz_mul_round_ph<const ROUNDING: i32>(
2206    k: __mmask32,
2207    a: __m512h,
2208    b: __m512h,
2209) -> __m512h {
2210    unsafe {
2211        static_assert_rounding!(ROUNDING);
2212        let r = _mm512_mul_round_ph::<ROUNDING>(a, b);
2213        simd_select_bitmask(k, r, _mm512_setzero_ph())
2214    }
2215}
2216
2217/// Multiply the lower half-precision (16-bit) floating-point elements in a and b, store the result in the
2218/// lower element of dst, and copy the upper 7 packed elements from a to the upper elements of dst.
2219/// Rounding is done according to the rounding parameter, which can be one of:
2220///
2221/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
2222/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
2223/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
2224/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
2225/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
2226///
2227/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mul_round_sh)
2228#[inline]
2229#[target_feature(enable = "avx512fp16")]
2230#[cfg_attr(test, assert_instr(vmulsh, ROUNDING = 8))]
2231#[rustc_legacy_const_generics(2)]
2232#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2233pub fn _mm_mul_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128h {
2234    static_assert_rounding!(ROUNDING);
2235    _mm_mask_mul_round_sh::<ROUNDING>(f16x8::ZERO.as_m128h(), 0xff, a, b)
2236}
2237
2238/// Multiply the lower half-precision (16-bit) floating-point elements in a and b, store the result in the
2239/// lower element of dst, and copy the upper 7 packed elements from a to the upper elements of dst using
2240/// writemask k (the element is copied from src when mask bit 0 is not set).
2241/// Rounding is done according to the rounding parameter, which can be one of:
2242///
2243/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
2244/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
2245/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
2246/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
2247/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
2248///
2249/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_mul_round_sh)
2250#[inline]
2251#[target_feature(enable = "avx512fp16")]
2252#[cfg_attr(test, assert_instr(vmulsh, ROUNDING = 8))]
2253#[rustc_legacy_const_generics(4)]
2254#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2255pub fn _mm_mask_mul_round_sh<const ROUNDING: i32>(
2256    src: __m128h,
2257    k: __mmask8,
2258    a: __m128h,
2259    b: __m128h,
2260) -> __m128h {
2261    unsafe {
2262        static_assert_rounding!(ROUNDING);
2263        vmulsh(a, b, src, k, ROUNDING)
2264    }
2265}
2266
2267/// Multiply the lower half-precision (16-bit) floating-point elements in a and b, store the result in the
2268/// lower element of dst, and copy the upper 7 packed elements from a to the upper elements of dst using
2269/// zeromask k (the element is zeroed out when mask bit 0 is not set).
2270/// Rounding is done according to the rounding parameter, which can be one of:
2271///
2272/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
2273/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
2274/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
2275/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
2276/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
2277///
2278/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_mul_round_sh)
2279#[inline]
2280#[target_feature(enable = "avx512fp16")]
2281#[cfg_attr(test, assert_instr(vmulsh, ROUNDING = 8))]
2282#[rustc_legacy_const_generics(3)]
2283#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2284pub fn _mm_maskz_mul_round_sh<const ROUNDING: i32>(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
2285    static_assert_rounding!(ROUNDING);
2286    _mm_mask_mul_round_sh::<ROUNDING>(f16x8::ZERO.as_m128h(), k, a, b)
2287}
2288
2289/// Multiply the lower half-precision (16-bit) floating-point elements in a and b, store the result in the
2290/// lower element of dst, and copy the upper 7 packed elements from a to the upper elements of dst.
2291///
2292/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mul_sh)
2293#[inline]
2294#[target_feature(enable = "avx512fp16")]
2295#[cfg_attr(test, assert_instr(vmulsh))]
2296#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2297#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
2298pub const fn _mm_mul_sh(a: __m128h, b: __m128h) -> __m128h {
2299    unsafe { simd_insert!(a, 0, _mm_cvtsh_h(a) * _mm_cvtsh_h(b)) }
2300}
2301
2302/// Multiply the lower half-precision (16-bit) floating-point elements in a and b, store the result in the
2303/// lower element of dst, and copy the upper 7 packed elements from a to the upper elements of dst using
2304/// writemask k (the element is copied from src when mask bit 0 is not set).
2305///
2306/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_mul_sh)
2307#[inline]
2308#[target_feature(enable = "avx512fp16")]
2309#[cfg_attr(test, assert_instr(vmulsh))]
2310#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2311#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
2312pub const fn _mm_mask_mul_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
2313    unsafe {
2314        let extractsrc: f16 = simd_extract!(src, 0);
2315        let mut add: f16 = extractsrc;
2316        if (k & 0b00000001) != 0 {
2317            let extracta: f16 = simd_extract!(a, 0);
2318            let extractb: f16 = simd_extract!(b, 0);
2319            add = extracta * extractb;
2320        }
2321        simd_insert!(a, 0, add)
2322    }
2323}
2324
2325/// Multiply the lower half-precision (16-bit) floating-point elements in a and b, store the result in the
2326/// lower element of dst, and copy the upper 7 packed elements from a to the upper elements of dst using
2327/// zeromask k (the element is zeroed out when mask bit 0 is not set).
2328///
2329/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_mul_sh)
2330#[inline]
2331#[target_feature(enable = "avx512fp16")]
2332#[cfg_attr(test, assert_instr(vmulsh))]
2333#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2334#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
2335pub const fn _mm_maskz_mul_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
2336    unsafe {
2337        let mut add: f16 = 0.;
2338        if (k & 0b00000001) != 0 {
2339            let extracta: f16 = simd_extract!(a, 0);
2340            let extractb: f16 = simd_extract!(b, 0);
2341            add = extracta * extractb;
2342        }
2343        simd_insert!(a, 0, add)
2344    }
2345}
2346
2347/// Divide packed half-precision (16-bit) floating-point elements in a by b, and store the results in dst.
2348///
2349/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_div_ph)
2350#[inline]
2351#[target_feature(enable = "avx512fp16,avx512vl")]
2352#[cfg_attr(test, assert_instr(vdivph))]
2353#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2354#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
2355pub const fn _mm_div_ph(a: __m128h, b: __m128h) -> __m128h {
2356    unsafe { simd_div(a, b) }
2357}
2358
2359/// Divide packed half-precision (16-bit) floating-point elements in a by b, and store the results in dst using
2360/// writemask k (elements are copied from src when the corresponding mask bit is not set).
2361///
2362/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_div_ph)
2363#[inline]
2364#[target_feature(enable = "avx512fp16,avx512vl")]
2365#[cfg_attr(test, assert_instr(vdivph))]
2366#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2367#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
2368pub const fn _mm_mask_div_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
2369    unsafe {
2370        let r = _mm_div_ph(a, b);
2371        simd_select_bitmask(k, r, src)
2372    }
2373}
2374
2375/// Divide packed half-precision (16-bit) floating-point elements in a by b, and store the results in dst using
2376/// zeromask k (elements are zeroed out when the corresponding mask bit is not set).
2377///
2378/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_div_ph)
2379#[inline]
2380#[target_feature(enable = "avx512fp16,avx512vl")]
2381#[cfg_attr(test, assert_instr(vdivph))]
2382#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2383#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
2384pub const fn _mm_maskz_div_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
2385    unsafe {
2386        let r = _mm_div_ph(a, b);
2387        simd_select_bitmask(k, r, _mm_setzero_ph())
2388    }
2389}
2390
2391/// Divide packed half-precision (16-bit) floating-point elements in a by b, and store the results in dst.
2392///
2393/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_div_ph)
2394#[inline]
2395#[target_feature(enable = "avx512fp16,avx512vl")]
2396#[cfg_attr(test, assert_instr(vdivph))]
2397#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2398#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
2399pub const fn _mm256_div_ph(a: __m256h, b: __m256h) -> __m256h {
2400    unsafe { simd_div(a, b) }
2401}
2402
2403/// Divide packed half-precision (16-bit) floating-point elements in a by b, and store the results in dst using
2404/// writemask k (elements are copied from src when the corresponding mask bit is not set).
2405///
2406/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_div_ph)
2407#[inline]
2408#[target_feature(enable = "avx512fp16,avx512vl")]
2409#[cfg_attr(test, assert_instr(vdivph))]
2410#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2411#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
2412pub const fn _mm256_mask_div_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
2413    unsafe {
2414        let r = _mm256_div_ph(a, b);
2415        simd_select_bitmask(k, r, src)
2416    }
2417}
2418
2419/// Divide packed half-precision (16-bit) floating-point elements in a by b, and store the results in dst using
2420/// zeromask k (elements are zeroed out when the corresponding mask bit is not set).
2421///
2422/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_div_ph)
2423#[inline]
2424#[target_feature(enable = "avx512fp16,avx512vl")]
2425#[cfg_attr(test, assert_instr(vdivph))]
2426#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2427#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
2428pub const fn _mm256_maskz_div_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
2429    unsafe {
2430        let r = _mm256_div_ph(a, b);
2431        simd_select_bitmask(k, r, _mm256_setzero_ph())
2432    }
2433}
2434
2435/// Divide packed half-precision (16-bit) floating-point elements in a by b, and store the results in dst.
2436///
2437/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_div_ph)
2438#[inline]
2439#[target_feature(enable = "avx512fp16")]
2440#[cfg_attr(test, assert_instr(vdivph))]
2441#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2442#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
2443pub const fn _mm512_div_ph(a: __m512h, b: __m512h) -> __m512h {
2444    unsafe { simd_div(a, b) }
2445}
2446
2447/// Divide packed half-precision (16-bit) floating-point elements in a by b, and store the results in dst using
2448/// writemask k (elements are copied from src when the corresponding mask bit is not set).
2449///
2450/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_div_ph)
2451#[inline]
2452#[target_feature(enable = "avx512fp16")]
2453#[cfg_attr(test, assert_instr(vdivph))]
2454#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2455#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
2456pub const fn _mm512_mask_div_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
2457    unsafe {
2458        let r = _mm512_div_ph(a, b);
2459        simd_select_bitmask(k, r, src)
2460    }
2461}
2462
2463/// Divide packed half-precision (16-bit) floating-point elements in a by b, and store the results in dst using
2464/// zeromask k (elements are zeroed out when the corresponding mask bit is not set).
2465///
2466/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_div_ph)
2467#[inline]
2468#[target_feature(enable = "avx512fp16")]
2469#[cfg_attr(test, assert_instr(vdivph))]
2470#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2471#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
2472pub const fn _mm512_maskz_div_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
2473    unsafe {
2474        let r = _mm512_div_ph(a, b);
2475        simd_select_bitmask(k, r, _mm512_setzero_ph())
2476    }
2477}
2478
2479/// Divide packed half-precision (16-bit) floating-point elements in a by b, and store the results in dst.
2480/// Rounding is done according to the rounding parameter, which can be one of:
2481///
2482/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
2483/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
2484/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
2485/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
2486/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
2487///
2488/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_div_round_ph)
2489#[inline]
2490#[target_feature(enable = "avx512fp16")]
2491#[cfg_attr(test, assert_instr(vdivph, ROUNDING = 8))]
2492#[rustc_legacy_const_generics(2)]
2493#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2494pub fn _mm512_div_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __m512h {
2495    unsafe {
2496        static_assert_rounding!(ROUNDING);
2497        vdivph(a, b, ROUNDING)
2498    }
2499}
2500
2501/// Divide packed half-precision (16-bit) floating-point elements in a by b, and store the results in dst using
2502/// writemask k (elements are copied from src when the corresponding mask bit is not set).
2503/// Rounding is done according to the rounding parameter, which can be one of:
2504///
2505/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
2506/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
2507/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
2508/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
2509/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
2510///
2511/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_div_round_ph)
2512#[inline]
2513#[target_feature(enable = "avx512fp16")]
2514#[cfg_attr(test, assert_instr(vdivph, ROUNDING = 8))]
2515#[rustc_legacy_const_generics(4)]
2516#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2517pub fn _mm512_mask_div_round_ph<const ROUNDING: i32>(
2518    src: __m512h,
2519    k: __mmask32,
2520    a: __m512h,
2521    b: __m512h,
2522) -> __m512h {
2523    unsafe {
2524        static_assert_rounding!(ROUNDING);
2525        let r = _mm512_div_round_ph::<ROUNDING>(a, b);
2526        simd_select_bitmask(k, r, src)
2527    }
2528}
2529
2530/// Divide packed half-precision (16-bit) floating-point elements in a by b, and store the results in dst using
2531/// zeromask k (elements are zeroed out when the corresponding mask bit is not set).
2532/// Rounding is done according to the rounding parameter, which can be one of:
2533///
2534/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
2535/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
2536/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
2537/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
2538/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
2539///
2540/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_div_round_ph)
2541#[inline]
2542#[target_feature(enable = "avx512fp16")]
2543#[cfg_attr(test, assert_instr(vdivph, ROUNDING = 8))]
2544#[rustc_legacy_const_generics(3)]
2545#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2546pub fn _mm512_maskz_div_round_ph<const ROUNDING: i32>(
2547    k: __mmask32,
2548    a: __m512h,
2549    b: __m512h,
2550) -> __m512h {
2551    unsafe {
2552        static_assert_rounding!(ROUNDING);
2553        let r = _mm512_div_round_ph::<ROUNDING>(a, b);
2554        simd_select_bitmask(k, r, _mm512_setzero_ph())
2555    }
2556}
2557
2558/// Divide the lower half-precision (16-bit) floating-point elements in a by b, store the result in the
2559/// lower element of dst, and copy the upper 7 packed elements from a to the upper elements of dst.
2560/// Rounding is done according to the rounding parameter, which can be one of:
2561///
2562/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
2563/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
2564/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
2565/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
2566/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
2567///
2568/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_div_round_sh)
2569#[inline]
2570#[target_feature(enable = "avx512fp16")]
2571#[cfg_attr(test, assert_instr(vdivsh, ROUNDING = 8))]
2572#[rustc_legacy_const_generics(2)]
2573#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2574pub fn _mm_div_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128h {
2575    static_assert_rounding!(ROUNDING);
2576    _mm_mask_div_round_sh::<ROUNDING>(f16x8::ZERO.as_m128h(), 0xff, a, b)
2577}
2578
2579/// Divide the lower half-precision (16-bit) floating-point elements in a by b, store the result in the
2580/// lower element of dst, and copy the upper 7 packed elements from a to the upper elements of dst using
2581/// writemask k (the element is copied from src when mask bit 0 is not set).
2582/// Rounding is done according to the rounding parameter, which can be one of:
2583///
2584/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
2585/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
2586/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
2587/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
2588/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
2589///
2590/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_div_round_sh)
2591#[inline]
2592#[target_feature(enable = "avx512fp16")]
2593#[cfg_attr(test, assert_instr(vdivsh, ROUNDING = 8))]
2594#[rustc_legacy_const_generics(4)]
2595#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2596pub fn _mm_mask_div_round_sh<const ROUNDING: i32>(
2597    src: __m128h,
2598    k: __mmask8,
2599    a: __m128h,
2600    b: __m128h,
2601) -> __m128h {
2602    unsafe {
2603        static_assert_rounding!(ROUNDING);
2604        vdivsh(a, b, src, k, ROUNDING)
2605    }
2606}
2607
2608/// Divide the lower half-precision (16-bit) floating-point elements in a by b, store the result in the
2609/// lower element of dst, and copy the upper 7 packed elements from a to the upper elements of dst using
2610/// zeromask k (the element is zeroed out when mask bit 0 is not set).
2611/// Rounding is done according to the rounding parameter, which can be one of:
2612///
2613/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
2614/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
2615/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
2616/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
2617/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
2618///
2619/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_div_round_sh)
2620#[inline]
2621#[target_feature(enable = "avx512fp16")]
2622#[cfg_attr(test, assert_instr(vdivsh, ROUNDING = 8))]
2623#[rustc_legacy_const_generics(3)]
2624#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2625pub fn _mm_maskz_div_round_sh<const ROUNDING: i32>(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
2626    static_assert_rounding!(ROUNDING);
2627    _mm_mask_div_round_sh::<ROUNDING>(f16x8::ZERO.as_m128h(), k, a, b)
2628}
2629
2630/// Divide the lower half-precision (16-bit) floating-point elements in a by b, store the result in the
2631/// lower element of dst, and copy the upper 7 packed elements from a to the upper elements of dst.
2632///
2633/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_div_sh)
2634#[inline]
2635#[target_feature(enable = "avx512fp16")]
2636#[cfg_attr(test, assert_instr(vdivsh))]
2637#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2638#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
2639pub const fn _mm_div_sh(a: __m128h, b: __m128h) -> __m128h {
2640    unsafe { simd_insert!(a, 0, _mm_cvtsh_h(a) / _mm_cvtsh_h(b)) }
2641}
2642
2643/// Divide the lower half-precision (16-bit) floating-point elements in a by b, store the result in the
2644/// lower element of dst, and copy the upper 7 packed elements from a to the upper elements of dst using
2645/// writemask k (the element is copied from src when mask bit 0 is not set).
2646///
2647/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_div_sh)
2648#[inline]
2649#[target_feature(enable = "avx512fp16")]
2650#[cfg_attr(test, assert_instr(vdivsh))]
2651#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2652#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
2653pub const fn _mm_mask_div_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
2654    unsafe {
2655        let extractsrc: f16 = simd_extract!(src, 0);
2656        let mut add: f16 = extractsrc;
2657        if (k & 0b00000001) != 0 {
2658            let extracta: f16 = simd_extract!(a, 0);
2659            let extractb: f16 = simd_extract!(b, 0);
2660            add = extracta / extractb;
2661        }
2662        simd_insert!(a, 0, add)
2663    }
2664}
2665
2666/// Divide the lower half-precision (16-bit) floating-point elements in a by b, store the result in the
2667/// lower element of dst, and copy the upper 7 packed elements from a to the upper elements of dst using
2668/// zeromask k (the element is zeroed out when mask bit 0 is not set).
2669///
2670/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_div_sh)
2671#[inline]
2672#[target_feature(enable = "avx512fp16")]
2673#[cfg_attr(test, assert_instr(vdivsh))]
2674#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2675#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
2676pub const fn _mm_maskz_div_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
2677    unsafe {
2678        let mut add: f16 = 0.;
2679        if (k & 0b00000001) != 0 {
2680            let extracta: f16 = simd_extract!(a, 0);
2681            let extractb: f16 = simd_extract!(b, 0);
2682            add = extracta / extractb;
2683        }
2684        simd_insert!(a, 0, add)
2685    }
2686}
2687
2688/// Multiply packed complex numbers in a and b, and store the results in dst. Each complex number is
2689/// composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex
2690/// number `complex = vec.fp16[0] + i * vec.fp16[1]`.
2691///
2692/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mul_pch)
2693#[inline]
2694#[target_feature(enable = "avx512fp16,avx512vl")]
2695#[cfg_attr(test, assert_instr(vfmulcph))]
2696#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2697pub fn _mm_mul_pch(a: __m128h, b: __m128h) -> __m128h {
2698    _mm_mask_mul_pch(_mm_undefined_ph(), 0xff, a, b)
2699}
2700
2701/// Multiply packed complex numbers in a and b, and store the results in dst using writemask k (the element
2702/// is copied from src when corresponding mask bit is not set). Each complex number is composed of two adjacent
2703/// half-precision (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
2704///
2705/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_mul_pch)
2706#[inline]
2707#[target_feature(enable = "avx512fp16,avx512vl")]
2708#[cfg_attr(test, assert_instr(vfmulcph))]
2709#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2710pub fn _mm_mask_mul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
2711    unsafe { transmute(vfmulcph_128(transmute(a), transmute(b), transmute(src), k)) }
2712}
2713
2714/// Multiply packed complex numbers in a and b, and store the results in dst using zeromask k (the element
2715/// is zeroed out when corresponding mask bit is not set). Each complex number is composed of two adjacent
2716/// half-precision (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
2717///
2718/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_mul_pch)
2719#[inline]
2720#[target_feature(enable = "avx512fp16,avx512vl")]
2721#[cfg_attr(test, assert_instr(vfmulcph))]
2722#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2723pub fn _mm_maskz_mul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
2724    _mm_mask_mul_pch(_mm_setzero_ph(), k, a, b)
2725}
2726
2727/// Multiply packed complex numbers in a and b, and store the results in dst. Each complex number is
2728/// composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex
2729/// number `complex = vec.fp16[0] + i * vec.fp16[1]`.
2730///
2731/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mul_pch)
2732#[inline]
2733#[target_feature(enable = "avx512fp16,avx512vl")]
2734#[cfg_attr(test, assert_instr(vfmulcph))]
2735#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2736pub fn _mm256_mul_pch(a: __m256h, b: __m256h) -> __m256h {
2737    _mm256_mask_mul_pch(_mm256_undefined_ph(), 0xff, a, b)
2738}
2739
2740/// Multiply packed complex numbers in a and b, and store the results in dst using writemask k (the element
2741/// is copied from src when corresponding mask bit is not set). Each complex number is composed of two adjacent
2742/// half-precision (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
2743///
2744/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_mul_pch)
2745#[inline]
2746#[target_feature(enable = "avx512fp16,avx512vl")]
2747#[cfg_attr(test, assert_instr(vfmulcph))]
2748#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2749pub fn _mm256_mask_mul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h) -> __m256h {
2750    unsafe { transmute(vfmulcph_256(transmute(a), transmute(b), transmute(src), k)) }
2751}
2752
2753/// Multiply packed complex numbers in a and b, and store the results in dst using zeromask k (the element
2754/// is zeroed out when corresponding mask bit is not set). Each complex number is composed of two adjacent
2755/// half-precision (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
2756///
2757/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_mul_pch)
2758#[inline]
2759#[target_feature(enable = "avx512fp16,avx512vl")]
2760#[cfg_attr(test, assert_instr(vfmulcph))]
2761#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2762pub fn _mm256_maskz_mul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h {
2763    _mm256_mask_mul_pch(_mm256_setzero_ph(), k, a, b)
2764}
2765
2766/// Multiply packed complex numbers in a and b, and store the results in dst. Each complex number is
2767/// composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex
2768/// number `complex = vec.fp16[0] + i * vec.fp16[1]`.
2769///
2770/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mul_pch)
2771#[inline]
2772#[target_feature(enable = "avx512fp16")]
2773#[cfg_attr(test, assert_instr(vfmulcph))]
2774#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2775pub fn _mm512_mul_pch(a: __m512h, b: __m512h) -> __m512h {
2776    _mm512_mask_mul_pch(_mm512_undefined_ph(), 0xffff, a, b)
2777}
2778
2779/// Multiply packed complex numbers in a and b, and store the results in dst using writemask k (the element
2780/// is copied from src when corresponding mask bit is not set). Each complex number is composed of two adjacent
2781/// half-precision (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
2782///
2783/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_mul_pch)
2784#[inline]
2785#[target_feature(enable = "avx512fp16")]
2786#[cfg_attr(test, assert_instr(vfmulcph))]
2787#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2788pub fn _mm512_mask_mul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h) -> __m512h {
2789    _mm512_mask_mul_round_pch::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b)
2790}
2791
2792/// Multiply packed complex numbers in a and b, and store the results in dst using zeromask k (the element
2793/// is zeroed out when corresponding mask bit is not set). Each complex number is composed of two adjacent
2794/// half-precision (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
2795///
2796/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_mul_pch)
2797#[inline]
2798#[target_feature(enable = "avx512fp16")]
2799#[cfg_attr(test, assert_instr(vfmulcph))]
2800#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2801pub fn _mm512_maskz_mul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h {
2802    _mm512_mask_mul_pch(_mm512_setzero_ph(), k, a, b)
2803}
2804
2805/// Multiply the packed complex numbers in a and b, and store the results in dst. Each complex number is
2806/// composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex
2807/// number `complex = vec.fp16[0] + i * vec.fp16[1]`.
2808///
2809/// Rounding is done according to the rounding parameter, which can be one of:
2810///
2811/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
2812/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
2813/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
2814/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
2815/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
2816///
2817/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mul_round_pch)
2818#[inline]
2819#[target_feature(enable = "avx512fp16")]
2820#[cfg_attr(test, assert_instr(vfmulcph, ROUNDING = 8))]
2821#[rustc_legacy_const_generics(2)]
2822#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2823pub fn _mm512_mul_round_pch<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __m512h {
2824    static_assert_rounding!(ROUNDING);
2825    _mm512_mask_mul_round_pch::<ROUNDING>(_mm512_undefined_ph(), 0xffff, a, b)
2826}
2827
2828/// Multiply the packed complex numbers in a and b, and store the results in dst using writemask k (the element
2829/// is copied from src when corresponding mask bit is not set). Each complex number is composed of two adjacent
2830/// half-precision (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
2831///
2832/// Rounding is done according to the rounding parameter, which can be one of:
2833///
2834/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
2835/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
2836/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
2837/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
2838/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
2839///
2840/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_mul_round_pch)
2841#[inline]
2842#[target_feature(enable = "avx512fp16")]
2843#[cfg_attr(test, assert_instr(vfmulcph, ROUNDING = 8))]
2844#[rustc_legacy_const_generics(4)]
2845#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2846pub fn _mm512_mask_mul_round_pch<const ROUNDING: i32>(
2847    src: __m512h,
2848    k: __mmask16,
2849    a: __m512h,
2850    b: __m512h,
2851) -> __m512h {
2852    unsafe {
2853        static_assert_rounding!(ROUNDING);
2854        transmute(vfmulcph_512(
2855            transmute(a),
2856            transmute(b),
2857            transmute(src),
2858            k,
2859            ROUNDING,
2860        ))
2861    }
2862}
2863
2864/// Multiply the packed complex numbers in a and b, and store the results in dst using zeromask k (the element
2865/// is zeroed out when corresponding mask bit is not set). Each complex number is composed of two adjacent
2866/// half-precision (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
2867///
2868/// Rounding is done according to the rounding parameter, which can be one of:
2869///
2870/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
2871/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
2872/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
2873/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
2874/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
2875///
2876/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_mul_round_pch)
2877#[inline]
2878#[target_feature(enable = "avx512fp16")]
2879#[cfg_attr(test, assert_instr(vfmulcph, ROUNDING = 8))]
2880#[rustc_legacy_const_generics(3)]
2881#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2882pub fn _mm512_maskz_mul_round_pch<const ROUNDING: i32>(
2883    k: __mmask16,
2884    a: __m512h,
2885    b: __m512h,
2886) -> __m512h {
2887    static_assert_rounding!(ROUNDING);
2888    _mm512_mask_mul_round_pch::<ROUNDING>(_mm512_setzero_ph(), k, a, b)
2889}
2890
2891/// Multiply the lower complex numbers in a and b, and store the result in the lower elements of dst,
2892/// and copy the upper 6 packed elements from a to the upper elements of dst. Each complex number is
2893/// composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex
2894/// number `complex = vec.fp16[0] + i * vec.fp16[1]`.
2895///
2896/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mul_sch)
2897#[inline]
2898#[target_feature(enable = "avx512fp16")]
2899#[cfg_attr(test, assert_instr(vfmulcsh))]
2900#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2901pub fn _mm_mul_sch(a: __m128h, b: __m128h) -> __m128h {
2902    _mm_mask_mul_sch(f16x8::ZERO.as_m128h(), 0xff, a, b)
2903}
2904
2905/// Multiply the lower complex numbers in a and b, and store the result in the lower elements of dst using
2906/// writemask k (the element is copied from src when mask bit 0 is not set), and copy the upper 6 packed
2907/// elements from a to the upper elements of dst. Each complex number is composed of two adjacent
2908/// half-precision (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
2909///
2910/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_mul_sch)
2911#[inline]
2912#[target_feature(enable = "avx512fp16")]
2913#[cfg_attr(test, assert_instr(vfmulcsh))]
2914#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2915pub fn _mm_mask_mul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
2916    _mm_mask_mul_round_sch::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b)
2917}
2918
2919/// Multiply the lower complex numbers in a and b, and store the result in the lower elements of dst using
2920/// zeromask k (the element is zeroed out when mask bit 0 is not set), and copy the upper 6 packed elements
2921/// from a to the upper elements of dst. Each complex number is composed of two adjacent half-precision
2922/// (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
2923///
2924/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_mul_sch)
2925#[inline]
2926#[target_feature(enable = "avx512fp16")]
2927#[cfg_attr(test, assert_instr(vfmulcsh))]
2928#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2929pub fn _mm_maskz_mul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
2930    _mm_mask_mul_sch(f16x8::ZERO.as_m128h(), k, a, b)
2931}
2932
2933/// Multiply the lower complex numbers in a and b, and store the result in the lower elements of dst,
2934/// and copy the upper 6 packed elements from a to the upper elements of dst. Each complex number is
2935/// composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex
2936/// number `complex = vec.fp16[0] + i * vec.fp16[1]`.
2937///
2938/// Rounding is done according to the rounding parameter, which can be one of:
2939///
2940/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
2941/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
2942/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
2943/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
2944/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
2945///
2946/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mul_round_sch)
2947#[inline]
2948#[target_feature(enable = "avx512fp16")]
2949#[cfg_attr(test, assert_instr(vfmulcsh, ROUNDING = 8))]
2950#[rustc_legacy_const_generics(2)]
2951#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2952pub fn _mm_mul_round_sch<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128h {
2953    static_assert_rounding!(ROUNDING);
2954    _mm_mask_mul_round_sch::<ROUNDING>(f16x8::ZERO.as_m128h(), 0xff, a, b)
2955}
2956
2957/// Multiply the lower complex numbers in a and b, and store the result in the lower elements of dst using
2958/// writemask k (the element is copied from src when mask bit 0 is not set), and copy the upper 6 packed
2959/// elements from a to the upper elements of dst. Each complex number is composed of two adjacent half-precision
2960/// (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
2961///
2962/// Rounding is done according to the rounding parameter, which can be one of:
2963///
2964/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
2965/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
2966/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
2967/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
2968/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
2969///
2970/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_mul_round_sch)
2971#[inline]
2972#[target_feature(enable = "avx512fp16")]
2973#[cfg_attr(test, assert_instr(vfmulcsh, ROUNDING = 8))]
2974#[rustc_legacy_const_generics(4)]
2975#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
2976pub fn _mm_mask_mul_round_sch<const ROUNDING: i32>(
2977    src: __m128h,
2978    k: __mmask8,
2979    a: __m128h,
2980    b: __m128h,
2981) -> __m128h {
2982    unsafe {
2983        static_assert_rounding!(ROUNDING);
2984        transmute(vfmulcsh(
2985            transmute(a),
2986            transmute(b),
2987            transmute(src),
2988            k,
2989            ROUNDING,
2990        ))
2991    }
2992}
2993
2994/// Multiply the lower complex numbers in a and b, and store the result in the lower elements of dst using
2995/// zeromask k (the element is zeroed out when mask bit 0 is not set), and copy the upper 6 packed elements
2996/// from a to the upper elements of dst. Each complex number is composed of two adjacent half-precision
2997/// (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
2998///
2999/// Rounding is done according to the rounding parameter, which can be one of:
3000///
3001/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
3002/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
3003/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
3004/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
3005/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
3006///
3007/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_mul_round_sch)
3008#[inline]
3009#[target_feature(enable = "avx512fp16")]
3010#[cfg_attr(test, assert_instr(vfmulcsh, ROUNDING = 8))]
3011#[rustc_legacy_const_generics(3)]
3012#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3013pub fn _mm_maskz_mul_round_sch<const ROUNDING: i32>(
3014    k: __mmask8,
3015    a: __m128h,
3016    b: __m128h,
3017) -> __m128h {
3018    static_assert_rounding!(ROUNDING);
3019    _mm_mask_mul_round_sch::<ROUNDING>(f16x8::ZERO.as_m128h(), k, a, b)
3020}
3021
3022/// Multiply packed complex numbers in a and b, and store the results in dst. Each complex number is
3023/// composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex
3024/// number `complex = vec.fp16[0] + i * vec.fp16[1]`.
3025///
3026/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fmul_pch)
3027#[inline]
3028#[target_feature(enable = "avx512fp16,avx512vl")]
3029#[cfg_attr(test, assert_instr(vfmulcph))]
3030#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3031pub fn _mm_fmul_pch(a: __m128h, b: __m128h) -> __m128h {
3032    _mm_mul_pch(a, b)
3033}
3034
3035/// Multiply packed complex numbers in a and b, and store the results in dst using writemask k (the element
3036/// is copied from src when corresponding mask bit is not set). Each complex number is composed of two adjacent
3037/// half-precision (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
3038///
3039/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fmul_pch)
3040#[inline]
3041#[target_feature(enable = "avx512fp16,avx512vl")]
3042#[cfg_attr(test, assert_instr(vfmulcph))]
3043#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3044pub fn _mm_mask_fmul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
3045    _mm_mask_mul_pch(src, k, a, b)
3046}
3047
3048/// Multiply packed complex numbers in a and b, and store the results in dst using zeromask k (the element
3049/// is zeroed out when corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision
3050/// (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
3051///
3052/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fmul_pch)
3053#[inline]
3054#[target_feature(enable = "avx512fp16,avx512vl")]
3055#[cfg_attr(test, assert_instr(vfmulcph))]
3056#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3057pub fn _mm_maskz_fmul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
3058    _mm_maskz_mul_pch(k, a, b)
3059}
3060
3061/// Multiply packed complex numbers in a and b, and store the results in dst. Each complex number is
3062/// composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex
3063/// number `complex = vec.fp16[0] + i * vec.fp16[1]`.
3064///
3065/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_fmul_pch)
3066#[inline]
3067#[target_feature(enable = "avx512fp16,avx512vl")]
3068#[cfg_attr(test, assert_instr(vfmulcph))]
3069#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3070pub fn _mm256_fmul_pch(a: __m256h, b: __m256h) -> __m256h {
3071    _mm256_mul_pch(a, b)
3072}
3073
3074/// Multiply packed complex numbers in a and b, and store the results in dst using writemask k (the element
3075/// is copied from src when corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision
3076/// (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
3077///
3078/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_fmul_pch)
3079#[inline]
3080#[target_feature(enable = "avx512fp16,avx512vl")]
3081#[cfg_attr(test, assert_instr(vfmulcph))]
3082#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3083pub fn _mm256_mask_fmul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h) -> __m256h {
3084    _mm256_mask_mul_pch(src, k, a, b)
3085}
3086
3087/// Multiply packed complex numbers in a and b, and store the results in dst using zeromask k (the element
3088/// is zeroed out when corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision
3089/// (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
3090///
3091/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_fmul_pch)
3092#[inline]
3093#[target_feature(enable = "avx512fp16,avx512vl")]
3094#[cfg_attr(test, assert_instr(vfmulcph))]
3095#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3096pub fn _mm256_maskz_fmul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h {
3097    _mm256_maskz_mul_pch(k, a, b)
3098}
3099
3100/// Multiply packed complex numbers in a and b, and store the results in dst. Each complex number is composed
3101/// of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
3102///
3103/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fmul_pch)
3104#[inline]
3105#[target_feature(enable = "avx512fp16")]
3106#[cfg_attr(test, assert_instr(vfmulcph))]
3107#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3108pub fn _mm512_fmul_pch(a: __m512h, b: __m512h) -> __m512h {
3109    _mm512_mul_pch(a, b)
3110}
3111
3112/// Multiply packed complex numbers in a and b, and store the results in dst using writemask k (the element
3113/// is copied from src when corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision
3114/// (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
3115///
3116/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fmul_pch)
3117#[inline]
3118#[target_feature(enable = "avx512fp16")]
3119#[cfg_attr(test, assert_instr(vfmulcph))]
3120#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3121pub fn _mm512_mask_fmul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h) -> __m512h {
3122    _mm512_mask_mul_pch(src, k, a, b)
3123}
3124
3125/// Multiply packed complex numbers in a and b, and store the results in dst using zeromask k (the element
3126/// is zeroed out when corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision
3127/// (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
3128///
3129/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fmul_pch)
3130#[inline]
3131#[target_feature(enable = "avx512fp16")]
3132#[cfg_attr(test, assert_instr(vfmulcph))]
3133#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3134pub fn _mm512_maskz_fmul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h {
3135    _mm512_maskz_mul_pch(k, a, b)
3136}
3137
3138/// Multiply packed complex numbers in a and b, and store the results in dst. Each complex number is composed
3139/// of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
3140/// Rounding is done according to the rounding parameter, which can be one of:
3141///
3142/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
3143/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
3144/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
3145/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
3146/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
3147///
3148/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fmul_round_pch)
3149#[inline]
3150#[target_feature(enable = "avx512fp16")]
3151#[cfg_attr(test, assert_instr(vfmulcph, ROUNDING = 8))]
3152#[rustc_legacy_const_generics(2)]
3153#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3154pub fn _mm512_fmul_round_pch<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __m512h {
3155    static_assert_rounding!(ROUNDING);
3156    _mm512_mul_round_pch::<ROUNDING>(a, b)
3157}
3158
3159/// Multiply packed complex numbers in a and b, and store the results in dst using writemask k (the element
3160/// is copied from src when corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision
3161/// (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
3162/// Rounding is done according to the rounding parameter, which can be one of:
3163///
3164/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
3165/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
3166/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
3167/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
3168/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
3169///
3170/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fmul_round_pch)
3171#[inline]
3172#[target_feature(enable = "avx512fp16")]
3173#[cfg_attr(test, assert_instr(vfmulcph, ROUNDING = 8))]
3174#[rustc_legacy_const_generics(4)]
3175#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3176pub fn _mm512_mask_fmul_round_pch<const ROUNDING: i32>(
3177    src: __m512h,
3178    k: __mmask16,
3179    a: __m512h,
3180    b: __m512h,
3181) -> __m512h {
3182    static_assert_rounding!(ROUNDING);
3183    _mm512_mask_mul_round_pch::<ROUNDING>(src, k, a, b)
3184}
3185
3186/// Multiply packed complex numbers in a and b, and store the results in dst using zeromask k (the element
3187/// is zeroed out when corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision
3188/// (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
3189/// Rounding is done according to the rounding parameter, which can be one of:
3190///
3191/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
3192/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
3193/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
3194/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
3195/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
3196///
3197/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fmul_round_pch)
3198#[inline]
3199#[target_feature(enable = "avx512fp16")]
3200#[cfg_attr(test, assert_instr(vfmulcph, ROUNDING = 8))]
3201#[rustc_legacy_const_generics(3)]
3202#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3203pub fn _mm512_maskz_fmul_round_pch<const ROUNDING: i32>(
3204    k: __mmask16,
3205    a: __m512h,
3206    b: __m512h,
3207) -> __m512h {
3208    static_assert_rounding!(ROUNDING);
3209    _mm512_maskz_mul_round_pch::<ROUNDING>(k, a, b)
3210}
3211
3212/// Multiply the lower complex numbers in a and b, and store the results in dst. Each complex number is
3213/// composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex
3214/// number `complex = vec.fp16[0] + i * vec.fp16[1]`.
3215///
3216/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fmul_sch)
3217#[inline]
3218#[target_feature(enable = "avx512fp16")]
3219#[cfg_attr(test, assert_instr(vfmulcsh))]
3220#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3221pub fn _mm_fmul_sch(a: __m128h, b: __m128h) -> __m128h {
3222    _mm_mul_sch(a, b)
3223}
3224
3225/// Multiply the lower complex numbers in a and b, and store the results in dst using writemask k (the element
3226/// is copied from src when mask bit 0 is not set). Each complex number is composed of two adjacent half-precision
3227/// (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
3228///
3229/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fmul_sch)
3230#[inline]
3231#[target_feature(enable = "avx512fp16")]
3232#[cfg_attr(test, assert_instr(vfmulcsh))]
3233#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3234pub fn _mm_mask_fmul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
3235    _mm_mask_mul_sch(src, k, a, b)
3236}
3237
3238/// Multiply the lower complex numbers in a and b, and store the results in dst using zeromask k (the element
3239/// is zeroed out when mask bit 0 is not set). Each complex number is composed of two adjacent half-precision
3240/// (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
3241///
3242/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fmul_sch)
3243#[inline]
3244#[target_feature(enable = "avx512fp16")]
3245#[cfg_attr(test, assert_instr(vfmulcsh))]
3246#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3247pub fn _mm_maskz_fmul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
3248    _mm_maskz_mul_sch(k, a, b)
3249}
3250
3251/// Multiply the lower complex numbers in a and b, and store the results in dst. Each complex number is composed
3252/// of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
3253///
3254/// Rounding is done according to the rounding parameter, which can be one of:
3255///
3256/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
3257/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
3258/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
3259/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
3260/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
3261///
3262/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fmul_round_sch)
3263#[inline]
3264#[target_feature(enable = "avx512fp16")]
3265#[cfg_attr(test, assert_instr(vfmulcsh, ROUNDING = 8))]
3266#[rustc_legacy_const_generics(2)]
3267#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3268pub fn _mm_fmul_round_sch<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128h {
3269    static_assert_rounding!(ROUNDING);
3270    _mm_mul_round_sch::<ROUNDING>(a, b)
3271}
3272
3273/// Multiply the lower complex numbers in a and b, and store the results in dst using writemask k (the element
3274/// is copied from src when mask bit 0 is not set). Each complex number is composed of two adjacent half-precision
3275/// (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
3276///
3277/// Rounding is done according to the rounding parameter, which can be one of:
3278///
3279/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
3280/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
3281/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
3282/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
3283/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
3284///
3285/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fmul_round_sch)
3286#[inline]
3287#[target_feature(enable = "avx512fp16")]
3288#[cfg_attr(test, assert_instr(vfmulcsh, ROUNDING = 8))]
3289#[rustc_legacy_const_generics(4)]
3290#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3291pub fn _mm_mask_fmul_round_sch<const ROUNDING: i32>(
3292    src: __m128h,
3293    k: __mmask8,
3294    a: __m128h,
3295    b: __m128h,
3296) -> __m128h {
3297    static_assert_rounding!(ROUNDING);
3298    _mm_mask_mul_round_sch::<ROUNDING>(src, k, a, b)
3299}
3300
3301/// Multiply the lower complex numbers in a and b, and store the results in dst using zeromask k (the element
3302/// is zeroed out when mask bit 0 is not set). Each complex number is composed of two adjacent half-precision
3303/// (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
3304///
3305/// Rounding is done according to the rounding parameter, which can be one of:
3306///
3307/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
3308/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
3309/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
3310/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
3311/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
3312///
3313/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fmul_round_sch)
3314#[inline]
3315#[target_feature(enable = "avx512fp16")]
3316#[cfg_attr(test, assert_instr(vfmulcsh, ROUNDING = 8))]
3317#[rustc_legacy_const_generics(3)]
3318#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3319pub fn _mm_maskz_fmul_round_sch<const ROUNDING: i32>(
3320    k: __mmask8,
3321    a: __m128h,
3322    b: __m128h,
3323) -> __m128h {
3324    static_assert_rounding!(ROUNDING);
3325    _mm_maskz_mul_round_sch::<ROUNDING>(k, a, b)
3326}
3327
3328/// Multiply packed complex numbers in a by the complex conjugates of packed complex numbers in b, and
3329/// store the results in dst. Each complex number is composed of two adjacent half-precision (16-bit)
3330/// floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`,
3331/// or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
3332///
3333/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmul_pch)
3334#[inline]
3335#[target_feature(enable = "avx512fp16,avx512vl")]
3336#[cfg_attr(test, assert_instr(vfcmulcph))]
3337#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3338pub fn _mm_cmul_pch(a: __m128h, b: __m128h) -> __m128h {
3339    _mm_mask_cmul_pch(_mm_undefined_ph(), 0xff, a, b)
3340}
3341
3342/// Multiply packed complex numbers in a by the complex conjugates of packed complex numbers in b, and
3343/// store the results in dst using writemask k (the element is copied from src when corresponding mask bit is not set).
3344/// Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which
3345/// defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`, or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
3346///
3347/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cmul_pch)
3348#[inline]
3349#[target_feature(enable = "avx512fp16,avx512vl")]
3350#[cfg_attr(test, assert_instr(vfcmulcph))]
3351#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3352pub fn _mm_mask_cmul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
3353    unsafe { transmute(vfcmulcph_128(transmute(a), transmute(b), transmute(src), k)) }
3354}
3355
3356/// Multiply packed complex numbers in a by the complex conjugates of packed complex numbers in b, and
3357/// store the results in dst using zeromask k (the element is zeroed out when corresponding mask bit is not set).
3358/// Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which
3359/// defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`, or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
3360///
3361/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_cmul_pch)
3362#[inline]
3363#[target_feature(enable = "avx512fp16,avx512vl")]
3364#[cfg_attr(test, assert_instr(vfcmulcph))]
3365#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3366pub fn _mm_maskz_cmul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
3367    _mm_mask_cmul_pch(_mm_setzero_ph(), k, a, b)
3368}
3369
3370/// Multiply packed complex numbers in a by the complex conjugates of packed complex numbers in b, and
3371/// store the results in dst. Each complex number is composed of two adjacent half-precision (16-bit)
3372/// floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`,
3373/// or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
3374///
3375/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cmul_pch)
3376#[inline]
3377#[target_feature(enable = "avx512fp16,avx512vl")]
3378#[cfg_attr(test, assert_instr(vfcmulcph))]
3379#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3380pub fn _mm256_cmul_pch(a: __m256h, b: __m256h) -> __m256h {
3381    _mm256_mask_cmul_pch(_mm256_undefined_ph(), 0xff, a, b)
3382}
3383
3384/// Multiply packed complex numbers in a by the complex conjugates of packed complex numbers in b, and
3385/// store the results in dst using writemask k (the element is copied from src when corresponding mask bit is not set).
3386/// Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which
3387/// defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`, or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
3388///
3389/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_cmul_pch)
3390#[inline]
3391#[target_feature(enable = "avx512fp16,avx512vl")]
3392#[cfg_attr(test, assert_instr(vfcmulcph))]
3393#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3394pub fn _mm256_mask_cmul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h) -> __m256h {
3395    unsafe { transmute(vfcmulcph_256(transmute(a), transmute(b), transmute(src), k)) }
3396}
3397
3398/// Multiply packed complex numbers in a by the complex conjugates of packed complex numbers in b, and
3399/// store the results in dst using zeromask k (the element is zeroed out when corresponding mask bit is not set).
3400/// Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which
3401/// defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`, or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
3402///
3403/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_cmul_pch)
3404#[inline]
3405#[target_feature(enable = "avx512fp16,avx512vl")]
3406#[cfg_attr(test, assert_instr(vfcmulcph))]
3407#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3408pub fn _mm256_maskz_cmul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h {
3409    _mm256_mask_cmul_pch(_mm256_setzero_ph(), k, a, b)
3410}
3411
3412/// Multiply packed complex numbers in a by the complex conjugates of packed complex numbers in b, and
3413/// store the results in dst. Each complex number is composed of two adjacent half-precision (16-bit)
3414/// floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`,
3415/// or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
3416///
3417/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmul_pch)
3418#[inline]
3419#[target_feature(enable = "avx512fp16")]
3420#[cfg_attr(test, assert_instr(vfcmulcph))]
3421#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3422pub fn _mm512_cmul_pch(a: __m512h, b: __m512h) -> __m512h {
3423    _mm512_mask_cmul_pch(_mm512_undefined_ph(), 0xffff, a, b)
3424}
3425
3426/// Multiply packed complex numbers in a by the complex conjugates of packed complex numbers in b, and
3427/// store the results in dst using writemask k (the element is copied from src when corresponding mask bit is not set).
3428/// Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which
3429/// defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`, or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
3430///
3431/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmul_pch)
3432#[inline]
3433#[target_feature(enable = "avx512fp16")]
3434#[cfg_attr(test, assert_instr(vfcmulcph))]
3435#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3436pub fn _mm512_mask_cmul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h) -> __m512h {
3437    _mm512_mask_cmul_round_pch::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b)
3438}
3439
3440/// Multiply packed complex numbers in a by the complex conjugates of packed complex numbers in b, and
3441/// store the results in dst using zeromask k (the element is zeroed out when corresponding mask bit is not set).
3442/// Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which
3443/// defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`, or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
3444///
3445/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cmul_pch)
3446#[inline]
3447#[target_feature(enable = "avx512fp16")]
3448#[cfg_attr(test, assert_instr(vfcmulcph))]
3449#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3450pub fn _mm512_maskz_cmul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h {
3451    _mm512_mask_cmul_pch(_mm512_setzero_ph(), k, a, b)
3452}
3453
3454/// Multiply packed complex numbers in a by the complex conjugates of packed complex numbers in b, and
3455/// store the results in dst. Each complex number is composed of two adjacent half-precision (16-bit)
3456/// floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`,
3457/// or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
3458///
3459/// Rounding is done according to the rounding parameter, which can be one of:
3460///
3461/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
3462/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
3463/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
3464/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
3465/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
3466///
3467/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmul_round_pch)
3468#[inline]
3469#[target_feature(enable = "avx512fp16")]
3470#[cfg_attr(test, assert_instr(vfcmulcph, ROUNDING = 8))]
3471#[rustc_legacy_const_generics(2)]
3472#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3473pub fn _mm512_cmul_round_pch<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __m512h {
3474    static_assert_rounding!(ROUNDING);
3475    _mm512_mask_cmul_round_pch::<ROUNDING>(_mm512_undefined_ph(), 0xffff, a, b)
3476}
3477
3478/// Multiply packed complex numbers in a by the complex conjugates of packed complex numbers in b, and
3479/// store the results in dst using writemask k (the element is copied from src when corresponding mask bit is not set).
3480/// Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which
3481/// defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`, or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
3482///
3483/// Rounding is done according to the rounding parameter, which can be one of:
3484///
3485/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
3486/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
3487/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
3488/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
3489/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
3490///
3491/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmul_round_pch)
3492#[inline]
3493#[target_feature(enable = "avx512fp16")]
3494#[cfg_attr(test, assert_instr(vfcmulcph, ROUNDING = 8))]
3495#[rustc_legacy_const_generics(4)]
3496#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3497pub fn _mm512_mask_cmul_round_pch<const ROUNDING: i32>(
3498    src: __m512h,
3499    k: __mmask16,
3500    a: __m512h,
3501    b: __m512h,
3502) -> __m512h {
3503    unsafe {
3504        static_assert_rounding!(ROUNDING);
3505        transmute(vfcmulcph_512(
3506            transmute(a),
3507            transmute(b),
3508            transmute(src),
3509            k,
3510            ROUNDING,
3511        ))
3512    }
3513}
3514
3515/// Multiply packed complex numbers in a by the complex conjugates of packed complex numbers in b, and
3516/// store the results in dst using zeromask k (the element is zeroed out when corresponding mask bit is not set).
3517/// Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which
3518/// defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`, or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
3519///
3520/// Rounding is done according to the rounding parameter, which can be one of:
3521///
3522/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
3523/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
3524/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
3525/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
3526/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
3527///
3528/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cmul_round_pch)
3529#[inline]
3530#[target_feature(enable = "avx512fp16")]
3531#[cfg_attr(test, assert_instr(vfcmulcph, ROUNDING = 8))]
3532#[rustc_legacy_const_generics(3)]
3533#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3534pub fn _mm512_maskz_cmul_round_pch<const ROUNDING: i32>(
3535    k: __mmask16,
3536    a: __m512h,
3537    b: __m512h,
3538) -> __m512h {
3539    static_assert_rounding!(ROUNDING);
3540    _mm512_mask_cmul_round_pch::<ROUNDING>(_mm512_setzero_ph(), k, a, b)
3541}
3542
3543/// Multiply the lower complex numbers in a by the complex conjugates of the lower complex numbers in b,
3544/// and store the results in dst. Each complex number is composed of two adjacent half-precision (16-bit)
3545/// floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`,
3546///
3547/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmul_sch)
3548#[inline]
3549#[target_feature(enable = "avx512fp16")]
3550#[cfg_attr(test, assert_instr(vfcmulcsh))]
3551#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3552pub fn _mm_cmul_sch(a: __m128h, b: __m128h) -> __m128h {
3553    _mm_mask_cmul_sch(f16x8::ZERO.as_m128h(), 0xff, a, b)
3554}
3555
3556/// Multiply the lower complex numbers in a by the complex conjugates of the lower complex numbers in b,
3557/// and store the results in dst using writemask k (the element is copied from src when mask bit 0 is not set).
3558/// Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which
3559/// defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`,
3560///
3561/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cmul_sch)
3562#[inline]
3563#[target_feature(enable = "avx512fp16")]
3564#[cfg_attr(test, assert_instr(vfcmulcsh))]
3565#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3566pub fn _mm_mask_cmul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
3567    _mm_mask_cmul_round_sch::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b)
3568}
3569
3570/// Multiply the lower complex numbers in a by the complex conjugates of the lower complex numbers in b,
3571/// and store the results in dst using zeromask k (the element is zeroed out when mask bit 0 is not set).
3572/// Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which
3573/// defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`,
3574///
3575/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_cmul_sch)
3576#[inline]
3577#[target_feature(enable = "avx512fp16")]
3578#[cfg_attr(test, assert_instr(vfcmulcsh))]
3579#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3580pub fn _mm_maskz_cmul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
3581    _mm_mask_cmul_sch(f16x8::ZERO.as_m128h(), k, a, b)
3582}
3583
3584/// Multiply the lower complex numbers in a by the complex conjugates of the lower complex numbers in b,
3585/// and store the results in dst. Each complex number is composed of two adjacent half-precision (16-bit)
3586/// floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`,
3587///
3588/// Rounding is done according to the rounding parameter, which can be one of:
3589///
3590/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
3591/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
3592/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
3593/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
3594/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
3595///
3596/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmul_round_sch)
3597#[inline]
3598#[target_feature(enable = "avx512fp16")]
3599#[cfg_attr(test, assert_instr(vfcmulcsh, ROUNDING = 8))]
3600#[rustc_legacy_const_generics(2)]
3601#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3602pub fn _mm_cmul_round_sch<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128h {
3603    static_assert_rounding!(ROUNDING);
3604    _mm_mask_cmul_round_sch::<ROUNDING>(f16x8::ZERO.as_m128h(), 0xff, a, b)
3605}
3606
3607/// Multiply the lower complex numbers in a by the complex conjugates of the lower complex numbers in b,
3608/// and store the results in dst using writemask k (the element is copied from src when mask bit 0 is not set).
3609/// Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which
3610/// defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`, or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
3611///
3612/// Rounding is done according to the rounding parameter, which can be one of:
3613///
3614/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
3615/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
3616/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
3617/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
3618/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
3619///
3620/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cmul_round_sch)
3621#[inline]
3622#[target_feature(enable = "avx512fp16")]
3623#[cfg_attr(test, assert_instr(vfcmulcsh, ROUNDING = 8))]
3624#[rustc_legacy_const_generics(4)]
3625#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3626pub fn _mm_mask_cmul_round_sch<const ROUNDING: i32>(
3627    src: __m128h,
3628    k: __mmask8,
3629    a: __m128h,
3630    b: __m128h,
3631) -> __m128h {
3632    unsafe {
3633        static_assert_rounding!(ROUNDING);
3634        transmute(vfcmulcsh(
3635            transmute(a),
3636            transmute(b),
3637            transmute(src),
3638            k,
3639            ROUNDING,
3640        ))
3641    }
3642}
3643
3644/// Multiply the lower complex numbers in a by the complex conjugates of the lower complex numbers in b,
3645/// and store the results in dst using zeromask k (the element is zeroed out when mask bit 0 is not set).
3646/// Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which
3647/// defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`, or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
3648///
3649/// Rounding is done according to the rounding parameter, which can be one of:
3650///
3651/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
3652/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
3653/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
3654/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
3655/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
3656///
3657/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_cmul_round_sch)
3658#[inline]
3659#[target_feature(enable = "avx512fp16")]
3660#[cfg_attr(test, assert_instr(vfcmulcsh, ROUNDING = 8))]
3661#[rustc_legacy_const_generics(3)]
3662#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3663pub fn _mm_maskz_cmul_round_sch<const ROUNDING: i32>(
3664    k: __mmask8,
3665    a: __m128h,
3666    b: __m128h,
3667) -> __m128h {
3668    static_assert_rounding!(ROUNDING);
3669    _mm_mask_cmul_round_sch::<ROUNDING>(f16x8::ZERO.as_m128h(), k, a, b)
3670}
3671
3672/// Multiply packed complex numbers in a by the complex conjugates of packed complex numbers in b, and
3673/// store the results in dst. Each complex number is composed of two adjacent half-precision (16-bit)
3674/// floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`,
3675/// or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
3676///
3677/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fcmul_pch)
3678#[inline]
3679#[target_feature(enable = "avx512fp16,avx512vl")]
3680#[cfg_attr(test, assert_instr(vfcmulcph))]
3681#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3682pub fn _mm_fcmul_pch(a: __m128h, b: __m128h) -> __m128h {
3683    _mm_cmul_pch(a, b)
3684}
3685
3686/// Multiply packed complex numbers in a by the complex conjugates of packed complex numbers in b, and
3687/// store the results in dst using writemask k (the element is copied from src when corresponding mask bit is not set).
3688/// Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which
3689/// defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`, or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
3690///
3691/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fcmul_pch)
3692#[inline]
3693#[target_feature(enable = "avx512fp16,avx512vl")]
3694#[cfg_attr(test, assert_instr(vfcmulcph))]
3695#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3696pub fn _mm_mask_fcmul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
3697    _mm_mask_cmul_pch(src, k, a, b)
3698}
3699
3700/// Multiply packed complex numbers in a by the complex conjugates of packed complex numbers in b, and
3701/// store the results in dst using zeromask k (the element is zeroed out when corresponding mask bit is not set).
3702/// Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which
3703/// defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`, or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
3704///
3705/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fcmul_pch)
3706#[inline]
3707#[target_feature(enable = "avx512fp16,avx512vl")]
3708#[cfg_attr(test, assert_instr(vfcmulcph))]
3709#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3710pub fn _mm_maskz_fcmul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
3711    _mm_maskz_cmul_pch(k, a, b)
3712}
3713
3714/// Multiply packed complex numbers in a by the complex conjugates of packed complex numbers in b, and
3715/// store the results in dst. Each complex number is composed of two adjacent half-precision (16-bit)
3716/// floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`,
3717/// or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
3718///
3719/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_fcmul_pch)
3720#[inline]
3721#[target_feature(enable = "avx512fp16,avx512vl")]
3722#[cfg_attr(test, assert_instr(vfcmulcph))]
3723#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3724pub fn _mm256_fcmul_pch(a: __m256h, b: __m256h) -> __m256h {
3725    _mm256_cmul_pch(a, b)
3726}
3727
3728/// Multiply packed complex numbers in a by the complex conjugates of packed complex numbers in b, and
3729/// store the results in dst using writemask k (the element is copied from src when corresponding mask bit is not set).
3730/// Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which
3731/// defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`, or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
3732///
3733/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_fcmul_pch)
3734#[inline]
3735#[target_feature(enable = "avx512fp16,avx512vl")]
3736#[cfg_attr(test, assert_instr(vfcmulcph))]
3737#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3738pub fn _mm256_mask_fcmul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h) -> __m256h {
3739    _mm256_mask_cmul_pch(src, k, a, b)
3740}
3741
3742/// Multiply packed complex numbers in a by the complex conjugates of packed complex numbers in b, and
3743/// store the results in dst using zeromask k (the element is zeroed out when corresponding mask bit is not set).
3744/// Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which
3745/// defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`, or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
3746///
3747/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_fcmul_pch)
3748#[inline]
3749#[target_feature(enable = "avx512fp16,avx512vl")]
3750#[cfg_attr(test, assert_instr(vfcmulcph))]
3751#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3752pub fn _mm256_maskz_fcmul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h {
3753    _mm256_maskz_cmul_pch(k, a, b)
3754}
3755
3756/// Multiply packed complex numbers in a by the complex conjugates of packed complex numbers in b, and
3757/// store the results in dst. Each complex number is composed of two adjacent half-precision (16-bit)
3758/// floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`,
3759/// or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
3760///
3761/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fcmul_pch)
3762#[inline]
3763#[target_feature(enable = "avx512fp16")]
3764#[cfg_attr(test, assert_instr(vfcmulcph))]
3765#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3766pub fn _mm512_fcmul_pch(a: __m512h, b: __m512h) -> __m512h {
3767    _mm512_cmul_pch(a, b)
3768}
3769
3770/// Multiply packed complex numbers in a by the complex conjugates of packed complex numbers in b, and
3771/// store the results in dst using writemask k (the element is copied from src when corresponding mask bit is not set).
3772/// Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which
3773/// defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`, or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
3774///
3775/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fcmul_pch)
3776#[inline]
3777#[target_feature(enable = "avx512fp16")]
3778#[cfg_attr(test, assert_instr(vfcmulcph))]
3779#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3780pub fn _mm512_mask_fcmul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h) -> __m512h {
3781    _mm512_mask_cmul_pch(src, k, a, b)
3782}
3783
3784/// Multiply packed complex numbers in a by the complex conjugates of packed complex numbers in b, and
3785/// store the results in dst using zeromask k (the element is zeroed out when corresponding mask bit is not set).
3786/// Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which
3787/// defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`, or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
3788///
3789/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fcmul_pch)
3790#[inline]
3791#[target_feature(enable = "avx512fp16")]
3792#[cfg_attr(test, assert_instr(vfcmulcph))]
3793#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3794pub fn _mm512_maskz_fcmul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h {
3795    _mm512_maskz_cmul_pch(k, a, b)
3796}
3797
3798/// Multiply packed complex numbers in a by the complex conjugates of packed complex numbers in b, and
3799/// store the results in dst. Each complex number is composed of two adjacent half-precision (16-bit)
3800/// floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`,
3801///
3802/// Rounding is done according to the rounding parameter, which can be one of:
3803///
3804/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
3805/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
3806/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
3807/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
3808/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
3809///
3810/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fcmul_round_pch)
3811#[inline]
3812#[target_feature(enable = "avx512fp16")]
3813#[cfg_attr(test, assert_instr(vfcmulcph, ROUNDING = 8))]
3814#[rustc_legacy_const_generics(2)]
3815#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3816pub fn _mm512_fcmul_round_pch<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __m512h {
3817    static_assert_rounding!(ROUNDING);
3818    _mm512_cmul_round_pch::<ROUNDING>(a, b)
3819}
3820
3821/// Multiply packed complex numbers in a by the complex conjugates of packed complex numbers in b, and
3822/// store the results in dst using writemask k (the element is copied from src when corresponding mask bit is not set).
3823/// Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which
3824/// defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`, or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
3825///
3826/// Rounding is done according to the rounding parameter, which can be one of:
3827///
3828/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
3829/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
3830/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
3831/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
3832/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
3833///
3834/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fcmul_round_pch)
3835#[inline]
3836#[target_feature(enable = "avx512fp16")]
3837#[cfg_attr(test, assert_instr(vfcmulcph, ROUNDING = 8))]
3838#[rustc_legacy_const_generics(4)]
3839#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3840pub fn _mm512_mask_fcmul_round_pch<const ROUNDING: i32>(
3841    src: __m512h,
3842    k: __mmask16,
3843    a: __m512h,
3844    b: __m512h,
3845) -> __m512h {
3846    static_assert_rounding!(ROUNDING);
3847    _mm512_mask_cmul_round_pch::<ROUNDING>(src, k, a, b)
3848}
3849
3850/// Multiply packed complex numbers in a by the complex conjugates of packed complex numbers in b, and
3851/// store the results in dst using zeromask k (the element is zeroed out when corresponding mask bit is not set).
3852/// Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which
3853/// defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`, or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
3854///
3855/// Rounding is done according to the rounding parameter, which can be one of:
3856///
3857/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
3858/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
3859/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
3860/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
3861/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
3862///
3863/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fcmul_round_pch)
3864#[inline]
3865#[target_feature(enable = "avx512fp16")]
3866#[cfg_attr(test, assert_instr(vfcmulcph, ROUNDING = 8))]
3867#[rustc_legacy_const_generics(3)]
3868#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3869pub fn _mm512_maskz_fcmul_round_pch<const ROUNDING: i32>(
3870    k: __mmask16,
3871    a: __m512h,
3872    b: __m512h,
3873) -> __m512h {
3874    static_assert_rounding!(ROUNDING);
3875    _mm512_maskz_cmul_round_pch::<ROUNDING>(k, a, b)
3876}
3877
3878/// Multiply the lower complex numbers in a by the complex conjugates of the lower complex numbers in b,
3879/// and store the results in dst. Each complex number is composed of two adjacent half-precision (16-bit)
3880/// floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`,
3881/// or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
3882///
3883/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fcmul_sch)
3884#[inline]
3885#[target_feature(enable = "avx512fp16")]
3886#[cfg_attr(test, assert_instr(vfcmulcsh))]
3887#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3888pub fn _mm_fcmul_sch(a: __m128h, b: __m128h) -> __m128h {
3889    _mm_cmul_sch(a, b)
3890}
3891
3892/// Multiply the lower complex numbers in a by the complex conjugates of the lower complex numbers in b,
3893/// and store the results in dst using writemask k (the element is copied from src when mask bit 0 is not set).
3894/// Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which
3895/// defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`, or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
3896///
3897/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fcmul_sch)
3898#[inline]
3899#[target_feature(enable = "avx512fp16")]
3900#[cfg_attr(test, assert_instr(vfcmulcsh))]
3901#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3902pub fn _mm_mask_fcmul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
3903    _mm_mask_cmul_sch(src, k, a, b)
3904}
3905
3906/// Multiply the lower complex numbers in a by the complex conjugates of the lower complex numbers in b,
3907/// and store the results in dst using zeromask k (the element is zeroed out when mask bit 0 is not set).
3908/// Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which
3909/// defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`, or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
3910///
3911/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fcmul_sch)
3912#[inline]
3913#[target_feature(enable = "avx512fp16")]
3914#[cfg_attr(test, assert_instr(vfcmulcsh))]
3915#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3916pub fn _mm_maskz_fcmul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
3917    _mm_maskz_cmul_sch(k, a, b)
3918}
3919
3920/// Multiply the lower complex numbers in a by the complex conjugates of the lower complex numbers in b,
3921/// and store the results in dst. Each complex number is composed of two adjacent half-precision (16-bit)
3922/// floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`,
3923///
3924/// Rounding is done according to the rounding parameter, which can be one of:
3925///
3926/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
3927/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
3928/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
3929/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
3930/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
3931///
3932/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fcmul_round_sch)
3933#[inline]
3934#[target_feature(enable = "avx512fp16")]
3935#[cfg_attr(test, assert_instr(vfcmulcsh, ROUNDING = 8))]
3936#[rustc_legacy_const_generics(2)]
3937#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3938pub fn _mm_fcmul_round_sch<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128h {
3939    static_assert_rounding!(ROUNDING);
3940    _mm_cmul_round_sch::<ROUNDING>(a, b)
3941}
3942
3943/// Multiply the lower complex numbers in a by the complex conjugates of the lower complex numbers in b,
3944/// and store the results in dst using writemask k (the element is copied from src when mask bit 0 is not set).
3945/// Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which
3946/// defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`, or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
3947///
3948/// Rounding is done according to the rounding parameter, which can be one of:
3949///
3950/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
3951/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
3952/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
3953/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
3954/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
3955///
3956/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fcmul_round_sch)
3957#[inline]
3958#[target_feature(enable = "avx512fp16")]
3959#[cfg_attr(test, assert_instr(vfcmulcsh, ROUNDING = 8))]
3960#[rustc_legacy_const_generics(4)]
3961#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3962pub fn _mm_mask_fcmul_round_sch<const ROUNDING: i32>(
3963    src: __m128h,
3964    k: __mmask8,
3965    a: __m128h,
3966    b: __m128h,
3967) -> __m128h {
3968    static_assert_rounding!(ROUNDING);
3969    _mm_mask_cmul_round_sch::<ROUNDING>(src, k, a, b)
3970}
3971
3972/// Multiply the lower complex numbers in a by the complex conjugates of the lower complex numbers in b,
3973/// and store the results in dst using zeromask k (the element is zeroed out when mask bit 0 is not set).
3974/// Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which
3975/// defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`, or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
3976///
3977/// Rounding is done according to the rounding parameter, which can be one of:
3978///
3979/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
3980/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
3981/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
3982/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
3983/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
3984///
3985/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fcmul_round_sch)
3986#[inline]
3987#[target_feature(enable = "avx512fp16")]
3988#[cfg_attr(test, assert_instr(vfcmulcsh, ROUNDING = 8))]
3989#[rustc_legacy_const_generics(3)]
3990#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
3991pub fn _mm_maskz_fcmul_round_sch<const ROUNDING: i32>(
3992    k: __mmask8,
3993    a: __m128h,
3994    b: __m128h,
3995) -> __m128h {
3996    static_assert_rounding!(ROUNDING);
3997    _mm_maskz_cmul_round_sch::<ROUNDING>(k, a, b)
3998}
3999
4000/// Finds the absolute value of each packed half-precision (16-bit) floating-point element in v2, storing
4001/// the results in dst.
4002///
4003/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_abs_ph)
4004#[inline]
4005#[target_feature(enable = "avx512fp16,avx512vl")]
4006#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4007#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
4008pub const fn _mm_abs_ph(v2: __m128h) -> __m128h {
4009    unsafe { transmute(_mm_and_si128(transmute(v2), _mm_set1_epi16(i16::MAX))) }
4010}
4011
4012/// Finds the absolute value of each packed half-precision (16-bit) floating-point element in v2, storing
4013/// the result in dst.
4014///
4015/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_abs_ph)
4016#[inline]
4017#[target_feature(enable = "avx512fp16,avx512vl")]
4018#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4019#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
4020pub const fn _mm256_abs_ph(v2: __m256h) -> __m256h {
4021    unsafe { transmute(_mm256_and_si256(transmute(v2), _mm256_set1_epi16(i16::MAX))) }
4022}
4023
4024/// Finds the absolute value of each packed half-precision (16-bit) floating-point element in v2, storing
4025/// the result in dst.
4026///
4027/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_abs_ph)
4028#[inline]
4029#[target_feature(enable = "avx512fp16")]
4030#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4031#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
4032pub const fn _mm512_abs_ph(v2: __m512h) -> __m512h {
4033    unsafe { transmute(_mm512_and_si512(transmute(v2), _mm512_set1_epi16(i16::MAX))) }
4034}
4035
4036/// Compute the complex conjugates of complex numbers in a, and store the results in dst. Each complex
4037/// number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines
4038/// the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`, or the complex conjugate
4039/// `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
4040///
4041/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_conj_pch)
4042#[inline]
4043#[target_feature(enable = "avx512fp16,avx512vl")]
4044#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4045#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
4046pub const fn _mm_conj_pch(a: __m128h) -> __m128h {
4047    unsafe { transmute(_mm_xor_si128(transmute(a), _mm_set1_epi32(i32::MIN))) }
4048}
4049
4050/// Compute the complex conjugates of complex numbers in a, and store the results in dst using writemask k
4051/// (the element is copied from src when corresponding mask bit is not set). Each complex number is composed of two
4052/// adjacent half-precision (16-bit) floating-point elements, which defines the complex number
4053/// `complex = vec.fp16[0] + i * vec.fp16[1]`, or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
4054///
4055/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_conj_pch)
4056#[inline]
4057#[target_feature(enable = "avx512fp16,avx512vl")]
4058#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4059#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
4060pub const fn _mm_mask_conj_pch(src: __m128h, k: __mmask8, a: __m128h) -> __m128h {
4061    unsafe {
4062        let r: __m128 = transmute(_mm_conj_pch(a));
4063        transmute(simd_select_bitmask(k, r, transmute(src)))
4064    }
4065}
4066
4067/// Compute the complex conjugates of complex numbers in a, and store the results in dst using zeromask k
4068/// (the element is zeroed out when corresponding mask bit is not set). Each complex number is composed of two adjacent
4069/// half-precision (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`,
4070/// or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
4071///
4072/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_conj_pch)
4073#[inline]
4074#[target_feature(enable = "avx512fp16,avx512vl")]
4075#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4076#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
4077pub const fn _mm_maskz_conj_pch(k: __mmask8, a: __m128h) -> __m128h {
4078    _mm_mask_conj_pch(_mm_setzero_ph(), k, a)
4079}
4080
4081/// Compute the complex conjugates of complex numbers in a, and store the results in dst. Each complex number
4082/// is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex
4083/// number `complex = vec.fp16[0] + i * vec.fp16[1]`, or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
4084///
4085/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_conj_pch)
4086#[inline]
4087#[target_feature(enable = "avx512fp16,avx512vl")]
4088#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4089#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
4090pub const fn _mm256_conj_pch(a: __m256h) -> __m256h {
4091    unsafe { transmute(_mm256_xor_si256(transmute(a), _mm256_set1_epi32(i32::MIN))) }
4092}
4093
4094/// Compute the complex conjugates of complex numbers in a, and store the results in dst using writemask k
4095/// (the element is copied from src when corresponding mask bit is not set). Each complex number is composed of two
4096/// adjacent half-precision (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`,
4097/// or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
4098///
4099/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_conj_pch)
4100#[inline]
4101#[target_feature(enable = "avx512fp16,avx512vl")]
4102#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4103#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
4104pub const fn _mm256_mask_conj_pch(src: __m256h, k: __mmask8, a: __m256h) -> __m256h {
4105    unsafe {
4106        let r: __m256 = transmute(_mm256_conj_pch(a));
4107        transmute(simd_select_bitmask(k, r, transmute(src)))
4108    }
4109}
4110
4111/// Compute the complex conjugates of complex numbers in a, and store the results in dst using zeromask k
4112/// (the element is zeroed out when corresponding mask bit is not set). Each complex number is composed of two adjacent
4113/// half-precision (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`,
4114/// or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
4115///
4116/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_conj_pch)
4117#[inline]
4118#[target_feature(enable = "avx512fp16,avx512vl")]
4119#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4120#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
4121pub const fn _mm256_maskz_conj_pch(k: __mmask8, a: __m256h) -> __m256h {
4122    _mm256_mask_conj_pch(_mm256_setzero_ph(), k, a)
4123}
4124
4125/// Compute the complex conjugates of complex numbers in a, and store the results in dst. Each complex number
4126/// is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex
4127/// number `complex = vec.fp16[0] + i * vec.fp16[1]`, or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
4128///
4129/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_conj_pch)
4130#[inline]
4131#[target_feature(enable = "avx512fp16")]
4132#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4133#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
4134pub const fn _mm512_conj_pch(a: __m512h) -> __m512h {
4135    unsafe { transmute(_mm512_xor_si512(transmute(a), _mm512_set1_epi32(i32::MIN))) }
4136}
4137
4138/// Compute the complex conjugates of complex numbers in a, and store the results in dst using writemask k
4139/// (the element is copied from src when corresponding mask bit is not set). Each complex number is composed of two
4140/// adjacent half-precision (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`,
4141/// or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
4142///
4143/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_conj_pch)
4144#[inline]
4145#[target_feature(enable = "avx512fp16")]
4146#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4147#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
4148pub const fn _mm512_mask_conj_pch(src: __m512h, k: __mmask16, a: __m512h) -> __m512h {
4149    unsafe {
4150        let r: __m512 = transmute(_mm512_conj_pch(a));
4151        transmute(simd_select_bitmask(k, r, transmute(src)))
4152    }
4153}
4154
4155/// Compute the complex conjugates of complex numbers in a, and store the results in dst using zeromask k
4156/// (the element is zeroed out when corresponding mask bit is not set). Each complex number is composed of two adjacent
4157/// half-precision (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`,
4158/// or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
4159///
4160/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_conj_pch)
4161#[inline]
4162#[target_feature(enable = "avx512fp16")]
4163#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4164#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
4165pub const fn _mm512_maskz_conj_pch(k: __mmask16, a: __m512h) -> __m512h {
4166    _mm512_mask_conj_pch(_mm512_setzero_ph(), k, a)
4167}
4168
4169/// Multiply packed complex numbers in a and b, accumulate to the corresponding complex numbers in c,
4170/// and store the results in dst. Each complex number is composed of two adjacent half-precision (16-bit)
4171/// floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
4172///
4173/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fmadd_pch)
4174#[inline]
4175#[target_feature(enable = "avx512fp16,avx512vl")]
4176#[cfg_attr(test, assert_instr(vfmaddcph))]
4177#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4178pub fn _mm_fmadd_pch(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
4179    _mm_mask3_fmadd_pch(a, b, c, 0xff)
4180}
4181
4182/// Multiply packed complex numbers in a and b, accumulate to the corresponding complex numbers in c,
4183/// and store the results in dst using writemask k (the element is copied from a when the corresponding
4184/// mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit)
4185/// floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
4186///
4187/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fmadd_pch)
4188#[inline]
4189#[target_feature(enable = "avx512fp16,avx512vl")]
4190#[cfg_attr(test, assert_instr(vfmaddcph))]
4191#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4192pub fn _mm_mask_fmadd_pch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
4193    unsafe {
4194        let r: __m128 = transmute(_mm_mask3_fmadd_pch(a, b, c, k)); // using `0xff` would have been fine here, but this is what CLang does
4195        transmute(simd_select_bitmask(k, r, transmute(a)))
4196    }
4197}
4198
4199/// Multiply packed complex numbers in a and b, accumulate to the corresponding complex numbers in c,
4200/// and store the results in dst using writemask k (the element is copied from c when the corresponding
4201/// mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit)
4202/// floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
4203///
4204/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fmadd_pch)
4205#[inline]
4206#[target_feature(enable = "avx512fp16,avx512vl")]
4207#[cfg_attr(test, assert_instr(vfmaddcph))]
4208#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4209pub fn _mm_mask3_fmadd_pch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
4210    unsafe {
4211        transmute(vfmaddcph_mask3_128(
4212            transmute(a),
4213            transmute(b),
4214            transmute(c),
4215            k,
4216        ))
4217    }
4218}
4219
4220/// Multiply packed complex numbers in a and b, accumulate to the corresponding complex numbers in c,
4221/// and store the results in dst using zeromask k (the element is zeroed out when the corresponding mask
4222/// bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point
4223/// elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
4224///
4225/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fmadd_pch)
4226#[inline]
4227#[target_feature(enable = "avx512fp16,avx512vl")]
4228#[cfg_attr(test, assert_instr(vfmaddcph))]
4229#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4230pub fn _mm_maskz_fmadd_pch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
4231    unsafe {
4232        transmute(vfmaddcph_maskz_128(
4233            transmute(a),
4234            transmute(b),
4235            transmute(c),
4236            k,
4237        ))
4238    }
4239}
4240
4241/// Multiply packed complex numbers in a and b, accumulate to the corresponding complex numbers in c,
4242/// and store the results in dst. Each complex number is composed of two adjacent half-precision (16-bit)
4243/// floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
4244///
4245/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_fmadd_pch)
4246#[inline]
4247#[target_feature(enable = "avx512fp16,avx512vl")]
4248#[cfg_attr(test, assert_instr(vfmaddcph))]
4249#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4250pub fn _mm256_fmadd_pch(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
4251    _mm256_mask3_fmadd_pch(a, b, c, 0xff)
4252}
4253
4254/// Multiply packed complex numbers in a and b, accumulate to the corresponding complex numbers in c,
4255/// and store the results in dst using writemask k (the element is copied from a when the corresponding mask
4256/// bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point
4257/// elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
4258///
4259/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_fmadd_pch)
4260#[inline]
4261#[target_feature(enable = "avx512fp16,avx512vl")]
4262#[cfg_attr(test, assert_instr(vfmaddcph))]
4263#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4264pub fn _mm256_mask_fmadd_pch(a: __m256h, k: __mmask8, b: __m256h, c: __m256h) -> __m256h {
4265    unsafe {
4266        let r: __m256 = transmute(_mm256_mask3_fmadd_pch(a, b, c, k)); // using `0xff` would have been fine here, but this is what CLang does
4267        transmute(simd_select_bitmask(k, r, transmute(a)))
4268    }
4269}
4270
4271/// Multiply packed complex numbers in a and b, accumulate to the corresponding complex numbers in c,
4272/// and store the results in dst using writemask k (the element is copied from c when the corresponding
4273/// mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit)
4274/// floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
4275///
4276/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask3_fmadd_pch)
4277#[inline]
4278#[target_feature(enable = "avx512fp16,avx512vl")]
4279#[cfg_attr(test, assert_instr(vfmaddcph))]
4280#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4281pub fn _mm256_mask3_fmadd_pch(a: __m256h, b: __m256h, c: __m256h, k: __mmask8) -> __m256h {
4282    unsafe {
4283        transmute(vfmaddcph_mask3_256(
4284            transmute(a),
4285            transmute(b),
4286            transmute(c),
4287            k,
4288        ))
4289    }
4290}
4291
4292/// Multiply packed complex numbers in a and b, accumulate to the corresponding complex numbers in c,
4293/// and store the results in dst using zeromask k (the element is zeroed out when the corresponding mask
4294/// bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point
4295/// elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
4296///
4297/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_fmadd_pch)
4298#[inline]
4299#[target_feature(enable = "avx512fp16,avx512vl")]
4300#[cfg_attr(test, assert_instr(vfmaddcph))]
4301#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4302pub fn _mm256_maskz_fmadd_pch(k: __mmask8, a: __m256h, b: __m256h, c: __m256h) -> __m256h {
4303    unsafe {
4304        transmute(vfmaddcph_maskz_256(
4305            transmute(a),
4306            transmute(b),
4307            transmute(c),
4308            k,
4309        ))
4310    }
4311}
4312
4313/// Multiply packed complex numbers in a and b, accumulate to the corresponding complex numbers in c,
4314/// and store the results in dst. Each complex number is composed of two adjacent half-precision (16-bit)
4315/// floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
4316///
4317/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fmadd_pch)
4318#[inline]
4319#[target_feature(enable = "avx512fp16")]
4320#[cfg_attr(test, assert_instr(vfmaddcph))]
4321#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4322pub fn _mm512_fmadd_pch(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
4323    _mm512_fmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(a, b, c)
4324}
4325
4326/// Multiply packed complex numbers in a and b, accumulate to the corresponding complex numbers in c,
4327/// and store the results in dst using writemask k (the element is copied from a when the corresponding mask
4328/// bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point
4329/// elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
4330///
4331/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fmadd_pch)
4332#[inline]
4333#[target_feature(enable = "avx512fp16")]
4334#[cfg_attr(test, assert_instr(vfmaddcph))]
4335#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4336pub fn _mm512_mask_fmadd_pch(a: __m512h, k: __mmask16, b: __m512h, c: __m512h) -> __m512h {
4337    _mm512_mask_fmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(a, k, b, c)
4338}
4339
4340/// Multiply packed complex numbers in a and b, accumulate to the corresponding complex numbers in c,
4341/// and store the results in dst using writemask k (the element is copied from c when the corresponding
4342/// mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit)
4343/// floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
4344///
4345/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fmadd_pch)
4346#[inline]
4347#[target_feature(enable = "avx512fp16")]
4348#[cfg_attr(test, assert_instr(vfmaddcph))]
4349#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4350pub fn _mm512_mask3_fmadd_pch(a: __m512h, b: __m512h, c: __m512h, k: __mmask16) -> __m512h {
4351    _mm512_mask3_fmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(a, b, c, k)
4352}
4353
4354/// Multiply packed complex numbers in a and b, accumulate to the corresponding complex numbers in c,
4355/// and store the results in dst using zeromask k (the element is zeroed out when the corresponding mask
4356/// bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point
4357/// elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
4358///
4359/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fmadd_pch)
4360#[inline]
4361#[target_feature(enable = "avx512fp16")]
4362#[cfg_attr(test, assert_instr(vfmaddcph))]
4363#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4364pub fn _mm512_maskz_fmadd_pch(k: __mmask16, a: __m512h, b: __m512h, c: __m512h) -> __m512h {
4365    _mm512_maskz_fmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(k, a, b, c)
4366}
4367
4368/// Multiply packed complex numbers in a and b, accumulate to the corresponding complex numbers in c,
4369/// and store the results in dst. Each complex number is composed of two adjacent half-precision (16-bit)
4370/// floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
4371///
4372/// Rounding is done according to the rounding parameter, which can be one of:
4373///
4374/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
4375/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
4376/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
4377/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
4378/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
4379///
4380/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fmadd_round_pch)
4381#[inline]
4382#[target_feature(enable = "avx512fp16")]
4383#[cfg_attr(test, assert_instr(vfmaddcph, ROUNDING = 8))]
4384#[rustc_legacy_const_generics(3)]
4385#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4386pub fn _mm512_fmadd_round_pch<const ROUNDING: i32>(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
4387    static_assert_rounding!(ROUNDING);
4388    _mm512_mask3_fmadd_round_pch::<ROUNDING>(a, b, c, 0xffff)
4389}
4390
4391/// Multiply packed complex numbers in a and b, accumulate to the corresponding complex numbers in c,
4392/// and store the results in dst using writemask k (the element is copied from a when the corresponding mask
4393/// bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point
4394/// elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
4395///
4396/// Rounding is done according to the rounding parameter, which can be one of:
4397///
4398/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
4399/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
4400/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
4401/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
4402/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
4403///
4404/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fmadd_round_pch)
4405#[inline]
4406#[target_feature(enable = "avx512fp16")]
4407#[cfg_attr(test, assert_instr(vfmaddcph, ROUNDING = 8))]
4408#[rustc_legacy_const_generics(4)]
4409#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4410pub fn _mm512_mask_fmadd_round_pch<const ROUNDING: i32>(
4411    a: __m512h,
4412    k: __mmask16,
4413    b: __m512h,
4414    c: __m512h,
4415) -> __m512h {
4416    unsafe {
4417        static_assert_rounding!(ROUNDING);
4418        let r: __m512 = transmute(_mm512_mask3_fmadd_round_pch::<ROUNDING>(a, b, c, k)); // using `0xffff` would have been fine here, but this is what CLang does
4419        transmute(simd_select_bitmask(k, r, transmute(a)))
4420    }
4421}
4422
4423/// Multiply packed complex numbers in a and b, accumulate to the corresponding complex numbers in c,
4424/// and store the results in dst using writemask k (the element is copied from c when the corresponding
4425/// mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit)
4426/// floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
4427///
4428/// Rounding is done according to the rounding parameter, which can be one of:
4429///
4430/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
4431/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
4432/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
4433/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
4434/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
4435///
4436/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fmadd_round_pch)
4437#[inline]
4438#[target_feature(enable = "avx512fp16")]
4439#[cfg_attr(test, assert_instr(vfmaddcph, ROUNDING = 8))]
4440#[rustc_legacy_const_generics(4)]
4441#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4442pub fn _mm512_mask3_fmadd_round_pch<const ROUNDING: i32>(
4443    a: __m512h,
4444    b: __m512h,
4445    c: __m512h,
4446    k: __mmask16,
4447) -> __m512h {
4448    unsafe {
4449        static_assert_rounding!(ROUNDING);
4450        transmute(vfmaddcph_mask3_512(
4451            transmute(a),
4452            transmute(b),
4453            transmute(c),
4454            k,
4455            ROUNDING,
4456        ))
4457    }
4458}
4459
4460/// Multiply packed complex numbers in a and b, accumulate to the corresponding complex numbers in c,
4461/// and store the results in dst using zeromask k (the element is zeroed out when the corresponding mask
4462/// bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point
4463/// elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
4464///
4465/// Rounding is done according to the rounding parameter, which can be one of:
4466///
4467/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
4468/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
4469/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
4470/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
4471/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
4472///
4473/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fmadd_round_pch)
4474#[inline]
4475#[target_feature(enable = "avx512fp16")]
4476#[cfg_attr(test, assert_instr(vfmaddcph, ROUNDING = 8))]
4477#[rustc_legacy_const_generics(4)]
4478#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4479pub fn _mm512_maskz_fmadd_round_pch<const ROUNDING: i32>(
4480    k: __mmask16,
4481    a: __m512h,
4482    b: __m512h,
4483    c: __m512h,
4484) -> __m512h {
4485    unsafe {
4486        static_assert_rounding!(ROUNDING);
4487        transmute(vfmaddcph_maskz_512(
4488            transmute(a),
4489            transmute(b),
4490            transmute(c),
4491            k,
4492            ROUNDING,
4493        ))
4494    }
4495}
4496
4497/// Multiply the lower complex numbers in a and b, accumulate to the lower complex number in c, and
4498/// store the result in the lower elements of dst, and copy the upper 6 packed elements from a to the
4499/// upper elements of dst. Each complex number is composed of two adjacent half-precision (16-bit)
4500/// floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
4501///
4502/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fmadd_sch)
4503#[inline]
4504#[target_feature(enable = "avx512fp16")]
4505#[cfg_attr(test, assert_instr(vfmaddcsh))]
4506#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4507pub fn _mm_fmadd_sch(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
4508    _mm_fmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(a, b, c)
4509}
4510
4511/// Multiply the lower complex numbers in a and b, accumulate to the lower complex number in c, and
4512/// store the result in the lower elements of dst using writemask k (elements are copied from a when
4513/// mask bit 0 is not set), and copy the upper 6 packed elements from a to the upper elements of dst.
4514/// Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements,
4515/// which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
4516///
4517/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fmadd_sch)
4518#[inline]
4519#[target_feature(enable = "avx512fp16")]
4520#[cfg_attr(test, assert_instr(vfmaddcsh))]
4521#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4522pub fn _mm_mask_fmadd_sch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
4523    _mm_mask_fmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(a, k, b, c)
4524}
4525
4526/// Multiply the lower complex numbers in a and b, accumulate to the lower complex number in c, and
4527/// store the result in the lower elements of dst using writemask k (elements are copied from c when
4528/// mask bit 0 is not set), and copy the upper 6 packed elements from a to the upper elements of dst.
4529/// Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements,
4530/// which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
4531///
4532/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fmadd_sch)
4533#[inline]
4534#[target_feature(enable = "avx512fp16")]
4535#[cfg_attr(test, assert_instr(vfmaddcsh))]
4536#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4537pub fn _mm_mask3_fmadd_sch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
4538    _mm_mask3_fmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(a, b, c, k)
4539}
4540
4541/// Multiply the lower complex numbers in a and b, accumulate to the lower complex number in c, and
4542/// store the result in the lower elements of dst using zeromask k (elements are zeroed out when mask
4543/// bit 0 is not set), and copy the upper 6 packed elements from a to the upper elements of dst. Each
4544/// complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which
4545/// defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
4546///
4547/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fmadd_sch)
4548#[inline]
4549#[target_feature(enable = "avx512fp16")]
4550#[cfg_attr(test, assert_instr(vfmaddcsh))]
4551#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4552pub fn _mm_maskz_fmadd_sch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
4553    _mm_maskz_fmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(k, a, b, c)
4554}
4555
4556/// Multiply the lower complex numbers in a and b, accumulate to the lower complex number in c, and
4557/// store the result in the lower elements of dst. Each complex number is composed of two adjacent
4558/// half-precision (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
4559///
4560/// Rounding is done according to the rounding parameter, which can be one of:
4561///
4562/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
4563/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
4564/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
4565/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
4566/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
4567///
4568/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fmadd_round_sch)
4569#[inline]
4570#[target_feature(enable = "avx512fp16")]
4571#[cfg_attr(test, assert_instr(vfmaddcsh, ROUNDING = 8))]
4572#[rustc_legacy_const_generics(3)]
4573#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4574pub fn _mm_fmadd_round_sch<const ROUNDING: i32>(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
4575    unsafe {
4576        static_assert_rounding!(ROUNDING);
4577        transmute(vfmaddcsh_mask(
4578            transmute(a),
4579            transmute(b),
4580            transmute(c),
4581            0xff,
4582            ROUNDING,
4583        ))
4584    }
4585}
4586
4587/// Multiply the lower complex numbers in a and b, accumulate to the lower complex number in c, and
4588/// store the result in the lower elements of dst using writemask k (elements are copied from a when
4589/// mask bit 0 is not set), and copy the upper 6 packed elements from a to the upper elements of dst.
4590/// Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements,
4591/// which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
4592///
4593/// Rounding is done according to the rounding parameter, which can be one of:
4594///
4595/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
4596/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
4597/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
4598/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
4599/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
4600///
4601/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fmadd_round_sch)
4602#[inline]
4603#[target_feature(enable = "avx512fp16")]
4604#[cfg_attr(test, assert_instr(vfmaddcsh, ROUNDING = 8))]
4605#[rustc_legacy_const_generics(4)]
4606#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4607pub fn _mm_mask_fmadd_round_sch<const ROUNDING: i32>(
4608    a: __m128h,
4609    k: __mmask8,
4610    b: __m128h,
4611    c: __m128h,
4612) -> __m128h {
4613    unsafe {
4614        static_assert_rounding!(ROUNDING);
4615        let a = transmute(a);
4616        let r = vfmaddcsh_mask(a, transmute(b), transmute(c), k, ROUNDING); // using `0xff` would have been fine here, but this is what CLang does
4617        transmute(_mm_mask_move_ss(a, k, a, r))
4618    }
4619}
4620
4621/// Multiply the lower complex numbers in a and b, accumulate to the lower complex number in c, and
4622/// store the result in the lower elements of dst using writemask k (elements are copied from c when
4623/// mask bit 0 is not set), and copy the upper 6 packed elements from a to the upper elements of dst.
4624/// Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements,
4625/// which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
4626///
4627/// Rounding is done according to the rounding parameter, which can be one of:
4628///
4629/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
4630/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
4631/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
4632/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
4633/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
4634///
4635/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fmadd_round_sch)
4636#[inline]
4637#[target_feature(enable = "avx512fp16")]
4638#[cfg_attr(test, assert_instr(vfmaddcsh, ROUNDING = 8))]
4639#[rustc_legacy_const_generics(4)]
4640#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4641pub fn _mm_mask3_fmadd_round_sch<const ROUNDING: i32>(
4642    a: __m128h,
4643    b: __m128h,
4644    c: __m128h,
4645    k: __mmask8,
4646) -> __m128h {
4647    unsafe {
4648        static_assert_rounding!(ROUNDING);
4649        let c = transmute(c);
4650        let r = vfmaddcsh_mask(transmute(a), transmute(b), c, k, ROUNDING);
4651        transmute(_mm_move_ss(c, r))
4652    }
4653}
4654
4655/// Multiply the lower complex numbers in a and b, accumulate to the lower complex number in c, and
4656/// store the result in the lower elements of dst using zeromask k (elements are zeroed out when mask
4657/// bit 0 is not set), and copy the upper 6 packed elements from a to the upper elements of dst. Each
4658/// complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which
4659/// defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`.
4660///
4661/// Rounding is done according to the rounding parameter, which can be one of:
4662///
4663/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
4664/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
4665/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
4666/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
4667/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
4668///
4669/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fmadd_round_sch)
4670#[inline]
4671#[target_feature(enable = "avx512fp16")]
4672#[cfg_attr(test, assert_instr(vfmaddcsh, ROUNDING = 8))]
4673#[rustc_legacy_const_generics(4)]
4674#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4675pub fn _mm_maskz_fmadd_round_sch<const ROUNDING: i32>(
4676    k: __mmask8,
4677    a: __m128h,
4678    b: __m128h,
4679    c: __m128h,
4680) -> __m128h {
4681    unsafe {
4682        static_assert_rounding!(ROUNDING);
4683        transmute(vfmaddcsh_maskz(
4684            transmute(a),
4685            transmute(b),
4686            transmute(c),
4687            k,
4688            ROUNDING,
4689        ))
4690    }
4691}
4692
4693/// Multiply packed complex numbers in a by the complex conjugates of packed complex numbers in b, accumulate
4694/// to the corresponding complex numbers in c, and store the results in dst. Each complex number is composed
4695/// of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number
4696/// `complex = vec.fp16[0] + i * vec.fp16[1]`, or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
4697///
4698/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fcmadd_pch)
4699#[inline]
4700#[target_feature(enable = "avx512fp16,avx512vl")]
4701#[cfg_attr(test, assert_instr(vfcmaddcph))]
4702#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4703pub fn _mm_fcmadd_pch(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
4704    _mm_mask3_fcmadd_pch(a, b, c, 0xff)
4705}
4706
4707/// Multiply packed complex numbers in a by the complex conjugates of packed complex numbers in b, accumulate
4708/// to the corresponding complex numbers in c, and store the results in dst using writemask k (the element is
4709/// copied from a when the corresponding mask bit is not set). Each complex number is composed of two adjacent
4710/// half-precision (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`,
4711/// or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
4712///
4713/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fcmadd_pch)
4714#[inline]
4715#[target_feature(enable = "avx512fp16,avx512vl")]
4716#[cfg_attr(test, assert_instr(vfcmaddcph))]
4717#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4718pub fn _mm_mask_fcmadd_pch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
4719    unsafe {
4720        let r: __m128 = transmute(_mm_mask3_fcmadd_pch(a, b, c, k)); // using `0xff` would have been fine here, but this is what CLang does
4721        transmute(simd_select_bitmask(k, r, transmute(a)))
4722    }
4723}
4724
4725/// Multiply packed complex numbers in a by the complex conjugates of packed complex numbers in b, accumulate
4726/// to the corresponding complex numbers in c, and store the results in dst using writemask k (the element is
4727/// copied from c when the corresponding mask bit is not set). Each complex number is composed of two adjacent
4728/// half-precision (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`,
4729/// or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
4730///
4731/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fcmadd_pch)
4732#[inline]
4733#[target_feature(enable = "avx512fp16,avx512vl")]
4734#[cfg_attr(test, assert_instr(vfcmaddcph))]
4735#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4736pub fn _mm_mask3_fcmadd_pch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
4737    unsafe {
4738        transmute(vfcmaddcph_mask3_128(
4739            transmute(a),
4740            transmute(b),
4741            transmute(c),
4742            k,
4743        ))
4744    }
4745}
4746
4747/// Multiply packed complex numbers in a by the complex conjugates of packed complex numbers in b, accumulate
4748/// to the corresponding complex numbers in c, and store the results in dst using zeromask k (the element is
4749/// zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent
4750/// half-precision (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`,
4751/// or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
4752///
4753/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fcmadd_pch)
4754#[inline]
4755#[target_feature(enable = "avx512fp16,avx512vl")]
4756#[cfg_attr(test, assert_instr(vfcmaddcph))]
4757#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4758pub fn _mm_maskz_fcmadd_pch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
4759    unsafe {
4760        transmute(vfcmaddcph_maskz_128(
4761            transmute(a),
4762            transmute(b),
4763            transmute(c),
4764            k,
4765        ))
4766    }
4767}
4768
4769/// Multiply packed complex numbers in a by the complex conjugates of packed complex numbers in b, accumulate
4770/// to the corresponding complex numbers in c, and store the results in dst. Each complex number is composed
4771/// of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number
4772/// `complex = vec.fp16[0] + i * vec.fp16[1]`, or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
4773///
4774/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_fcmadd_pch)
4775#[inline]
4776#[target_feature(enable = "avx512fp16,avx512vl")]
4777#[cfg_attr(test, assert_instr(vfcmaddcph))]
4778#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4779pub fn _mm256_fcmadd_pch(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
4780    _mm256_mask3_fcmadd_pch(a, b, c, 0xff)
4781}
4782
4783/// Multiply packed complex numbers in a by the complex conjugates of packed complex numbers in b, accumulate
4784/// to the corresponding complex numbers in c, and store the results in dst using writemask k (the element is
4785/// copied from a when the corresponding mask bit is not set). Each complex number is composed of two adjacent
4786/// half-precision (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`,
4787/// or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
4788///
4789/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_fcmadd_pch)
4790#[inline]
4791#[target_feature(enable = "avx512fp16,avx512vl")]
4792#[cfg_attr(test, assert_instr(vfcmaddcph))]
4793#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4794pub fn _mm256_mask_fcmadd_pch(a: __m256h, k: __mmask8, b: __m256h, c: __m256h) -> __m256h {
4795    unsafe {
4796        let r: __m256 = transmute(_mm256_mask3_fcmadd_pch(a, b, c, k)); // using `0xff` would have been fine here, but this is what CLang does
4797        transmute(simd_select_bitmask(k, r, transmute(a)))
4798    }
4799}
4800
4801/// Multiply packed complex numbers in a by the complex conjugates of packed complex numbers in b, accumulate
4802/// to the corresponding complex numbers in c, and store the results in dst using writemask k (the element is
4803/// copied from c when the corresponding mask bit is not set). Each complex number is composed of two adjacent
4804/// half-precision (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`,
4805/// or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
4806///
4807/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask3_fcmadd_pch)
4808#[inline]
4809#[target_feature(enable = "avx512fp16,avx512vl")]
4810#[cfg_attr(test, assert_instr(vfcmaddcph))]
4811#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4812pub fn _mm256_mask3_fcmadd_pch(a: __m256h, b: __m256h, c: __m256h, k: __mmask8) -> __m256h {
4813    unsafe {
4814        transmute(vfcmaddcph_mask3_256(
4815            transmute(a),
4816            transmute(b),
4817            transmute(c),
4818            k,
4819        ))
4820    }
4821}
4822
4823/// Multiply packed complex numbers in a by the complex conjugates of packed complex numbers in b, accumulate
4824/// to the corresponding complex numbers in c, and store the results in dst using zeromask k (the element is
4825/// zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent
4826/// half-precision (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`,
4827/// or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
4828///
4829/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_fcmadd_pch)
4830#[inline]
4831#[target_feature(enable = "avx512fp16,avx512vl")]
4832#[cfg_attr(test, assert_instr(vfcmaddcph))]
4833#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4834pub fn _mm256_maskz_fcmadd_pch(k: __mmask8, a: __m256h, b: __m256h, c: __m256h) -> __m256h {
4835    unsafe {
4836        transmute(vfcmaddcph_maskz_256(
4837            transmute(a),
4838            transmute(b),
4839            transmute(c),
4840            k,
4841        ))
4842    }
4843}
4844
4845/// Multiply packed complex numbers in a by the complex conjugates of packed complex numbers in b, accumulate
4846/// to the corresponding complex numbers in c, and store the results in dst. Each complex number is composed
4847/// of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number
4848/// `complex = vec.fp16[0] + i * vec.fp16[1]`, or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
4849///
4850/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fcmadd_pch)
4851#[inline]
4852#[target_feature(enable = "avx512fp16")]
4853#[cfg_attr(test, assert_instr(vfcmaddcph))]
4854#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4855pub fn _mm512_fcmadd_pch(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
4856    _mm512_fcmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(a, b, c)
4857}
4858
4859/// Multiply packed complex numbers in a by the complex conjugates of packed complex numbers in b, accumulate
4860/// to the corresponding complex numbers in c, and store the results in dst using writemask k (the element is
4861/// copied from a when the corresponding mask bit is not set). Each complex number is composed of two adjacent
4862/// half-precision (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`,
4863/// or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
4864///
4865/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fcmadd_pch)
4866#[inline]
4867#[target_feature(enable = "avx512fp16")]
4868#[cfg_attr(test, assert_instr(vfcmaddcph))]
4869#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4870pub fn _mm512_mask_fcmadd_pch(a: __m512h, k: __mmask16, b: __m512h, c: __m512h) -> __m512h {
4871    _mm512_mask_fcmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(a, k, b, c)
4872}
4873
4874/// Multiply packed complex numbers in a by the complex conjugates of packed complex numbers in b, accumulate
4875/// to the corresponding complex numbers in c, and store the results in dst using writemask k (the element is
4876/// copied from c when the corresponding mask bit is not set). Each complex number is composed of two adjacent
4877/// half-precision (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`,
4878/// or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
4879///
4880/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fcmadd_pch)
4881#[inline]
4882#[target_feature(enable = "avx512fp16")]
4883#[cfg_attr(test, assert_instr(vfcmaddcph))]
4884#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4885pub fn _mm512_mask3_fcmadd_pch(a: __m512h, b: __m512h, c: __m512h, k: __mmask16) -> __m512h {
4886    _mm512_mask3_fcmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(a, b, c, k)
4887}
4888
4889/// Multiply packed complex numbers in a by the complex conjugates of packed complex numbers in b, accumulate
4890/// to the corresponding complex numbers in c, and store the results in dst using zeromask k (the element is
4891/// zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent
4892/// half-precision (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`,
4893/// or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
4894///
4895/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fcmadd_pch)
4896#[inline]
4897#[target_feature(enable = "avx512fp16")]
4898#[cfg_attr(test, assert_instr(vfcmaddcph))]
4899#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4900pub fn _mm512_maskz_fcmadd_pch(k: __mmask16, a: __m512h, b: __m512h, c: __m512h) -> __m512h {
4901    _mm512_maskz_fcmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(k, a, b, c)
4902}
4903
4904/// Multiply packed complex numbers in a by the complex conjugates of packed complex numbers in b, accumulate
4905/// to the corresponding complex numbers in c, and store the results in dst. Each complex number is composed
4906/// of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number
4907/// `complex = vec.fp16[0] + i * vec.fp16[1]`, or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
4908///
4909/// Rounding is done according to the rounding parameter, which can be one of:
4910///
4911/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
4912/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
4913/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
4914/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
4915/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
4916///
4917/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fcmadd_round_pch)
4918#[inline]
4919#[target_feature(enable = "avx512fp16")]
4920#[cfg_attr(test, assert_instr(vfcmaddcph, ROUNDING = 8))]
4921#[rustc_legacy_const_generics(3)]
4922#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4923pub fn _mm512_fcmadd_round_pch<const ROUNDING: i32>(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
4924    static_assert_rounding!(ROUNDING);
4925    _mm512_mask3_fcmadd_round_pch::<ROUNDING>(a, b, c, 0xffff)
4926}
4927
4928/// Multiply packed complex numbers in a by the complex conjugates of packed complex numbers in b, accumulate
4929/// to the corresponding complex numbers in c, and store the results in dst using writemask k (the element is
4930/// copied from a when the corresponding mask bit is not set). Each complex number is composed of two adjacent
4931/// half-precision (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`,
4932/// or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
4933///
4934/// Rounding is done according to the rounding parameter, which can be one of:
4935///
4936/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
4937/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
4938/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
4939/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
4940/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
4941///
4942/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fcmadd_round_pch)
4943#[inline]
4944#[target_feature(enable = "avx512fp16")]
4945#[cfg_attr(test, assert_instr(vfcmaddcph, ROUNDING = 8))]
4946#[rustc_legacy_const_generics(4)]
4947#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4948pub fn _mm512_mask_fcmadd_round_pch<const ROUNDING: i32>(
4949    a: __m512h,
4950    k: __mmask16,
4951    b: __m512h,
4952    c: __m512h,
4953) -> __m512h {
4954    unsafe {
4955        static_assert_rounding!(ROUNDING);
4956        let r: __m512 = transmute(_mm512_mask3_fcmadd_round_pch::<ROUNDING>(a, b, c, k)); // using `0xffff` would have been fine here, but this is what CLang does
4957        transmute(simd_select_bitmask(k, r, transmute(a)))
4958    }
4959}
4960
4961/// Multiply packed complex numbers in a by the complex conjugates of packed complex numbers in b, accumulate
4962/// to the corresponding complex numbers in c using writemask k (the element is copied from c when the corresponding
4963/// mask bit is not set), and store the results in dst. Each complex number is composed of two adjacent half-precision
4964/// (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1`, or the complex
4965/// conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
4966///
4967/// Rounding is done according to the rounding parameter, which can be one of:
4968///
4969/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
4970/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
4971/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
4972/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
4973/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
4974///
4975/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fcmadd_round_pch)
4976#[inline]
4977#[target_feature(enable = "avx512fp16")]
4978#[cfg_attr(test, assert_instr(vfcmaddcph, ROUNDING = 8))]
4979#[rustc_legacy_const_generics(4)]
4980#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
4981pub fn _mm512_mask3_fcmadd_round_pch<const ROUNDING: i32>(
4982    a: __m512h,
4983    b: __m512h,
4984    c: __m512h,
4985    k: __mmask16,
4986) -> __m512h {
4987    unsafe {
4988        static_assert_rounding!(ROUNDING);
4989        transmute(vfcmaddcph_mask3_512(
4990            transmute(a),
4991            transmute(b),
4992            transmute(c),
4993            k,
4994            ROUNDING,
4995        ))
4996    }
4997}
4998
4999/// Multiply packed complex numbers in a by the complex conjugates of packed complex numbers in b, accumulate
5000/// to the corresponding complex numbers in c using zeromask k (the element is zeroed out when the corresponding
5001/// mask bit is not set), and store the results in dst. Each complex number is composed of two adjacent half-precision
5002/// (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1`, or the complex
5003/// conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
5004///
5005/// Rounding is done according to the rounding parameter, which can be one of:
5006///
5007/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
5008/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
5009/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
5010/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
5011/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
5012///
5013/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fcmadd_round_pch)
5014#[inline]
5015#[target_feature(enable = "avx512fp16")]
5016#[cfg_attr(test, assert_instr(vfcmaddcph, ROUNDING = 8))]
5017#[rustc_legacy_const_generics(4)]
5018#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5019pub fn _mm512_maskz_fcmadd_round_pch<const ROUNDING: i32>(
5020    k: __mmask16,
5021    a: __m512h,
5022    b: __m512h,
5023    c: __m512h,
5024) -> __m512h {
5025    unsafe {
5026        static_assert_rounding!(ROUNDING);
5027        transmute(vfcmaddcph_maskz_512(
5028            transmute(a),
5029            transmute(b),
5030            transmute(c),
5031            k,
5032            ROUNDING,
5033        ))
5034    }
5035}
5036
5037/// Multiply the lower complex number in a by the complex conjugate of the lower complex number in b,
5038/// accumulate to the lower complex number in c, and store the result in the lower elements of dst,
5039/// and copy the upper 6 packed elements from a to the upper elements of dst. Each complex number is
5040/// composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex
5041/// number `complex = vec.fp16[0] + i * vec.fp16[1]`, or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
5042///
5043/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fcmadd_sch)
5044#[inline]
5045#[target_feature(enable = "avx512fp16")]
5046#[cfg_attr(test, assert_instr(vfcmaddcsh))]
5047#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5048pub fn _mm_fcmadd_sch(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
5049    _mm_fcmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(a, b, c)
5050}
5051
5052/// Multiply the lower complex number in a by the complex conjugate of the lower complex number in b,
5053/// accumulate to the lower complex number in c, and store the result in the lower elements of dst using
5054/// writemask k (the element is copied from a when the corresponding mask bit is not set), and copy the upper
5055/// 6 packed elements from a to the upper elements of dst. Each complex number is composed of two adjacent
5056/// half-precision (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`,
5057/// or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
5058///
5059/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fcmadd_sch)
5060#[inline]
5061#[target_feature(enable = "avx512fp16")]
5062#[cfg_attr(test, assert_instr(vfcmaddcsh))]
5063#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5064pub fn _mm_mask_fcmadd_sch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
5065    _mm_mask_fcmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(a, k, b, c)
5066}
5067
5068/// Multiply the lower complex number in a by the complex conjugate of the lower complex number in b,
5069/// accumulate to the lower complex number in c, and store the result in the lower elements of dst using
5070/// writemask k (the element is copied from c when the corresponding mask bit is not set), and copy the upper
5071/// 6 packed elements from a to the upper elements of dst. Each complex number is composed of two adjacent
5072/// half-precision (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`,
5073/// or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
5074///
5075/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fcmadd_sch)
5076#[inline]
5077#[target_feature(enable = "avx512fp16")]
5078#[cfg_attr(test, assert_instr(vfcmaddcsh))]
5079#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5080pub fn _mm_mask3_fcmadd_sch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
5081    _mm_mask3_fcmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(a, b, c, k)
5082}
5083
5084/// Multiply the lower complex number in a by the complex conjugate of the lower complex number in b,
5085/// accumulate to the lower complex number in c, and store the result in the lower elements of dst using
5086/// zeromask k (the element is zeroed out when the corresponding mask bit is not set), and copy the upper
5087/// 6 packed elements from a to the upper elements of dst. Each complex number is composed of two adjacent
5088/// half-precision (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`,
5089/// or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
5090///
5091/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fcmadd_sch)
5092#[inline]
5093#[target_feature(enable = "avx512fp16")]
5094#[cfg_attr(test, assert_instr(vfcmaddcsh))]
5095#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5096pub fn _mm_maskz_fcmadd_sch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
5097    _mm_maskz_fcmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(k, a, b, c)
5098}
5099
5100/// Multiply the lower complex number in a by the complex conjugate of the lower complex number in b,
5101/// accumulate to the lower complex number in c, and store the result in the lower elements of dst,
5102/// and copy the upper 6 packed elements from a to the upper elements of dst. Each complex number is
5103/// composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex
5104/// number `complex = vec.fp16[0] + i * vec.fp16[1]`, or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
5105///
5106/// Rounding is done according to the rounding parameter, which can be one of:
5107///
5108/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
5109/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
5110/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
5111/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
5112/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
5113///
5114/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fcmadd_round_sch)
5115#[inline]
5116#[target_feature(enable = "avx512fp16")]
5117#[cfg_attr(test, assert_instr(vfcmaddcsh, ROUNDING = 8))]
5118#[rustc_legacy_const_generics(3)]
5119#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5120pub fn _mm_fcmadd_round_sch<const ROUNDING: i32>(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
5121    unsafe {
5122        static_assert_rounding!(ROUNDING);
5123        transmute(vfcmaddcsh_mask(
5124            transmute(a),
5125            transmute(b),
5126            transmute(c),
5127            0xff,
5128            ROUNDING,
5129        ))
5130    }
5131}
5132
5133/// Multiply the lower complex number in a by the complex conjugate of the lower complex number in b,
5134/// accumulate to the lower complex number in c, and store the result in the lower elements of dst using
5135/// writemask k (the element is copied from a when the corresponding mask bit is not set), and copy the upper
5136/// 6 packed elements from a to the upper elements of dst. Each complex number is composed of two adjacent
5137/// half-precision (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`,
5138/// or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
5139///
5140/// Rounding is done according to the rounding parameter, which can be one of:
5141///
5142/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
5143/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
5144/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
5145/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
5146/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
5147///
5148/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fcmadd_round_sch)
5149#[inline]
5150#[target_feature(enable = "avx512fp16")]
5151#[cfg_attr(test, assert_instr(vfcmaddcsh, ROUNDING = 8))]
5152#[rustc_legacy_const_generics(4)]
5153#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5154pub fn _mm_mask_fcmadd_round_sch<const ROUNDING: i32>(
5155    a: __m128h,
5156    k: __mmask8,
5157    b: __m128h,
5158    c: __m128h,
5159) -> __m128h {
5160    unsafe {
5161        static_assert_rounding!(ROUNDING);
5162        let a = transmute(a);
5163        let r = vfcmaddcsh_mask(a, transmute(b), transmute(c), k, ROUNDING);
5164        transmute(_mm_mask_move_ss(a, k, a, r))
5165    }
5166}
5167
5168/// Multiply the lower complex number in a by the complex conjugate of the lower complex number in b,
5169/// accumulate to the lower complex number in c, and store the result in the lower elements of dst using
5170/// writemask k (the element is copied from c when the corresponding mask bit is not set), and copy the upper
5171/// 6 packed elements from a to the upper elements of dst. Each complex number is composed of two adjacent
5172/// half-precision (16-bit) floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1]`,
5173/// or the complex conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
5174///
5175/// Rounding is done according to the rounding parameter, which can be one of:
5176///
5177/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
5178/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
5179/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
5180/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
5181/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
5182///
5183/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fcmadd_round_sch)
5184#[inline]
5185#[target_feature(enable = "avx512fp16")]
5186#[cfg_attr(test, assert_instr(vfcmaddcsh, ROUNDING = 8))]
5187#[rustc_legacy_const_generics(4)]
5188#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5189pub fn _mm_mask3_fcmadd_round_sch<const ROUNDING: i32>(
5190    a: __m128h,
5191    b: __m128h,
5192    c: __m128h,
5193    k: __mmask8,
5194) -> __m128h {
5195    unsafe {
5196        static_assert_rounding!(ROUNDING);
5197        let c = transmute(c);
5198        let r = vfcmaddcsh_mask(transmute(a), transmute(b), c, k, ROUNDING);
5199        transmute(_mm_move_ss(c, r))
5200    }
5201}
5202
5203/// Multiply the lower complex number in a by the complex conjugate of the lower complex number in b,
5204/// accumulate to the lower complex number in c using zeromask k (the element is zeroed out when the corresponding
5205/// mask bit is not set), and store the result in the lower elements of dst, and copy the upper 6 packed elements
5206/// from a to the upper elements of dst. Each complex number is composed of two adjacent half-precision (16-bit)
5207/// floating-point elements, which defines the complex number `complex = vec.fp16[0] + i * vec.fp16[1`, or the complex
5208/// conjugate `conjugate = vec.fp16[0] - i * vec.fp16[1]`.
5209///
5210/// Rounding is done according to the rounding parameter, which can be one of:
5211///
5212/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
5213/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
5214/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
5215/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
5216/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
5217///
5218/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fcmadd_round_sch)
5219#[inline]
5220#[target_feature(enable = "avx512fp16")]
5221#[cfg_attr(test, assert_instr(vfcmaddcsh, ROUNDING = 8))]
5222#[rustc_legacy_const_generics(4)]
5223#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5224pub fn _mm_maskz_fcmadd_round_sch<const ROUNDING: i32>(
5225    k: __mmask8,
5226    a: __m128h,
5227    b: __m128h,
5228    c: __m128h,
5229) -> __m128h {
5230    unsafe {
5231        static_assert_rounding!(ROUNDING);
5232        transmute(vfcmaddcsh_maskz(
5233            transmute(a),
5234            transmute(b),
5235            transmute(c),
5236            k,
5237            ROUNDING,
5238        ))
5239    }
5240}
5241
5242/// Multiply packed half-precision (16-bit) floating-point elements in a and b, add the intermediate
5243/// result to packed elements in c, and store the results in dst.
5244///
5245/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fmadd_ph)
5246#[inline]
5247#[target_feature(enable = "avx512fp16,avx512vl")]
5248#[cfg_attr(test, assert_instr(vfmadd))]
5249#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5250#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
5251pub const fn _mm_fmadd_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
5252    unsafe { simd_fma(a, b, c) }
5253}
5254
5255/// Multiply packed half-precision (16-bit) floating-point elements in a and b, add the intermediate
5256/// result to packed elements in c, and store the results in dst using writemask k (the element is copied
5257/// from a when the corresponding mask bit is not set).
5258///
5259/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fmadd_ph)
5260#[inline]
5261#[target_feature(enable = "avx512fp16,avx512vl")]
5262#[cfg_attr(test, assert_instr(vfmadd))]
5263#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5264#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
5265pub const fn _mm_mask_fmadd_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
5266    unsafe { simd_select_bitmask(k, _mm_fmadd_ph(a, b, c), a) }
5267}
5268
5269/// Multiply packed half-precision (16-bit) floating-point elements in a and b, add the intermediate
5270/// result to packed elements in c, and store the results in dst using writemask k (the element is copied
5271/// from c when the corresponding mask bit is not set).
5272///
5273/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fmadd_ph)
5274#[inline]
5275#[target_feature(enable = "avx512fp16,avx512vl")]
5276#[cfg_attr(test, assert_instr(vfmadd))]
5277#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5278#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
5279pub const fn _mm_mask3_fmadd_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
5280    unsafe { simd_select_bitmask(k, _mm_fmadd_ph(a, b, c), c) }
5281}
5282
5283/// Multiply packed half-precision (16-bit) floating-point elements in a and b, add the intermediate
5284/// result to packed elements in c, and store the results in dst using zeromask k (the element is zeroed
5285/// out when the corresponding mask bit is not set).
5286///
5287/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fmadd_ph)
5288#[inline]
5289#[target_feature(enable = "avx512fp16,avx512vl")]
5290#[cfg_attr(test, assert_instr(vfmadd))]
5291#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5292#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
5293pub const fn _mm_maskz_fmadd_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
5294    unsafe { simd_select_bitmask(k, _mm_fmadd_ph(a, b, c), _mm_setzero_ph()) }
5295}
5296
5297/// Multiply packed half-precision (16-bit) floating-point elements in a and b, add the intermediate
5298/// result to packed elements in c, and store the results in dst.
5299///
5300/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_fmadd_ph)
5301#[inline]
5302#[target_feature(enable = "avx512fp16,avx512vl")]
5303#[cfg_attr(test, assert_instr(vfmadd))]
5304#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5305#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
5306pub const fn _mm256_fmadd_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
5307    unsafe { simd_fma(a, b, c) }
5308}
5309
5310/// Multiply packed half-precision (16-bit) floating-point elements in a and b, add the intermediate
5311/// result to packed elements in c, and store the results in dst using writemask k (the element is copied
5312/// from a when the corresponding mask bit is not set).
5313///
5314/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_fmadd_ph)
5315#[inline]
5316#[target_feature(enable = "avx512fp16,avx512vl")]
5317#[cfg_attr(test, assert_instr(vfmadd))]
5318#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5319#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
5320pub const fn _mm256_mask_fmadd_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h {
5321    unsafe { simd_select_bitmask(k, _mm256_fmadd_ph(a, b, c), a) }
5322}
5323
5324/// Multiply packed half-precision (16-bit) floating-point elements in a and b, add the intermediate
5325/// result to packed elements in c, and store the results in dst using writemask k (the element is copied
5326/// from c when the corresponding mask bit is not set).
5327///
5328/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask3_fmadd_ph)
5329#[inline]
5330#[target_feature(enable = "avx512fp16,avx512vl")]
5331#[cfg_attr(test, assert_instr(vfmadd))]
5332#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5333#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
5334pub const fn _mm256_mask3_fmadd_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h {
5335    unsafe { simd_select_bitmask(k, _mm256_fmadd_ph(a, b, c), c) }
5336}
5337
5338/// Multiply packed half-precision (16-bit) floating-point elements in a and b, add the intermediate
5339/// result to packed elements in c, and store the results in dst using zeromask k (the element is zeroed
5340/// out when the corresponding mask bit is not set).
5341///
5342/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_fmadd_ph)
5343#[inline]
5344#[target_feature(enable = "avx512fp16,avx512vl")]
5345#[cfg_attr(test, assert_instr(vfmadd))]
5346#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5347#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
5348pub const fn _mm256_maskz_fmadd_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h {
5349    unsafe { simd_select_bitmask(k, _mm256_fmadd_ph(a, b, c), _mm256_setzero_ph()) }
5350}
5351
5352/// Multiply packed half-precision (16-bit) floating-point elements in a and b, add the intermediate
5353/// result to packed elements in c, and store the results in dst.
5354///
5355/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fmadd_ph)
5356#[inline]
5357#[target_feature(enable = "avx512fp16")]
5358#[cfg_attr(test, assert_instr(vfmadd))]
5359#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5360#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
5361pub const fn _mm512_fmadd_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
5362    unsafe { simd_fma(a, b, c) }
5363}
5364
5365/// Multiply packed half-precision (16-bit) floating-point elements in a and b, add the intermediate
5366/// result to packed elements in c, and store the results in dst using writemask k (the element is copied
5367/// from a when the corresponding mask bit is not set).
5368///
5369/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fmadd_ph)
5370#[inline]
5371#[target_feature(enable = "avx512fp16")]
5372#[cfg_attr(test, assert_instr(vfmadd))]
5373#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5374#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
5375pub const fn _mm512_mask_fmadd_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h {
5376    unsafe { simd_select_bitmask(k, _mm512_fmadd_ph(a, b, c), a) }
5377}
5378
5379/// Multiply packed half-precision (16-bit) floating-point elements in a and b, add the intermediate
5380/// result to packed elements in c, and store the results in dst using writemask k (the element is copied
5381/// from c when the corresponding mask bit is not set).
5382///
5383/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fmadd_ph)
5384#[inline]
5385#[target_feature(enable = "avx512fp16")]
5386#[cfg_attr(test, assert_instr(vfmadd))]
5387#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5388#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
5389pub const fn _mm512_mask3_fmadd_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h {
5390    unsafe { simd_select_bitmask(k, _mm512_fmadd_ph(a, b, c), c) }
5391}
5392
5393/// Multiply packed half-precision (16-bit) floating-point elements in a and b, add the intermediate
5394/// result to packed elements in c, and store the results in dst using zeromask k (the element is zeroed
5395/// out when the corresponding mask bit is not set).
5396///
5397/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fmadd_ph)
5398#[inline]
5399#[target_feature(enable = "avx512fp16")]
5400#[cfg_attr(test, assert_instr(vfmadd))]
5401#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5402#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
5403pub const fn _mm512_maskz_fmadd_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h {
5404    unsafe { simd_select_bitmask(k, _mm512_fmadd_ph(a, b, c), _mm512_setzero_ph()) }
5405}
5406
5407/// Multiply packed half-precision (16-bit) floating-point elements in a and b, add the intermediate
5408/// result to packed elements in c, and store the results in dst.
5409///
5410/// Rounding is done according to the rounding parameter, which can be one of:
5411///
5412/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
5413/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
5414/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
5415/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
5416/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
5417///
5418/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fmadd_round_ph)
5419#[inline]
5420#[target_feature(enable = "avx512fp16")]
5421#[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))]
5422#[rustc_legacy_const_generics(3)]
5423#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5424pub fn _mm512_fmadd_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
5425    unsafe {
5426        static_assert_rounding!(ROUNDING);
5427        vfmaddph_512(a, b, c, ROUNDING)
5428    }
5429}
5430
5431/// Multiply packed half-precision (16-bit) floating-point elements in a and b, add the intermediate
5432/// result to packed elements in c, and store the results in dst using writemask k (the element is copied
5433/// from a when the corresponding mask bit is not set).
5434///
5435/// Rounding is done according to the rounding parameter, which can be one of:
5436///
5437/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
5438/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
5439/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
5440/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
5441/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
5442///
5443/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fmadd_round_ph)
5444#[inline]
5445#[target_feature(enable = "avx512fp16")]
5446#[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))]
5447#[rustc_legacy_const_generics(4)]
5448#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5449pub fn _mm512_mask_fmadd_round_ph<const ROUNDING: i32>(
5450    a: __m512h,
5451    k: __mmask32,
5452    b: __m512h,
5453    c: __m512h,
5454) -> __m512h {
5455    unsafe {
5456        static_assert_rounding!(ROUNDING);
5457        simd_select_bitmask(k, _mm512_fmadd_round_ph::<ROUNDING>(a, b, c), a)
5458    }
5459}
5460
5461/// Multiply packed half-precision (16-bit) floating-point elements in a and b, add the intermediate
5462/// result to packed elements in c, and store the results in dst using writemask k (the element is copied
5463/// from c when the corresponding mask bit is not set).
5464///
5465/// Rounding is done according to the rounding parameter, which can be one of:
5466///
5467/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
5468/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
5469/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
5470/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
5471/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
5472///
5473/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fmadd_round_ph)
5474#[inline]
5475#[target_feature(enable = "avx512fp16")]
5476#[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))]
5477#[rustc_legacy_const_generics(4)]
5478#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5479pub fn _mm512_mask3_fmadd_round_ph<const ROUNDING: i32>(
5480    a: __m512h,
5481    b: __m512h,
5482    c: __m512h,
5483    k: __mmask32,
5484) -> __m512h {
5485    unsafe {
5486        static_assert_rounding!(ROUNDING);
5487        simd_select_bitmask(k, _mm512_fmadd_round_ph::<ROUNDING>(a, b, c), c)
5488    }
5489}
5490
5491/// Multiply packed half-precision (16-bit) floating-point elements in a and b, add the intermediate
5492/// result to packed elements in c, and store the results in dst using zeromask k (the element is zeroed
5493/// out when the corresponding mask bit is not set).
5494///
5495/// Rounding is done according to the rounding parameter, which can be one of:
5496///
5497/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
5498/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
5499/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
5500/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
5501/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
5502///
5503/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fmadd_round_ph)
5504#[inline]
5505#[target_feature(enable = "avx512fp16")]
5506#[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))]
5507#[rustc_legacy_const_generics(4)]
5508#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5509pub fn _mm512_maskz_fmadd_round_ph<const ROUNDING: i32>(
5510    k: __mmask32,
5511    a: __m512h,
5512    b: __m512h,
5513    c: __m512h,
5514) -> __m512h {
5515    unsafe {
5516        static_assert_rounding!(ROUNDING);
5517        simd_select_bitmask(
5518            k,
5519            _mm512_fmadd_round_ph::<ROUNDING>(a, b, c),
5520            _mm512_setzero_ph(),
5521        )
5522    }
5523}
5524
5525/// Multiply the lower half-precision (16-bit) floating-point elements in a and b, and add the intermediate
5526/// result to the lower element in c. Store the result in the lower element of dst, and copy the upper
5527/// 7 packed elements from a to the upper elements of dst.
5528///
5529/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fmadd_sh)
5530#[inline]
5531#[target_feature(enable = "avx512fp16")]
5532#[cfg_attr(test, assert_instr(vfmadd))]
5533#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5534#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
5535pub const fn _mm_fmadd_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
5536    unsafe {
5537        let extracta: f16 = simd_extract!(a, 0);
5538        let extractb: f16 = simd_extract!(b, 0);
5539        let extractc: f16 = simd_extract!(c, 0);
5540        let r = fmaf16(extracta, extractb, extractc);
5541        simd_insert!(a, 0, r)
5542    }
5543}
5544
5545/// Multiply the lower half-precision (16-bit) floating-point elements in a and b, and add the intermediate
5546/// result to the lower element in c. Store the result in the lower element of dst using writemask k (the element
5547/// is copied from a when the mask bit 0 is not set), and copy the upper 7 packed elements from a to the
5548/// upper elements of dst.
5549///
5550/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fmadd_sh)
5551#[inline]
5552#[target_feature(enable = "avx512fp16")]
5553#[cfg_attr(test, assert_instr(vfmadd))]
5554#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5555#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
5556pub const fn _mm_mask_fmadd_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
5557    unsafe {
5558        let mut fmadd: f16 = simd_extract!(a, 0);
5559        if k & 1 != 0 {
5560            let extractb: f16 = simd_extract!(b, 0);
5561            let extractc: f16 = simd_extract!(c, 0);
5562            fmadd = fmaf16(fmadd, extractb, extractc);
5563        }
5564        simd_insert!(a, 0, fmadd)
5565    }
5566}
5567
5568/// Multiply the lower half-precision (16-bit) floating-point elements in a and b, and add the intermediate
5569/// result to the lower element in c. Store the result in the lower element of dst using writemask k (the element
5570/// is copied from c when the mask bit 0 is not set), and copy the upper 7 packed elements from c to the
5571/// upper elements of dst.
5572///
5573/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fmadd_sh)
5574#[inline]
5575#[target_feature(enable = "avx512fp16")]
5576#[cfg_attr(test, assert_instr(vfmadd))]
5577#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5578#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
5579pub const fn _mm_mask3_fmadd_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
5580    unsafe {
5581        let mut fmadd: f16 = simd_extract!(c, 0);
5582        if k & 1 != 0 {
5583            let extracta: f16 = simd_extract!(a, 0);
5584            let extractb: f16 = simd_extract!(b, 0);
5585            fmadd = fmaf16(extracta, extractb, fmadd);
5586        }
5587        simd_insert!(c, 0, fmadd)
5588    }
5589}
5590
5591/// Multiply the lower half-precision (16-bit) floating-point elements in a and b, and add the intermediate
5592/// result to the lower element in c. Store the result in the lower element of dst using zeromask k (the element
5593/// is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from a to the
5594/// upper elements of dst.
5595///
5596/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fmadd_sh)
5597#[inline]
5598#[target_feature(enable = "avx512fp16")]
5599#[cfg_attr(test, assert_instr(vfmadd))]
5600#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5601#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
5602pub const fn _mm_maskz_fmadd_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
5603    unsafe {
5604        let mut fmadd: f16 = 0.0;
5605        if k & 1 != 0 {
5606            let extracta: f16 = simd_extract!(a, 0);
5607            let extractb: f16 = simd_extract!(b, 0);
5608            let extractc: f16 = simd_extract!(c, 0);
5609            fmadd = fmaf16(extracta, extractb, extractc);
5610        }
5611        simd_insert!(a, 0, fmadd)
5612    }
5613}
5614
5615/// Multiply the lower half-precision (16-bit) floating-point elements in a and b, and add the intermediate
5616/// result to the lower element in c. Store the result in the lower element of dst, and copy the upper
5617/// 7 packed elements from a to the upper elements of dst.
5618///
5619/// Rounding is done according to the rounding parameter, which can be one of:
5620///
5621/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
5622/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
5623/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
5624/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
5625/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
5626///
5627/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fmadd_round_sh)
5628#[inline]
5629#[target_feature(enable = "avx512fp16")]
5630#[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))]
5631#[rustc_legacy_const_generics(3)]
5632#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5633pub fn _mm_fmadd_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
5634    unsafe {
5635        static_assert_rounding!(ROUNDING);
5636        let extracta: f16 = simd_extract!(a, 0);
5637        let extractb: f16 = simd_extract!(b, 0);
5638        let extractc: f16 = simd_extract!(c, 0);
5639        let r = vfmaddsh(extracta, extractb, extractc, ROUNDING);
5640        simd_insert!(a, 0, r)
5641    }
5642}
5643
5644/// Multiply the lower half-precision (16-bit) floating-point elements in a and b, and add the intermediate
5645/// result to the lower element in c. Store the result in the lower element of dst using writemask k (the element
5646/// is copied from a when the mask bit 0 is not set), and copy the upper 7 packed elements from a to the
5647/// upper elements of dst.
5648///
5649/// Rounding is done according to the rounding parameter, which can be one of:
5650///
5651/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
5652/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
5653/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
5654/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
5655/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
5656///
5657/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fmadd_round_sh)
5658#[inline]
5659#[target_feature(enable = "avx512fp16")]
5660#[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))]
5661#[rustc_legacy_const_generics(4)]
5662#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5663pub fn _mm_mask_fmadd_round_sh<const ROUNDING: i32>(
5664    a: __m128h,
5665    k: __mmask8,
5666    b: __m128h,
5667    c: __m128h,
5668) -> __m128h {
5669    unsafe {
5670        static_assert_rounding!(ROUNDING);
5671        let mut fmadd: f16 = simd_extract!(a, 0);
5672        if k & 1 != 0 {
5673            let extractb: f16 = simd_extract!(b, 0);
5674            let extractc: f16 = simd_extract!(c, 0);
5675            fmadd = vfmaddsh(fmadd, extractb, extractc, ROUNDING);
5676        }
5677        simd_insert!(a, 0, fmadd)
5678    }
5679}
5680
5681/// Multiply the lower half-precision (16-bit) floating-point elements in a and b, and add the intermediate
5682/// result to the lower element in c. Store the result in the lower element of dst using writemask k (the element
5683/// is copied from c when the mask bit 0 is not set), and copy the upper 7 packed elements from c to the
5684/// upper elements of dst.
5685///
5686/// Rounding is done according to the rounding parameter, which can be one of:
5687///
5688/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
5689/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
5690/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
5691/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
5692/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
5693///
5694/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fmadd_round_sh)
5695#[inline]
5696#[target_feature(enable = "avx512fp16")]
5697#[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))]
5698#[rustc_legacy_const_generics(4)]
5699#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5700pub fn _mm_mask3_fmadd_round_sh<const ROUNDING: i32>(
5701    a: __m128h,
5702    b: __m128h,
5703    c: __m128h,
5704    k: __mmask8,
5705) -> __m128h {
5706    unsafe {
5707        static_assert_rounding!(ROUNDING);
5708        let mut fmadd: f16 = simd_extract!(c, 0);
5709        if k & 1 != 0 {
5710            let extracta: f16 = simd_extract!(a, 0);
5711            let extractb: f16 = simd_extract!(b, 0);
5712            fmadd = vfmaddsh(extracta, extractb, fmadd, ROUNDING);
5713        }
5714        simd_insert!(c, 0, fmadd)
5715    }
5716}
5717
5718/// Multiply the lower half-precision (16-bit) floating-point elements in a and b, and add the intermediate
5719/// result to the lower element in c. Store the result in the lower element of dst using zeromask k (the element
5720/// is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from a to the
5721/// upper elements of dst.
5722///
5723/// Rounding is done according to the rounding parameter, which can be one of:
5724///
5725/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
5726/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
5727/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
5728/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
5729/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
5730///
5731/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fmadd_round_sh)
5732#[inline]
5733#[target_feature(enable = "avx512fp16")]
5734#[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))]
5735#[rustc_legacy_const_generics(4)]
5736#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5737pub fn _mm_maskz_fmadd_round_sh<const ROUNDING: i32>(
5738    k: __mmask8,
5739    a: __m128h,
5740    b: __m128h,
5741    c: __m128h,
5742) -> __m128h {
5743    unsafe {
5744        static_assert_rounding!(ROUNDING);
5745        let mut fmadd: f16 = 0.0;
5746        if k & 1 != 0 {
5747            let extracta: f16 = simd_extract!(a, 0);
5748            let extractb: f16 = simd_extract!(b, 0);
5749            let extractc: f16 = simd_extract!(c, 0);
5750            fmadd = vfmaddsh(extracta, extractb, extractc, ROUNDING);
5751        }
5752        simd_insert!(a, 0, fmadd)
5753    }
5754}
5755
5756/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract packed elements
5757/// in c from the intermediate result, and store the results in dst.
5758/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
5759///
5760/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fmsub_ph)
5761#[inline]
5762#[target_feature(enable = "avx512fp16,avx512vl")]
5763#[cfg_attr(test, assert_instr(vfmsub))]
5764#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5765#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
5766pub const fn _mm_fmsub_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
5767    unsafe { simd_fma(a, b, simd_neg(c)) }
5768}
5769
5770/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract packed elements
5771/// in c from the intermediate result, and store the results in dst using writemask k (the element is copied
5772/// from a when the corresponding mask bit is not set).
5773///
5774/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fmsub_ph)
5775#[inline]
5776#[target_feature(enable = "avx512fp16,avx512vl")]
5777#[cfg_attr(test, assert_instr(vfmsub))]
5778#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5779#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
5780pub const fn _mm_mask_fmsub_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
5781    unsafe { simd_select_bitmask(k, _mm_fmsub_ph(a, b, c), a) }
5782}
5783
5784/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract packed elements
5785/// in c from the intermediate result, and store the results in dst using writemask k (the element is copied
5786/// from c when the corresponding mask bit is not set).
5787///
5788/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fmsub_ph)
5789#[inline]
5790#[target_feature(enable = "avx512fp16,avx512vl")]
5791#[cfg_attr(test, assert_instr(vfmsub))]
5792#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5793#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
5794pub const fn _mm_mask3_fmsub_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
5795    unsafe { simd_select_bitmask(k, _mm_fmsub_ph(a, b, c), c) }
5796}
5797
5798/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract packed elements
5799/// in c from the intermediate result, and store the results in dst using zeromask k (the element is zeroed
5800/// out when the corresponding mask bit is not set).
5801///
5802/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fmsub_ph)
5803#[inline]
5804#[target_feature(enable = "avx512fp16,avx512vl")]
5805#[cfg_attr(test, assert_instr(vfmsub))]
5806#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5807#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
5808pub const fn _mm_maskz_fmsub_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
5809    unsafe { simd_select_bitmask(k, _mm_fmsub_ph(a, b, c), _mm_setzero_ph()) }
5810}
5811
5812/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract packed elements
5813/// in c from the intermediate result, and store the results in dst.
5814///
5815/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_fmsub_ph)
5816#[inline]
5817#[target_feature(enable = "avx512fp16,avx512vl")]
5818#[cfg_attr(test, assert_instr(vfmsub))]
5819#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5820#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
5821pub const fn _mm256_fmsub_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
5822    unsafe { simd_fma(a, b, simd_neg(c)) }
5823}
5824
5825/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract packed elements
5826/// in c from the intermediate result, and store the results in dst using writemask k (the element is copied
5827/// from a when the corresponding mask bit is not set).
5828///
5829/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_fmsub_ph)
5830#[inline]
5831#[target_feature(enable = "avx512fp16,avx512vl")]
5832#[cfg_attr(test, assert_instr(vfmsub))]
5833#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5834#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
5835pub const fn _mm256_mask_fmsub_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h {
5836    unsafe { simd_select_bitmask(k, _mm256_fmsub_ph(a, b, c), a) }
5837}
5838
5839/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract packed elements
5840/// in c from the intermediate result, and store the results in dst using writemask k (the element is copied
5841/// from c when the corresponding mask bit is not set).
5842///
5843/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask3_fmsub_ph)
5844#[inline]
5845#[target_feature(enable = "avx512fp16,avx512vl")]
5846#[cfg_attr(test, assert_instr(vfmsub))]
5847#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5848#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
5849pub const fn _mm256_mask3_fmsub_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h {
5850    unsafe { simd_select_bitmask(k, _mm256_fmsub_ph(a, b, c), c) }
5851}
5852
5853/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract packed elements
5854/// in c from the intermediate result, and store the results in dst using zeromask k (the element is zeroed
5855/// out when the corresponding mask bit is not set).
5856///
5857/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_fmsub_ph)
5858#[inline]
5859#[target_feature(enable = "avx512fp16,avx512vl")]
5860#[cfg_attr(test, assert_instr(vfmsub))]
5861#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5862#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
5863pub const fn _mm256_maskz_fmsub_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h {
5864    unsafe { simd_select_bitmask(k, _mm256_fmsub_ph(a, b, c), _mm256_setzero_ph()) }
5865}
5866
5867/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract packed elements
5868/// in c from the intermediate result, and store the results in dst.
5869///
5870/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fmsub_ph)
5871#[inline]
5872#[target_feature(enable = "avx512fp16")]
5873#[cfg_attr(test, assert_instr(vfmsub))]
5874#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5875#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
5876pub const fn _mm512_fmsub_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
5877    unsafe { simd_fma(a, b, simd_neg(c)) }
5878}
5879
5880/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract packed elements
5881/// in c from the intermediate result, and store the results in dst using writemask k (the element is copied
5882/// from a when the corresponding mask bit is not set).
5883///
5884/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fmsub_ph)
5885#[inline]
5886#[target_feature(enable = "avx512fp16")]
5887#[cfg_attr(test, assert_instr(vfmsub))]
5888#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5889#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
5890pub const fn _mm512_mask_fmsub_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h {
5891    unsafe { simd_select_bitmask(k, _mm512_fmsub_ph(a, b, c), a) }
5892}
5893
5894/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract packed elements
5895/// in c from the intermediate result, and store the results in dst using writemask k (the element is copied
5896/// from c when the corresponding mask bit is not set).
5897///
5898/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fmsub_ph)
5899#[inline]
5900#[target_feature(enable = "avx512fp16")]
5901#[cfg_attr(test, assert_instr(vfmsub))]
5902#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5903#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
5904pub const fn _mm512_mask3_fmsub_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h {
5905    unsafe { simd_select_bitmask(k, _mm512_fmsub_ph(a, b, c), c) }
5906}
5907
5908/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract packed elements
5909/// in c from the intermediate result, and store the results in dst using zeromask k (the element is zeroed
5910/// out when the corresponding mask bit is not set).
5911///
5912/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fmsub_ph)
5913#[inline]
5914#[target_feature(enable = "avx512fp16")]
5915#[cfg_attr(test, assert_instr(vfmsub))]
5916#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5917#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
5918pub const fn _mm512_maskz_fmsub_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h {
5919    unsafe { simd_select_bitmask(k, _mm512_fmsub_ph(a, b, c), _mm512_setzero_ph()) }
5920}
5921
5922/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract packed elements
5923/// in c from the intermediate result, and store the results in dst.
5924///
5925/// Rounding is done according to the rounding parameter, which can be one of:
5926///
5927/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
5928/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
5929/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
5930/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
5931/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
5932///
5933/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fmsub_round_ph)
5934#[inline]
5935#[target_feature(enable = "avx512fp16")]
5936#[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))]
5937#[rustc_legacy_const_generics(3)]
5938#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5939pub fn _mm512_fmsub_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
5940    unsafe {
5941        static_assert_rounding!(ROUNDING);
5942        vfmaddph_512(a, b, simd_neg(c), ROUNDING)
5943    }
5944}
5945
5946/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract packed elements
5947/// in c from the intermediate result, and store the results in dst using writemask k (the element is copied
5948/// from a when the corresponding mask bit is not set).
5949///
5950/// Rounding is done according to the rounding parameter, which can be one of:
5951///
5952/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
5953/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
5954/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
5955/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
5956/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
5957///
5958/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fmsub_round_ph)
5959#[inline]
5960#[target_feature(enable = "avx512fp16")]
5961#[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))]
5962#[rustc_legacy_const_generics(4)]
5963#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5964pub fn _mm512_mask_fmsub_round_ph<const ROUNDING: i32>(
5965    a: __m512h,
5966    k: __mmask32,
5967    b: __m512h,
5968    c: __m512h,
5969) -> __m512h {
5970    unsafe {
5971        static_assert_rounding!(ROUNDING);
5972        simd_select_bitmask(k, _mm512_fmsub_round_ph::<ROUNDING>(a, b, c), a)
5973    }
5974}
5975
5976/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract packed elements
5977/// in c from the intermediate result, and store the results in dst using writemask k (the element is copied
5978/// from c when the corresponding mask bit is not set).
5979///
5980/// Rounding is done according to the rounding parameter, which can be one of:
5981///
5982/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
5983/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
5984/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
5985/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
5986/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
5987///
5988/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fmsub_round_ph)
5989#[inline]
5990#[target_feature(enable = "avx512fp16")]
5991#[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))]
5992#[rustc_legacy_const_generics(4)]
5993#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
5994pub fn _mm512_mask3_fmsub_round_ph<const ROUNDING: i32>(
5995    a: __m512h,
5996    b: __m512h,
5997    c: __m512h,
5998    k: __mmask32,
5999) -> __m512h {
6000    unsafe {
6001        static_assert_rounding!(ROUNDING);
6002        simd_select_bitmask(k, _mm512_fmsub_round_ph::<ROUNDING>(a, b, c), c)
6003    }
6004}
6005
6006/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract packed elements
6007/// in c from the intermediate result, and store the results in dst using zeromask k (the element is zeroed
6008/// out when the corresponding mask bit is not set).
6009///
6010/// Rounding is done according to the rounding parameter, which can be one of:
6011///
6012/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
6013/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
6014/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
6015/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
6016/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
6017///
6018/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fmsub_round_ph)
6019#[inline]
6020#[target_feature(enable = "avx512fp16")]
6021#[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))]
6022#[rustc_legacy_const_generics(4)]
6023#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6024pub fn _mm512_maskz_fmsub_round_ph<const ROUNDING: i32>(
6025    k: __mmask32,
6026    a: __m512h,
6027    b: __m512h,
6028    c: __m512h,
6029) -> __m512h {
6030    unsafe {
6031        static_assert_rounding!(ROUNDING);
6032        simd_select_bitmask(
6033            k,
6034            _mm512_fmsub_round_ph::<ROUNDING>(a, b, c),
6035            _mm512_setzero_ph(),
6036        )
6037    }
6038}
6039
6040/// Multiply the lower half-precision (16-bit) floating-point elements in a and b, and subtract packed elements
6041/// in c from the intermediate result. Store the result in the lower element of dst, and copy the upper
6042/// 7 packed elements from a to the upper elements of dst.
6043///
6044/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fmsub_sh)
6045#[inline]
6046#[target_feature(enable = "avx512fp16")]
6047#[cfg_attr(test, assert_instr(vfmsub))]
6048#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6049#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
6050pub const fn _mm_fmsub_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
6051    unsafe {
6052        let extracta: f16 = simd_extract!(a, 0);
6053        let extractb: f16 = simd_extract!(b, 0);
6054        let extractc: f16 = simd_extract!(c, 0);
6055        let r = fmaf16(extracta, extractb, -extractc);
6056        simd_insert!(a, 0, r)
6057    }
6058}
6059
6060/// Multiply the lower half-precision (16-bit) floating-point elements in a and b, and subtract packed elements
6061/// in c from the intermediate result. Store the result in the lower element of dst using writemask k (the element
6062/// is copied from a when the mask bit 0 is not set), and copy the upper 7 packed elements from a to the
6063/// upper elements of dst.
6064///
6065/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fmsub_sh)
6066#[inline]
6067#[target_feature(enable = "avx512fp16")]
6068#[cfg_attr(test, assert_instr(vfmsub))]
6069#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6070#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
6071pub const fn _mm_mask_fmsub_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
6072    unsafe {
6073        let mut fmsub: f16 = simd_extract!(a, 0);
6074        if k & 1 != 0 {
6075            let extractb: f16 = simd_extract!(b, 0);
6076            let extractc: f16 = simd_extract!(c, 0);
6077            fmsub = fmaf16(fmsub, extractb, -extractc);
6078        }
6079        simd_insert!(a, 0, fmsub)
6080    }
6081}
6082
6083/// Multiply the lower half-precision (16-bit) floating-point elements in a and b, and subtract packed elements
6084/// in c from the intermediate result. Store the result in the lower element of dst using writemask k (the element
6085/// is copied from c when the mask bit 0 is not set), and copy the upper 7 packed elements from c to the
6086/// upper elements of dst.
6087///
6088/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fmsub_sh)
6089#[inline]
6090#[target_feature(enable = "avx512fp16")]
6091#[cfg_attr(test, assert_instr(vfmsub))]
6092#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6093#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
6094pub const fn _mm_mask3_fmsub_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
6095    unsafe {
6096        let mut fmsub: f16 = simd_extract!(c, 0);
6097        if k & 1 != 0 {
6098            let extracta: f16 = simd_extract!(a, 0);
6099            let extractb: f16 = simd_extract!(b, 0);
6100            fmsub = fmaf16(extracta, extractb, -fmsub);
6101        }
6102        simd_insert!(c, 0, fmsub)
6103    }
6104}
6105
6106/// Multiply the lower half-precision (16-bit) floating-point elements in a and b, and subtract packed elements
6107/// in c from the intermediate result. Store the result in the lower element of dst using zeromask k (the element
6108/// is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from a to the
6109/// upper elements of dst.
6110///
6111/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fmsub_sh)
6112#[inline]
6113#[target_feature(enable = "avx512fp16")]
6114#[cfg_attr(test, assert_instr(vfmsub))]
6115#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6116#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
6117pub const fn _mm_maskz_fmsub_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
6118    unsafe {
6119        let mut fmsub: f16 = 0.0;
6120        if k & 1 != 0 {
6121            let extracta: f16 = simd_extract!(a, 0);
6122            let extractb: f16 = simd_extract!(b, 0);
6123            let extractc: f16 = simd_extract!(c, 0);
6124            fmsub = fmaf16(extracta, extractb, -extractc);
6125        }
6126        simd_insert!(a, 0, fmsub)
6127    }
6128}
6129
6130/// Multiply the lower half-precision (16-bit) floating-point elements in a and b, and subtract packed elements
6131/// in c from the intermediate result. Store the result in the lower element of dst, and copy the upper
6132/// 7 packed elements from a to the upper elements of dst.
6133///
6134/// Rounding is done according to the rounding parameter, which can be one of:
6135///
6136/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
6137/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
6138/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
6139/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
6140/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
6141///
6142/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fmsub_round_sh)
6143#[inline]
6144#[target_feature(enable = "avx512fp16")]
6145#[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))]
6146#[rustc_legacy_const_generics(3)]
6147#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6148pub fn _mm_fmsub_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
6149    unsafe {
6150        static_assert_rounding!(ROUNDING);
6151        let extracta: f16 = simd_extract!(a, 0);
6152        let extractb: f16 = simd_extract!(b, 0);
6153        let extractc: f16 = simd_extract!(c, 0);
6154        let r = vfmaddsh(extracta, extractb, -extractc, ROUNDING);
6155        simd_insert!(a, 0, r)
6156    }
6157}
6158
6159/// Multiply the lower half-precision (16-bit) floating-point elements in a and b, and subtract packed elements
6160/// in c from the intermediate result. Store the result in the lower element of dst using writemask k (the element
6161/// is copied from a when the mask bit 0 is not set), and copy the upper 7 packed elements from a to the
6162/// upper elements of dst.
6163///
6164/// Rounding is done according to the rounding parameter, which can be one of:
6165///
6166/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
6167/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
6168/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
6169/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
6170/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
6171///
6172/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fmsub_round_sh)
6173#[inline]
6174#[target_feature(enable = "avx512fp16")]
6175#[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))]
6176#[rustc_legacy_const_generics(4)]
6177#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6178pub fn _mm_mask_fmsub_round_sh<const ROUNDING: i32>(
6179    a: __m128h,
6180    k: __mmask8,
6181    b: __m128h,
6182    c: __m128h,
6183) -> __m128h {
6184    unsafe {
6185        static_assert_rounding!(ROUNDING);
6186        let mut fmsub: f16 = simd_extract!(a, 0);
6187        if k & 1 != 0 {
6188            let extractb: f16 = simd_extract!(b, 0);
6189            let extractc: f16 = simd_extract!(c, 0);
6190            fmsub = vfmaddsh(fmsub, extractb, -extractc, ROUNDING);
6191        }
6192        simd_insert!(a, 0, fmsub)
6193    }
6194}
6195
6196/// Multiply the lower half-precision (16-bit) floating-point elements in a and b, and subtract packed elements
6197/// in c from the intermediate result. Store the result in the lower element of dst using writemask k (the element
6198/// is copied from c when the mask bit 0 is not set), and copy the upper 7 packed elements from c to the
6199/// upper elements of dst.
6200///
6201/// Rounding is done according to the rounding parameter, which can be one of:
6202///
6203/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
6204/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
6205/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
6206/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
6207/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
6208///
6209/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fmsub_round_sh)
6210#[inline]
6211#[target_feature(enable = "avx512fp16")]
6212#[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))]
6213#[rustc_legacy_const_generics(4)]
6214#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6215pub fn _mm_mask3_fmsub_round_sh<const ROUNDING: i32>(
6216    a: __m128h,
6217    b: __m128h,
6218    c: __m128h,
6219    k: __mmask8,
6220) -> __m128h {
6221    unsafe {
6222        static_assert_rounding!(ROUNDING);
6223        let mut fmsub: f16 = simd_extract!(c, 0);
6224        if k & 1 != 0 {
6225            let extracta: f16 = simd_extract!(a, 0);
6226            let extractb: f16 = simd_extract!(b, 0);
6227            fmsub = vfmaddsh(extracta, extractb, -fmsub, ROUNDING);
6228        }
6229        simd_insert!(c, 0, fmsub)
6230    }
6231}
6232
6233/// Multiply the lower half-precision (16-bit) floating-point elements in a and b, and subtract packed elements
6234/// in c from the intermediate result. Store the result in the lower element of dst using zeromask k (the element
6235/// is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from a to the
6236/// upper elements of dst.
6237///
6238/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fmsub_round_sh)
6239#[inline]
6240#[target_feature(enable = "avx512fp16")]
6241#[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))]
6242#[rustc_legacy_const_generics(4)]
6243#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6244pub fn _mm_maskz_fmsub_round_sh<const ROUNDING: i32>(
6245    k: __mmask8,
6246    a: __m128h,
6247    b: __m128h,
6248    c: __m128h,
6249) -> __m128h {
6250    unsafe {
6251        static_assert_rounding!(ROUNDING);
6252        let mut fmsub: f16 = 0.0;
6253        if k & 1 != 0 {
6254            let extracta: f16 = simd_extract!(a, 0);
6255            let extractb: f16 = simd_extract!(b, 0);
6256            let extractc: f16 = simd_extract!(c, 0);
6257            fmsub = vfmaddsh(extracta, extractb, -extractc, ROUNDING);
6258        }
6259        simd_insert!(a, 0, fmsub)
6260    }
6261}
6262
6263/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract the intermediate
6264/// result from packed elements in c, and store the results in dst.
6265///
6266/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fnmadd_ph)
6267#[inline]
6268#[target_feature(enable = "avx512fp16,avx512vl")]
6269#[cfg_attr(test, assert_instr(vfnmadd))]
6270#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6271#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
6272pub const fn _mm_fnmadd_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
6273    unsafe { simd_fma(simd_neg(a), b, c) }
6274}
6275
6276/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract the intermediate
6277/// result from packed elements in c, and store the results in dst using writemask k (the element is copied
6278/// from a when the corresponding mask bit is not set).
6279///
6280/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fnmadd_ph)
6281#[inline]
6282#[target_feature(enable = "avx512fp16,avx512vl")]
6283#[cfg_attr(test, assert_instr(vfnmadd))]
6284#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6285#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
6286pub const fn _mm_mask_fnmadd_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
6287    unsafe { simd_select_bitmask(k, _mm_fnmadd_ph(a, b, c), a) }
6288}
6289
6290/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract the intermediate
6291/// result from packed elements in c, and store the results in dst using writemask k (the element is copied
6292/// from c when the corresponding mask bit is not set).
6293///
6294/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fnmadd_ph)
6295#[inline]
6296#[target_feature(enable = "avx512fp16,avx512vl")]
6297#[cfg_attr(test, assert_instr(vfnmadd))]
6298#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6299#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
6300pub const fn _mm_mask3_fnmadd_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
6301    unsafe { simd_select_bitmask(k, _mm_fnmadd_ph(a, b, c), c) }
6302}
6303
6304/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract the intermediate
6305/// result from packed elements in c, and store the results in dst using zeromask k (the element is zeroed
6306/// out when the corresponding mask bit is not set).
6307///
6308/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fnmadd_ph)
6309#[inline]
6310#[target_feature(enable = "avx512fp16,avx512vl")]
6311#[cfg_attr(test, assert_instr(vfnmadd))]
6312#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6313#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
6314pub const fn _mm_maskz_fnmadd_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
6315    unsafe { simd_select_bitmask(k, _mm_fnmadd_ph(a, b, c), _mm_setzero_ph()) }
6316}
6317
6318/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract the intermediate
6319/// result from packed elements in c, and store the results in dst.
6320///
6321/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_fnmadd_ph)
6322#[inline]
6323#[target_feature(enable = "avx512fp16,avx512vl")]
6324#[cfg_attr(test, assert_instr(vfnmadd))]
6325#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6326#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
6327pub const fn _mm256_fnmadd_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
6328    unsafe { simd_fma(simd_neg(a), b, c) }
6329}
6330
6331/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract the intermediate
6332/// result from packed elements in c, and store the results in dst using writemask k (the element is copied
6333/// from a when the corresponding mask bit is not set).
6334///
6335/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_fnmadd_ph)
6336#[inline]
6337#[target_feature(enable = "avx512fp16,avx512vl")]
6338#[cfg_attr(test, assert_instr(vfnmadd))]
6339#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6340#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
6341pub const fn _mm256_mask_fnmadd_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h {
6342    unsafe { simd_select_bitmask(k, _mm256_fnmadd_ph(a, b, c), a) }
6343}
6344
6345/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract the intermediate
6346/// result from packed elements in c, and store the results in dst using writemask k (the element is copied
6347/// from c when the corresponding mask bit is not set).
6348///
6349/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask3_fnmadd_ph)
6350#[inline]
6351#[target_feature(enable = "avx512fp16,avx512vl")]
6352#[cfg_attr(test, assert_instr(vfnmadd))]
6353#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6354#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
6355pub const fn _mm256_mask3_fnmadd_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h {
6356    unsafe { simd_select_bitmask(k, _mm256_fnmadd_ph(a, b, c), c) }
6357}
6358
6359/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract the intermediate
6360/// result from packed elements in c, and store the results in dst using zeromask k (the element is zeroed
6361/// out when the corresponding mask bit is not set).
6362///
6363/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_fnmadd_ph)
6364#[inline]
6365#[target_feature(enable = "avx512fp16,avx512vl")]
6366#[cfg_attr(test, assert_instr(vfnmadd))]
6367#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6368#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
6369pub const fn _mm256_maskz_fnmadd_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h {
6370    unsafe { simd_select_bitmask(k, _mm256_fnmadd_ph(a, b, c), _mm256_setzero_ph()) }
6371}
6372
6373/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract the intermediate
6374/// result from packed elements in c, and store the results in dst.
6375///
6376/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fnmadd_ph)
6377#[inline]
6378#[target_feature(enable = "avx512fp16")]
6379#[cfg_attr(test, assert_instr(vfnmadd))]
6380#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6381#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
6382pub const fn _mm512_fnmadd_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
6383    unsafe { simd_fma(simd_neg(a), b, c) }
6384}
6385
6386/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract the intermediate
6387/// result from packed elements in c, and store the results in dst using writemask k (the element is copied
6388/// from a when the corresponding mask bit is not set).
6389///
6390/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fnmadd_ph)
6391#[inline]
6392#[target_feature(enable = "avx512fp16")]
6393#[cfg_attr(test, assert_instr(vfnmadd))]
6394#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6395#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
6396pub const fn _mm512_mask_fnmadd_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h {
6397    unsafe { simd_select_bitmask(k, _mm512_fnmadd_ph(a, b, c), a) }
6398}
6399
6400/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract the intermediate
6401/// result from packed elements in c, and store the results in dst using writemask k (the element is copied
6402/// from c when the corresponding mask bit is not set).
6403///
6404/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fnmadd_ph)
6405#[inline]
6406#[target_feature(enable = "avx512fp16")]
6407#[cfg_attr(test, assert_instr(vfnmadd))]
6408#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6409#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
6410pub const fn _mm512_mask3_fnmadd_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h {
6411    unsafe { simd_select_bitmask(k, _mm512_fnmadd_ph(a, b, c), c) }
6412}
6413
6414/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract the intermediate
6415/// result from packed elements in c, and store the results in dst using zeromask k (the element is zeroed
6416/// out when the corresponding mask bit is not set).
6417///
6418/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fnmadd_ph)
6419#[inline]
6420#[target_feature(enable = "avx512fp16")]
6421#[cfg_attr(test, assert_instr(vfnmadd))]
6422#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6423#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
6424pub const fn _mm512_maskz_fnmadd_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h {
6425    unsafe { simd_select_bitmask(k, _mm512_fnmadd_ph(a, b, c), _mm512_setzero_ph()) }
6426}
6427
6428/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract the intermediate
6429/// result from packed elements in c, and store the results in dst.
6430///
6431/// Rounding is done according to the rounding parameter, which can be one of:
6432///
6433/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
6434/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
6435/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
6436/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
6437/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
6438///
6439/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fnmadd_round_ph)
6440#[inline]
6441#[target_feature(enable = "avx512fp16")]
6442#[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))]
6443#[rustc_legacy_const_generics(3)]
6444#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6445pub fn _mm512_fnmadd_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
6446    unsafe {
6447        static_assert_rounding!(ROUNDING);
6448        vfmaddph_512(simd_neg(a), b, c, ROUNDING)
6449    }
6450}
6451
6452/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract the intermediate
6453/// result from packed elements in c, and store the results in dst using writemask k (the element is copied
6454/// from a when the corresponding mask bit is not set).
6455///
6456/// Rounding is done according to the rounding parameter, which can be one of:
6457///
6458/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
6459/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
6460/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
6461/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
6462/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
6463///
6464/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fnmadd_round_ph)
6465#[inline]
6466#[target_feature(enable = "avx512fp16")]
6467#[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))]
6468#[rustc_legacy_const_generics(4)]
6469#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6470pub fn _mm512_mask_fnmadd_round_ph<const ROUNDING: i32>(
6471    a: __m512h,
6472    k: __mmask32,
6473    b: __m512h,
6474    c: __m512h,
6475) -> __m512h {
6476    unsafe {
6477        static_assert_rounding!(ROUNDING);
6478        simd_select_bitmask(k, _mm512_fnmadd_round_ph::<ROUNDING>(a, b, c), a)
6479    }
6480}
6481
6482/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract the intermediate
6483/// result from packed elements in c, and store the results in dst using writemask k (the element is copied
6484/// from c when the corresponding mask bit is not set).
6485///
6486/// Rounding is done according to the rounding parameter, which can be one of:
6487///
6488/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
6489/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
6490/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
6491/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
6492/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
6493///
6494/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fnmadd_round_ph)
6495#[inline]
6496#[target_feature(enable = "avx512fp16")]
6497#[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))]
6498#[rustc_legacy_const_generics(4)]
6499#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6500pub fn _mm512_mask3_fnmadd_round_ph<const ROUNDING: i32>(
6501    a: __m512h,
6502    b: __m512h,
6503    c: __m512h,
6504    k: __mmask32,
6505) -> __m512h {
6506    unsafe {
6507        static_assert_rounding!(ROUNDING);
6508        simd_select_bitmask(k, _mm512_fnmadd_round_ph::<ROUNDING>(a, b, c), c)
6509    }
6510}
6511
6512/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract the intermediate
6513/// result from packed elements in c, and store the results in dst using zeromask k (the element is zeroed
6514/// out when the corresponding mask bit is not set).
6515///
6516/// Rounding is done according to the rounding parameter, which can be one of:
6517///
6518/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
6519/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
6520/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
6521/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
6522/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
6523///
6524/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fnmadd_round_ph)
6525#[inline]
6526#[target_feature(enable = "avx512fp16")]
6527#[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))]
6528#[rustc_legacy_const_generics(4)]
6529#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6530pub fn _mm512_maskz_fnmadd_round_ph<const ROUNDING: i32>(
6531    k: __mmask32,
6532    a: __m512h,
6533    b: __m512h,
6534    c: __m512h,
6535) -> __m512h {
6536    unsafe {
6537        static_assert_rounding!(ROUNDING);
6538        simd_select_bitmask(
6539            k,
6540            _mm512_fnmadd_round_ph::<ROUNDING>(a, b, c),
6541            _mm512_setzero_ph(),
6542        )
6543    }
6544}
6545
6546/// Multiply the lower half-precision (16-bit) floating-point elements in a and b, and subtract the intermediate
6547/// result from the lower element in c. Store the result in the lower element of dst, and copy the upper 7 packed
6548/// elements from a to the upper elements of dst.
6549///
6550/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fnmadd_sh)
6551#[inline]
6552#[target_feature(enable = "avx512fp16")]
6553#[cfg_attr(test, assert_instr(vfnmadd))]
6554#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6555#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
6556pub const fn _mm_fnmadd_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
6557    unsafe {
6558        let extracta: f16 = simd_extract!(a, 0);
6559        let extractb: f16 = simd_extract!(b, 0);
6560        let extractc: f16 = simd_extract!(c, 0);
6561        let r = fmaf16(-extracta, extractb, extractc);
6562        simd_insert!(a, 0, r)
6563    }
6564}
6565
6566/// Multiply the lower half-precision (16-bit) floating-point elements in a and b, and subtract the intermediate
6567/// result from the lower element in c. Store the result in the lower element of dst using writemask k (the element
6568/// is copied from a when the mask bit 0 is not set), and copy the upper 7 packed elements from a to the upper
6569/// elements of dst.
6570///
6571/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fnmadd_sh)
6572#[inline]
6573#[target_feature(enable = "avx512fp16")]
6574#[cfg_attr(test, assert_instr(vfnmadd))]
6575#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6576#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
6577pub const fn _mm_mask_fnmadd_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
6578    unsafe {
6579        let mut fnmadd: f16 = simd_extract!(a, 0);
6580        if k & 1 != 0 {
6581            let extractb: f16 = simd_extract!(b, 0);
6582            let extractc: f16 = simd_extract!(c, 0);
6583            fnmadd = fmaf16(-fnmadd, extractb, extractc);
6584        }
6585        simd_insert!(a, 0, fnmadd)
6586    }
6587}
6588
6589/// Multiply the lower half-precision (16-bit) floating-point elements in a and b, and subtract the intermediate
6590/// result from the lower element in c. Store the result in the lower element of dst using writemask k (the element
6591/// is copied from c when the mask bit 0 is not set), and copy the upper 7 packed elements from c to the upper
6592/// elements of dst.
6593///
6594/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fnmadd_sh)
6595#[inline]
6596#[target_feature(enable = "avx512fp16")]
6597#[cfg_attr(test, assert_instr(vfnmadd))]
6598#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6599#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
6600pub const fn _mm_mask3_fnmadd_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
6601    unsafe {
6602        let mut fnmadd: f16 = simd_extract!(c, 0);
6603        if k & 1 != 0 {
6604            let extracta: f16 = simd_extract!(a, 0);
6605            let extractb: f16 = simd_extract!(b, 0);
6606            fnmadd = fmaf16(-extracta, extractb, fnmadd);
6607        }
6608        simd_insert!(c, 0, fnmadd)
6609    }
6610}
6611
6612/// Multiply the lower half-precision (16-bit) floating-point elements in a and b, and subtract the intermediate
6613/// result from the lower element in c. Store the result in the lower element of dst using zeromask k (the element
6614/// is zeroed out when the mask bit 0 is not set), and copy the upper 7 packed elements from a to the upper
6615/// elements of dst.
6616///
6617/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fnmadd_sh)
6618#[inline]
6619#[target_feature(enable = "avx512fp16")]
6620#[cfg_attr(test, assert_instr(vfnmadd))]
6621#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6622#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
6623pub const fn _mm_maskz_fnmadd_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
6624    unsafe {
6625        let mut fnmadd: f16 = 0.0;
6626        if k & 1 != 0 {
6627            let extracta: f16 = simd_extract!(a, 0);
6628            let extractb: f16 = simd_extract!(b, 0);
6629            let extractc: f16 = simd_extract!(c, 0);
6630            fnmadd = fmaf16(-extracta, extractb, extractc);
6631        }
6632        simd_insert!(a, 0, fnmadd)
6633    }
6634}
6635
6636/// Multiply the lower half-precision (16-bit) floating-point elements in a and b, and subtract the intermediate
6637/// result from the lower element in c. Store the result in the lower element of dst, and copy the upper 7 packed
6638/// elements from a to the upper elements of dst.
6639///
6640/// Rounding is done according to the rounding parameter, which can be one of:
6641///
6642/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
6643/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
6644/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
6645/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
6646/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
6647///
6648/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fnmadd_round_sh)
6649#[inline]
6650#[target_feature(enable = "avx512fp16")]
6651#[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))]
6652#[rustc_legacy_const_generics(3)]
6653#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6654pub fn _mm_fnmadd_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
6655    unsafe {
6656        static_assert_rounding!(ROUNDING);
6657        let extracta: f16 = simd_extract!(a, 0);
6658        let extractb: f16 = simd_extract!(b, 0);
6659        let extractc: f16 = simd_extract!(c, 0);
6660        let r = vfmaddsh(-extracta, extractb, extractc, ROUNDING);
6661        simd_insert!(a, 0, r)
6662    }
6663}
6664
6665/// Multiply the lower half-precision (16-bit) floating-point elements in a and b, and subtract the intermediate
6666/// result from the lower element in c. Store the result in the lower element of dst using writemask k (the element
6667/// is copied from a when the mask bit 0 is not set), and copy the upper 7 packed elements from a to the upper
6668/// elements of dst.
6669///
6670/// Rounding is done according to the rounding parameter, which can be one of:
6671///
6672/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
6673/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
6674/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
6675/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
6676/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
6677///
6678/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fnmadd_round_sh)
6679#[inline]
6680#[target_feature(enable = "avx512fp16")]
6681#[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))]
6682#[rustc_legacy_const_generics(4)]
6683#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6684pub fn _mm_mask_fnmadd_round_sh<const ROUNDING: i32>(
6685    a: __m128h,
6686    k: __mmask8,
6687    b: __m128h,
6688    c: __m128h,
6689) -> __m128h {
6690    unsafe {
6691        static_assert_rounding!(ROUNDING);
6692        let mut fnmadd: f16 = simd_extract!(a, 0);
6693        if k & 1 != 0 {
6694            let extractb: f16 = simd_extract!(b, 0);
6695            let extractc: f16 = simd_extract!(c, 0);
6696            fnmadd = vfmaddsh(-fnmadd, extractb, extractc, ROUNDING);
6697        }
6698        simd_insert!(a, 0, fnmadd)
6699    }
6700}
6701
6702/// Multiply the lower half-precision (16-bit) floating-point elements in a and b, and subtract the intermediate
6703/// result from the lower element in c. Store the result in the lower element of dst using writemask k (the element
6704/// is copied from c when the mask bit 0 is not set), and copy the upper 7 packed elements from c to the upper
6705/// elements of dst.
6706///
6707/// Rounding is done according to the rounding parameter, which can be one of:
6708///
6709/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
6710/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
6711/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
6712/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
6713/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
6714///
6715/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fnmadd_round_sh)
6716#[inline]
6717#[target_feature(enable = "avx512fp16")]
6718#[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))]
6719#[rustc_legacy_const_generics(4)]
6720#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6721pub fn _mm_mask3_fnmadd_round_sh<const ROUNDING: i32>(
6722    a: __m128h,
6723    b: __m128h,
6724    c: __m128h,
6725    k: __mmask8,
6726) -> __m128h {
6727    unsafe {
6728        static_assert_rounding!(ROUNDING);
6729        let mut fnmadd: f16 = simd_extract!(c, 0);
6730        if k & 1 != 0 {
6731            let extracta: f16 = simd_extract!(a, 0);
6732            let extractb: f16 = simd_extract!(b, 0);
6733            fnmadd = vfmaddsh(-extracta, extractb, fnmadd, ROUNDING);
6734        }
6735        simd_insert!(c, 0, fnmadd)
6736    }
6737}
6738
6739/// Multiply the lower half-precision (16-bit) floating-point elements in a and b, and subtract the intermediate
6740/// result from the lower element in c. Store the result in the lower element of dst using zeromask k (the element
6741/// is zeroed out when the mask bit 0 is not set), and copy the upper 7 packed elements from a to the upper
6742/// elements of dst.
6743///
6744/// Rounding is done according to the rounding parameter, which can be one of:
6745///
6746/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
6747/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
6748/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
6749/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
6750/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
6751///
6752/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fnmadd_round_sh)
6753#[inline]
6754#[target_feature(enable = "avx512fp16")]
6755#[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))]
6756#[rustc_legacy_const_generics(4)]
6757#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6758pub fn _mm_maskz_fnmadd_round_sh<const ROUNDING: i32>(
6759    k: __mmask8,
6760    a: __m128h,
6761    b: __m128h,
6762    c: __m128h,
6763) -> __m128h {
6764    unsafe {
6765        static_assert_rounding!(ROUNDING);
6766        let mut fnmadd: f16 = 0.0;
6767        if k & 1 != 0 {
6768            let extracta: f16 = simd_extract!(a, 0);
6769            let extractb: f16 = simd_extract!(b, 0);
6770            let extractc: f16 = simd_extract!(c, 0);
6771            fnmadd = vfmaddsh(-extracta, extractb, extractc, ROUNDING);
6772        }
6773        simd_insert!(a, 0, fnmadd)
6774    }
6775}
6776
6777/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract packed elements
6778/// in c from the negated intermediate result, and store the results in dst.
6779///
6780/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fnmsub_ph)
6781#[inline]
6782#[target_feature(enable = "avx512fp16,avx512vl")]
6783#[cfg_attr(test, assert_instr(vfnmsub))]
6784#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6785#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
6786pub const fn _mm_fnmsub_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
6787    unsafe { simd_fma(simd_neg(a), b, simd_neg(c)) }
6788}
6789
6790/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract packed elements
6791/// in c from the negated intermediate result, and store the results in dst using writemask k (the element is
6792/// copied from a when the corresponding mask bit is not set).
6793///
6794/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fnmsub_ph)
6795#[inline]
6796#[target_feature(enable = "avx512fp16,avx512vl")]
6797#[cfg_attr(test, assert_instr(vfnmsub))]
6798#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6799#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
6800pub const fn _mm_mask_fnmsub_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
6801    unsafe { simd_select_bitmask(k, _mm_fnmsub_ph(a, b, c), a) }
6802}
6803
6804/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract packed elements
6805/// in c from the negated intermediate result, and store the results in dst using writemask k (the element is
6806/// copied from c when the corresponding mask bit is not set).
6807///
6808/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fnmsub_ph)
6809#[inline]
6810#[target_feature(enable = "avx512fp16,avx512vl")]
6811#[cfg_attr(test, assert_instr(vfnmsub))]
6812#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6813#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
6814pub const fn _mm_mask3_fnmsub_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
6815    unsafe { simd_select_bitmask(k, _mm_fnmsub_ph(a, b, c), c) }
6816}
6817
6818/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract packed elements
6819/// in c from the negated intermediate result, and store the results in dst using zeromask k (the element is
6820/// zeroed out when the corresponding mask bit is not set).
6821///
6822/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fnmsub_ph)
6823#[inline]
6824#[target_feature(enable = "avx512fp16,avx512vl")]
6825#[cfg_attr(test, assert_instr(vfnmsub))]
6826#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6827#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
6828pub const fn _mm_maskz_fnmsub_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
6829    unsafe { simd_select_bitmask(k, _mm_fnmsub_ph(a, b, c), _mm_setzero_ph()) }
6830}
6831
6832/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract packed elements
6833/// in c from the negated intermediate result, and store the results in dst.
6834///
6835/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_fnmsub_ph)
6836#[inline]
6837#[target_feature(enable = "avx512fp16,avx512vl")]
6838#[cfg_attr(test, assert_instr(vfnmsub))]
6839#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6840#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
6841pub const fn _mm256_fnmsub_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
6842    unsafe { simd_fma(simd_neg(a), b, simd_neg(c)) }
6843}
6844
6845/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract packed elements
6846/// in c from the negated intermediate result, and store the results in dst using writemask k (the element is
6847/// copied from a when the corresponding mask bit is not set).
6848///
6849/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_fnmsub_ph)
6850#[inline]
6851#[target_feature(enable = "avx512fp16,avx512vl")]
6852#[cfg_attr(test, assert_instr(vfnmsub))]
6853#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6854#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
6855pub const fn _mm256_mask_fnmsub_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h {
6856    unsafe { simd_select_bitmask(k, _mm256_fnmsub_ph(a, b, c), a) }
6857}
6858
6859/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract packed elements
6860/// in c from the negated intermediate result, and store the results in dst using writemask k (the element is
6861/// copied from c when the corresponding mask bit is not set).
6862///
6863/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask3_fnmsub_ph)
6864#[inline]
6865#[target_feature(enable = "avx512fp16,avx512vl")]
6866#[cfg_attr(test, assert_instr(vfnmsub))]
6867#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6868#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
6869pub const fn _mm256_mask3_fnmsub_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h {
6870    unsafe { simd_select_bitmask(k, _mm256_fnmsub_ph(a, b, c), c) }
6871}
6872
6873/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract packed elements
6874/// in c from the negated intermediate result, and store the results in dst using zeromask k (the element is
6875/// zeroed out when the corresponding mask bit is not set).
6876///
6877/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_fnmsub_ph)
6878#[inline]
6879#[target_feature(enable = "avx512fp16,avx512vl")]
6880#[cfg_attr(test, assert_instr(vfnmsub))]
6881#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6882#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
6883pub const fn _mm256_maskz_fnmsub_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h {
6884    unsafe { simd_select_bitmask(k, _mm256_fnmsub_ph(a, b, c), _mm256_setzero_ph()) }
6885}
6886
6887/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract packed elements
6888/// in c from the negated intermediate result, and store the results in dst.
6889///
6890/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fnmsub_ph)
6891#[inline]
6892#[target_feature(enable = "avx512fp16")]
6893#[cfg_attr(test, assert_instr(vfnmsub))]
6894#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6895#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
6896pub const fn _mm512_fnmsub_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
6897    unsafe { simd_fma(simd_neg(a), b, simd_neg(c)) }
6898}
6899
6900/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract packed elements
6901/// in c from the negated intermediate result, and store the results in dst using writemask k (the element is
6902/// copied from a when the corresponding mask bit is not set).
6903///
6904/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fnmsub_ph)
6905#[inline]
6906#[target_feature(enable = "avx512fp16")]
6907#[cfg_attr(test, assert_instr(vfnmsub))]
6908#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6909#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
6910pub const fn _mm512_mask_fnmsub_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h {
6911    unsafe { simd_select_bitmask(k, _mm512_fnmsub_ph(a, b, c), a) }
6912}
6913
6914/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract packed elements
6915/// in c from the negated intermediate result, and store the results in dst using writemask k (the element is
6916/// copied from c when the corresponding mask bit is not set).
6917///
6918/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fnmsub_ph)
6919#[inline]
6920#[target_feature(enable = "avx512fp16")]
6921#[cfg_attr(test, assert_instr(vfnmsub))]
6922#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6923#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
6924pub const fn _mm512_mask3_fnmsub_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h {
6925    unsafe { simd_select_bitmask(k, _mm512_fnmsub_ph(a, b, c), c) }
6926}
6927
6928/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract packed elements
6929/// in c from the negated intermediate result, and store the results in dst using zeromask k (the element is
6930/// zeroed out when the corresponding mask bit is not set).
6931///
6932/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fnmsub_ph)
6933#[inline]
6934#[target_feature(enable = "avx512fp16")]
6935#[cfg_attr(test, assert_instr(vfnmsub))]
6936#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6937#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
6938pub const fn _mm512_maskz_fnmsub_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h {
6939    unsafe { simd_select_bitmask(k, _mm512_fnmsub_ph(a, b, c), _mm512_setzero_ph()) }
6940}
6941
6942/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract packed elements
6943/// in c from the negated intermediate result, and store the results in dst.
6944///
6945/// Rounding is done according to the rounding parameter, which can be one of:
6946///
6947/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
6948/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
6949/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
6950/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
6951/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
6952///
6953/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fnmsub_round_ph)
6954#[inline]
6955#[target_feature(enable = "avx512fp16")]
6956#[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))]
6957#[rustc_legacy_const_generics(3)]
6958#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6959pub fn _mm512_fnmsub_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
6960    unsafe {
6961        static_assert_rounding!(ROUNDING);
6962        vfmaddph_512(simd_neg(a), b, simd_neg(c), ROUNDING)
6963    }
6964}
6965
6966/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract packed elements
6967/// in c from the negated intermediate result, and store the results in dst using writemask k (the element is
6968/// copied from a when the corresponding mask bit is not set).
6969///
6970/// Rounding is done according to the rounding parameter, which can be one of:
6971///
6972/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
6973/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
6974/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
6975/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
6976/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
6977///
6978/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fnmsub_round_ph)
6979#[inline]
6980#[target_feature(enable = "avx512fp16")]
6981#[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))]
6982#[rustc_legacy_const_generics(4)]
6983#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
6984pub fn _mm512_mask_fnmsub_round_ph<const ROUNDING: i32>(
6985    a: __m512h,
6986    k: __mmask32,
6987    b: __m512h,
6988    c: __m512h,
6989) -> __m512h {
6990    unsafe {
6991        static_assert_rounding!(ROUNDING);
6992        simd_select_bitmask(k, _mm512_fnmsub_round_ph::<ROUNDING>(a, b, c), a)
6993    }
6994}
6995
6996/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract packed elements
6997/// in c from the negated intermediate result, and store the results in dst using writemask k (the element is
6998/// copied from c when the corresponding mask bit is not set).
6999///
7000/// Rounding is done according to the rounding parameter, which can be one of:
7001///
7002/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
7003/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
7004/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
7005/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
7006/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
7007///
7008/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fnmsub_round_ph)
7009#[inline]
7010#[target_feature(enable = "avx512fp16")]
7011#[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))]
7012#[rustc_legacy_const_generics(4)]
7013#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7014pub fn _mm512_mask3_fnmsub_round_ph<const ROUNDING: i32>(
7015    a: __m512h,
7016    b: __m512h,
7017    c: __m512h,
7018    k: __mmask32,
7019) -> __m512h {
7020    unsafe {
7021        static_assert_rounding!(ROUNDING);
7022        simd_select_bitmask(k, _mm512_fnmsub_round_ph::<ROUNDING>(a, b, c), c)
7023    }
7024}
7025
7026/// Multiply packed half-precision (16-bit) floating-point elements in a and b, subtract packed elements
7027/// in c from the negated intermediate result, and store the results in dst using zeromask k (the element is
7028/// zeroed out when the corresponding mask bit is not set).
7029///
7030/// Rounding is done according to the rounding parameter, which can be one of:
7031///
7032/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
7033/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
7034/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
7035/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
7036/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
7037///
7038/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fnmsub_round_ph)
7039#[inline]
7040#[target_feature(enable = "avx512fp16")]
7041#[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))]
7042#[rustc_legacy_const_generics(4)]
7043#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7044pub fn _mm512_maskz_fnmsub_round_ph<const ROUNDING: i32>(
7045    k: __mmask32,
7046    a: __m512h,
7047    b: __m512h,
7048    c: __m512h,
7049) -> __m512h {
7050    unsafe {
7051        static_assert_rounding!(ROUNDING);
7052        simd_select_bitmask(
7053            k,
7054            _mm512_fnmsub_round_ph::<ROUNDING>(a, b, c),
7055            _mm512_setzero_ph(),
7056        )
7057    }
7058}
7059
7060/// Multiply the lower half-precision (16-bit) floating-point elements in a and b, and subtract the intermediate
7061/// result from the lower element in c. Store the result in the lower element of dst, and copy the upper 7 packed
7062/// elements from a to the upper elements of dst.
7063///
7064/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fnmsub_sh)
7065#[inline]
7066#[target_feature(enable = "avx512fp16")]
7067#[cfg_attr(test, assert_instr(vfnmsub))]
7068#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7069#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
7070pub const fn _mm_fnmsub_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
7071    unsafe {
7072        let extracta: f16 = simd_extract!(a, 0);
7073        let extractb: f16 = simd_extract!(b, 0);
7074        let extractc: f16 = simd_extract!(c, 0);
7075        let r = fmaf16(-extracta, extractb, -extractc);
7076        simd_insert!(a, 0, r)
7077    }
7078}
7079
7080/// Multiply the lower half-precision (16-bit) floating-point elements in a and b, and subtract the intermediate
7081/// result from the lower element in c. Store the result in the lower element of dst using writemask k (the element
7082/// is copied from a when the mask bit 0 is not set), and copy the upper 7 packed elements from a to the upper
7083/// elements of dst.
7084///
7085/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fnmsub_sh)
7086#[inline]
7087#[target_feature(enable = "avx512fp16")]
7088#[cfg_attr(test, assert_instr(vfnmsub))]
7089#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7090#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
7091pub const fn _mm_mask_fnmsub_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
7092    unsafe {
7093        let mut fnmsub: f16 = simd_extract!(a, 0);
7094        if k & 1 != 0 {
7095            let extractb: f16 = simd_extract!(b, 0);
7096            let extractc: f16 = simd_extract!(c, 0);
7097            fnmsub = fmaf16(-fnmsub, extractb, -extractc);
7098        }
7099        simd_insert!(a, 0, fnmsub)
7100    }
7101}
7102
7103/// Multiply the lower half-precision (16-bit) floating-point elements in a and b, and subtract the intermediate
7104/// result from the lower element in c. Store the result in the lower element of dst using writemask k (the element
7105/// is copied from c when the mask bit 0 is not set), and copy the upper 7 packed elements from c to the upper
7106/// elements of dst.
7107///
7108/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fnmsub_sh)
7109#[inline]
7110#[target_feature(enable = "avx512fp16")]
7111#[cfg_attr(test, assert_instr(vfnmsub))]
7112#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7113#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
7114pub const fn _mm_mask3_fnmsub_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
7115    unsafe {
7116        let mut fnmsub: f16 = simd_extract!(c, 0);
7117        if k & 1 != 0 {
7118            let extracta: f16 = simd_extract!(a, 0);
7119            let extractb: f16 = simd_extract!(b, 0);
7120            fnmsub = fmaf16(-extracta, extractb, -fnmsub);
7121        }
7122        simd_insert!(c, 0, fnmsub)
7123    }
7124}
7125
7126/// Multiply the lower half-precision (16-bit) floating-point elements in a and b, and subtract the intermediate
7127/// result from the lower element in c. Store the result in the lower element of dst using zeromask k (the element
7128/// is zeroed out when the mask bit 0 is not set), and copy the upper 7 packed elements from a to the upper
7129/// elements of dst.
7130///
7131/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fnmsub_sh)
7132#[inline]
7133#[target_feature(enable = "avx512fp16")]
7134#[cfg_attr(test, assert_instr(vfnmsub))]
7135#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7136#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
7137pub const fn _mm_maskz_fnmsub_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
7138    unsafe {
7139        let mut fnmsub: f16 = 0.0;
7140        if k & 1 != 0 {
7141            let extracta: f16 = simd_extract!(a, 0);
7142            let extractb: f16 = simd_extract!(b, 0);
7143            let extractc: f16 = simd_extract!(c, 0);
7144            fnmsub = fmaf16(-extracta, extractb, -extractc);
7145        }
7146        simd_insert!(a, 0, fnmsub)
7147    }
7148}
7149
7150/// Multiply the lower half-precision (16-bit) floating-point elements in a and b, and subtract the intermediate
7151/// result from the lower element in c. Store the result in the lower element of dst, and copy the upper 7 packed
7152/// elements from a to the upper elements of dst.
7153///
7154/// Rounding is done according to the rounding parameter, which can be one of:
7155///
7156/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
7157/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
7158/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
7159/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
7160/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
7161///
7162/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fnmsub_round_sh)
7163#[inline]
7164#[target_feature(enable = "avx512fp16")]
7165#[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))]
7166#[rustc_legacy_const_generics(3)]
7167#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7168pub fn _mm_fnmsub_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
7169    unsafe {
7170        static_assert_rounding!(ROUNDING);
7171        let extracta: f16 = simd_extract!(a, 0);
7172        let extractb: f16 = simd_extract!(b, 0);
7173        let extractc: f16 = simd_extract!(c, 0);
7174        let r = vfmaddsh(-extracta, extractb, -extractc, ROUNDING);
7175        simd_insert!(a, 0, r)
7176    }
7177}
7178
7179/// Multiply the lower half-precision (16-bit) floating-point elements in a and b, and subtract the intermediate
7180/// result from the lower element in c. Store the result in the lower element of dst using writemask k (the element
7181/// is copied from a when the mask bit 0 is not set), and copy the upper 7 packed elements from a to the upper
7182/// elements of dst.
7183///
7184/// Rounding is done according to the rounding parameter, which can be one of:
7185///
7186/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
7187/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
7188/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
7189/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
7190/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
7191///
7192/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fnmsub_round_sh)
7193#[inline]
7194#[target_feature(enable = "avx512fp16")]
7195#[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))]
7196#[rustc_legacy_const_generics(4)]
7197#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7198pub fn _mm_mask_fnmsub_round_sh<const ROUNDING: i32>(
7199    a: __m128h,
7200    k: __mmask8,
7201    b: __m128h,
7202    c: __m128h,
7203) -> __m128h {
7204    unsafe {
7205        static_assert_rounding!(ROUNDING);
7206        let mut fnmsub: f16 = simd_extract!(a, 0);
7207        if k & 1 != 0 {
7208            let extractb: f16 = simd_extract!(b, 0);
7209            let extractc: f16 = simd_extract!(c, 0);
7210            fnmsub = vfmaddsh(-fnmsub, extractb, -extractc, ROUNDING);
7211        }
7212        simd_insert!(a, 0, fnmsub)
7213    }
7214}
7215
7216/// Multiply the lower half-precision (16-bit) floating-point elements in a and b, and subtract the intermediate
7217/// result from the lower element in c. Store the result in the lower element of dst using writemask k (the element
7218/// is copied from c when the mask bit 0 is not set), and copy the upper 7 packed elements from c to the upper
7219/// elements of dst.
7220///
7221/// Rounding is done according to the rounding parameter, which can be one of:
7222///
7223/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
7224/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
7225/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
7226/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
7227/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
7228///
7229/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fnmsub_round_sh)
7230#[inline]
7231#[target_feature(enable = "avx512fp16")]
7232#[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))]
7233#[rustc_legacy_const_generics(4)]
7234#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7235pub fn _mm_mask3_fnmsub_round_sh<const ROUNDING: i32>(
7236    a: __m128h,
7237    b: __m128h,
7238    c: __m128h,
7239    k: __mmask8,
7240) -> __m128h {
7241    unsafe {
7242        static_assert_rounding!(ROUNDING);
7243        let mut fnmsub: f16 = simd_extract!(c, 0);
7244        if k & 1 != 0 {
7245            let extracta: f16 = simd_extract!(a, 0);
7246            let extractb: f16 = simd_extract!(b, 0);
7247            fnmsub = vfmaddsh(-extracta, extractb, -fnmsub, ROUNDING);
7248        }
7249        simd_insert!(c, 0, fnmsub)
7250    }
7251}
7252
7253/// Multiply the lower half-precision (16-bit) floating-point elements in a and b, and subtract the intermediate
7254/// result from the lower element in c. Store the result in the lower element of dst using zeromask k (the element
7255/// is zeroed out when the mask bit 0 is not set), and copy the upper 7 packed elements from a to the upper
7256/// elements of dst.
7257///
7258/// Rounding is done according to the rounding parameter, which can be one of:
7259///
7260/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
7261/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
7262/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
7263/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
7264/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
7265///
7266/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fnmsub_round_sh)
7267#[inline]
7268#[target_feature(enable = "avx512fp16")]
7269#[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))]
7270#[rustc_legacy_const_generics(4)]
7271#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7272pub fn _mm_maskz_fnmsub_round_sh<const ROUNDING: i32>(
7273    k: __mmask8,
7274    a: __m128h,
7275    b: __m128h,
7276    c: __m128h,
7277) -> __m128h {
7278    unsafe {
7279        static_assert_rounding!(ROUNDING);
7280        let mut fnmsub: f16 = 0.0;
7281        if k & 1 != 0 {
7282            let extracta: f16 = simd_extract!(a, 0);
7283            let extractb: f16 = simd_extract!(b, 0);
7284            let extractc: f16 = simd_extract!(c, 0);
7285            fnmsub = vfmaddsh(-extracta, extractb, -extractc, ROUNDING);
7286        }
7287        simd_insert!(a, 0, fnmsub)
7288    }
7289}
7290
7291/// Multiply packed half-precision (16-bit) floating-point elements in a and b, alternatively add and
7292/// subtract packed elements in c to/from the intermediate result, and store the results in dst.
7293///
7294/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fmaddsub_ph)
7295#[inline]
7296#[target_feature(enable = "avx512fp16,avx512vl")]
7297#[cfg_attr(test, assert_instr(vfmaddsub))]
7298#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7299#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
7300pub const fn _mm_fmaddsub_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
7301    unsafe {
7302        let add = simd_fma(a, b, c);
7303        let sub = simd_fma(a, b, simd_neg(c));
7304        simd_shuffle!(sub, add, [0, 9, 2, 11, 4, 13, 6, 15])
7305    }
7306}
7307
7308/// Multiply packed half-precision (16-bit) floating-point elements in a and b, alternatively add and
7309/// subtract packed elements in c to/from the intermediate result, and store the results in dst using writemask k
7310/// (the element is copied from a when the corresponding mask bit is not set).
7311///
7312/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fmaddsub_ph)
7313#[inline]
7314#[target_feature(enable = "avx512fp16,avx512vl")]
7315#[cfg_attr(test, assert_instr(vfmaddsub))]
7316#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7317#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
7318pub const fn _mm_mask_fmaddsub_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
7319    unsafe { simd_select_bitmask(k, _mm_fmaddsub_ph(a, b, c), a) }
7320}
7321
7322/// Multiply packed half-precision (16-bit) floating-point elements in a and b, alternatively add and
7323/// subtract packed elements in c to/from the intermediate result, and store the results in dst using writemask k
7324/// (the element is copied from c when the corresponding mask bit is not set).
7325///
7326/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fmaddsub_ph)
7327#[inline]
7328#[target_feature(enable = "avx512fp16,avx512vl")]
7329#[cfg_attr(test, assert_instr(vfmaddsub))]
7330#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7331#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
7332pub const fn _mm_mask3_fmaddsub_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
7333    unsafe { simd_select_bitmask(k, _mm_fmaddsub_ph(a, b, c), c) }
7334}
7335
7336/// Multiply packed half-precision (16-bit) floating-point elements in a and b, alternatively add and
7337/// subtract packed elements in c to/from the intermediate result, and store the results in dst using zeromask k
7338/// (the element is zeroed out when the corresponding mask bit is not set).
7339///
7340/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fmaddsub_ph)
7341#[inline]
7342#[target_feature(enable = "avx512fp16,avx512vl")]
7343#[cfg_attr(test, assert_instr(vfmaddsub))]
7344#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7345#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
7346pub const fn _mm_maskz_fmaddsub_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
7347    unsafe { simd_select_bitmask(k, _mm_fmaddsub_ph(a, b, c), _mm_setzero_ph()) }
7348}
7349
7350/// Multiply packed half-precision (16-bit) floating-point elements in a and b, alternatively add and
7351/// subtract packed elements in c to/from the intermediate result, and store the results in dst.
7352///
7353/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_fmaddsub_ph)
7354#[inline]
7355#[target_feature(enable = "avx512fp16,avx512vl")]
7356#[cfg_attr(test, assert_instr(vfmaddsub))]
7357#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7358#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
7359pub const fn _mm256_fmaddsub_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
7360    unsafe {
7361        let add = simd_fma(a, b, c);
7362        let sub = simd_fma(a, b, simd_neg(c));
7363        simd_shuffle!(
7364            sub,
7365            add,
7366            [0, 17, 2, 19, 4, 21, 6, 23, 8, 25, 10, 27, 12, 29, 14, 31]
7367        )
7368    }
7369}
7370
7371/// Multiply packed half-precision (16-bit) floating-point elements in a and b, alternatively add and
7372/// subtract packed elements in c to/from the intermediate result, and store the results in dst using writemask k
7373/// (the element is copied from a when the corresponding mask bit is not set).
7374///
7375/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_fmaddsub_ph)
7376#[inline]
7377#[target_feature(enable = "avx512fp16,avx512vl")]
7378#[cfg_attr(test, assert_instr(vfmaddsub))]
7379#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7380#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
7381pub const fn _mm256_mask_fmaddsub_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h {
7382    unsafe { simd_select_bitmask(k, _mm256_fmaddsub_ph(a, b, c), a) }
7383}
7384
7385/// Multiply packed half-precision (16-bit) floating-point elements in a and b, alternatively add and
7386/// subtract packed elements in c to/from the intermediate result, and store the results in dst using writemask k
7387/// (the element is copied from c when the corresponding mask bit is not set).
7388///
7389/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask3_fmaddsub_ph)
7390#[inline]
7391#[target_feature(enable = "avx512fp16,avx512vl")]
7392#[cfg_attr(test, assert_instr(vfmaddsub))]
7393#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7394#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
7395pub const fn _mm256_mask3_fmaddsub_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h {
7396    unsafe { simd_select_bitmask(k, _mm256_fmaddsub_ph(a, b, c), c) }
7397}
7398
7399/// Multiply packed half-precision (16-bit) floating-point elements in a and b, alternatively add and
7400/// subtract packed elements in c to/from the intermediate result, and store the results in dst using zeromask k
7401/// (the element is zeroed out when the corresponding mask bit is not set).
7402///
7403/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_fmaddsub_ph)
7404#[inline]
7405#[target_feature(enable = "avx512fp16,avx512vl")]
7406#[cfg_attr(test, assert_instr(vfmaddsub))]
7407#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7408#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
7409pub const fn _mm256_maskz_fmaddsub_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h {
7410    unsafe { simd_select_bitmask(k, _mm256_fmaddsub_ph(a, b, c), _mm256_setzero_ph()) }
7411}
7412
7413/// Multiply packed half-precision (16-bit) floating-point elements in a and b, alternatively add and
7414/// subtract packed elements in c to/from the intermediate result, and store the results in dst.
7415///
7416/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fmaddsub_ph)
7417#[inline]
7418#[target_feature(enable = "avx512fp16")]
7419#[cfg_attr(test, assert_instr(vfmaddsub))]
7420#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7421#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
7422pub const fn _mm512_fmaddsub_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
7423    unsafe {
7424        let add = simd_fma(a, b, c);
7425        let sub = simd_fma(a, b, simd_neg(c));
7426        simd_shuffle!(
7427            sub,
7428            add,
7429            [
7430                0, 33, 2, 35, 4, 37, 6, 39, 8, 41, 10, 43, 12, 45, 14, 47, 16, 49, 18, 51, 20, 53,
7431                22, 55, 24, 57, 26, 59, 28, 61, 30, 63
7432            ]
7433        )
7434    }
7435}
7436
7437/// Multiply packed half-precision (16-bit) floating-point elements in a and b, alternatively add and
7438/// subtract packed elements in c to/from the intermediate result, and store the results in dst using writemask k
7439/// (the element is copied from a when the corresponding mask bit is not set).
7440///
7441/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fmaddsub_ph)
7442#[inline]
7443#[target_feature(enable = "avx512fp16")]
7444#[cfg_attr(test, assert_instr(vfmaddsub))]
7445#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7446#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
7447pub const fn _mm512_mask_fmaddsub_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h {
7448    unsafe { simd_select_bitmask(k, _mm512_fmaddsub_ph(a, b, c), a) }
7449}
7450
7451/// Multiply packed half-precision (16-bit) floating-point elements in a and b, alternatively add and
7452/// subtract packed elements in c to/from the intermediate result, and store the results in dst using writemask k
7453/// (the element is copied from c when the corresponding mask bit is not set).
7454///
7455/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fmaddsub_ph)
7456#[inline]
7457#[target_feature(enable = "avx512fp16")]
7458#[cfg_attr(test, assert_instr(vfmaddsub))]
7459#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7460#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
7461pub const fn _mm512_mask3_fmaddsub_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h {
7462    unsafe { simd_select_bitmask(k, _mm512_fmaddsub_ph(a, b, c), c) }
7463}
7464
7465/// Multiply packed half-precision (16-bit) floating-point elements in a and b, alternatively add and
7466/// subtract packed elements in c to/from the intermediate result, and store the results in dst using zeromask k
7467/// (the element is zeroed out when the corresponding mask bit is not set).
7468///
7469/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fmaddsub_ph)
7470#[inline]
7471#[target_feature(enable = "avx512fp16")]
7472#[cfg_attr(test, assert_instr(vfmaddsub))]
7473#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7474#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
7475pub const fn _mm512_maskz_fmaddsub_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h {
7476    unsafe { simd_select_bitmask(k, _mm512_fmaddsub_ph(a, b, c), _mm512_setzero_ph()) }
7477}
7478
7479/// Multiply packed half-precision (16-bit) floating-point elements in a and b, alternatively add and
7480/// subtract packed elements in c to/from the intermediate result, and store the results in dst.
7481///
7482/// Rounding is done according to the rounding parameter, which can be one of:
7483///
7484/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
7485/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
7486/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
7487/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
7488/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
7489///
7490/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fmaddsub_round_ph)
7491#[inline]
7492#[target_feature(enable = "avx512fp16")]
7493#[cfg_attr(test, assert_instr(vfmaddsub, ROUNDING = 8))]
7494#[rustc_legacy_const_generics(3)]
7495#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7496pub fn _mm512_fmaddsub_round_ph<const ROUNDING: i32>(
7497    a: __m512h,
7498    b: __m512h,
7499    c: __m512h,
7500) -> __m512h {
7501    unsafe {
7502        static_assert_rounding!(ROUNDING);
7503        vfmaddsubph_512(a, b, c, ROUNDING)
7504    }
7505}
7506
7507/// Multiply packed half-precision (16-bit) floating-point elements in a and b, alternatively add and
7508/// subtract packed elements in c to/from the intermediate result, and store the results in dst using writemask k
7509/// (the element is copied from a when the corresponding mask bit is not set).
7510///
7511/// Rounding is done according to the rounding parameter, which can be one of:
7512///
7513/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
7514/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
7515/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
7516/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
7517/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
7518///
7519/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fmaddsub_round_ph)
7520#[inline]
7521#[target_feature(enable = "avx512fp16")]
7522#[cfg_attr(test, assert_instr(vfmaddsub, ROUNDING = 8))]
7523#[rustc_legacy_const_generics(4)]
7524#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7525pub fn _mm512_mask_fmaddsub_round_ph<const ROUNDING: i32>(
7526    a: __m512h,
7527    k: __mmask32,
7528    b: __m512h,
7529    c: __m512h,
7530) -> __m512h {
7531    unsafe {
7532        static_assert_rounding!(ROUNDING);
7533        simd_select_bitmask(k, _mm512_fmaddsub_round_ph::<ROUNDING>(a, b, c), a)
7534    }
7535}
7536
7537/// Multiply packed half-precision (16-bit) floating-point elements in a and b, alternatively add and
7538/// subtract packed elements in c to/from the intermediate result, and store the results in dst using writemask k
7539/// (the element is copied from c when the corresponding mask bit is not set).
7540///
7541/// Rounding is done according to the rounding parameter, which can be one of:
7542///
7543/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
7544/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
7545/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
7546/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
7547/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
7548///
7549/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fmaddsub_round_ph)
7550#[inline]
7551#[target_feature(enable = "avx512fp16")]
7552#[cfg_attr(test, assert_instr(vfmaddsub, ROUNDING = 8))]
7553#[rustc_legacy_const_generics(4)]
7554#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7555pub fn _mm512_mask3_fmaddsub_round_ph<const ROUNDING: i32>(
7556    a: __m512h,
7557    b: __m512h,
7558    c: __m512h,
7559    k: __mmask32,
7560) -> __m512h {
7561    unsafe {
7562        static_assert_rounding!(ROUNDING);
7563        simd_select_bitmask(k, _mm512_fmaddsub_round_ph::<ROUNDING>(a, b, c), c)
7564    }
7565}
7566
7567/// Multiply packed half-precision (16-bit) floating-point elements in a and b, alternatively add and
7568/// subtract packed elements in c to/from the intermediate result, and store the results in dst using zeromask k
7569/// (the element is zeroed out when the corresponding mask bit is not set).
7570///
7571/// Rounding is done according to the rounding parameter, which can be one of:
7572///
7573/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
7574/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
7575/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
7576/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
7577/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
7578///
7579/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fmaddsub_round_ph)
7580#[inline]
7581#[target_feature(enable = "avx512fp16")]
7582#[cfg_attr(test, assert_instr(vfmaddsub, ROUNDING = 8))]
7583#[rustc_legacy_const_generics(4)]
7584#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7585pub fn _mm512_maskz_fmaddsub_round_ph<const ROUNDING: i32>(
7586    k: __mmask32,
7587    a: __m512h,
7588    b: __m512h,
7589    c: __m512h,
7590) -> __m512h {
7591    unsafe {
7592        static_assert_rounding!(ROUNDING);
7593        simd_select_bitmask(
7594            k,
7595            _mm512_fmaddsub_round_ph::<ROUNDING>(a, b, c),
7596            _mm512_setzero_ph(),
7597        )
7598    }
7599}
7600
7601/// Multiply packed half-precision (16-bit) floating-point elements in a and b, alternatively subtract
7602/// and add packed elements in c to/from the intermediate result, and store the results in dst.
7603///
7604/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fmsubadd_ph)
7605#[inline]
7606#[target_feature(enable = "avx512fp16,avx512vl")]
7607#[cfg_attr(test, assert_instr(vfmsubadd))]
7608#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7609#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
7610pub const fn _mm_fmsubadd_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
7611    _mm_fmaddsub_ph(a, b, unsafe { simd_neg(c) })
7612}
7613
7614/// Multiply packed half-precision (16-bit) floating-point elements in a and b, alternatively subtract
7615/// and add packed elements in c to/from the intermediate result, and store the results in dst using writemask k
7616/// (the element is copied from a when the corresponding mask bit is not set).
7617///
7618/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fmsubadd_ph)
7619#[inline]
7620#[target_feature(enable = "avx512fp16,avx512vl")]
7621#[cfg_attr(test, assert_instr(vfmsubadd))]
7622#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7623#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
7624pub const fn _mm_mask_fmsubadd_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
7625    unsafe { simd_select_bitmask(k, _mm_fmsubadd_ph(a, b, c), a) }
7626}
7627
7628/// Multiply packed half-precision (16-bit) floating-point elements in a and b, alternatively subtract
7629/// and add packed elements in c to/from the intermediate result, and store the results in dst using writemask k
7630/// (the element is copied from c when the corresponding mask bit is not set).
7631///
7632/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fmsubadd_ph)
7633#[inline]
7634#[target_feature(enable = "avx512fp16,avx512vl")]
7635#[cfg_attr(test, assert_instr(vfmsubadd))]
7636#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7637#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
7638pub const fn _mm_mask3_fmsubadd_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
7639    unsafe { simd_select_bitmask(k, _mm_fmsubadd_ph(a, b, c), c) }
7640}
7641
7642/// Multiply packed half-precision (16-bit) floating-point elements in a and b, alternatively subtract
7643/// and add packed elements in c to/from the intermediate result, and store the results in dst using zeromask k
7644/// (the element is zeroed out when the corresponding mask bit is not set).
7645///
7646/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fmsubadd_ph)
7647#[inline]
7648#[target_feature(enable = "avx512fp16,avx512vl")]
7649#[cfg_attr(test, assert_instr(vfmsubadd))]
7650#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7651#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
7652pub const fn _mm_maskz_fmsubadd_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
7653    unsafe { simd_select_bitmask(k, _mm_fmsubadd_ph(a, b, c), _mm_setzero_ph()) }
7654}
7655
7656/// Multiply packed half-precision (16-bit) floating-point elements in a and b, alternatively subtract
7657/// and add packed elements in c to/from the intermediate result, and store the results in dst.
7658///
7659/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_fmsubadd_ph)
7660#[inline]
7661#[target_feature(enable = "avx512fp16,avx512vl")]
7662#[cfg_attr(test, assert_instr(vfmsubadd))]
7663#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7664#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
7665pub const fn _mm256_fmsubadd_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
7666    _mm256_fmaddsub_ph(a, b, unsafe { simd_neg(c) })
7667}
7668
7669/// Multiply packed half-precision (16-bit) floating-point elements in a and b, alternatively subtract
7670/// and add packed elements in c to/from the intermediate result, and store the results in dst using writemask k
7671/// (the element is copied from a when the corresponding mask bit is not set).
7672///
7673/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_fmsubadd_ph)
7674#[inline]
7675#[target_feature(enable = "avx512fp16,avx512vl")]
7676#[cfg_attr(test, assert_instr(vfmsubadd))]
7677#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7678#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
7679pub const fn _mm256_mask_fmsubadd_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h {
7680    unsafe { simd_select_bitmask(k, _mm256_fmsubadd_ph(a, b, c), a) }
7681}
7682
7683/// Multiply packed half-precision (16-bit) floating-point elements in a and b, alternatively subtract
7684/// and add packed elements in c to/from the intermediate result, and store the results in dst using writemask k
7685/// (the element is copied from c when the corresponding mask bit is not set).
7686///
7687/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask3_fmsubadd_ph)
7688#[inline]
7689#[target_feature(enable = "avx512fp16,avx512vl")]
7690#[cfg_attr(test, assert_instr(vfmsubadd))]
7691#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7692#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
7693pub const fn _mm256_mask3_fmsubadd_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h {
7694    unsafe { simd_select_bitmask(k, _mm256_fmsubadd_ph(a, b, c), c) }
7695}
7696
7697/// Multiply packed half-precision (16-bit) floating-point elements in a and b, alternatively subtract
7698/// and add packed elements in c to/from the intermediate result, and store the results in dst using zeromask k
7699/// (the element is zeroed out when the corresponding mask bit is not set).
7700///
7701/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_fmsubadd_ph)
7702#[inline]
7703#[target_feature(enable = "avx512fp16,avx512vl")]
7704#[cfg_attr(test, assert_instr(vfmsubadd))]
7705#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7706#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
7707pub const fn _mm256_maskz_fmsubadd_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h {
7708    unsafe { simd_select_bitmask(k, _mm256_fmsubadd_ph(a, b, c), _mm256_setzero_ph()) }
7709}
7710
7711/// Multiply packed half-precision (16-bit) floating-point elements in a and b, alternatively subtract
7712/// and add packed elements in c to/from the intermediate result, and store the results in dst.
7713///
7714/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fmsubadd_ph)
7715#[inline]
7716#[target_feature(enable = "avx512fp16")]
7717#[cfg_attr(test, assert_instr(vfmsubadd))]
7718#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7719#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
7720pub const fn _mm512_fmsubadd_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
7721    _mm512_fmaddsub_ph(a, b, unsafe { simd_neg(c) })
7722}
7723
7724/// Multiply packed half-precision (16-bit) floating-point elements in a and b, alternatively subtract
7725/// and add packed elements in c to/from the intermediate result, and store the results in dst using writemask k
7726/// (the element is copied from a when the corresponding mask bit is not set).
7727///
7728/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fmsubadd_ph)
7729#[inline]
7730#[target_feature(enable = "avx512fp16")]
7731#[cfg_attr(test, assert_instr(vfmsubadd))]
7732#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7733#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
7734pub const fn _mm512_mask_fmsubadd_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h {
7735    unsafe { simd_select_bitmask(k, _mm512_fmsubadd_ph(a, b, c), a) }
7736}
7737
7738/// Multiply packed half-precision (16-bit) floating-point elements in a and b, alternatively subtract
7739/// and add packed elements in c to/from the intermediate result, and store the results in dst using writemask k
7740/// (the element is copied from c when the corresponding mask bit is not set).
7741///
7742/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fmsubadd_ph)
7743#[inline]
7744#[target_feature(enable = "avx512fp16")]
7745#[cfg_attr(test, assert_instr(vfmsubadd))]
7746#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7747#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
7748pub const fn _mm512_mask3_fmsubadd_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h {
7749    unsafe { simd_select_bitmask(k, _mm512_fmsubadd_ph(a, b, c), c) }
7750}
7751
7752/// Multiply packed half-precision (16-bit) floating-point elements in a and b, alternatively subtract
7753/// and add packed elements in c to/from the intermediate result, and store the results in dst using zeromask k
7754/// (the element is zeroed out when the corresponding mask bit is not set).
7755///
7756/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fmsubadd_ph)
7757#[inline]
7758#[target_feature(enable = "avx512fp16")]
7759#[cfg_attr(test, assert_instr(vfmsubadd))]
7760#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7761#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
7762pub const fn _mm512_maskz_fmsubadd_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h {
7763    unsafe { simd_select_bitmask(k, _mm512_fmsubadd_ph(a, b, c), _mm512_setzero_ph()) }
7764}
7765
7766/// Multiply packed half-precision (16-bit) floating-point elements in a and b, alternatively subtract
7767/// and add packed elements in c to/from the intermediate result, and store the results in dst.
7768///
7769/// Rounding is done according to the rounding parameter, which can be one of:
7770///
7771/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
7772/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
7773/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
7774/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
7775/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
7776///
7777/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fmsubadd_round_ph)
7778#[inline]
7779#[target_feature(enable = "avx512fp16")]
7780#[cfg_attr(test, assert_instr(vfmsubadd, ROUNDING = 8))]
7781#[rustc_legacy_const_generics(3)]
7782#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7783pub fn _mm512_fmsubadd_round_ph<const ROUNDING: i32>(
7784    a: __m512h,
7785    b: __m512h,
7786    c: __m512h,
7787) -> __m512h {
7788    unsafe {
7789        static_assert_rounding!(ROUNDING);
7790        vfmaddsubph_512(a, b, simd_neg(c), ROUNDING)
7791    }
7792}
7793
7794/// Multiply packed half-precision (16-bit) floating-point elements in a and b, alternatively subtract
7795/// and add packed elements in c to/from the intermediate result, and store the results in dst using writemask k
7796/// (the element is copied from a when the corresponding mask bit is not set).
7797///
7798/// Rounding is done according to the rounding parameter, which can be one of:
7799///
7800/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
7801/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
7802/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
7803/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
7804/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
7805///
7806/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fmsubadd_round_ph)
7807#[inline]
7808#[target_feature(enable = "avx512fp16")]
7809#[cfg_attr(test, assert_instr(vfmsubadd, ROUNDING = 8))]
7810#[rustc_legacy_const_generics(4)]
7811#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7812pub fn _mm512_mask_fmsubadd_round_ph<const ROUNDING: i32>(
7813    a: __m512h,
7814    k: __mmask32,
7815    b: __m512h,
7816    c: __m512h,
7817) -> __m512h {
7818    unsafe {
7819        static_assert_rounding!(ROUNDING);
7820        simd_select_bitmask(k, _mm512_fmsubadd_round_ph::<ROUNDING>(a, b, c), a)
7821    }
7822}
7823
7824/// Multiply packed half-precision (16-bit) floating-point elements in a and b, alternatively subtract
7825/// and add packed elements in c to/from the intermediate result, and store the results in dst using writemask k
7826/// (the element is copied from c when the corresponding mask bit is not set).
7827///
7828/// Rounding is done according to the rounding parameter, which can be one of:
7829///
7830/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
7831/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
7832/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
7833/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
7834/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
7835///
7836/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fmsubadd_round_ph)
7837#[inline]
7838#[target_feature(enable = "avx512fp16")]
7839#[cfg_attr(test, assert_instr(vfmsubadd, ROUNDING = 8))]
7840#[rustc_legacy_const_generics(4)]
7841#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7842pub fn _mm512_mask3_fmsubadd_round_ph<const ROUNDING: i32>(
7843    a: __m512h,
7844    b: __m512h,
7845    c: __m512h,
7846    k: __mmask32,
7847) -> __m512h {
7848    unsafe {
7849        static_assert_rounding!(ROUNDING);
7850        simd_select_bitmask(k, _mm512_fmsubadd_round_ph::<ROUNDING>(a, b, c), c)
7851    }
7852}
7853
7854/// Multiply packed half-precision (16-bit) floating-point elements in a and b, alternatively subtract
7855/// and add packed elements in c to/from the intermediate result, and store the results in dst using zeromask k
7856/// (the element is zeroed out when the corresponding mask bit is not set).
7857///
7858/// Rounding is done according to the rounding parameter, which can be one of:
7859///
7860/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
7861/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
7862/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
7863/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
7864/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
7865///
7866/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fmsubadd_round_ph)
7867#[inline]
7868#[target_feature(enable = "avx512fp16")]
7869#[cfg_attr(test, assert_instr(vfmsubadd, ROUNDING = 8))]
7870#[rustc_legacy_const_generics(4)]
7871#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7872pub fn _mm512_maskz_fmsubadd_round_ph<const ROUNDING: i32>(
7873    k: __mmask32,
7874    a: __m512h,
7875    b: __m512h,
7876    c: __m512h,
7877) -> __m512h {
7878    unsafe {
7879        static_assert_rounding!(ROUNDING);
7880        simd_select_bitmask(
7881            k,
7882            _mm512_fmsubadd_round_ph::<ROUNDING>(a, b, c),
7883            _mm512_setzero_ph(),
7884        )
7885    }
7886}
7887
7888/// Compute the approximate reciprocal of packed 16-bit floating-point elements in `a` and stores the results in `dst`.
7889/// The maximum relative error for this approximation is less than `1.5*2^-12`.
7890///
7891/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_rcp_ph)
7892#[inline]
7893#[target_feature(enable = "avx512fp16,avx512vl")]
7894#[cfg_attr(test, assert_instr(vrcpph))]
7895#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7896pub fn _mm_rcp_ph(a: __m128h) -> __m128h {
7897    _mm_mask_rcp_ph(_mm_undefined_ph(), 0xff, a)
7898}
7899
7900/// Compute the approximate reciprocal of packed 16-bit floating-point elements in `a` and stores the results in `dst`
7901/// using writemask `k` (elements are copied from `src` when the corresponding mask bit is not set).
7902/// The maximum relative error for this approximation is less than `1.5*2^-12`.
7903///
7904/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_rcp_ph)
7905#[inline]
7906#[target_feature(enable = "avx512fp16,avx512vl")]
7907#[cfg_attr(test, assert_instr(vrcpph))]
7908#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7909pub fn _mm_mask_rcp_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h {
7910    unsafe { vrcpph_128(a, src, k) }
7911}
7912
7913/// Compute the approximate reciprocal of packed 16-bit floating-point elements in `a` and stores the results in `dst`
7914/// using zeromask `k` (elements are zeroed out when the corresponding mask bit is not set).
7915/// The maximum relative error for this approximation is less than `1.5*2^-12`.
7916///
7917/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_rcp_ph)
7918#[inline]
7919#[target_feature(enable = "avx512fp16,avx512vl")]
7920#[cfg_attr(test, assert_instr(vrcpph))]
7921#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7922pub fn _mm_maskz_rcp_ph(k: __mmask8, a: __m128h) -> __m128h {
7923    _mm_mask_rcp_ph(_mm_setzero_ph(), k, a)
7924}
7925
7926/// Compute the approximate reciprocal of packed 16-bit floating-point elements in `a` and stores the results in `dst`.
7927/// The maximum relative error for this approximation is less than `1.5*2^-12`.
7928///
7929/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_rcp_ph)
7930#[inline]
7931#[target_feature(enable = "avx512fp16,avx512vl")]
7932#[cfg_attr(test, assert_instr(vrcpph))]
7933#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7934pub fn _mm256_rcp_ph(a: __m256h) -> __m256h {
7935    _mm256_mask_rcp_ph(_mm256_undefined_ph(), 0xffff, a)
7936}
7937
7938/// Compute the approximate reciprocal of packed 16-bit floating-point elements in `a` and stores the results in `dst`
7939/// using writemask `k` (elements are copied from `src` when the corresponding mask bit is not set).
7940/// The maximum relative error for this approximation is less than `1.5*2^-12`.
7941///
7942/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_rcp_ph)
7943#[inline]
7944#[target_feature(enable = "avx512fp16,avx512vl")]
7945#[cfg_attr(test, assert_instr(vrcpph))]
7946#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7947pub fn _mm256_mask_rcp_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h {
7948    unsafe { vrcpph_256(a, src, k) }
7949}
7950
7951/// Compute the approximate reciprocal of packed 16-bit floating-point elements in `a` and stores the results in `dst`
7952/// using zeromask `k` (elements are zeroed out when the corresponding mask bit is not set).
7953/// The maximum relative error for this approximation is less than `1.5*2^-12`.
7954///
7955/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_rcp_ph)
7956#[inline]
7957#[target_feature(enable = "avx512fp16,avx512vl")]
7958#[cfg_attr(test, assert_instr(vrcpph))]
7959#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7960pub fn _mm256_maskz_rcp_ph(k: __mmask16, a: __m256h) -> __m256h {
7961    _mm256_mask_rcp_ph(_mm256_setzero_ph(), k, a)
7962}
7963
7964/// Compute the approximate reciprocal of packed 16-bit floating-point elements in `a` and stores the results in `dst`.
7965/// The maximum relative error for this approximation is less than `1.5*2^-12`.
7966///
7967/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_rcp_ph)
7968#[inline]
7969#[target_feature(enable = "avx512fp16")]
7970#[cfg_attr(test, assert_instr(vrcpph))]
7971#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7972pub fn _mm512_rcp_ph(a: __m512h) -> __m512h {
7973    _mm512_mask_rcp_ph(_mm512_undefined_ph(), 0xffffffff, a)
7974}
7975
7976/// Compute the approximate reciprocal of packed 16-bit floating-point elements in `a` and stores the results in `dst`
7977/// using writemask `k` (elements are copied from `src` when the corresponding mask bit is not set).
7978/// The maximum relative error for this approximation is less than `1.5*2^-12`.
7979///
7980/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_rcp_ph)
7981#[inline]
7982#[target_feature(enable = "avx512fp16")]
7983#[cfg_attr(test, assert_instr(vrcpph))]
7984#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7985pub fn _mm512_mask_rcp_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h {
7986    unsafe { vrcpph_512(a, src, k) }
7987}
7988
7989/// Compute the approximate reciprocal of packed 16-bit floating-point elements in `a` and stores the results in `dst`
7990/// using zeromask `k` (elements are zeroed out when the corresponding mask bit is not set).
7991/// The maximum relative error for this approximation is less than `1.5*2^-12`.
7992///
7993/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_rcp_ph)
7994#[inline]
7995#[target_feature(enable = "avx512fp16")]
7996#[cfg_attr(test, assert_instr(vrcpph))]
7997#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
7998pub fn _mm512_maskz_rcp_ph(k: __mmask32, a: __m512h) -> __m512h {
7999    _mm512_mask_rcp_ph(_mm512_setzero_ph(), k, a)
8000}
8001
8002/// Compute the approximate reciprocal of the lower half-precision (16-bit) floating-point element in b,
8003/// store the result in the lower element of dst, and copy the upper 7 packed elements from a to the
8004/// upper elements of dst.
8005/// The maximum relative error for this approximation is less than `1.5*2^-12`.
8006///
8007/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_rcp_sh)
8008#[inline]
8009#[target_feature(enable = "avx512fp16")]
8010#[cfg_attr(test, assert_instr(vrcpsh))]
8011#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8012pub fn _mm_rcp_sh(a: __m128h, b: __m128h) -> __m128h {
8013    _mm_mask_rcp_sh(f16x8::ZERO.as_m128h(), 0xff, a, b)
8014}
8015
8016/// Compute the approximate reciprocal of the lower half-precision (16-bit) floating-point element in b,
8017/// store the result in the lower element of dst using writemask k (the element is copied from src when
8018/// mask bit 0 is not set), and copy the upper 7 packed elements from a to the upper elements of dst.
8019/// The maximum relative error for this approximation is less than `1.5*2^-12`.
8020///
8021/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_rcp_sh)
8022#[inline]
8023#[target_feature(enable = "avx512fp16")]
8024#[cfg_attr(test, assert_instr(vrcpsh))]
8025#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8026pub fn _mm_mask_rcp_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
8027    unsafe { vrcpsh(a, b, src, k) }
8028}
8029
8030/// Compute the approximate reciprocal of the lower half-precision (16-bit) floating-point element in b,
8031/// store the result in the lower element of dst using zeromask k (the element is zeroed out when mask bit 0
8032/// is not set), and copy the upper 7 packed elements from a to the upper elements of dst.
8033/// The maximum relative error for this approximation is less than `1.5*2^-12`.
8034///
8035/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_rcp_sh)
8036#[inline]
8037#[target_feature(enable = "avx512fp16")]
8038#[cfg_attr(test, assert_instr(vrcpsh))]
8039#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8040pub fn _mm_maskz_rcp_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
8041    _mm_mask_rcp_sh(f16x8::ZERO.as_m128h(), k, a, b)
8042}
8043
8044/// Compute the approximate reciprocal square root of packed half-precision (16-bit) floating-point
8045/// elements in a, and store the results in dst.
8046/// The maximum relative error for this approximation is less than `1.5*2^-12`.
8047///
8048/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_rsqrt_ph)
8049#[inline]
8050#[target_feature(enable = "avx512fp16,avx512vl")]
8051#[cfg_attr(test, assert_instr(vrsqrtph))]
8052#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8053pub fn _mm_rsqrt_ph(a: __m128h) -> __m128h {
8054    _mm_mask_rsqrt_ph(_mm_undefined_ph(), 0xff, a)
8055}
8056
8057/// Compute the approximate reciprocal square root of packed half-precision (16-bit) floating-point
8058/// elements in a, and store the results in dst using writemask k (elements are copied from src when
8059/// the corresponding mask bit is not set).
8060/// The maximum relative error for this approximation is less than `1.5*2^-12`.
8061///
8062/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_rsqrt_ph)
8063#[inline]
8064#[target_feature(enable = "avx512fp16,avx512vl")]
8065#[cfg_attr(test, assert_instr(vrsqrtph))]
8066#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8067pub fn _mm_mask_rsqrt_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h {
8068    unsafe { vrsqrtph_128(a, src, k) }
8069}
8070
8071/// Compute the approximate reciprocal square root of packed half-precision (16-bit) floating-point
8072/// elements in a, and store the results in dst using zeromask k (elements are zeroed out when the
8073/// corresponding mask bit is not set).
8074/// The maximum relative error for this approximation is less than `1.5*2^-12`.
8075///
8076/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_rsqrt_ph)
8077#[inline]
8078#[target_feature(enable = "avx512fp16,avx512vl")]
8079#[cfg_attr(test, assert_instr(vrsqrtph))]
8080#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8081pub fn _mm_maskz_rsqrt_ph(k: __mmask8, a: __m128h) -> __m128h {
8082    _mm_mask_rsqrt_ph(_mm_setzero_ph(), k, a)
8083}
8084
8085/// Compute the approximate reciprocal square root of packed half-precision (16-bit) floating-point
8086/// elements in a, and store the results in dst.
8087/// The maximum relative error for this approximation is less than `1.5*2^-12`.
8088///
8089/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_rsqrt_ph)
8090#[inline]
8091#[target_feature(enable = "avx512fp16,avx512vl")]
8092#[cfg_attr(test, assert_instr(vrsqrtph))]
8093#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8094pub fn _mm256_rsqrt_ph(a: __m256h) -> __m256h {
8095    _mm256_mask_rsqrt_ph(_mm256_undefined_ph(), 0xffff, a)
8096}
8097
8098/// Compute the approximate reciprocal square root of packed half-precision (16-bit) floating-point
8099/// elements in a, and store the results in dst using writemask k (elements are copied from src when
8100/// the corresponding mask bit is not set).
8101/// The maximum relative error for this approximation is less than `1.5*2^-12`.
8102///
8103/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_rsqrt_ph)
8104#[inline]
8105#[target_feature(enable = "avx512fp16,avx512vl")]
8106#[cfg_attr(test, assert_instr(vrsqrtph))]
8107#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8108pub fn _mm256_mask_rsqrt_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h {
8109    unsafe { vrsqrtph_256(a, src, k) }
8110}
8111
8112/// Compute the approximate reciprocal square root of packed half-precision (16-bit) floating-point
8113/// elements in a, and store the results in dst using zeromask k (elements are zeroed out when the
8114/// corresponding mask bit is not set).
8115/// The maximum relative error for this approximation is less than `1.5*2^-12`.
8116///
8117/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_rsqrt_ph)
8118#[inline]
8119#[target_feature(enable = "avx512fp16,avx512vl")]
8120#[cfg_attr(test, assert_instr(vrsqrtph))]
8121#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8122pub fn _mm256_maskz_rsqrt_ph(k: __mmask16, a: __m256h) -> __m256h {
8123    _mm256_mask_rsqrt_ph(_mm256_setzero_ph(), k, a)
8124}
8125
8126/// Compute the approximate reciprocal square root of packed half-precision (16-bit) floating-point
8127/// elements in a, and store the results in dst.
8128/// The maximum relative error for this approximation is less than `1.5*2^-12`.
8129///
8130/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_rsqrt_ph)
8131#[inline]
8132#[target_feature(enable = "avx512fp16")]
8133#[cfg_attr(test, assert_instr(vrsqrtph))]
8134#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8135pub fn _mm512_rsqrt_ph(a: __m512h) -> __m512h {
8136    _mm512_mask_rsqrt_ph(_mm512_undefined_ph(), 0xffffffff, a)
8137}
8138
8139/// Compute the approximate reciprocal square root of packed half-precision (16-bit) floating-point
8140/// elements in a, and store the results in dst using writemask k (elements are copied from src when
8141/// the corresponding mask bit is not set).
8142/// The maximum relative error for this approximation is less than `1.5*2^-12`.
8143///
8144/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_rsqrt_ph)
8145#[inline]
8146#[target_feature(enable = "avx512fp16")]
8147#[cfg_attr(test, assert_instr(vrsqrtph))]
8148#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8149pub fn _mm512_mask_rsqrt_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h {
8150    unsafe { vrsqrtph_512(a, src, k) }
8151}
8152
8153/// Compute the approximate reciprocal square root of packed half-precision (16-bit) floating-point
8154/// elements in a, and store the results in dst using zeromask k (elements are zeroed out when the
8155/// corresponding mask bit is not set).
8156/// The maximum relative error for this approximation is less than `1.5*2^-12`.
8157///
8158/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_rsqrt_ph)
8159#[inline]
8160#[target_feature(enable = "avx512fp16")]
8161#[cfg_attr(test, assert_instr(vrsqrtph))]
8162#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8163pub fn _mm512_maskz_rsqrt_ph(k: __mmask32, a: __m512h) -> __m512h {
8164    _mm512_mask_rsqrt_ph(_mm512_setzero_ph(), k, a)
8165}
8166
8167/// Compute the approximate reciprocal square root of the lower half-precision (16-bit) floating-point
8168/// element in b, store the result in the lower element of dst, and copy the upper 7 packed elements from a
8169/// to the upper elements of dst.
8170/// The maximum relative error for this approximation is less than `1.5*2^-12`.
8171///
8172/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_rsqrt_sh)
8173#[inline]
8174#[target_feature(enable = "avx512fp16")]
8175#[cfg_attr(test, assert_instr(vrsqrtsh))]
8176#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8177pub fn _mm_rsqrt_sh(a: __m128h, b: __m128h) -> __m128h {
8178    _mm_mask_rsqrt_sh(f16x8::ZERO.as_m128h(), 0xff, a, b)
8179}
8180
8181/// Compute the approximate reciprocal square root of the lower half-precision (16-bit) floating-point
8182/// element in b, store the result in the lower element of dst using writemask k (the element is copied from src
8183/// when mask bit 0 is not set), and copy the upper 7 packed elements from a to the upper elements of dst.
8184/// The maximum relative error for this approximation is less than `1.5*2^-12`.
8185///
8186/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_rsqrt_sh)
8187#[inline]
8188#[target_feature(enable = "avx512fp16")]
8189#[cfg_attr(test, assert_instr(vrsqrtsh))]
8190#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8191pub fn _mm_mask_rsqrt_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
8192    unsafe { vrsqrtsh(a, b, src, k) }
8193}
8194
8195/// Compute the approximate reciprocal square root of the lower half-precision (16-bit) floating-point
8196/// element in b, store the result in the lower element of dst using zeromask k (the element is zeroed out when
8197/// mask bit 0 is not set), and copy the upper 7 packed elements from a to the upper elements of dst.
8198/// The maximum relative error for this approximation is less than `1.5*2^-12`.
8199///
8200/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_rsqrt_sh)
8201#[inline]
8202#[target_feature(enable = "avx512fp16")]
8203#[cfg_attr(test, assert_instr(vrsqrtsh))]
8204#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8205pub fn _mm_maskz_rsqrt_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
8206    _mm_mask_rsqrt_sh(f16x8::ZERO.as_m128h(), k, a, b)
8207}
8208
8209/// Compute the square root of packed half-precision (16-bit) floating-point elements in a, and store the
8210/// results in dst.
8211///
8212/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sqrt_ph)
8213#[inline]
8214#[target_feature(enable = "avx512fp16,avx512vl")]
8215#[cfg_attr(test, assert_instr(vsqrtph))]
8216#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8217pub fn _mm_sqrt_ph(a: __m128h) -> __m128h {
8218    unsafe { simd_fsqrt(a) }
8219}
8220
8221/// Compute the square root of packed half-precision (16-bit) floating-point elements in a, and store the
8222/// results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
8223///
8224/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_sqrt_ph)
8225#[inline]
8226#[target_feature(enable = "avx512fp16,avx512vl")]
8227#[cfg_attr(test, assert_instr(vsqrtph))]
8228#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8229pub fn _mm_mask_sqrt_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h {
8230    unsafe { simd_select_bitmask(k, _mm_sqrt_ph(a), src) }
8231}
8232
8233/// Compute the square root of packed half-precision (16-bit) floating-point elements in a, and store the
8234/// results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
8235///
8236/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_sqrt_ph)
8237#[inline]
8238#[target_feature(enable = "avx512fp16,avx512vl")]
8239#[cfg_attr(test, assert_instr(vsqrtph))]
8240#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8241pub fn _mm_maskz_sqrt_ph(k: __mmask8, a: __m128h) -> __m128h {
8242    unsafe { simd_select_bitmask(k, _mm_sqrt_ph(a), _mm_setzero_ph()) }
8243}
8244
8245/// Compute the square root of packed half-precision (16-bit) floating-point elements in a, and store the
8246/// results in dst.
8247///
8248/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_sqrt_ph)
8249#[inline]
8250#[target_feature(enable = "avx512fp16,avx512vl")]
8251#[cfg_attr(test, assert_instr(vsqrtph))]
8252#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8253pub fn _mm256_sqrt_ph(a: __m256h) -> __m256h {
8254    unsafe { simd_fsqrt(a) }
8255}
8256
8257/// Compute the square root of packed half-precision (16-bit) floating-point elements in a, and store the
8258/// results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
8259///
8260/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_sqrt_ph)
8261#[inline]
8262#[target_feature(enable = "avx512fp16,avx512vl")]
8263#[cfg_attr(test, assert_instr(vsqrtph))]
8264#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8265pub fn _mm256_mask_sqrt_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h {
8266    unsafe { simd_select_bitmask(k, _mm256_sqrt_ph(a), src) }
8267}
8268
8269/// Compute the square root of packed half-precision (16-bit) floating-point elements in a, and store the
8270/// results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
8271///
8272/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_sqrt_ph)
8273#[inline]
8274#[target_feature(enable = "avx512fp16,avx512vl")]
8275#[cfg_attr(test, assert_instr(vsqrtph))]
8276#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8277pub fn _mm256_maskz_sqrt_ph(k: __mmask16, a: __m256h) -> __m256h {
8278    unsafe { simd_select_bitmask(k, _mm256_sqrt_ph(a), _mm256_setzero_ph()) }
8279}
8280
8281/// Compute the square root of packed half-precision (16-bit) floating-point elements in a, and store the
8282/// results in dst.
8283///
8284/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_sqrt_ph)
8285#[inline]
8286#[target_feature(enable = "avx512fp16")]
8287#[cfg_attr(test, assert_instr(vsqrtph))]
8288#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8289pub fn _mm512_sqrt_ph(a: __m512h) -> __m512h {
8290    unsafe { simd_fsqrt(a) }
8291}
8292
8293/// Compute the square root of packed half-precision (16-bit) floating-point elements in a, and store the
8294/// results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
8295///
8296/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_sqrt_ph)
8297#[inline]
8298#[target_feature(enable = "avx512fp16")]
8299#[cfg_attr(test, assert_instr(vsqrtph))]
8300#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8301pub fn _mm512_mask_sqrt_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h {
8302    unsafe { simd_select_bitmask(k, _mm512_sqrt_ph(a), src) }
8303}
8304
8305/// Compute the square root of packed half-precision (16-bit) floating-point elements in a, and store the
8306/// results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
8307///
8308/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_sqrt_ph)
8309#[inline]
8310#[target_feature(enable = "avx512fp16")]
8311#[cfg_attr(test, assert_instr(vsqrtph))]
8312#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8313pub fn _mm512_maskz_sqrt_ph(k: __mmask32, a: __m512h) -> __m512h {
8314    unsafe { simd_select_bitmask(k, _mm512_sqrt_ph(a), _mm512_setzero_ph()) }
8315}
8316
8317/// Compute the square root of packed half-precision (16-bit) floating-point elements in a, and store the
8318/// results in dst.
8319/// Rounding is done according to the rounding parameter, which can be one of:
8320///
8321/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
8322/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
8323/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
8324/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
8325/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
8326///
8327/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_sqrt_round_ph)
8328#[inline]
8329#[target_feature(enable = "avx512fp16")]
8330#[cfg_attr(test, assert_instr(vsqrtph, ROUNDING = 8))]
8331#[rustc_legacy_const_generics(1)]
8332#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8333pub fn _mm512_sqrt_round_ph<const ROUNDING: i32>(a: __m512h) -> __m512h {
8334    unsafe {
8335        static_assert_rounding!(ROUNDING);
8336        vsqrtph_512(a, ROUNDING)
8337    }
8338}
8339
8340/// Compute the square root of packed half-precision (16-bit) floating-point elements in a, and store the
8341/// results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
8342/// Rounding is done according to the rounding parameter, which can be one of:
8343///
8344/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
8345/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
8346/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
8347/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
8348/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
8349///
8350/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_sqrt_round_ph)
8351#[inline]
8352#[target_feature(enable = "avx512fp16")]
8353#[cfg_attr(test, assert_instr(vsqrtph, ROUNDING = 8))]
8354#[rustc_legacy_const_generics(3)]
8355#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8356pub fn _mm512_mask_sqrt_round_ph<const ROUNDING: i32>(
8357    src: __m512h,
8358    k: __mmask32,
8359    a: __m512h,
8360) -> __m512h {
8361    unsafe {
8362        static_assert_rounding!(ROUNDING);
8363        simd_select_bitmask(k, _mm512_sqrt_round_ph::<ROUNDING>(a), src)
8364    }
8365}
8366
8367/// Compute the square root of packed half-precision (16-bit) floating-point elements in a, and store the
8368/// results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
8369/// Rounding is done according to the rounding parameter, which can be one of:
8370///
8371/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
8372/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
8373/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
8374/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
8375/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
8376///
8377/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_sqrt_round_ph)
8378#[inline]
8379#[target_feature(enable = "avx512fp16")]
8380#[cfg_attr(test, assert_instr(vsqrtph, ROUNDING = 8))]
8381#[rustc_legacy_const_generics(2)]
8382#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8383pub fn _mm512_maskz_sqrt_round_ph<const ROUNDING: i32>(k: __mmask32, a: __m512h) -> __m512h {
8384    unsafe {
8385        static_assert_rounding!(ROUNDING);
8386        simd_select_bitmask(k, _mm512_sqrt_round_ph::<ROUNDING>(a), _mm512_setzero_ph())
8387    }
8388}
8389
8390/// Compute the square root of the lower half-precision (16-bit) floating-point element in b, store
8391/// the result in the lower element of dst, and copy the upper 7 packed elements from a to the upper
8392/// elements of dst.
8393///
8394/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sqrt_sh)
8395#[inline]
8396#[target_feature(enable = "avx512fp16")]
8397#[cfg_attr(test, assert_instr(vsqrtsh))]
8398#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8399pub fn _mm_sqrt_sh(a: __m128h, b: __m128h) -> __m128h {
8400    _mm_mask_sqrt_sh(f16x8::ZERO.as_m128h(), 0xff, a, b)
8401}
8402
8403/// Compute the square root of the lower half-precision (16-bit) floating-point element in b, store
8404/// the result in the lower element of dst using writemask k (the element is copied from src when mask
8405/// bit 0 is not set), and copy the upper 7 packed elements from a to the upper elements of dst.
8406///
8407/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_sqrt_sh)
8408#[inline]
8409#[target_feature(enable = "avx512fp16")]
8410#[cfg_attr(test, assert_instr(vsqrtsh))]
8411#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8412pub fn _mm_mask_sqrt_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
8413    _mm_mask_sqrt_round_sh::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b)
8414}
8415
8416/// Compute the square root of the lower half-precision (16-bit) floating-point element in b, store
8417/// the result in the lower element of dst using zeromask k (the element is zeroed out when mask bit 0
8418/// is not set), and copy the upper 7 packed elements from a to the upper elements of dst.
8419///
8420/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_sqrt_sh)
8421#[inline]
8422#[target_feature(enable = "avx512fp16")]
8423#[cfg_attr(test, assert_instr(vsqrtsh))]
8424#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8425pub fn _mm_maskz_sqrt_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
8426    _mm_mask_sqrt_sh(f16x8::ZERO.as_m128h(), k, a, b)
8427}
8428
8429/// Compute the square root of the lower half-precision (16-bit) floating-point element in b, store
8430/// the result in the lower element of dst, and copy the upper 7 packed elements from a to the upper
8431/// elements of dst.
8432/// Rounding is done according to the rounding parameter, which can be one of:
8433///
8434/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
8435/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
8436/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
8437/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
8438/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
8439///
8440/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sqrt_round_sh)
8441#[inline]
8442#[target_feature(enable = "avx512fp16")]
8443#[cfg_attr(test, assert_instr(vsqrtsh, ROUNDING = 8))]
8444#[rustc_legacy_const_generics(2)]
8445#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8446pub fn _mm_sqrt_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128h {
8447    static_assert_rounding!(ROUNDING);
8448    _mm_mask_sqrt_round_sh::<ROUNDING>(f16x8::ZERO.as_m128h(), 0xff, a, b)
8449}
8450
8451/// Compute the square root of the lower half-precision (16-bit) floating-point element in b, store
8452/// the result in the lower element of dst using writemask k (the element is copied from src when mask
8453/// bit 0 is not set), and copy the upper 7 packed elements from a to the upper elements of dst.
8454/// Rounding is done according to the rounding parameter, which can be one of:
8455///
8456/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
8457/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
8458/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
8459/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
8460/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
8461///
8462/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_sqrt_round_sh)
8463#[inline]
8464#[target_feature(enable = "avx512fp16")]
8465#[cfg_attr(test, assert_instr(vsqrtsh, ROUNDING = 8))]
8466#[rustc_legacy_const_generics(4)]
8467#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8468pub fn _mm_mask_sqrt_round_sh<const ROUNDING: i32>(
8469    src: __m128h,
8470    k: __mmask8,
8471    a: __m128h,
8472    b: __m128h,
8473) -> __m128h {
8474    unsafe {
8475        static_assert_rounding!(ROUNDING);
8476        vsqrtsh(a, b, src, k, ROUNDING)
8477    }
8478}
8479
8480/// Compute the square root of the lower half-precision (16-bit) floating-point element in b, store
8481/// the result in the lower element of dst using zeromask k (the element is zeroed out when mask bit 0
8482/// is not set), and copy the upper 7 packed elements from a to the upper elements of dst.
8483/// Rounding is done according to the rounding parameter, which can be one of:
8484///
8485/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
8486/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
8487/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
8488/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
8489/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
8490///
8491/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_sqrt_round_sh)
8492#[inline]
8493#[target_feature(enable = "avx512fp16")]
8494#[cfg_attr(test, assert_instr(vsqrtsh, ROUNDING = 8))]
8495#[rustc_legacy_const_generics(3)]
8496#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8497pub fn _mm_maskz_sqrt_round_sh<const ROUNDING: i32>(
8498    k: __mmask8,
8499    a: __m128h,
8500    b: __m128h,
8501) -> __m128h {
8502    static_assert_rounding!(ROUNDING);
8503    _mm_mask_sqrt_round_sh::<ROUNDING>(f16x8::ZERO.as_m128h(), k, a, b)
8504}
8505
8506/// Compare packed half-precision (16-bit) floating-point elements in a and b, and store packed maximum
8507/// values in dst. Does not follow the IEEE Standard for Floating-Point Arithmetic (IEEE 754) maximum
8508/// value when inputs are NaN or signed-zero values.
8509///
8510/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_max_ph)
8511#[inline]
8512#[target_feature(enable = "avx512fp16,avx512vl")]
8513#[cfg_attr(test, assert_instr(vmaxph))]
8514#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8515pub fn _mm_max_ph(a: __m128h, b: __m128h) -> __m128h {
8516    unsafe { vmaxph_128(a, b) }
8517}
8518
8519/// Compare packed half-precision (16-bit) floating-point elements in a and b, and store packed maximum
8520/// values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
8521/// Does not follow the IEEE Standard for Floating-Point Arithmetic (IEEE 754) maximum value when inputs are
8522/// NaN or signed-zero values.
8523///
8524/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_max_ph)
8525#[inline]
8526#[target_feature(enable = "avx512fp16,avx512vl")]
8527#[cfg_attr(test, assert_instr(vmaxph))]
8528#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8529pub fn _mm_mask_max_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
8530    unsafe { simd_select_bitmask(k, _mm_max_ph(a, b), src) }
8531}
8532
8533/// Compare packed half-precision (16-bit) floating-point elements in a and b, and store packed maximum
8534/// values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
8535/// Does not follow the IEEE Standard for Floating-Point Arithmetic (IEEE 754) maximum value when inputs are
8536/// NaN or signed-zero values.
8537///
8538/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_max_ph)
8539#[inline]
8540#[target_feature(enable = "avx512fp16,avx512vl")]
8541#[cfg_attr(test, assert_instr(vmaxph))]
8542#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8543pub fn _mm_maskz_max_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
8544    unsafe { simd_select_bitmask(k, _mm_max_ph(a, b), _mm_setzero_ph()) }
8545}
8546
8547/// Compare packed half-precision (16-bit) floating-point elements in a and b, and store packed maximum
8548/// values in dst. Does not follow the IEEE Standard for Floating-Point Arithmetic (IEEE 754) maximum
8549/// value when inputs are NaN or signed-zero values.
8550///
8551/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_max_ph)
8552#[inline]
8553#[target_feature(enable = "avx512fp16,avx512vl")]
8554#[cfg_attr(test, assert_instr(vmaxph))]
8555#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8556pub fn _mm256_max_ph(a: __m256h, b: __m256h) -> __m256h {
8557    unsafe { vmaxph_256(a, b) }
8558}
8559
8560/// Compare packed half-precision (16-bit) floating-point elements in a and b, and store packed maximum
8561/// values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
8562/// Does not follow the IEEE Standard for Floating-Point Arithmetic (IEEE 754) maximum value when inputs are
8563/// NaN or signed-zero values.
8564///
8565/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_max_ph)
8566#[inline]
8567#[target_feature(enable = "avx512fp16,avx512vl")]
8568#[cfg_attr(test, assert_instr(vmaxph))]
8569#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8570pub fn _mm256_mask_max_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
8571    unsafe { simd_select_bitmask(k, _mm256_max_ph(a, b), src) }
8572}
8573
8574/// Compare packed half-precision (16-bit) floating-point elements in a and b, and store packed maximum
8575/// values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
8576/// Does not follow the IEEE Standard for Floating-Point Arithmetic (IEEE 754) maximum value when inputs are
8577/// NaN or signed-zero values.
8578///
8579/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_max_ph)
8580#[inline]
8581#[target_feature(enable = "avx512fp16,avx512vl")]
8582#[cfg_attr(test, assert_instr(vmaxph))]
8583#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8584pub fn _mm256_maskz_max_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
8585    unsafe { simd_select_bitmask(k, _mm256_max_ph(a, b), _mm256_setzero_ph()) }
8586}
8587
8588/// Compare packed half-precision (16-bit) floating-point elements in a and b, and store packed maximum
8589/// values in dst. Does not follow the IEEE Standard for Floating-Point Arithmetic (IEEE 754) maximum
8590/// value when inputs are NaN or signed-zero values.
8591///
8592/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_max_ph)
8593#[inline]
8594#[target_feature(enable = "avx512fp16")]
8595#[cfg_attr(test, assert_instr(vmaxph))]
8596#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8597pub fn _mm512_max_ph(a: __m512h, b: __m512h) -> __m512h {
8598    _mm512_max_round_ph::<_MM_FROUND_CUR_DIRECTION>(a, b)
8599}
8600
8601/// Compare packed half-precision (16-bit) floating-point elements in a and b, and store packed maximum
8602/// values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
8603/// Does not follow the IEEE Standard for Floating-Point Arithmetic (IEEE 754) maximum value when inputs are
8604/// NaN or signed-zero values.
8605///
8606/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_max_ph)
8607#[inline]
8608#[target_feature(enable = "avx512fp16")]
8609#[cfg_attr(test, assert_instr(vmaxph))]
8610#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8611pub fn _mm512_mask_max_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
8612    unsafe { simd_select_bitmask(k, _mm512_max_ph(a, b), src) }
8613}
8614
8615/// Compare packed half-precision (16-bit) floating-point elements in a and b, and store packed maximum
8616/// values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
8617/// Does not follow the IEEE Standard for Floating-Point Arithmetic (IEEE 754) maximum value when inputs are
8618/// NaN or signed-zero values.
8619///
8620/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_max_ph)
8621#[inline]
8622#[target_feature(enable = "avx512fp16")]
8623#[cfg_attr(test, assert_instr(vmaxph))]
8624#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8625pub fn _mm512_maskz_max_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
8626    unsafe { simd_select_bitmask(k, _mm512_max_ph(a, b), _mm512_setzero_ph()) }
8627}
8628
8629/// Compare packed half-precision (16-bit) floating-point elements in a and b, and store packed maximum
8630/// values in dst. Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
8631/// Does not follow the IEEE Standard for Floating-Point Arithmetic (IEEE 754) maximum value when inputs are
8632/// NaN or signed-zero values.
8633///
8634/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_max_round_ph)
8635#[inline]
8636#[target_feature(enable = "avx512fp16")]
8637#[cfg_attr(test, assert_instr(vmaxph, SAE = 8))]
8638#[rustc_legacy_const_generics(2)]
8639#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8640pub fn _mm512_max_round_ph<const SAE: i32>(a: __m512h, b: __m512h) -> __m512h {
8641    unsafe {
8642        static_assert_sae!(SAE);
8643        vmaxph_512(a, b, SAE)
8644    }
8645}
8646
8647/// Compare packed half-precision (16-bit) floating-point elements in a and b, and store packed maximum
8648/// values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
8649/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter. Does not follow the
8650/// IEEE Standard for Floating-Point Arithmetic (IEEE 754) maximum value when inputs are NaN or signed-zero values.
8651///
8652/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_max_round_ph)
8653#[inline]
8654#[target_feature(enable = "avx512fp16")]
8655#[cfg_attr(test, assert_instr(vmaxph, SAE = 8))]
8656#[rustc_legacy_const_generics(4)]
8657#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8658pub fn _mm512_mask_max_round_ph<const SAE: i32>(
8659    src: __m512h,
8660    k: __mmask32,
8661    a: __m512h,
8662    b: __m512h,
8663) -> __m512h {
8664    unsafe {
8665        static_assert_sae!(SAE);
8666        simd_select_bitmask(k, _mm512_max_round_ph::<SAE>(a, b), src)
8667    }
8668}
8669
8670/// Compare packed half-precision (16-bit) floating-point elements in a and b, and store packed maximum
8671/// values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
8672/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter. Does not follow the
8673/// IEEE Standard for Floating-Point Arithmetic (IEEE 754) maximum value when inputs are NaN or signed-zero values.
8674///
8675/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_max_round_ph)
8676#[inline]
8677#[target_feature(enable = "avx512fp16")]
8678#[cfg_attr(test, assert_instr(vmaxph, SAE = 8))]
8679#[rustc_legacy_const_generics(3)]
8680#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8681pub fn _mm512_maskz_max_round_ph<const SAE: i32>(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
8682    unsafe {
8683        static_assert_sae!(SAE);
8684        simd_select_bitmask(k, _mm512_max_round_ph::<SAE>(a, b), _mm512_setzero_ph())
8685    }
8686}
8687
8688/// Compare the lower half-precision (16-bit) floating-point elements in a and b, store the maximum
8689/// value in the lower element of dst, and copy the upper 7 packed elements from a to the upper elements
8690/// of dst. Does not follow the IEEE Standard for Floating-Point Arithmetic (IEEE 754) maximum value
8691/// when inputs are NaN or signed-zero values.
8692///
8693/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_max_sh)
8694#[inline]
8695#[target_feature(enable = "avx512fp16,avx512vl")]
8696#[cfg_attr(test, assert_instr(vmaxsh))]
8697#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8698pub fn _mm_max_sh(a: __m128h, b: __m128h) -> __m128h {
8699    _mm_mask_max_sh(_mm_undefined_ph(), 0xff, a, b)
8700}
8701
8702/// Compare the lower half-precision (16-bit) floating-point elements in a and b, store the maximum
8703/// value in the lower element of dst using writemask k (the element is copied from src when mask bit 0
8704/// is not set), and copy the upper 7 packed elements from a to the upper elements of dst. Does not follow
8705/// the IEEE Standard for Floating-Point Arithmetic (IEEE 754) maximum value when inputs are NaN or signed-zero values.
8706///
8707/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_max_sh)
8708#[inline]
8709#[target_feature(enable = "avx512fp16,avx512vl")]
8710#[cfg_attr(test, assert_instr(vmaxsh))]
8711#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8712pub fn _mm_mask_max_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
8713    _mm_mask_max_round_sh::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b)
8714}
8715
8716/// Compare the lower half-precision (16-bit) floating-point elements in a and b, store the maximum value
8717/// in the lower element of dst using zeromask k (the element is zeroed out when mask bit 0 is not set), and
8718/// copy the upper 7 packed elements from a to the upper elements of dst. Does not follow the IEEE Standard
8719/// for Floating-Point Arithmetic (IEEE 754) maximum value when inputs are NaN or signed-zero values.
8720///
8721/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_max_sh)
8722#[inline]
8723#[target_feature(enable = "avx512fp16,avx512vl")]
8724#[cfg_attr(test, assert_instr(vmaxsh))]
8725#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8726pub fn _mm_maskz_max_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
8727    _mm_mask_max_sh(f16x8::ZERO.as_m128h(), k, a, b)
8728}
8729
8730/// Compare the lower half-precision (16-bit) floating-point elements in a and b, store the maximum value
8731/// in the lower element of dst, and copy the upper 7 packed elements from a to the upper elements of dst.
8732/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter. Does not follow the
8733/// IEEE Standard for Floating-Point Arithmetic (IEEE 754) maximum value when inputs are NaN or signed-zero values.
8734///
8735/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_max_round_sh)
8736#[inline]
8737#[target_feature(enable = "avx512fp16,avx512vl")]
8738#[cfg_attr(test, assert_instr(vmaxsh, SAE = 8))]
8739#[rustc_legacy_const_generics(2)]
8740#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8741pub fn _mm_max_round_sh<const SAE: i32>(a: __m128h, b: __m128h) -> __m128h {
8742    static_assert_sae!(SAE);
8743    _mm_mask_max_round_sh::<SAE>(_mm_undefined_ph(), 0xff, a, b)
8744}
8745
8746/// Compare the lower half-precision (16-bit) floating-point elements in a and b, store the maximum value
8747/// in the lower element of dst using writemask k (the element is copied from src when mask bit 0 is not set),
8748/// and copy the upper 7 packed elements from a to the upper elements of dst. Exceptions can be suppressed by
8749/// passing _MM_FROUND_NO_EXC in the sae parameter. Does not follow the IEEE Standard for Floating-Point Arithmetic
8750/// (IEEE 754) maximum value when inputs are NaN or signed-zero values.
8751///
8752/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_max_round_sh)
8753#[inline]
8754#[target_feature(enable = "avx512fp16,avx512vl")]
8755#[cfg_attr(test, assert_instr(vmaxsh, SAE = 8))]
8756#[rustc_legacy_const_generics(4)]
8757#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8758pub fn _mm_mask_max_round_sh<const SAE: i32>(
8759    src: __m128h,
8760    k: __mmask8,
8761    a: __m128h,
8762    b: __m128h,
8763) -> __m128h {
8764    unsafe {
8765        static_assert_sae!(SAE);
8766        vmaxsh(a, b, src, k, SAE)
8767    }
8768}
8769
8770/// Compare the lower half-precision (16-bit) floating-point elements in a and b, store the maximum value
8771/// in the lower element of dst using zeromask k (the element is zeroed out when mask bit 0 is not set), and
8772/// copy the upper 7 packed elements from a to the upper elements of dst. Exceptions can be suppressed by
8773/// passing _MM_FROUND_NO_EXC in the sae parameter. Does not follow the IEEE Standard for Floating-Point Arithmetic
8774/// (IEEE 754) maximum value when inputs are NaN or signed-zero values.
8775///
8776/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_max_round_sh)
8777#[inline]
8778#[target_feature(enable = "avx512fp16,avx512vl")]
8779#[cfg_attr(test, assert_instr(vmaxsh, SAE = 8))]
8780#[rustc_legacy_const_generics(3)]
8781#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8782pub fn _mm_maskz_max_round_sh<const SAE: i32>(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
8783    static_assert_sae!(SAE);
8784    _mm_mask_max_round_sh::<SAE>(f16x8::ZERO.as_m128h(), k, a, b)
8785}
8786
8787/// Compare packed half-precision (16-bit) floating-point elements in a and b, and store packed minimum
8788/// values in dst. Does not follow the IEEE Standard for Floating-Point Arithmetic (IEEE 754) minimum value
8789/// when inputs are NaN or signed-zero values.
8790///
8791/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_min_ph)
8792#[inline]
8793#[target_feature(enable = "avx512fp16,avx512vl")]
8794#[cfg_attr(test, assert_instr(vminph))]
8795#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8796pub fn _mm_min_ph(a: __m128h, b: __m128h) -> __m128h {
8797    unsafe { vminph_128(a, b) }
8798}
8799
8800/// Compare packed half-precision (16-bit) floating-point elements in a and b, and store packed minimum
8801/// values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
8802/// Does not follow the IEEE Standard for Floating-Point Arithmetic (IEEE 754) minimum value when inputs are
8803/// NaN or signed-zero values.
8804///
8805/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_min_ph)
8806#[inline]
8807#[target_feature(enable = "avx512fp16,avx512vl")]
8808#[cfg_attr(test, assert_instr(vminph))]
8809#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8810pub fn _mm_mask_min_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
8811    unsafe { simd_select_bitmask(k, _mm_min_ph(a, b), src) }
8812}
8813
8814/// Compare packed half-precision (16-bit) floating-point elements in a and b, and store packed minimum
8815/// values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
8816/// Does not follow the IEEE Standard for Floating-Point Arithmetic (IEEE 754) minimum value when inputs are
8817/// NaN or signed-zero values.
8818///
8819/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_min_ph)
8820#[inline]
8821#[target_feature(enable = "avx512fp16,avx512vl")]
8822#[cfg_attr(test, assert_instr(vminph))]
8823#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8824pub fn _mm_maskz_min_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
8825    unsafe { simd_select_bitmask(k, _mm_min_ph(a, b), _mm_setzero_ph()) }
8826}
8827
8828/// Compare packed half-precision (16-bit) floating-point elements in a and b, and store packed minimum
8829/// values in dst. Does not follow the IEEE Standard for Floating-Point Arithmetic (IEEE 754) minimum value
8830/// when inputs are NaN or signed-zero values.
8831///
8832/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_min_ph)
8833#[inline]
8834#[target_feature(enable = "avx512fp16,avx512vl")]
8835#[cfg_attr(test, assert_instr(vminph))]
8836#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8837pub fn _mm256_min_ph(a: __m256h, b: __m256h) -> __m256h {
8838    unsafe { vminph_256(a, b) }
8839}
8840
8841/// Compare packed half-precision (16-bit) floating-point elements in a and b, and store packed minimum
8842/// values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
8843/// Does not follow the IEEE Standard for Floating-Point Arithmetic (IEEE 754) minimum value when inputs are
8844/// NaN or signed-zero values.
8845///
8846/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_min_ph)
8847#[inline]
8848#[target_feature(enable = "avx512fp16,avx512vl")]
8849#[cfg_attr(test, assert_instr(vminph))]
8850#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8851pub fn _mm256_mask_min_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
8852    unsafe { simd_select_bitmask(k, _mm256_min_ph(a, b), src) }
8853}
8854
8855/// Compare packed half-precision (16-bit) floating-point elements in a and b, and store packed minimum
8856/// values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
8857/// Does not follow the IEEE Standard for Floating-Point Arithmetic (IEEE 754) minimum value when inputs are
8858/// NaN or signed-zero values.
8859///
8860/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_min_ph)
8861#[inline]
8862#[target_feature(enable = "avx512fp16,avx512vl")]
8863#[cfg_attr(test, assert_instr(vminph))]
8864#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8865pub fn _mm256_maskz_min_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
8866    unsafe { simd_select_bitmask(k, _mm256_min_ph(a, b), _mm256_setzero_ph()) }
8867}
8868
8869/// Compare packed half-precision (16-bit) floating-point elements in a and b, and store packed minimum
8870/// values in dst. Does not follow the IEEE Standard for Floating-Point Arithmetic (IEEE 754) minimum value
8871/// when inputs are NaN or signed-zero values.
8872///
8873/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_min_ph)
8874#[inline]
8875#[target_feature(enable = "avx512fp16")]
8876#[cfg_attr(test, assert_instr(vminph))]
8877#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8878pub fn _mm512_min_ph(a: __m512h, b: __m512h) -> __m512h {
8879    _mm512_min_round_ph::<_MM_FROUND_CUR_DIRECTION>(a, b)
8880}
8881
8882/// Compare packed half-precision (16-bit) floating-point elements in a and b, and store packed minimum
8883/// values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
8884/// Does not follow the IEEE Standard for Floating-Point Arithmetic (IEEE 754) minimum value when inputs are
8885/// NaN or signed-zero values.
8886///
8887/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_min_ph)
8888#[inline]
8889#[target_feature(enable = "avx512fp16")]
8890#[cfg_attr(test, assert_instr(vminph))]
8891#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8892pub fn _mm512_mask_min_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
8893    unsafe { simd_select_bitmask(k, _mm512_min_ph(a, b), src) }
8894}
8895
8896/// Compare packed half-precision (16-bit) floating-point elements in a and b, and store packed minimum
8897/// values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
8898/// Does not follow the IEEE Standard for Floating-Point Arithmetic (IEEE 754) minimum value when inputs are
8899/// NaN or signed-zero values.
8900///
8901/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_min_ph)
8902#[inline]
8903#[target_feature(enable = "avx512fp16")]
8904#[cfg_attr(test, assert_instr(vminph))]
8905#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8906pub fn _mm512_maskz_min_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
8907    unsafe { simd_select_bitmask(k, _mm512_min_ph(a, b), _mm512_setzero_ph()) }
8908}
8909
8910/// Compare packed half-precision (16-bit) floating-point elements in a and b, and store packed minimum
8911/// values in dst. Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter. Does not
8912/// follow the IEEE Standard for Floating-Point Arithmetic (IEEE 754) minimum value when inputs are NaN or signed-zero values.
8913///
8914/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_min_round_ph)
8915#[inline]
8916#[target_feature(enable = "avx512fp16")]
8917#[cfg_attr(test, assert_instr(vminph, SAE = 8))]
8918#[rustc_legacy_const_generics(2)]
8919#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8920pub fn _mm512_min_round_ph<const SAE: i32>(a: __m512h, b: __m512h) -> __m512h {
8921    unsafe {
8922        static_assert_sae!(SAE);
8923        vminph_512(a, b, SAE)
8924    }
8925}
8926
8927/// Compare packed half-precision (16-bit) floating-point elements in a and b, and store packed minimum
8928/// values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
8929/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter. Does not follow the
8930/// IEEE Standard for Floating-Point Arithmetic (IEEE 754) minimum value when inputs are NaN or signed-zero values.
8931///
8932/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_min_round_ph)
8933#[inline]
8934#[target_feature(enable = "avx512fp16")]
8935#[cfg_attr(test, assert_instr(vminph, SAE = 8))]
8936#[rustc_legacy_const_generics(4)]
8937#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8938pub fn _mm512_mask_min_round_ph<const SAE: i32>(
8939    src: __m512h,
8940    k: __mmask32,
8941    a: __m512h,
8942    b: __m512h,
8943) -> __m512h {
8944    unsafe {
8945        static_assert_sae!(SAE);
8946        simd_select_bitmask(k, _mm512_min_round_ph::<SAE>(a, b), src)
8947    }
8948}
8949
8950/// Compare packed half-precision (16-bit) floating-point elements in a and b, and store packed minimum
8951/// values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
8952/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter. Does not follow the
8953/// IEEE Standard for Floating-Point Arithmetic (IEEE 754) minimum value when inputs are NaN or signed-zero values.
8954///
8955/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_min_round_ph)
8956#[inline]
8957#[target_feature(enable = "avx512fp16")]
8958#[cfg_attr(test, assert_instr(vminph, SAE = 8))]
8959#[rustc_legacy_const_generics(3)]
8960#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8961pub fn _mm512_maskz_min_round_ph<const SAE: i32>(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
8962    unsafe {
8963        static_assert_sae!(SAE);
8964        simd_select_bitmask(k, _mm512_min_round_ph::<SAE>(a, b), _mm512_setzero_ph())
8965    }
8966}
8967
8968/// Compare the lower half-precision (16-bit) floating-point elements in a and b, store the minimum
8969/// value in the lower element of dst, and copy the upper 7 packed elements from a to the upper elements
8970/// of dst. Does not follow the IEEE Standard for Floating-Point Arithmetic (IEEE 754) minimum value when
8971/// inputs are NaN or signed-zero values.
8972///
8973/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_min_sh)
8974#[inline]
8975#[target_feature(enable = "avx512fp16,avx512vl")]
8976#[cfg_attr(test, assert_instr(vminsh))]
8977#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8978pub fn _mm_min_sh(a: __m128h, b: __m128h) -> __m128h {
8979    _mm_mask_min_sh(_mm_undefined_ph(), 0xff, a, b)
8980}
8981
8982/// Compare the lower half-precision (16-bit) floating-point elements in a and b, store the minimum
8983/// value in the lower element of dst using writemask k (the element is copied from src when mask bit 0
8984/// is not set), and copy the upper 7 packed elements from a to the upper elements of dst. Does not follow
8985/// the IEEE Standard for Floating-Point Arithmetic (IEEE 754) minimum value when inputs are NaN or signed-zero values.
8986///
8987/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_min_sh)
8988#[inline]
8989#[target_feature(enable = "avx512fp16,avx512vl")]
8990#[cfg_attr(test, assert_instr(vminsh))]
8991#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
8992pub fn _mm_mask_min_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
8993    _mm_mask_min_round_sh::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b)
8994}
8995
8996/// Compare the lower half-precision (16-bit) floating-point elements in a and b, store the minimum value
8997/// in the lower element of dst using zeromask k (the element is zeroed out when mask bit 0 is not set), and
8998/// copy the upper 7 packed elements from a to the upper elements of dst. Does not follow the IEEE Standard
8999/// for Floating-Point Arithmetic (IEEE 754) minimum value when inputs are NaN or signed-zero values.
9000///
9001/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_min_sh)
9002#[inline]
9003#[target_feature(enable = "avx512fp16,avx512vl")]
9004#[cfg_attr(test, assert_instr(vminsh))]
9005#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
9006pub fn _mm_maskz_min_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
9007    _mm_mask_min_sh(f16x8::ZERO.as_m128h(), k, a, b)
9008}
9009
9010/// Compare the lower half-precision (16-bit) floating-point elements in a and b, store the minimum value
9011/// in the lower element of dst, and copy the upper 7 packed elements from a to the upper elements of dst.
9012/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter. Does not follow the
9013/// IEEE Standard for Floating-Point Arithmetic (IEEE 754) minimum value when inputs are NaN or signed-zero values.
9014///
9015/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_min_round_sh)
9016#[inline]
9017#[target_feature(enable = "avx512fp16,avx512vl")]
9018#[cfg_attr(test, assert_instr(vminsh, SAE = 8))]
9019#[rustc_legacy_const_generics(2)]
9020#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
9021pub fn _mm_min_round_sh<const SAE: i32>(a: __m128h, b: __m128h) -> __m128h {
9022    static_assert_sae!(SAE);
9023    _mm_mask_min_round_sh::<SAE>(_mm_undefined_ph(), 0xff, a, b)
9024}
9025
9026/// Compare the lower half-precision (16-bit) floating-point elements in a and b, store the minimum value
9027/// in the lower element of dst using writemask k (the element is copied from src when mask bit 0 is not set),
9028/// and copy the upper 7 packed elements from a to the upper elements of dst. Exceptions can be suppressed by
9029/// passing _MM_FROUND_NO_EXC in the sae parameter. Does not follow the IEEE Standard for Floating-Point Arithmetic
9030/// (IEEE 754) minimum value when inputs are NaN or signed-zero values.
9031///
9032/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_min_round_sh)
9033#[inline]
9034#[target_feature(enable = "avx512fp16,avx512vl")]
9035#[cfg_attr(test, assert_instr(vminsh, SAE = 8))]
9036#[rustc_legacy_const_generics(4)]
9037#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
9038pub fn _mm_mask_min_round_sh<const SAE: i32>(
9039    src: __m128h,
9040    k: __mmask8,
9041    a: __m128h,
9042    b: __m128h,
9043) -> __m128h {
9044    unsafe {
9045        static_assert_sae!(SAE);
9046        vminsh(a, b, src, k, SAE)
9047    }
9048}
9049
9050/// Compare the lower half-precision (16-bit) floating-point elements in a and b, store the minimum value
9051/// in the lower element of dst using zeromask k (the element is zeroed out when mask bit 0 is not set), and
9052/// copy the upper 7 packed elements from a to the upper elements of dst. Exceptions can be suppressed by
9053/// passing _MM_FROUND_NO_EXC in the sae parameter. Does not follow the IEEE Standard for Floating-Point Arithmetic
9054/// (IEEE 754) minimum value when inputs are NaN or signed-zero values.
9055///
9056/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_min_round_sh)
9057#[inline]
9058#[target_feature(enable = "avx512fp16,avx512vl")]
9059#[cfg_attr(test, assert_instr(vminsh, SAE = 8))]
9060#[rustc_legacy_const_generics(3)]
9061#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
9062pub fn _mm_maskz_min_round_sh<const SAE: i32>(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
9063    static_assert_sae!(SAE);
9064    _mm_mask_min_round_sh::<SAE>(f16x8::ZERO.as_m128h(), k, a, b)
9065}
9066
9067/// Convert the exponent of each packed half-precision (16-bit) floating-point element in a to a half-precision
9068/// (16-bit) floating-point number representing the integer exponent, and store the results in dst.
9069/// This intrinsic essentially calculates `floor(log2(x))` for each element.
9070///
9071/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_getexp_ph)
9072#[inline]
9073#[target_feature(enable = "avx512fp16,avx512vl")]
9074#[cfg_attr(test, assert_instr(vgetexpph))]
9075#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
9076pub fn _mm_getexp_ph(a: __m128h) -> __m128h {
9077    _mm_mask_getexp_ph(_mm_undefined_ph(), 0xff, a)
9078}
9079
9080/// Convert the exponent of each packed half-precision (16-bit) floating-point element in a to a half-precision
9081/// (16-bit) floating-point number representing the integer exponent, and store the results in dst using writemask k
9082/// (elements are copied from src when the corresponding mask bit is not set). This intrinsic essentially calculates
9083/// `floor(log2(x))` for each element.
9084///
9085/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_getexp_ph)
9086#[inline]
9087#[target_feature(enable = "avx512fp16,avx512vl")]
9088#[cfg_attr(test, assert_instr(vgetexpph))]
9089#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
9090pub fn _mm_mask_getexp_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h {
9091    unsafe { vgetexpph_128(a, src, k) }
9092}
9093
9094/// Convert the exponent of each packed half-precision (16-bit) floating-point element in a to a half-precision
9095/// (16-bit) floating-point number representing the integer exponent, and store the results in dst using zeromask
9096/// k (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates
9097/// `floor(log2(x))` for each element.
9098///
9099/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_getexp_ph)
9100#[inline]
9101#[target_feature(enable = "avx512fp16,avx512vl")]
9102#[cfg_attr(test, assert_instr(vgetexpph))]
9103#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
9104pub fn _mm_maskz_getexp_ph(k: __mmask8, a: __m128h) -> __m128h {
9105    _mm_mask_getexp_ph(_mm_setzero_ph(), k, a)
9106}
9107
9108/// Convert the exponent of each packed half-precision (16-bit) floating-point element in a to a half-precision
9109/// (16-bit) floating-point number representing the integer exponent, and store the results in dst.
9110/// This intrinsic essentially calculates `floor(log2(x))` for each element.
9111///
9112/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_getexp_ph)
9113#[inline]
9114#[target_feature(enable = "avx512fp16,avx512vl")]
9115#[cfg_attr(test, assert_instr(vgetexpph))]
9116#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
9117pub fn _mm256_getexp_ph(a: __m256h) -> __m256h {
9118    _mm256_mask_getexp_ph(_mm256_undefined_ph(), 0xffff, a)
9119}
9120
9121/// Convert the exponent of each packed half-precision (16-bit) floating-point element in a to a half-precision
9122/// (16-bit) floating-point number representing the integer exponent, and store the results in dst using writemask k
9123/// (elements are copied from src when the corresponding mask bit is not set). This intrinsic essentially calculates
9124/// `floor(log2(x))` for each element.
9125///
9126/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_getexp_ph)
9127#[inline]
9128#[target_feature(enable = "avx512fp16,avx512vl")]
9129#[cfg_attr(test, assert_instr(vgetexpph))]
9130#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
9131pub fn _mm256_mask_getexp_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h {
9132    unsafe { vgetexpph_256(a, src, k) }
9133}
9134
9135/// Convert the exponent of each packed half-precision (16-bit) floating-point element in a to a half-precision
9136/// (16-bit) floating-point number representing the integer exponent, and store the results in dst using zeromask
9137/// k (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates
9138/// `floor(log2(x))` for each element.
9139///
9140/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_getexp_ph)
9141#[inline]
9142#[target_feature(enable = "avx512fp16,avx512vl")]
9143#[cfg_attr(test, assert_instr(vgetexpph))]
9144#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
9145pub fn _mm256_maskz_getexp_ph(k: __mmask16, a: __m256h) -> __m256h {
9146    _mm256_mask_getexp_ph(_mm256_setzero_ph(), k, a)
9147}
9148
9149/// Convert the exponent of each packed half-precision (16-bit) floating-point element in a to a half-precision
9150/// (16-bit) floating-point number representing the integer exponent, and store the results in dst.
9151/// This intrinsic essentially calculates `floor(log2(x))` for each element.
9152///
9153/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_getexp_ph)
9154#[inline]
9155#[target_feature(enable = "avx512fp16")]
9156#[cfg_attr(test, assert_instr(vgetexpph))]
9157#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
9158pub fn _mm512_getexp_ph(a: __m512h) -> __m512h {
9159    _mm512_mask_getexp_ph(_mm512_undefined_ph(), 0xffffffff, a)
9160}
9161
9162/// Convert the exponent of each packed half-precision (16-bit) floating-point element in a to a half-precision
9163/// (16-bit) floating-point number representing the integer exponent, and store the results in dst using writemask k
9164/// (elements are copied from src when the corresponding mask bit is not set). This intrinsic essentially calculates
9165/// `floor(log2(x))` for each element.
9166///
9167/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_getexp_ph)
9168#[inline]
9169#[target_feature(enable = "avx512fp16")]
9170#[cfg_attr(test, assert_instr(vgetexpph))]
9171#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
9172pub fn _mm512_mask_getexp_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h {
9173    _mm512_mask_getexp_round_ph::<_MM_FROUND_CUR_DIRECTION>(src, k, a)
9174}
9175
9176/// Convert the exponent of each packed half-precision (16-bit) floating-point element in a to a half-precision
9177/// (16-bit) floating-point number representing the integer exponent, and store the results in dst using zeromask
9178/// k (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates
9179/// `floor(log2(x))` for each element.
9180///
9181/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_getexp_ph)
9182#[inline]
9183#[target_feature(enable = "avx512fp16")]
9184#[cfg_attr(test, assert_instr(vgetexpph))]
9185#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
9186pub fn _mm512_maskz_getexp_ph(k: __mmask32, a: __m512h) -> __m512h {
9187    _mm512_mask_getexp_ph(_mm512_setzero_ph(), k, a)
9188}
9189
9190/// Convert the exponent of each packed half-precision (16-bit) floating-point element in a to a half-precision
9191/// (16-bit) floating-point number representing the integer exponent, and store the results in dst.
9192/// This intrinsic essentially calculates `floor(log2(x))` for each element. Exceptions can be suppressed
9193/// by passing _MM_FROUND_NO_EXC in the sae parameter
9194///
9195/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_getexp_round_ph)
9196#[inline]
9197#[target_feature(enable = "avx512fp16")]
9198#[cfg_attr(test, assert_instr(vgetexpph, SAE = 8))]
9199#[rustc_legacy_const_generics(1)]
9200#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
9201pub fn _mm512_getexp_round_ph<const SAE: i32>(a: __m512h) -> __m512h {
9202    static_assert_sae!(SAE);
9203    _mm512_mask_getexp_round_ph::<SAE>(_mm512_undefined_ph(), 0xffffffff, a)
9204}
9205
9206/// Convert the exponent of each packed half-precision (16-bit) floating-point element in a to a half-precision
9207/// (16-bit) floating-point number representing the integer exponent, and store the results in dst using writemask k
9208/// (elements are copied from src when the corresponding mask bit is not set). This intrinsic essentially calculates
9209/// `floor(log2(x))` for each element. Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter
9210///
9211/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_getexp_round_ph)
9212#[inline]
9213#[target_feature(enable = "avx512fp16")]
9214#[cfg_attr(test, assert_instr(vgetexpph, SAE = 8))]
9215#[rustc_legacy_const_generics(3)]
9216#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
9217pub fn _mm512_mask_getexp_round_ph<const SAE: i32>(
9218    src: __m512h,
9219    k: __mmask32,
9220    a: __m512h,
9221) -> __m512h {
9222    unsafe {
9223        static_assert_sae!(SAE);
9224        vgetexpph_512(a, src, k, SAE)
9225    }
9226}
9227
9228/// Convert the exponent of each packed half-precision (16-bit) floating-point element in a to a half-precision
9229/// (16-bit) floating-point number representing the integer exponent, and store the results in dst using zeromask
9230/// k (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates
9231/// `floor(log2(x))` for each element. Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter
9232///
9233/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_getexp_round_ph)
9234#[inline]
9235#[target_feature(enable = "avx512fp16")]
9236#[cfg_attr(test, assert_instr(vgetexpph, SAE = 8))]
9237#[rustc_legacy_const_generics(2)]
9238#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
9239pub fn _mm512_maskz_getexp_round_ph<const SAE: i32>(k: __mmask32, a: __m512h) -> __m512h {
9240    static_assert_sae!(SAE);
9241    _mm512_mask_getexp_round_ph::<SAE>(_mm512_setzero_ph(), k, a)
9242}
9243
9244/// Convert the exponent of the lower half-precision (16-bit) floating-point element in b to a half-precision
9245/// (16-bit) floating-point number representing the integer exponent, store the result in the lower element
9246/// of dst, and copy the upper 7 packed elements from a to the upper elements of dst. This intrinsic essentially
9247/// calculates `floor(log2(x))` for the lower element.
9248///
9249/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_getexp_sh)
9250#[inline]
9251#[target_feature(enable = "avx512fp16")]
9252#[cfg_attr(test, assert_instr(vgetexpsh))]
9253#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
9254pub fn _mm_getexp_sh(a: __m128h, b: __m128h) -> __m128h {
9255    _mm_mask_getexp_sh(f16x8::ZERO.as_m128h(), 0xff, a, b)
9256}
9257
9258/// Convert the exponent of the lower half-precision (16-bit) floating-point element in b to a half-precision
9259/// (16-bit) floating-point number representing the integer exponent, store the result in the lower element
9260/// of dst using writemask k (the element is copied from src when mask bit 0 is not set), and copy the upper 7
9261/// packed elements from a to the upper elements of dst. This intrinsic essentially calculates `floor(log2(x))`
9262/// for the lower element.
9263///
9264/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_getexp_sh)
9265#[inline]
9266#[target_feature(enable = "avx512fp16")]
9267#[cfg_attr(test, assert_instr(vgetexpsh))]
9268#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
9269pub fn _mm_mask_getexp_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
9270    _mm_mask_getexp_round_sh::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b)
9271}
9272
9273/// Convert the exponent of the lower half-precision (16-bit) floating-point element in b to a half-precision
9274/// (16-bit) floating-point number representing the integer exponent, store the result in the lower element
9275/// of dst using zeromask k (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed
9276/// elements from a to the upper elements of dst. This intrinsic essentially calculates `floor(log2(x))` for the
9277/// lower element.
9278///
9279/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_getexp_sh)
9280#[inline]
9281#[target_feature(enable = "avx512fp16")]
9282#[cfg_attr(test, assert_instr(vgetexpsh))]
9283#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
9284pub fn _mm_maskz_getexp_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
9285    _mm_mask_getexp_sh(f16x8::ZERO.as_m128h(), k, a, b)
9286}
9287
9288/// Convert the exponent of the lower half-precision (16-bit) floating-point element in b to a half-precision
9289/// (16-bit) floating-point number representing the integer exponent, store the result in the lower element
9290/// of dst, and copy the upper 7 packed elements from a to the upper elements of dst. This intrinsic essentially
9291/// calculates `floor(log2(x))` for the lower element. Exceptions can be suppressed by passing _MM_FROUND_NO_EXC
9292/// in the sae parameter
9293///
9294/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_getexp_round_sh)
9295#[inline]
9296#[target_feature(enable = "avx512fp16")]
9297#[cfg_attr(test, assert_instr(vgetexpsh, SAE = 8))]
9298#[rustc_legacy_const_generics(2)]
9299#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
9300pub fn _mm_getexp_round_sh<const SAE: i32>(a: __m128h, b: __m128h) -> __m128h {
9301    static_assert_sae!(SAE);
9302    _mm_mask_getexp_round_sh::<SAE>(f16x8::ZERO.as_m128h(), 0xff, a, b)
9303}
9304
9305/// Convert the exponent of the lower half-precision (16-bit) floating-point element in b to a half-precision
9306/// (16-bit) floating-point number representing the integer exponent, store the result in the lower element
9307/// of dst using writemask k (the element is copied from src when mask bit 0 is not set), and copy the upper 7
9308/// packed elements from a to the upper elements of dst. This intrinsic essentially calculates `floor(log2(x))`
9309/// for the lower element. Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter
9310///
9311/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_getexp_round_sh)
9312#[inline]
9313#[target_feature(enable = "avx512fp16")]
9314#[cfg_attr(test, assert_instr(vgetexpsh, SAE = 8))]
9315#[rustc_legacy_const_generics(4)]
9316#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
9317pub fn _mm_mask_getexp_round_sh<const SAE: i32>(
9318    src: __m128h,
9319    k: __mmask8,
9320    a: __m128h,
9321    b: __m128h,
9322) -> __m128h {
9323    unsafe {
9324        static_assert_sae!(SAE);
9325        vgetexpsh(a, b, src, k, SAE)
9326    }
9327}
9328
9329/// Convert the exponent of the lower half-precision (16-bit) floating-point element in b to a half-precision
9330/// (16-bit) floating-point number representing the integer exponent, store the result in the lower element
9331/// of dst using zeromask k (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed
9332/// elements from a to the upper elements of dst. This intrinsic essentially calculates `floor(log2(x))` for the
9333/// lower element. Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter
9334///
9335/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_getexp_round_sh)
9336#[inline]
9337#[target_feature(enable = "avx512fp16")]
9338#[cfg_attr(test, assert_instr(vgetexpsh, SAE = 8))]
9339#[rustc_legacy_const_generics(3)]
9340#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
9341pub fn _mm_maskz_getexp_round_sh<const SAE: i32>(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
9342    static_assert_sae!(SAE);
9343    _mm_mask_getexp_round_sh::<SAE>(f16x8::ZERO.as_m128h(), k, a, b)
9344}
9345
9346/// Normalize the mantissas of packed half-precision (16-bit) floating-point elements in a, and store
9347/// the results in dst. This intrinsic essentially calculates `±(2^k)*|x.significand|`, where k depends
9348/// on the interval range defined by norm and the sign depends on sign and the source sign.
9349///
9350/// The mantissa is normalized to the interval specified by interv, which can take the following values:
9351///
9352///     _MM_MANT_NORM_1_2     // interval [1, 2)
9353///     _MM_MANT_NORM_p5_2    // interval [0.5, 2)
9354///     _MM_MANT_NORM_p5_1    // interval [0.5, 1)
9355///     _MM_MANT_NORM_p75_1p5 // interval [0.75, 1.5)
9356///
9357/// The sign is determined by sc which can take the following values:
9358///
9359///     _MM_MANT_SIGN_src     // sign = sign(src)
9360///     _MM_MANT_SIGN_zero    // sign = 0
9361///     _MM_MANT_SIGN_nan     // dst = NaN if sign(src) = 1
9362///
9363/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_getmant_ph)
9364#[inline]
9365#[target_feature(enable = "avx512fp16,avx512vl")]
9366#[cfg_attr(test, assert_instr(vgetmantph, NORM = 0, SIGN = 0))]
9367#[rustc_legacy_const_generics(1, 2)]
9368#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
9369pub fn _mm_getmant_ph<const NORM: _MM_MANTISSA_NORM_ENUM, const SIGN: _MM_MANTISSA_SIGN_ENUM>(
9370    a: __m128h,
9371) -> __m128h {
9372    static_assert_uimm_bits!(NORM, 4);
9373    static_assert_uimm_bits!(SIGN, 2);
9374    _mm_mask_getmant_ph::<NORM, SIGN>(_mm_undefined_ph(), 0xff, a)
9375}
9376
9377/// Normalize the mantissas of packed half-precision (16-bit) floating-point elements in a, and store
9378/// the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
9379/// This intrinsic essentially calculates `±(2^k)*|x.significand|`, where k depends on the interval range defined
9380/// by norm and the sign depends on sign and the source sign.
9381///
9382/// The mantissa is normalized to the interval specified by interv, which can take the following values:
9383///
9384///     _MM_MANT_NORM_1_2     // interval [1, 2)
9385///     _MM_MANT_NORM_p5_2    // interval [0.5, 2)
9386///     _MM_MANT_NORM_p5_1    // interval [0.5, 1)
9387///     _MM_MANT_NORM_p75_1p5 // interval [0.75, 1.5)
9388///
9389/// The sign is determined by sc which can take the following values:
9390///
9391///     _MM_MANT_SIGN_src     // sign = sign(src)
9392///     _MM_MANT_SIGN_zero    // sign = 0
9393///     _MM_MANT_SIGN_nan     // dst = NaN if sign(src) = 1
9394///
9395/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_getmant_ph)
9396#[inline]
9397#[target_feature(enable = "avx512fp16,avx512vl")]
9398#[cfg_attr(test, assert_instr(vgetmantph, NORM = 0, SIGN = 0))]
9399#[rustc_legacy_const_generics(3, 4)]
9400#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
9401pub fn _mm_mask_getmant_ph<
9402    const NORM: _MM_MANTISSA_NORM_ENUM,
9403    const SIGN: _MM_MANTISSA_SIGN_ENUM,
9404>(
9405    src: __m128h,
9406    k: __mmask8,
9407    a: __m128h,
9408) -> __m128h {
9409    unsafe {
9410        static_assert_uimm_bits!(NORM, 4);
9411        static_assert_uimm_bits!(SIGN, 2);
9412        vgetmantph_128(a, (SIGN << 2) | NORM, src, k)
9413    }
9414}
9415
9416/// Normalize the mantissas of packed half-precision (16-bit) floating-point elements in a, and store
9417/// the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
9418/// This intrinsic essentially calculates `±(2^k)*|x.significand|`, where k depends on the interval range defined
9419/// by norm and the sign depends on sign and the source sign.
9420///
9421/// The mantissa is normalized to the interval specified by interv, which can take the following values:
9422///
9423///     _MM_MANT_NORM_1_2     // interval [1, 2)
9424///     _MM_MANT_NORM_p5_2    // interval [0.5, 2)
9425///     _MM_MANT_NORM_p5_1    // interval [0.5, 1)
9426///     _MM_MANT_NORM_p75_1p5 // interval [0.75, 1.5)
9427///
9428/// The sign is determined by sc which can take the following values:
9429///
9430///     _MM_MANT_SIGN_src     // sign = sign(src)
9431///     _MM_MANT_SIGN_zero    // sign = 0
9432///     _MM_MANT_SIGN_nan     // dst = NaN if sign(src) = 1
9433///
9434/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_getmant_ph)
9435#[inline]
9436#[target_feature(enable = "avx512fp16,avx512vl")]
9437#[cfg_attr(test, assert_instr(vgetmantph, NORM = 0, SIGN = 0))]
9438#[rustc_legacy_const_generics(2, 3)]
9439#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
9440pub fn _mm_maskz_getmant_ph<
9441    const NORM: _MM_MANTISSA_NORM_ENUM,
9442    const SIGN: _MM_MANTISSA_SIGN_ENUM,
9443>(
9444    k: __mmask8,
9445    a: __m128h,
9446) -> __m128h {
9447    static_assert_uimm_bits!(NORM, 4);
9448    static_assert_uimm_bits!(SIGN, 2);
9449    _mm_mask_getmant_ph::<NORM, SIGN>(_mm_setzero_ph(), k, a)
9450}
9451
9452/// Normalize the mantissas of packed half-precision (16-bit) floating-point elements in a, and store
9453/// the results in dst. This intrinsic essentially calculates `±(2^k)*|x.significand|`, where k depends
9454/// on the interval range defined by norm and the sign depends on sign and the source sign.
9455///
9456/// The mantissa is normalized to the interval specified by interv, which can take the following values:
9457///
9458///     _MM_MANT_NORM_1_2     // interval [1, 2)
9459///     _MM_MANT_NORM_p5_2    // interval [0.5, 2)
9460///     _MM_MANT_NORM_p5_1    // interval [0.5, 1)
9461///     _MM_MANT_NORM_p75_1p5 // interval [0.75, 1.5)
9462///
9463/// The sign is determined by sc which can take the following values:
9464///
9465///     _MM_MANT_SIGN_src     // sign = sign(src)
9466///     _MM_MANT_SIGN_zero    // sign = 0
9467///     _MM_MANT_SIGN_nan     // dst = NaN if sign(src) = 1
9468///
9469/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_getmant_ph)
9470#[inline]
9471#[target_feature(enable = "avx512fp16,avx512vl")]
9472#[cfg_attr(test, assert_instr(vgetmantph, NORM = 0, SIGN = 0))]
9473#[rustc_legacy_const_generics(1, 2)]
9474#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
9475pub fn _mm256_getmant_ph<const NORM: _MM_MANTISSA_NORM_ENUM, const SIGN: _MM_MANTISSA_SIGN_ENUM>(
9476    a: __m256h,
9477) -> __m256h {
9478    static_assert_uimm_bits!(NORM, 4);
9479    static_assert_uimm_bits!(SIGN, 2);
9480    _mm256_mask_getmant_ph::<NORM, SIGN>(_mm256_undefined_ph(), 0xffff, a)
9481}
9482
9483/// Normalize the mantissas of packed half-precision (16-bit) floating-point elements in a, and store
9484/// the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
9485/// This intrinsic essentially calculates `±(2^k)*|x.significand|`, where k depends on the interval range defined
9486/// by norm and the sign depends on sign and the source sign.
9487///
9488/// The mantissa is normalized to the interval specified by interv, which can take the following values:
9489///
9490///     _MM_MANT_NORM_1_2     // interval [1, 2)
9491///     _MM_MANT_NORM_p5_2    // interval [0.5, 2)
9492///     _MM_MANT_NORM_p5_1    // interval [0.5, 1)
9493///     _MM_MANT_NORM_p75_1p5 // interval [0.75, 1.5)
9494///
9495/// The sign is determined by sc which can take the following values:
9496///
9497///     _MM_MANT_SIGN_src     // sign = sign(src)
9498///     _MM_MANT_SIGN_zero    // sign = 0
9499///     _MM_MANT_SIGN_nan     // dst = NaN if sign(src) = 1
9500///
9501/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_getmant_ph)
9502#[inline]
9503#[target_feature(enable = "avx512fp16,avx512vl")]
9504#[cfg_attr(test, assert_instr(vgetmantph, NORM = 0, SIGN = 0))]
9505#[rustc_legacy_const_generics(3, 4)]
9506#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
9507pub fn _mm256_mask_getmant_ph<
9508    const NORM: _MM_MANTISSA_NORM_ENUM,
9509    const SIGN: _MM_MANTISSA_SIGN_ENUM,
9510>(
9511    src: __m256h,
9512    k: __mmask16,
9513    a: __m256h,
9514) -> __m256h {
9515    unsafe {
9516        static_assert_uimm_bits!(NORM, 4);
9517        static_assert_uimm_bits!(SIGN, 2);
9518        vgetmantph_256(a, (SIGN << 2) | NORM, src, k)
9519    }
9520}
9521
9522/// Normalize the mantissas of packed half-precision (16-bit) floating-point elements in a, and store
9523/// the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
9524/// This intrinsic essentially calculates `±(2^k)*|x.significand|`, where k depends on the interval range defined
9525/// by norm and the sign depends on sign and the source sign.
9526///
9527/// The mantissa is normalized to the interval specified by interv, which can take the following values:
9528///
9529///     _MM_MANT_NORM_1_2     // interval [1, 2)
9530///     _MM_MANT_NORM_p5_2    // interval [0.5, 2)
9531///     _MM_MANT_NORM_p5_1    // interval [0.5, 1)
9532///     _MM_MANT_NORM_p75_1p5 // interval [0.75, 1.5)
9533///
9534/// The sign is determined by sc which can take the following values:
9535///
9536///     _MM_MANT_SIGN_src     // sign = sign(src)
9537///     _MM_MANT_SIGN_zero    // sign = 0
9538///     _MM_MANT_SIGN_nan     // dst = NaN if sign(src) = 1
9539///
9540/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_getmant_ph)
9541#[inline]
9542#[target_feature(enable = "avx512fp16,avx512vl")]
9543#[cfg_attr(test, assert_instr(vgetmantph, NORM = 0, SIGN = 0))]
9544#[rustc_legacy_const_generics(2, 3)]
9545#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
9546pub fn _mm256_maskz_getmant_ph<
9547    const NORM: _MM_MANTISSA_NORM_ENUM,
9548    const SIGN: _MM_MANTISSA_SIGN_ENUM,
9549>(
9550    k: __mmask16,
9551    a: __m256h,
9552) -> __m256h {
9553    static_assert_uimm_bits!(NORM, 4);
9554    static_assert_uimm_bits!(SIGN, 2);
9555    _mm256_mask_getmant_ph::<NORM, SIGN>(_mm256_setzero_ph(), k, a)
9556}
9557
9558/// Normalize the mantissas of packed half-precision (16-bit) floating-point elements in a, and store
9559/// the results in dst. This intrinsic essentially calculates `±(2^k)*|x.significand|`, where k depends
9560/// on the interval range defined by norm and the sign depends on sign and the source sign.
9561///
9562/// The mantissa is normalized to the interval specified by interv, which can take the following values:
9563///
9564///     _MM_MANT_NORM_1_2     // interval [1, 2)
9565///     _MM_MANT_NORM_p5_2    // interval [0.5, 2)
9566///     _MM_MANT_NORM_p5_1    // interval [0.5, 1)
9567///     _MM_MANT_NORM_p75_1p5 // interval [0.75, 1.5)
9568///
9569/// The sign is determined by sc which can take the following values:
9570///
9571///     _MM_MANT_SIGN_src     // sign = sign(src)
9572///     _MM_MANT_SIGN_zero    // sign = 0
9573///     _MM_MANT_SIGN_nan     // dst = NaN if sign(src) = 1
9574///
9575/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_getmant_ph)
9576#[inline]
9577#[target_feature(enable = "avx512fp16")]
9578#[cfg_attr(test, assert_instr(vgetmantph, NORM = 0, SIGN = 0))]
9579#[rustc_legacy_const_generics(1, 2)]
9580#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
9581pub fn _mm512_getmant_ph<const NORM: _MM_MANTISSA_NORM_ENUM, const SIGN: _MM_MANTISSA_SIGN_ENUM>(
9582    a: __m512h,
9583) -> __m512h {
9584    static_assert_uimm_bits!(NORM, 4);
9585    static_assert_uimm_bits!(SIGN, 2);
9586    _mm512_mask_getmant_ph::<NORM, SIGN>(_mm512_undefined_ph(), 0xffffffff, a)
9587}
9588
9589/// Normalize the mantissas of packed half-precision (16-bit) floating-point elements in a, and store
9590/// the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
9591/// This intrinsic essentially calculates `±(2^k)*|x.significand|`, where k depends on the interval range defined
9592/// by norm and the sign depends on sign and the source sign.
9593///
9594/// The mantissa is normalized to the interval specified by interv, which can take the following values:
9595///
9596///     _MM_MANT_NORM_1_2     // interval [1, 2)
9597///     _MM_MANT_NORM_p5_2    // interval [0.5, 2)
9598///     _MM_MANT_NORM_p5_1    // interval [0.5, 1)
9599///     _MM_MANT_NORM_p75_1p5 // interval [0.75, 1.5)
9600///
9601/// The sign is determined by sc which can take the following values:
9602///
9603///     _MM_MANT_SIGN_src     // sign = sign(src)
9604///     _MM_MANT_SIGN_zero    // sign = 0
9605///     _MM_MANT_SIGN_nan     // dst = NaN if sign(src) = 1
9606///
9607/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_getmant_ph)
9608#[inline]
9609#[target_feature(enable = "avx512fp16")]
9610#[cfg_attr(test, assert_instr(vgetmantph, NORM = 0, SIGN = 0))]
9611#[rustc_legacy_const_generics(3, 4)]
9612#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
9613pub fn _mm512_mask_getmant_ph<
9614    const NORM: _MM_MANTISSA_NORM_ENUM,
9615    const SIGN: _MM_MANTISSA_SIGN_ENUM,
9616>(
9617    src: __m512h,
9618    k: __mmask32,
9619    a: __m512h,
9620) -> __m512h {
9621    static_assert_uimm_bits!(NORM, 4);
9622    static_assert_uimm_bits!(SIGN, 2);
9623    _mm512_mask_getmant_round_ph::<NORM, SIGN, _MM_FROUND_CUR_DIRECTION>(src, k, a)
9624}
9625
9626/// Normalize the mantissas of packed half-precision (16-bit) floating-point elements in a, and store
9627/// the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
9628/// This intrinsic essentially calculates `±(2^k)*|x.significand|`, where k depends on the interval range defined
9629/// by norm and the sign depends on sign and the source sign.
9630///
9631/// The mantissa is normalized to the interval specified by interv, which can take the following values:
9632///
9633///     _MM_MANT_NORM_1_2     // interval [1, 2)
9634///     _MM_MANT_NORM_p5_2    // interval [0.5, 2)
9635///     _MM_MANT_NORM_p5_1    // interval [0.5, 1)
9636///     _MM_MANT_NORM_p75_1p5 // interval [0.75, 1.5)
9637///
9638/// The sign is determined by sc which can take the following values:
9639///
9640///     _MM_MANT_SIGN_src     // sign = sign(src)
9641///     _MM_MANT_SIGN_zero    // sign = 0
9642///     _MM_MANT_SIGN_nan     // dst = NaN if sign(src) = 1
9643///
9644/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_getmant_ph)
9645#[inline]
9646#[target_feature(enable = "avx512fp16")]
9647#[cfg_attr(test, assert_instr(vgetmantph, NORM = 0, SIGN = 0))]
9648#[rustc_legacy_const_generics(2, 3)]
9649#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
9650pub fn _mm512_maskz_getmant_ph<
9651    const NORM: _MM_MANTISSA_NORM_ENUM,
9652    const SIGN: _MM_MANTISSA_SIGN_ENUM,
9653>(
9654    k: __mmask32,
9655    a: __m512h,
9656) -> __m512h {
9657    static_assert_uimm_bits!(NORM, 4);
9658    static_assert_uimm_bits!(SIGN, 2);
9659    _mm512_mask_getmant_ph::<NORM, SIGN>(_mm512_setzero_ph(), k, a)
9660}
9661
9662/// Normalize the mantissas of packed half-precision (16-bit) floating-point elements in a, and store
9663/// the results in dst. This intrinsic essentially calculates `±(2^k)*|x.significand|`, where k depends
9664/// on the interval range defined by norm and the sign depends on sign and the source sign. Exceptions can
9665/// be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter
9666///
9667/// The mantissa is normalized to the interval specified by interv, which can take the following values:
9668///
9669///     _MM_MANT_NORM_1_2     // interval [1, 2)
9670///     _MM_MANT_NORM_p5_2    // interval [0.5, 2)
9671///     _MM_MANT_NORM_p5_1    // interval [0.5, 1)
9672///     _MM_MANT_NORM_p75_1p5 // interval [0.75, 1.5)
9673///
9674/// The sign is determined by sc which can take the following values:
9675///
9676///     _MM_MANT_SIGN_src     // sign = sign(src)
9677///     _MM_MANT_SIGN_zero    // sign = 0
9678///     _MM_MANT_SIGN_nan     // dst = NaN if sign(src) = 1
9679///
9680/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter
9681///
9682/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_getmant_round_ph)
9683#[inline]
9684#[target_feature(enable = "avx512fp16")]
9685#[cfg_attr(test, assert_instr(vgetmantph, NORM = 0, SIGN = 0, SAE = 8))]
9686#[rustc_legacy_const_generics(1, 2, 3)]
9687#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
9688pub fn _mm512_getmant_round_ph<
9689    const NORM: _MM_MANTISSA_NORM_ENUM,
9690    const SIGN: _MM_MANTISSA_SIGN_ENUM,
9691    const SAE: i32,
9692>(
9693    a: __m512h,
9694) -> __m512h {
9695    static_assert_uimm_bits!(NORM, 4);
9696    static_assert_uimm_bits!(SIGN, 2);
9697    static_assert_sae!(SAE);
9698    _mm512_mask_getmant_round_ph::<NORM, SIGN, SAE>(_mm512_undefined_ph(), 0xffffffff, a)
9699}
9700
9701/// Normalize the mantissas of packed half-precision (16-bit) floating-point elements in a, and store
9702/// the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
9703/// This intrinsic essentially calculates `±(2^k)*|x.significand|`, where k depends on the interval range defined
9704/// by norm and the sign depends on sign and the source sign. Exceptions can be suppressed by passing _MM_FROUND_NO_EXC
9705/// in the sae parameter
9706///
9707/// The mantissa is normalized to the interval specified by interv, which can take the following values:
9708///
9709///     _MM_MANT_NORM_1_2     // interval [1, 2)
9710///     _MM_MANT_NORM_p5_2    // interval [0.5, 2)
9711///     _MM_MANT_NORM_p5_1    // interval [0.5, 1)
9712///     _MM_MANT_NORM_p75_1p5 // interval [0.75, 1.5)
9713///
9714/// The sign is determined by sc which can take the following values:
9715///
9716///     _MM_MANT_SIGN_src     // sign = sign(src)
9717///     _MM_MANT_SIGN_zero    // sign = 0
9718///     _MM_MANT_SIGN_nan     // dst = NaN if sign(src) = 1
9719///
9720/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter
9721///
9722/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_getmant_round_ph)
9723#[inline]
9724#[target_feature(enable = "avx512fp16")]
9725#[cfg_attr(test, assert_instr(vgetmantph, NORM = 0, SIGN = 0, SAE = 8))]
9726#[rustc_legacy_const_generics(3, 4, 5)]
9727#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
9728pub fn _mm512_mask_getmant_round_ph<
9729    const NORM: _MM_MANTISSA_NORM_ENUM,
9730    const SIGN: _MM_MANTISSA_SIGN_ENUM,
9731    const SAE: i32,
9732>(
9733    src: __m512h,
9734    k: __mmask32,
9735    a: __m512h,
9736) -> __m512h {
9737    unsafe {
9738        static_assert_uimm_bits!(NORM, 4);
9739        static_assert_uimm_bits!(SIGN, 2);
9740        static_assert_sae!(SAE);
9741        vgetmantph_512(a, (SIGN << 2) | NORM, src, k, SAE)
9742    }
9743}
9744
9745/// Normalize the mantissas of packed half-precision (16-bit) floating-point elements in a, and store
9746/// the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
9747/// This intrinsic essentially calculates `±(2^k)*|x.significand|`, where k depends on the interval range defined
9748/// by norm and the sign depends on sign and the source sign. Exceptions can be suppressed by passing _MM_FROUND_NO_EXC
9749/// in the sae parameter
9750///
9751/// The mantissa is normalized to the interval specified by interv, which can take the following values:
9752///
9753///     _MM_MANT_NORM_1_2     // interval [1, 2)
9754///     _MM_MANT_NORM_p5_2    // interval [0.5, 2)
9755///     _MM_MANT_NORM_p5_1    // interval [0.5, 1)
9756///     _MM_MANT_NORM_p75_1p5 // interval [0.75, 1.5)
9757///
9758/// The sign is determined by sc which can take the following values:
9759///
9760///     _MM_MANT_SIGN_src     // sign = sign(src)
9761///     _MM_MANT_SIGN_zero    // sign = 0
9762///     _MM_MANT_SIGN_nan     // dst = NaN if sign(src) = 1
9763///
9764/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter
9765///
9766/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_getmant_round_ph)
9767#[inline]
9768#[target_feature(enable = "avx512fp16")]
9769#[cfg_attr(test, assert_instr(vgetmantph, NORM = 0, SIGN = 0, SAE = 8))]
9770#[rustc_legacy_const_generics(2, 3, 4)]
9771#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
9772pub fn _mm512_maskz_getmant_round_ph<
9773    const NORM: _MM_MANTISSA_NORM_ENUM,
9774    const SIGN: _MM_MANTISSA_SIGN_ENUM,
9775    const SAE: i32,
9776>(
9777    k: __mmask32,
9778    a: __m512h,
9779) -> __m512h {
9780    static_assert_uimm_bits!(NORM, 4);
9781    static_assert_uimm_bits!(SIGN, 2);
9782    static_assert_sae!(SAE);
9783    _mm512_mask_getmant_round_ph::<NORM, SIGN, SAE>(_mm512_setzero_ph(), k, a)
9784}
9785
9786/// Normalize the mantissas of the lower half-precision (16-bit) floating-point element in b, store
9787/// the result in the lower element of dst, and copy the upper 7 packed elements from a to the upper
9788/// elements of dst. This intrinsic essentially calculates `±(2^k)*|x.significand|`, where k depends
9789/// on the interval range defined by norm and the sign depends on sign and the source sign.
9790///
9791/// The mantissa is normalized to the interval specified by interv, which can take the following values:
9792///
9793///     _MM_MANT_NORM_1_2     // interval [1, 2)
9794///     _MM_MANT_NORM_p5_2    // interval [0.5, 2)
9795///     _MM_MANT_NORM_p5_1    // interval [0.5, 1)
9796///     _MM_MANT_NORM_p75_1p5 // interval [0.75, 1.5)
9797///
9798/// The sign is determined by sc which can take the following values:
9799///
9800///     _MM_MANT_SIGN_src     // sign = sign(src)
9801///     _MM_MANT_SIGN_zero    // sign = 0
9802///     _MM_MANT_SIGN_nan     // dst = NaN if sign(src) = 1
9803///
9804/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_getmant_sh)
9805#[inline]
9806#[target_feature(enable = "avx512fp16")]
9807#[cfg_attr(test, assert_instr(vgetmantsh, NORM = 0, SIGN = 0))]
9808#[rustc_legacy_const_generics(2, 3)]
9809#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
9810pub fn _mm_getmant_sh<const NORM: _MM_MANTISSA_NORM_ENUM, const SIGN: _MM_MANTISSA_SIGN_ENUM>(
9811    a: __m128h,
9812    b: __m128h,
9813) -> __m128h {
9814    static_assert_uimm_bits!(NORM, 4);
9815    static_assert_uimm_bits!(SIGN, 2);
9816    _mm_mask_getmant_sh::<NORM, SIGN>(f16x8::ZERO.as_m128h(), 0xff, a, b)
9817}
9818
9819/// Normalize the mantissas of the lower half-precision (16-bit) floating-point element in b, store
9820/// the result in the lower element of dst using writemask k (the element is copied from src when mask bit 0 is not set),
9821/// and copy the upper 7 packed elements from a to the upper elements of dst. This intrinsic essentially calculates
9822/// `±(2^k)*|x.significand|`, where k depends on the interval range defined by norm and the sign depends on sign and
9823/// the source sign.
9824///
9825/// The mantissa is normalized to the interval specified by interv, which can take the following values:
9826///
9827///     _MM_MANT_NORM_1_2     // interval [1, 2)
9828///     _MM_MANT_NORM_p5_2    // interval [0.5, 2)
9829///     _MM_MANT_NORM_p5_1    // interval [0.5, 1)
9830///     _MM_MANT_NORM_p75_1p5 // interval [0.75, 1.5)
9831///
9832/// The sign is determined by sc which can take the following values:
9833///
9834///     _MM_MANT_SIGN_src     // sign = sign(src)
9835///     _MM_MANT_SIGN_zero    // sign = 0
9836///     _MM_MANT_SIGN_nan     // dst = NaN if sign(src) = 1
9837///
9838/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_getmant_sh)
9839#[inline]
9840#[target_feature(enable = "avx512fp16")]
9841#[cfg_attr(test, assert_instr(vgetmantsh, NORM = 0, SIGN = 0))]
9842#[rustc_legacy_const_generics(4, 5)]
9843#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
9844pub fn _mm_mask_getmant_sh<
9845    const NORM: _MM_MANTISSA_NORM_ENUM,
9846    const SIGN: _MM_MANTISSA_SIGN_ENUM,
9847>(
9848    src: __m128h,
9849    k: __mmask8,
9850    a: __m128h,
9851    b: __m128h,
9852) -> __m128h {
9853    static_assert_uimm_bits!(NORM, 4);
9854    static_assert_uimm_bits!(SIGN, 2);
9855    _mm_mask_getmant_round_sh::<NORM, SIGN, _MM_FROUND_CUR_DIRECTION>(src, k, a, b)
9856}
9857
9858/// Normalize the mantissas of the lower half-precision (16-bit) floating-point element in b, store
9859/// the result in the lower element of dst using zeromask k (the element is zeroed out when mask bit 0 is not set),
9860/// and copy the upper 7 packed elements from a to the upper elements of dst. This intrinsic essentially calculates
9861/// `±(2^k)*|x.significand|`, where k depends on the interval range defined by norm and the sign depends on sign and
9862/// the source sign.
9863///
9864/// The mantissa is normalized to the interval specified by interv, which can take the following values:
9865///
9866///     _MM_MANT_NORM_1_2     // interval [1, 2)
9867///     _MM_MANT_NORM_p5_2    // interval [0.5, 2)
9868///     _MM_MANT_NORM_p5_1    // interval [0.5, 1)
9869///     _MM_MANT_NORM_p75_1p5 // interval [0.75, 1.5)
9870///
9871/// The sign is determined by sc which can take the following values:
9872///
9873///     _MM_MANT_SIGN_src     // sign = sign(src)
9874///     _MM_MANT_SIGN_zero    // sign = 0
9875///     _MM_MANT_SIGN_nan     // dst = NaN if sign(src) = 1
9876///
9877/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_getmant_sh)
9878#[inline]
9879#[target_feature(enable = "avx512fp16")]
9880#[cfg_attr(test, assert_instr(vgetmantsh, NORM = 0, SIGN = 0))]
9881#[rustc_legacy_const_generics(3, 4)]
9882#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
9883pub fn _mm_maskz_getmant_sh<
9884    const NORM: _MM_MANTISSA_NORM_ENUM,
9885    const SIGN: _MM_MANTISSA_SIGN_ENUM,
9886>(
9887    k: __mmask8,
9888    a: __m128h,
9889    b: __m128h,
9890) -> __m128h {
9891    static_assert_uimm_bits!(NORM, 4);
9892    static_assert_uimm_bits!(SIGN, 2);
9893    _mm_mask_getmant_sh::<NORM, SIGN>(f16x8::ZERO.as_m128h(), k, a, b)
9894}
9895
9896/// Normalize the mantissas of the lower half-precision (16-bit) floating-point element in b, store
9897/// the result in the lower element of dst, and copy the upper 7 packed elements from a to the upper
9898/// elements of dst. This intrinsic essentially calculates `±(2^k)*|x.significand|`, where k depends
9899/// on the interval range defined by norm and the sign depends on sign and the source sign. Exceptions can
9900/// be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter
9901///
9902/// The mantissa is normalized to the interval specified by interv, which can take the following values:
9903///
9904///     _MM_MANT_NORM_1_2     // interval [1, 2)
9905///     _MM_MANT_NORM_p5_2    // interval [0.5, 2)
9906///     _MM_MANT_NORM_p5_1    // interval [0.5, 1)
9907///     _MM_MANT_NORM_p75_1p5 // interval [0.75, 1.5)
9908///
9909/// The sign is determined by sc which can take the following values:
9910///
9911///     _MM_MANT_SIGN_src     // sign = sign(src)
9912///     _MM_MANT_SIGN_zero    // sign = 0
9913///     _MM_MANT_SIGN_nan     // dst = NaN if sign(src) = 1
9914///
9915/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter
9916///
9917/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_getmant_round_sh)
9918#[inline]
9919#[target_feature(enable = "avx512fp16")]
9920#[cfg_attr(test, assert_instr(vgetmantsh, NORM = 0, SIGN = 0, SAE = 8))]
9921#[rustc_legacy_const_generics(2, 3, 4)]
9922#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
9923pub fn _mm_getmant_round_sh<
9924    const NORM: _MM_MANTISSA_NORM_ENUM,
9925    const SIGN: _MM_MANTISSA_SIGN_ENUM,
9926    const SAE: i32,
9927>(
9928    a: __m128h,
9929    b: __m128h,
9930) -> __m128h {
9931    static_assert_uimm_bits!(NORM, 4);
9932    static_assert_uimm_bits!(SIGN, 2);
9933    static_assert_sae!(SAE);
9934    _mm_mask_getmant_round_sh::<NORM, SIGN, SAE>(f16x8::ZERO.as_m128h(), 0xff, a, b)
9935}
9936
9937/// Normalize the mantissas of the lower half-precision (16-bit) floating-point element in b, store
9938/// the result in the lower element of dst using writemask k (the element is copied from src when mask bit 0 is not set),
9939/// and copy the upper 7 packed elements from a to the upper elements of dst. This intrinsic essentially calculates
9940/// `±(2^k)*|x.significand|`, where k depends on the interval range defined by norm and the sign depends on sign and
9941/// the source sign. Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter
9942///
9943/// The mantissa is normalized to the interval specified by interv, which can take the following values:
9944///
9945///     _MM_MANT_NORM_1_2     // interval [1, 2)
9946///     _MM_MANT_NORM_p5_2    // interval [0.5, 2)
9947///     _MM_MANT_NORM_p5_1    // interval [0.5, 1)
9948///     _MM_MANT_NORM_p75_1p5 // interval [0.75, 1.5)
9949///
9950/// The sign is determined by sc which can take the following values:
9951///
9952///     _MM_MANT_SIGN_src     // sign = sign(src)
9953///     _MM_MANT_SIGN_zero    // sign = 0
9954///     _MM_MANT_SIGN_nan     // dst = NaN if sign(src) = 1
9955///
9956/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter
9957///
9958/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_getmant_round_sh)
9959#[inline]
9960#[target_feature(enable = "avx512fp16")]
9961#[cfg_attr(test, assert_instr(vgetmantsh, NORM = 0, SIGN = 0, SAE = 8))]
9962#[rustc_legacy_const_generics(4, 5, 6)]
9963#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
9964pub fn _mm_mask_getmant_round_sh<
9965    const NORM: _MM_MANTISSA_NORM_ENUM,
9966    const SIGN: _MM_MANTISSA_SIGN_ENUM,
9967    const SAE: i32,
9968>(
9969    src: __m128h,
9970    k: __mmask8,
9971    a: __m128h,
9972    b: __m128h,
9973) -> __m128h {
9974    unsafe {
9975        static_assert_uimm_bits!(NORM, 4);
9976        static_assert_uimm_bits!(SIGN, 2);
9977        static_assert_sae!(SAE);
9978        vgetmantsh(a, b, (SIGN << 2) | NORM, src, k, SAE)
9979    }
9980}
9981
9982/// Normalize the mantissas of the lower half-precision (16-bit) floating-point element in b, store
9983/// the result in the lower element of dst using zeromask k (the element is zeroed out when mask bit 0 is not set),
9984/// and copy the upper 7 packed elements from a to the upper elements of dst. This intrinsic essentially calculates
9985/// `±(2^k)*|x.significand|`, where k depends on the interval range defined by norm and the sign depends on sign and
9986/// the source sign. Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter
9987///
9988/// The mantissa is normalized to the interval specified by interv, which can take the following values:
9989///
9990///     _MM_MANT_NORM_1_2     // interval [1, 2)
9991///     _MM_MANT_NORM_p5_2    // interval [0.5, 2)
9992///     _MM_MANT_NORM_p5_1    // interval [0.5, 1)
9993///     _MM_MANT_NORM_p75_1p5 // interval [0.75, 1.5)
9994///
9995/// The sign is determined by sc which can take the following values:
9996///
9997///     _MM_MANT_SIGN_src     // sign = sign(src)
9998///     _MM_MANT_SIGN_zero    // sign = 0
9999///     _MM_MANT_SIGN_nan     // dst = NaN if sign(src) = 1
10000///
10001/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter
10002///
10003/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_getmant_round_sh)
10004#[inline]
10005#[target_feature(enable = "avx512fp16")]
10006#[cfg_attr(test, assert_instr(vgetmantsh, NORM = 0, SIGN = 0, SAE = 8))]
10007#[rustc_legacy_const_generics(3, 4, 5)]
10008#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10009pub fn _mm_maskz_getmant_round_sh<
10010    const NORM: _MM_MANTISSA_NORM_ENUM,
10011    const SIGN: _MM_MANTISSA_SIGN_ENUM,
10012    const SAE: i32,
10013>(
10014    k: __mmask8,
10015    a: __m128h,
10016    b: __m128h,
10017) -> __m128h {
10018    static_assert_uimm_bits!(NORM, 4);
10019    static_assert_uimm_bits!(SIGN, 2);
10020    static_assert_sae!(SAE);
10021    _mm_mask_getmant_round_sh::<NORM, SIGN, SAE>(f16x8::ZERO.as_m128h(), k, a, b)
10022}
10023
10024/// Round packed half-precision (16-bit) floating-point elements in a to the number of fraction bits
10025/// specified by imm8, and store the results in dst.
10026///
10027/// Rounding is done according to the imm8 parameter, which can be one of:
10028///
10029/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest
10030/// * [`_MM_FROUND_TO_NEG_INF`] : round down
10031/// * [`_MM_FROUND_TO_POS_INF`] : round up
10032/// * [`_MM_FROUND_TO_ZERO`] : truncate
10033/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
10034///
10035/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_roundscale_ph)
10036#[inline]
10037#[target_feature(enable = "avx512fp16,avx512vl")]
10038#[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))]
10039#[rustc_legacy_const_generics(1)]
10040#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10041pub fn _mm_roundscale_ph<const IMM8: i32>(a: __m128h) -> __m128h {
10042    static_assert_uimm_bits!(IMM8, 8);
10043    _mm_mask_roundscale_ph::<IMM8>(_mm_undefined_ph(), 0xff, a)
10044}
10045
10046/// Round packed half-precision (16-bit) floating-point elements in a to the number of fraction bits
10047/// specified by imm8, and store the results in dst using writemask k (elements are copied from src when
10048/// the corresponding mask bit is not set).
10049///
10050/// Rounding is done according to the imm8 parameter, which can be one of:
10051///
10052/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest
10053/// * [`_MM_FROUND_TO_NEG_INF`] : round down
10054/// * [`_MM_FROUND_TO_POS_INF`] : round up
10055/// * [`_MM_FROUND_TO_ZERO`] : truncate
10056/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
10057///
10058/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_roundscale_ph)
10059#[inline]
10060#[target_feature(enable = "avx512fp16,avx512vl")]
10061#[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))]
10062#[rustc_legacy_const_generics(3)]
10063#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10064pub fn _mm_mask_roundscale_ph<const IMM8: i32>(src: __m128h, k: __mmask8, a: __m128h) -> __m128h {
10065    unsafe {
10066        static_assert_uimm_bits!(IMM8, 8);
10067        vrndscaleph_128(a, IMM8, src, k)
10068    }
10069}
10070
10071/// Round packed half-precision (16-bit) floating-point elements in a to the number of fraction bits
10072/// specified by imm8, and store the results in dst using zeromask k (elements are zeroed out when the corresponding
10073/// mask bit is not set).
10074///
10075/// Rounding is done according to the imm8 parameter, which can be one of:
10076///
10077/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest
10078/// * [`_MM_FROUND_TO_NEG_INF`] : round down
10079/// * [`_MM_FROUND_TO_POS_INF`] : round up
10080/// * [`_MM_FROUND_TO_ZERO`] : truncate
10081/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
10082///
10083/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_roundscale_ph)
10084#[inline]
10085#[target_feature(enable = "avx512fp16,avx512vl")]
10086#[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))]
10087#[rustc_legacy_const_generics(2)]
10088#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10089pub fn _mm_maskz_roundscale_ph<const IMM8: i32>(k: __mmask8, a: __m128h) -> __m128h {
10090    static_assert_uimm_bits!(IMM8, 8);
10091    _mm_mask_roundscale_ph::<IMM8>(_mm_setzero_ph(), k, a)
10092}
10093
10094/// Round packed half-precision (16-bit) floating-point elements in a to the number of fraction bits
10095/// specified by imm8, and store the results in dst.
10096///
10097/// Rounding is done according to the imm8 parameter, which can be one of:
10098///
10099/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest
10100/// * [`_MM_FROUND_TO_NEG_INF`] : round down
10101/// * [`_MM_FROUND_TO_POS_INF`] : round up
10102/// * [`_MM_FROUND_TO_ZERO`] : truncate
10103/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
10104///
10105/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_roundscale_ph)
10106#[inline]
10107#[target_feature(enable = "avx512fp16,avx512vl")]
10108#[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))]
10109#[rustc_legacy_const_generics(1)]
10110#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10111pub fn _mm256_roundscale_ph<const IMM8: i32>(a: __m256h) -> __m256h {
10112    static_assert_uimm_bits!(IMM8, 8);
10113    _mm256_mask_roundscale_ph::<IMM8>(_mm256_undefined_ph(), 0xffff, a)
10114}
10115
10116/// Round packed half-precision (16-bit) floating-point elements in a to the number of fraction bits
10117/// specified by imm8, and store the results in dst using writemask k (elements are copied from src when
10118/// the corresponding mask bit is not set).
10119///
10120/// Rounding is done according to the imm8 parameter, which can be one of:
10121///
10122/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest
10123/// * [`_MM_FROUND_TO_NEG_INF`] : round down
10124/// * [`_MM_FROUND_TO_POS_INF`] : round up
10125/// * [`_MM_FROUND_TO_ZERO`] : truncate
10126/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
10127///
10128/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_roundscale_ph)
10129#[inline]
10130#[target_feature(enable = "avx512fp16,avx512vl")]
10131#[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))]
10132#[rustc_legacy_const_generics(3)]
10133#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10134pub fn _mm256_mask_roundscale_ph<const IMM8: i32>(
10135    src: __m256h,
10136    k: __mmask16,
10137    a: __m256h,
10138) -> __m256h {
10139    unsafe {
10140        static_assert_uimm_bits!(IMM8, 8);
10141        vrndscaleph_256(a, IMM8, src, k)
10142    }
10143}
10144
10145/// Round packed half-precision (16-bit) floating-point elements in a to the number of fraction bits
10146/// specified by imm8, and store the results in dst using zeromask k (elements are zeroed out when the corresponding
10147/// mask bit is not set).
10148///
10149/// Rounding is done according to the imm8 parameter, which can be one of:
10150///
10151/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest
10152/// * [`_MM_FROUND_TO_NEG_INF`] : round down
10153/// * [`_MM_FROUND_TO_POS_INF`] : round up
10154/// * [`_MM_FROUND_TO_ZERO`] : truncate
10155/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
10156///
10157/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_roundscale_ph)
10158#[inline]
10159#[target_feature(enable = "avx512fp16,avx512vl")]
10160#[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))]
10161#[rustc_legacy_const_generics(2)]
10162#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10163pub fn _mm256_maskz_roundscale_ph<const IMM8: i32>(k: __mmask16, a: __m256h) -> __m256h {
10164    static_assert_uimm_bits!(IMM8, 8);
10165    _mm256_mask_roundscale_ph::<IMM8>(_mm256_setzero_ph(), k, a)
10166}
10167
10168/// Round packed half-precision (16-bit) floating-point elements in a to the number of fraction bits
10169/// specified by imm8, and store the results in dst.
10170///
10171/// Rounding is done according to the imm8 parameter, which can be one of:
10172///
10173/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest
10174/// * [`_MM_FROUND_TO_NEG_INF`] : round down
10175/// * [`_MM_FROUND_TO_POS_INF`] : round up
10176/// * [`_MM_FROUND_TO_ZERO`] : truncate
10177/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
10178///
10179/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_roundscale_ph)
10180#[inline]
10181#[target_feature(enable = "avx512fp16")]
10182#[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))]
10183#[rustc_legacy_const_generics(1)]
10184#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10185pub fn _mm512_roundscale_ph<const IMM8: i32>(a: __m512h) -> __m512h {
10186    static_assert_uimm_bits!(IMM8, 8);
10187    _mm512_mask_roundscale_ph::<IMM8>(_mm512_undefined_ph(), 0xffffffff, a)
10188}
10189
10190/// Round packed half-precision (16-bit) floating-point elements in a to the number of fraction bits
10191/// specified by imm8, and store the results in dst using writemask k (elements are copied from src when
10192/// the corresponding mask bit is not set).
10193///
10194/// Rounding is done according to the imm8 parameter, which can be one of:
10195///
10196/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest
10197/// * [`_MM_FROUND_TO_NEG_INF`] : round down
10198/// * [`_MM_FROUND_TO_POS_INF`] : round up
10199/// * [`_MM_FROUND_TO_ZERO`] : truncate
10200/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
10201///
10202/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_roundscale_ph)
10203#[inline]
10204#[target_feature(enable = "avx512fp16")]
10205#[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))]
10206#[rustc_legacy_const_generics(3)]
10207#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10208pub fn _mm512_mask_roundscale_ph<const IMM8: i32>(
10209    src: __m512h,
10210    k: __mmask32,
10211    a: __m512h,
10212) -> __m512h {
10213    static_assert_uimm_bits!(IMM8, 8);
10214    _mm512_mask_roundscale_round_ph::<IMM8, _MM_FROUND_CUR_DIRECTION>(src, k, a)
10215}
10216
10217/// Round packed half-precision (16-bit) floating-point elements in a to the number of fraction bits
10218/// specified by imm8, and store the results in dst using zeromask k (elements are zeroed out when the corresponding
10219/// mask bit is not set).
10220///
10221/// Rounding is done according to the imm8 parameter, which can be one of:
10222///
10223/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest
10224/// * [`_MM_FROUND_TO_NEG_INF`] : round down
10225/// * [`_MM_FROUND_TO_POS_INF`] : round up
10226/// * [`_MM_FROUND_TO_ZERO`] : truncate
10227/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
10228///
10229/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_roundscale_ph)
10230#[inline]
10231#[target_feature(enable = "avx512fp16")]
10232#[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))]
10233#[rustc_legacy_const_generics(2)]
10234#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10235pub fn _mm512_maskz_roundscale_ph<const IMM8: i32>(k: __mmask32, a: __m512h) -> __m512h {
10236    static_assert_uimm_bits!(IMM8, 8);
10237    _mm512_mask_roundscale_ph::<IMM8>(_mm512_setzero_ph(), k, a)
10238}
10239
10240/// Round packed half-precision (16-bit) floating-point elements in a to the number of fraction bits
10241/// specified by imm8, and store the results in dst. Exceptions can be suppressed by passing _MM_FROUND_NO_EXC
10242/// in the sae parameter
10243///
10244/// Rounding is done according to the imm8 parameter, which can be one of:
10245///
10246/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest
10247/// * [`_MM_FROUND_TO_NEG_INF`] : round down
10248/// * [`_MM_FROUND_TO_POS_INF`] : round up
10249/// * [`_MM_FROUND_TO_ZERO`] : truncate
10250/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
10251///
10252/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_roundscale_round_ph)
10253#[inline]
10254#[target_feature(enable = "avx512fp16")]
10255#[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0, SAE = 8))]
10256#[rustc_legacy_const_generics(1, 2)]
10257#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10258pub fn _mm512_roundscale_round_ph<const IMM8: i32, const SAE: i32>(a: __m512h) -> __m512h {
10259    static_assert_uimm_bits!(IMM8, 8);
10260    static_assert_sae!(SAE);
10261    _mm512_mask_roundscale_round_ph::<IMM8, SAE>(_mm512_undefined_ph(), 0xffffffff, a)
10262}
10263
10264/// Round packed half-precision (16-bit) floating-point elements in a to the number of fraction bits
10265/// specified by imm8, and store the results in dst using writemask k (elements are copied from src when
10266/// the corresponding mask bit is not set). Exceptions can be suppressed by passing _MM_FROUND_NO_EXC
10267/// in the sae parameter
10268///
10269/// Rounding is done according to the imm8 parameter, which can be one of:
10270///
10271/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest
10272/// * [`_MM_FROUND_TO_NEG_INF`] : round down
10273/// * [`_MM_FROUND_TO_POS_INF`] : round up
10274/// * [`_MM_FROUND_TO_ZERO`] : truncate
10275/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
10276///
10277/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_roundscale_round_ph)
10278#[inline]
10279#[target_feature(enable = "avx512fp16")]
10280#[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0, SAE = 8))]
10281#[rustc_legacy_const_generics(3, 4)]
10282#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10283pub fn _mm512_mask_roundscale_round_ph<const IMM8: i32, const SAE: i32>(
10284    src: __m512h,
10285    k: __mmask32,
10286    a: __m512h,
10287) -> __m512h {
10288    unsafe {
10289        static_assert_uimm_bits!(IMM8, 8);
10290        static_assert_sae!(SAE);
10291        vrndscaleph_512(a, IMM8, src, k, SAE)
10292    }
10293}
10294
10295/// Round packed half-precision (16-bit) floating-point elements in a to the number of fraction bits
10296/// specified by imm8, and store the results in dst using zeromask k (elements are zeroed out when the corresponding
10297/// mask bit is not set). Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter
10298///
10299/// Rounding is done according to the imm8 parameter, which can be one of:
10300///
10301/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest
10302/// * [`_MM_FROUND_TO_NEG_INF`] : round down
10303/// * [`_MM_FROUND_TO_POS_INF`] : round up
10304/// * [`_MM_FROUND_TO_ZERO`] : truncate
10305/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
10306///
10307/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_roundscale_round_ph)
10308#[inline]
10309#[target_feature(enable = "avx512fp16")]
10310#[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0, SAE = 8))]
10311#[rustc_legacy_const_generics(2, 3)]
10312#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10313pub fn _mm512_maskz_roundscale_round_ph<const IMM8: i32, const SAE: i32>(
10314    k: __mmask32,
10315    a: __m512h,
10316) -> __m512h {
10317    static_assert_uimm_bits!(IMM8, 8);
10318    static_assert_sae!(SAE);
10319    _mm512_mask_roundscale_round_ph::<IMM8, SAE>(_mm512_setzero_ph(), k, a)
10320}
10321
10322/// Round the lower half-precision (16-bit) floating-point element in b to the number of fraction bits
10323/// specified by imm8, store the result in the lower element of dst, and copy the upper 7 packed elements
10324/// from a to the upper elements of dst.
10325///
10326/// Rounding is done according to the imm8 parameter, which can be one of:
10327///
10328/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest
10329/// * [`_MM_FROUND_TO_NEG_INF`] : round down
10330/// * [`_MM_FROUND_TO_POS_INF`] : round up
10331/// * [`_MM_FROUND_TO_ZERO`] : truncate
10332/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
10333///
10334/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_roundscale_sh)
10335#[inline]
10336#[target_feature(enable = "avx512fp16")]
10337#[cfg_attr(test, assert_instr(vrndscalesh, IMM8 = 0))]
10338#[rustc_legacy_const_generics(2)]
10339#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10340pub fn _mm_roundscale_sh<const IMM8: i32>(a: __m128h, b: __m128h) -> __m128h {
10341    static_assert_uimm_bits!(IMM8, 8);
10342    _mm_mask_roundscale_sh::<IMM8>(f16x8::ZERO.as_m128h(), 0xff, a, b)
10343}
10344
10345/// Round the lower half-precision (16-bit) floating-point element in b to the number of fraction bits
10346/// specified by imm8, store the result in the lower element of dst using writemask k (the element is copied
10347/// from src when mask bit 0 is not set), and copy the upper 7 packed elements from a to the upper elements of dst.
10348///
10349/// Rounding is done according to the imm8 parameter, which can be one of:
10350///
10351/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest
10352/// * [`_MM_FROUND_TO_NEG_INF`] : round down
10353/// * [`_MM_FROUND_TO_POS_INF`] : round up
10354/// * [`_MM_FROUND_TO_ZERO`] : truncate
10355/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
10356///
10357/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_roundscale_sh)
10358#[inline]
10359#[target_feature(enable = "avx512fp16")]
10360#[cfg_attr(test, assert_instr(vrndscalesh, IMM8 = 0))]
10361#[rustc_legacy_const_generics(4)]
10362#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10363pub fn _mm_mask_roundscale_sh<const IMM8: i32>(
10364    src: __m128h,
10365    k: __mmask8,
10366    a: __m128h,
10367    b: __m128h,
10368) -> __m128h {
10369    static_assert_uimm_bits!(IMM8, 8);
10370    _mm_mask_roundscale_round_sh::<IMM8, _MM_FROUND_CUR_DIRECTION>(src, k, a, b)
10371}
10372
10373/// Round the lower half-precision (16-bit) floating-point element in b to the number of fraction bits
10374/// specified by imm8, store the result in the lower element of dst using zeromask k (the element is zeroed
10375/// out when mask bit 0 is not set), and copy the upper 7 packed elements from a to the upper elements of dst.
10376///
10377/// Rounding is done according to the imm8 parameter, which can be one of:
10378///
10379/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest
10380/// * [`_MM_FROUND_TO_NEG_INF`] : round down
10381/// * [`_MM_FROUND_TO_POS_INF`] : round up
10382/// * [`_MM_FROUND_TO_ZERO`] : truncate
10383/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
10384///
10385/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_roundscale_sh)
10386#[inline]
10387#[target_feature(enable = "avx512fp16")]
10388#[cfg_attr(test, assert_instr(vrndscalesh, IMM8 = 0))]
10389#[rustc_legacy_const_generics(3)]
10390#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10391pub fn _mm_maskz_roundscale_sh<const IMM8: i32>(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
10392    static_assert_uimm_bits!(IMM8, 8);
10393    _mm_mask_roundscale_sh::<IMM8>(f16x8::ZERO.as_m128h(), k, a, b)
10394}
10395
10396/// Round the lower half-precision (16-bit) floating-point element in b to the number of fraction bits
10397/// specified by imm8, store the result in the lower element of dst, and copy the upper 7 packed elements
10398/// from a to the upper elements of dst.
10399///
10400/// Rounding is done according to the imm8 parameter, which can be one of:
10401///
10402/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest
10403/// * [`_MM_FROUND_TO_NEG_INF`] : round down
10404/// * [`_MM_FROUND_TO_POS_INF`] : round up
10405/// * [`_MM_FROUND_TO_ZERO`] : truncate
10406/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
10407///
10408/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter
10409///
10410/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_roundscale_round_sh)
10411#[inline]
10412#[target_feature(enable = "avx512fp16")]
10413#[cfg_attr(test, assert_instr(vrndscalesh, IMM8 = 0, SAE = 8))]
10414#[rustc_legacy_const_generics(2, 3)]
10415#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10416pub fn _mm_roundscale_round_sh<const IMM8: i32, const SAE: i32>(a: __m128h, b: __m128h) -> __m128h {
10417    static_assert_uimm_bits!(IMM8, 8);
10418    static_assert_sae!(SAE);
10419    _mm_mask_roundscale_round_sh::<IMM8, SAE>(f16x8::ZERO.as_m128h(), 0xff, a, b)
10420}
10421
10422/// Round the lower half-precision (16-bit) floating-point element in b to the number of fraction bits
10423/// specified by imm8, store the result in the lower element of dst using writemask k (the element is copied
10424/// from src when mask bit 0 is not set), and copy the upper 7 packed elements from a to the upper elements of dst.
10425///
10426/// Rounding is done according to the imm8 parameter, which can be one of:
10427///
10428/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest
10429/// * [`_MM_FROUND_TO_NEG_INF`] : round down
10430/// * [`_MM_FROUND_TO_POS_INF`] : round up
10431/// * [`_MM_FROUND_TO_ZERO`] : truncate
10432/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
10433///
10434/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter
10435///
10436/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_roundscale_round_sh)
10437#[inline]
10438#[target_feature(enable = "avx512fp16")]
10439#[cfg_attr(test, assert_instr(vrndscalesh, IMM8 = 0, SAE = 8))]
10440#[rustc_legacy_const_generics(4, 5)]
10441#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10442pub fn _mm_mask_roundscale_round_sh<const IMM8: i32, const SAE: i32>(
10443    src: __m128h,
10444    k: __mmask8,
10445    a: __m128h,
10446    b: __m128h,
10447) -> __m128h {
10448    unsafe {
10449        static_assert_uimm_bits!(IMM8, 8);
10450        static_assert_sae!(SAE);
10451        vrndscalesh(a, b, src, k, IMM8, SAE)
10452    }
10453}
10454
10455/// Round the lower half-precision (16-bit) floating-point element in b to the number of fraction bits
10456/// specified by imm8, store the result in the lower element of dst using zeromask k (the element is zeroed
10457/// out when mask bit 0 is not set), and copy the upper 7 packed elements from a to the upper elements of dst.
10458///
10459/// Rounding is done according to the imm8 parameter, which can be one of:
10460///
10461/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest
10462/// * [`_MM_FROUND_TO_NEG_INF`] : round down
10463/// * [`_MM_FROUND_TO_POS_INF`] : round up
10464/// * [`_MM_FROUND_TO_ZERO`] : truncate
10465/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
10466///
10467/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter
10468///
10469/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_roundscale_round_sh)
10470#[inline]
10471#[target_feature(enable = "avx512fp16")]
10472#[cfg_attr(test, assert_instr(vrndscalesh, IMM8 = 0, SAE = 8))]
10473#[rustc_legacy_const_generics(3, 4)]
10474#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10475pub fn _mm_maskz_roundscale_round_sh<const IMM8: i32, const SAE: i32>(
10476    k: __mmask8,
10477    a: __m128h,
10478    b: __m128h,
10479) -> __m128h {
10480    static_assert_uimm_bits!(IMM8, 8);
10481    static_assert_sae!(SAE);
10482    _mm_mask_roundscale_round_sh::<IMM8, SAE>(f16x8::ZERO.as_m128h(), k, a, b)
10483}
10484
10485/// Scale the packed half-precision (16-bit) floating-point elements in a using values from b, and store
10486/// the results in dst.
10487///
10488/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_scalef_ph)
10489#[inline]
10490#[target_feature(enable = "avx512fp16,avx512vl")]
10491#[cfg_attr(test, assert_instr(vscalefph))]
10492#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10493pub fn _mm_scalef_ph(a: __m128h, b: __m128h) -> __m128h {
10494    _mm_mask_scalef_ph(_mm_undefined_ph(), 0xff, a, b)
10495}
10496
10497/// Scale the packed half-precision (16-bit) floating-point elements in a using values from b, and store
10498/// the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
10499///
10500/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_scalef_ph)
10501#[inline]
10502#[target_feature(enable = "avx512fp16,avx512vl")]
10503#[cfg_attr(test, assert_instr(vscalefph))]
10504#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10505pub fn _mm_mask_scalef_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
10506    unsafe { vscalefph_128(a, b, src, k) }
10507}
10508
10509/// Scale the packed half-precision (16-bit) floating-point elements in a using values from b, and store
10510/// the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
10511///
10512/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_scalef_ph)
10513#[inline]
10514#[target_feature(enable = "avx512fp16,avx512vl")]
10515#[cfg_attr(test, assert_instr(vscalefph))]
10516#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10517pub fn _mm_maskz_scalef_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
10518    _mm_mask_scalef_ph(_mm_setzero_ph(), k, a, b)
10519}
10520
10521/// Scale the packed half-precision (16-bit) floating-point elements in a using values from b, and store
10522/// the results in dst.
10523///
10524/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_scalef_ph)
10525#[inline]
10526#[target_feature(enable = "avx512fp16,avx512vl")]
10527#[cfg_attr(test, assert_instr(vscalefph))]
10528#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10529pub fn _mm256_scalef_ph(a: __m256h, b: __m256h) -> __m256h {
10530    _mm256_mask_scalef_ph(_mm256_undefined_ph(), 0xffff, a, b)
10531}
10532
10533/// Scale the packed half-precision (16-bit) floating-point elements in a using values from b, and store
10534/// the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
10535///
10536/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_scalef_ph)
10537#[inline]
10538#[target_feature(enable = "avx512fp16,avx512vl")]
10539#[cfg_attr(test, assert_instr(vscalefph))]
10540#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10541pub fn _mm256_mask_scalef_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
10542    unsafe { vscalefph_256(a, b, src, k) }
10543}
10544
10545/// Scale the packed half-precision (16-bit) floating-point elements in a using values from b, and store
10546/// the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
10547///
10548/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_scalef_ph)
10549#[inline]
10550#[target_feature(enable = "avx512fp16,avx512vl")]
10551#[cfg_attr(test, assert_instr(vscalefph))]
10552#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10553pub fn _mm256_maskz_scalef_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
10554    _mm256_mask_scalef_ph(_mm256_setzero_ph(), k, a, b)
10555}
10556
10557/// Scale the packed half-precision (16-bit) floating-point elements in a using values from b, and store
10558/// the results in dst.
10559///
10560/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_scalef_ph)
10561#[inline]
10562#[target_feature(enable = "avx512fp16")]
10563#[cfg_attr(test, assert_instr(vscalefph))]
10564#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10565pub fn _mm512_scalef_ph(a: __m512h, b: __m512h) -> __m512h {
10566    _mm512_mask_scalef_ph(_mm512_undefined_ph(), 0xffffffff, a, b)
10567}
10568
10569/// Scale the packed half-precision (16-bit) floating-point elements in a using values from b, and store
10570/// the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
10571///
10572/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_scalef_ph)
10573#[inline]
10574#[target_feature(enable = "avx512fp16")]
10575#[cfg_attr(test, assert_instr(vscalefph))]
10576#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10577pub fn _mm512_mask_scalef_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
10578    _mm512_mask_scalef_round_ph::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b)
10579}
10580
10581/// Scale the packed half-precision (16-bit) floating-point elements in a using values from b, and store
10582/// the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
10583///
10584/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_scalef_ph)
10585#[inline]
10586#[target_feature(enable = "avx512fp16")]
10587#[cfg_attr(test, assert_instr(vscalefph))]
10588#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10589pub fn _mm512_maskz_scalef_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
10590    _mm512_mask_scalef_ph(_mm512_setzero_ph(), k, a, b)
10591}
10592
10593/// Scale the packed half-precision (16-bit) floating-point elements in a using values from b, and store
10594/// the results in dst.
10595///
10596/// Rounding is done according to the rounding parameter, which can be one of:
10597///
10598/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
10599/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
10600/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
10601/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
10602/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
10603///
10604/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_scalef_round_ph)
10605#[inline]
10606#[target_feature(enable = "avx512fp16")]
10607#[cfg_attr(test, assert_instr(vscalefph, ROUNDING = 8))]
10608#[rustc_legacy_const_generics(2)]
10609#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10610pub fn _mm512_scalef_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __m512h {
10611    static_assert_rounding!(ROUNDING);
10612    _mm512_mask_scalef_round_ph::<ROUNDING>(_mm512_undefined_ph(), 0xffffffff, a, b)
10613}
10614
10615/// Scale the packed half-precision (16-bit) floating-point elements in a using values from b, and store
10616/// the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
10617///
10618/// Rounding is done according to the rounding parameter, which can be one of:
10619///
10620/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
10621/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
10622/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
10623/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
10624/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
10625///
10626/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_scalef_round_ph)
10627#[inline]
10628#[target_feature(enable = "avx512fp16")]
10629#[cfg_attr(test, assert_instr(vscalefph, ROUNDING = 8))]
10630#[rustc_legacy_const_generics(4)]
10631#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10632pub fn _mm512_mask_scalef_round_ph<const ROUNDING: i32>(
10633    src: __m512h,
10634    k: __mmask32,
10635    a: __m512h,
10636    b: __m512h,
10637) -> __m512h {
10638    unsafe {
10639        static_assert_rounding!(ROUNDING);
10640        vscalefph_512(a, b, src, k, ROUNDING)
10641    }
10642}
10643
10644/// Scale the packed half-precision (16-bit) floating-point elements in a using values from b, and store
10645/// the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
10646///
10647/// Rounding is done according to the rounding parameter, which can be one of:
10648///
10649/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
10650/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
10651/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
10652/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
10653/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
10654///
10655/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_scalef_round_ph)
10656#[inline]
10657#[target_feature(enable = "avx512fp16")]
10658#[cfg_attr(test, assert_instr(vscalefph, ROUNDING = 8))]
10659#[rustc_legacy_const_generics(3)]
10660#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10661pub fn _mm512_maskz_scalef_round_ph<const ROUNDING: i32>(
10662    k: __mmask32,
10663    a: __m512h,
10664    b: __m512h,
10665) -> __m512h {
10666    static_assert_rounding!(ROUNDING);
10667    _mm512_mask_scalef_round_ph::<ROUNDING>(_mm512_setzero_ph(), k, a, b)
10668}
10669
10670/// Scale the packed single-precision (32-bit) floating-point elements in a using values from b, store
10671/// the result in the lower element of dst, and copy the upper 7 packed elements from a to the upper
10672/// elements of dst.
10673///
10674/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_scalef_sh)
10675#[inline]
10676#[target_feature(enable = "avx512fp16")]
10677#[cfg_attr(test, assert_instr(vscalefsh))]
10678#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10679pub fn _mm_scalef_sh(a: __m128h, b: __m128h) -> __m128h {
10680    _mm_mask_scalef_sh(f16x8::ZERO.as_m128h(), 0xff, a, b)
10681}
10682
10683/// Scale the packed single-precision (32-bit) floating-point elements in a using values from b, store
10684/// the result in the lower element of dst using writemask k (the element is copied from src when mask bit 0 is not set),
10685/// and copy the upper 7 packed elements from a to the upper elements of dst.
10686///
10687/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_scalef_sh)
10688#[inline]
10689#[target_feature(enable = "avx512fp16")]
10690#[cfg_attr(test, assert_instr(vscalefsh))]
10691#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10692pub fn _mm_mask_scalef_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
10693    _mm_mask_scalef_round_sh::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b)
10694}
10695
10696/// Scale the packed single-precision (32-bit) floating-point elements in a using values from b, store
10697/// the result in the lower element of dst using zeromask k (the element is zeroed out when mask bit 0 is not set),
10698/// and copy the upper 7 packed elements from a to the upper elements of dst.
10699///
10700/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_scalef_sh)
10701#[inline]
10702#[target_feature(enable = "avx512fp16")]
10703#[cfg_attr(test, assert_instr(vscalefsh))]
10704#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10705pub fn _mm_maskz_scalef_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
10706    _mm_mask_scalef_sh(f16x8::ZERO.as_m128h(), k, a, b)
10707}
10708
10709/// Scale the packed single-precision (32-bit) floating-point elements in a using values from b, store
10710/// the result in the lower element of dst, and copy the upper 7 packed elements from a to the upper
10711/// elements of dst.
10712///
10713/// Rounding is done according to the rounding parameter, which can be one of:
10714///
10715/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
10716/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
10717/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
10718/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
10719/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
10720///
10721/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_scalef_round_sh)
10722#[inline]
10723#[target_feature(enable = "avx512fp16")]
10724#[cfg_attr(test, assert_instr(vscalefsh, ROUNDING = 8))]
10725#[rustc_legacy_const_generics(2)]
10726#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10727pub fn _mm_scalef_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128h {
10728    static_assert_rounding!(ROUNDING);
10729    _mm_mask_scalef_round_sh::<ROUNDING>(f16x8::ZERO.as_m128h(), 0xff, a, b)
10730}
10731
10732/// Scale the packed single-precision (32-bit) floating-point elements in a using values from b, store
10733/// the result in the lower element of dst using writemask k (the element is copied from src when mask bit 0 is not set),
10734/// and copy the upper 7 packed elements from a to the upper elements of dst.
10735///
10736/// Rounding is done according to the rounding parameter, which can be one of:
10737///
10738/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
10739/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
10740/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
10741/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
10742/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
10743///
10744/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_scalef_round_sh)
10745#[inline]
10746#[target_feature(enable = "avx512fp16")]
10747#[cfg_attr(test, assert_instr(vscalefsh, ROUNDING = 8))]
10748#[rustc_legacy_const_generics(4)]
10749#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10750pub fn _mm_mask_scalef_round_sh<const ROUNDING: i32>(
10751    src: __m128h,
10752    k: __mmask8,
10753    a: __m128h,
10754    b: __m128h,
10755) -> __m128h {
10756    unsafe {
10757        static_assert_rounding!(ROUNDING);
10758        vscalefsh(a, b, src, k, ROUNDING)
10759    }
10760}
10761
10762/// Scale the packed single-precision (32-bit) floating-point elements in a using values from b, store
10763/// the result in the lower element of dst using zeromask k (the element is zeroed out when mask bit 0 is not set),
10764/// and copy the upper 7 packed elements from a to the upper elements of dst.
10765///
10766/// Rounding is done according to the rounding parameter, which can be one of:
10767///
10768/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
10769/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
10770/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
10771/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
10772/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
10773///
10774/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_scalef_round_sh)
10775#[inline]
10776#[target_feature(enable = "avx512fp16")]
10777#[cfg_attr(test, assert_instr(vscalefsh, ROUNDING = 8))]
10778#[rustc_legacy_const_generics(3)]
10779#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10780pub fn _mm_maskz_scalef_round_sh<const ROUNDING: i32>(
10781    k: __mmask8,
10782    a: __m128h,
10783    b: __m128h,
10784) -> __m128h {
10785    static_assert_rounding!(ROUNDING);
10786    _mm_mask_scalef_round_sh::<ROUNDING>(f16x8::ZERO.as_m128h(), k, a, b)
10787}
10788
10789/// Extract the reduced argument of packed half-precision (16-bit) floating-point elements in a by the
10790/// number of bits specified by imm8, and store the results in dst.
10791///
10792/// Rounding is done according to the imm8 parameter, which can be one of:
10793///
10794/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest
10795/// * [`_MM_FROUND_TO_NEG_INF`] : round down
10796/// * [`_MM_FROUND_TO_POS_INF`] : round up
10797/// * [`_MM_FROUND_TO_ZERO`] : truncate
10798/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
10799///
10800/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_reduce_ph)
10801#[inline]
10802#[target_feature(enable = "avx512fp16,avx512vl")]
10803#[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))]
10804#[rustc_legacy_const_generics(1)]
10805#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10806pub fn _mm_reduce_ph<const IMM8: i32>(a: __m128h) -> __m128h {
10807    static_assert_uimm_bits!(IMM8, 8);
10808    _mm_mask_reduce_ph::<IMM8>(_mm_undefined_ph(), 0xff, a)
10809}
10810
10811/// Extract the reduced argument of packed half-precision (16-bit) floating-point elements in a by the
10812/// number of bits specified by imm8, and store the results in dst using writemask k (elements are copied
10813/// from src when the corresponding mask bit is not set).
10814///
10815/// Rounding is done according to the imm8 parameter, which can be one of:
10816///
10817/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest
10818/// * [`_MM_FROUND_TO_NEG_INF`] : round down
10819/// * [`_MM_FROUND_TO_POS_INF`] : round up
10820/// * [`_MM_FROUND_TO_ZERO`] : truncate
10821/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
10822///
10823/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_reduce_ph)
10824#[inline]
10825#[target_feature(enable = "avx512fp16,avx512vl")]
10826#[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))]
10827#[rustc_legacy_const_generics(3)]
10828#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10829pub fn _mm_mask_reduce_ph<const IMM8: i32>(src: __m128h, k: __mmask8, a: __m128h) -> __m128h {
10830    unsafe {
10831        static_assert_uimm_bits!(IMM8, 8);
10832        vreduceph_128(a, IMM8, src, k)
10833    }
10834}
10835
10836/// Extract the reduced argument of packed half-precision (16-bit) floating-point elements in a by the
10837/// number of bits specified by imm8, and store the results in dst using zeromask k (elements are zeroed
10838/// out when the corresponding mask bit is not set).
10839///
10840/// Rounding is done according to the imm8 parameter, which can be one of:
10841///
10842/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest
10843/// * [`_MM_FROUND_TO_NEG_INF`] : round down
10844/// * [`_MM_FROUND_TO_POS_INF`] : round up
10845/// * [`_MM_FROUND_TO_ZERO`] : truncate
10846/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
10847///
10848/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_reduce_ph)
10849#[inline]
10850#[target_feature(enable = "avx512fp16,avx512vl")]
10851#[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))]
10852#[rustc_legacy_const_generics(2)]
10853#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10854pub fn _mm_maskz_reduce_ph<const IMM8: i32>(k: __mmask8, a: __m128h) -> __m128h {
10855    static_assert_uimm_bits!(IMM8, 8);
10856    _mm_mask_reduce_ph::<IMM8>(_mm_setzero_ph(), k, a)
10857}
10858
10859/// Extract the reduced argument of packed half-precision (16-bit) floating-point elements in a by the
10860/// number of bits specified by imm8, and store the results in dst.
10861///
10862/// Rounding is done according to the imm8 parameter, which can be one of:
10863///
10864/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest
10865/// * [`_MM_FROUND_TO_NEG_INF`] : round down
10866/// * [`_MM_FROUND_TO_POS_INF`] : round up
10867/// * [`_MM_FROUND_TO_ZERO`] : truncate
10868/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
10869///
10870/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_reduce_ph)
10871#[inline]
10872#[target_feature(enable = "avx512fp16,avx512vl")]
10873#[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))]
10874#[rustc_legacy_const_generics(1)]
10875#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10876pub fn _mm256_reduce_ph<const IMM8: i32>(a: __m256h) -> __m256h {
10877    static_assert_uimm_bits!(IMM8, 8);
10878    _mm256_mask_reduce_ph::<IMM8>(_mm256_undefined_ph(), 0xffff, a)
10879}
10880
10881/// Extract the reduced argument of packed half-precision (16-bit) floating-point elements in a by the
10882/// number of bits specified by imm8, and store the results in dst using writemask k (elements are copied
10883/// from src when the corresponding mask bit is not set).
10884///
10885/// Rounding is done according to the imm8 parameter, which can be one of:
10886///
10887/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest
10888/// * [`_MM_FROUND_TO_NEG_INF`] : round down
10889/// * [`_MM_FROUND_TO_POS_INF`] : round up
10890/// * [`_MM_FROUND_TO_ZERO`] : truncate
10891/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
10892///
10893/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_reduce_ph)
10894#[inline]
10895#[target_feature(enable = "avx512fp16,avx512vl")]
10896#[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))]
10897#[rustc_legacy_const_generics(3)]
10898#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10899pub fn _mm256_mask_reduce_ph<const IMM8: i32>(src: __m256h, k: __mmask16, a: __m256h) -> __m256h {
10900    unsafe {
10901        static_assert_uimm_bits!(IMM8, 8);
10902        vreduceph_256(a, IMM8, src, k)
10903    }
10904}
10905
10906/// Extract the reduced argument of packed half-precision (16-bit) floating-point elements in a by the
10907/// number of bits specified by imm8, and store the results in dst using zeromask k (elements are zeroed
10908/// out when the corresponding mask bit is not set).
10909///
10910/// Rounding is done according to the imm8 parameter, which can be one of:
10911///
10912/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest
10913/// * [`_MM_FROUND_TO_NEG_INF`] : round down
10914/// * [`_MM_FROUND_TO_POS_INF`] : round up
10915/// * [`_MM_FROUND_TO_ZERO`] : truncate
10916/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
10917///
10918/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_reduce_ph)
10919#[inline]
10920#[target_feature(enable = "avx512fp16,avx512vl")]
10921#[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))]
10922#[rustc_legacy_const_generics(2)]
10923#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10924pub fn _mm256_maskz_reduce_ph<const IMM8: i32>(k: __mmask16, a: __m256h) -> __m256h {
10925    static_assert_uimm_bits!(IMM8, 8);
10926    _mm256_mask_reduce_ph::<IMM8>(_mm256_setzero_ph(), k, a)
10927}
10928
10929/// Extract the reduced argument of packed half-precision (16-bit) floating-point elements in a by the
10930/// number of bits specified by imm8, and store the results in dst.
10931///
10932/// Rounding is done according to the imm8 parameter, which can be one of:
10933///
10934/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest
10935/// * [`_MM_FROUND_TO_NEG_INF`] : round down
10936/// * [`_MM_FROUND_TO_POS_INF`] : round up
10937/// * [`_MM_FROUND_TO_ZERO`] : truncate
10938/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
10939///
10940/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_ph)
10941#[inline]
10942#[target_feature(enable = "avx512fp16")]
10943#[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))]
10944#[rustc_legacy_const_generics(1)]
10945#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10946pub fn _mm512_reduce_ph<const IMM8: i32>(a: __m512h) -> __m512h {
10947    static_assert_uimm_bits!(IMM8, 8);
10948    _mm512_mask_reduce_ph::<IMM8>(_mm512_undefined_ph(), 0xffffffff, a)
10949}
10950
10951/// Extract the reduced argument of packed half-precision (16-bit) floating-point elements in a by the
10952/// number of bits specified by imm8, and store the results in dst using writemask k (elements are copied
10953/// from src when the corresponding mask bit is not set).
10954///
10955/// Rounding is done according to the imm8 parameter, which can be one of:
10956///
10957/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest
10958/// * [`_MM_FROUND_TO_NEG_INF`] : round down
10959/// * [`_MM_FROUND_TO_POS_INF`] : round up
10960/// * [`_MM_FROUND_TO_ZERO`] : truncate
10961/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
10962///
10963/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_ph)
10964#[inline]
10965#[target_feature(enable = "avx512fp16")]
10966#[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))]
10967#[rustc_legacy_const_generics(3)]
10968#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10969pub fn _mm512_mask_reduce_ph<const IMM8: i32>(src: __m512h, k: __mmask32, a: __m512h) -> __m512h {
10970    static_assert_uimm_bits!(IMM8, 8);
10971    _mm512_mask_reduce_round_ph::<IMM8, _MM_FROUND_CUR_DIRECTION>(src, k, a)
10972}
10973
10974/// Extract the reduced argument of packed half-precision (16-bit) floating-point elements in a by the
10975/// number of bits specified by imm8, and store the results in dst using zeromask k (elements are zeroed
10976/// out when the corresponding mask bit is not set).
10977///
10978/// Rounding is done according to the imm8 parameter, which can be one of:
10979///
10980/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest
10981/// * [`_MM_FROUND_TO_NEG_INF`] : round down
10982/// * [`_MM_FROUND_TO_POS_INF`] : round up
10983/// * [`_MM_FROUND_TO_ZERO`] : truncate
10984/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
10985///
10986/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_reduce_ph)
10987#[inline]
10988#[target_feature(enable = "avx512fp16")]
10989#[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))]
10990#[rustc_legacy_const_generics(2)]
10991#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
10992pub fn _mm512_maskz_reduce_ph<const IMM8: i32>(k: __mmask32, a: __m512h) -> __m512h {
10993    static_assert_uimm_bits!(IMM8, 8);
10994    _mm512_mask_reduce_ph::<IMM8>(_mm512_setzero_ph(), k, a)
10995}
10996
10997/// Extract the reduced argument of packed half-precision (16-bit) floating-point elements in a by the
10998/// number of bits specified by imm8, and store the results in dst.
10999///
11000/// Rounding is done according to the imm8 parameter, which can be one of:
11001///
11002/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest
11003/// * [`_MM_FROUND_TO_NEG_INF`] : round down
11004/// * [`_MM_FROUND_TO_POS_INF`] : round up
11005/// * [`_MM_FROUND_TO_ZERO`] : truncate
11006/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
11007///
11008/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
11009///
11010/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_round_ph)
11011#[inline]
11012#[target_feature(enable = "avx512fp16")]
11013#[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0, SAE = 8))]
11014#[rustc_legacy_const_generics(1, 2)]
11015#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
11016pub fn _mm512_reduce_round_ph<const IMM8: i32, const SAE: i32>(a: __m512h) -> __m512h {
11017    static_assert_uimm_bits!(IMM8, 8);
11018    static_assert_sae!(SAE);
11019    _mm512_mask_reduce_round_ph::<IMM8, SAE>(_mm512_undefined_ph(), 0xffffffff, a)
11020}
11021
11022/// Extract the reduced argument of packed half-precision (16-bit) floating-point elements in a by the
11023/// number of bits specified by imm8, and store the results in dst using writemask k (elements are copied
11024/// from src when the corresponding mask bit is not set).
11025///
11026/// Rounding is done according to the imm8 parameter, which can be one of:
11027///
11028/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest
11029/// * [`_MM_FROUND_TO_NEG_INF`] : round down
11030/// * [`_MM_FROUND_TO_POS_INF`] : round up
11031/// * [`_MM_FROUND_TO_ZERO`] : truncate
11032/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
11033///
11034/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
11035///
11036/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_round_ph)
11037#[inline]
11038#[target_feature(enable = "avx512fp16")]
11039#[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0, SAE = 8))]
11040#[rustc_legacy_const_generics(3, 4)]
11041#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
11042pub fn _mm512_mask_reduce_round_ph<const IMM8: i32, const SAE: i32>(
11043    src: __m512h,
11044    k: __mmask32,
11045    a: __m512h,
11046) -> __m512h {
11047    unsafe {
11048        static_assert_uimm_bits!(IMM8, 8);
11049        static_assert_sae!(SAE);
11050        vreduceph_512(a, IMM8, src, k, SAE)
11051    }
11052}
11053
11054/// Extract the reduced argument of packed half-precision (16-bit) floating-point elements in a by the
11055/// number of bits specified by imm8, and store the results in dst using zeromask k (elements are zeroed
11056/// out when the corresponding mask bit is not set).
11057///
11058/// Rounding is done according to the imm8 parameter, which can be one of:
11059///
11060/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest
11061/// * [`_MM_FROUND_TO_NEG_INF`] : round down
11062/// * [`_MM_FROUND_TO_POS_INF`] : round up
11063/// * [`_MM_FROUND_TO_ZERO`] : truncate
11064/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
11065///
11066/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
11067///
11068/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_reduce_round_ph)
11069#[inline]
11070#[target_feature(enable = "avx512fp16")]
11071#[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0, SAE = 8))]
11072#[rustc_legacy_const_generics(2, 3)]
11073#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
11074pub fn _mm512_maskz_reduce_round_ph<const IMM8: i32, const SAE: i32>(
11075    k: __mmask32,
11076    a: __m512h,
11077) -> __m512h {
11078    static_assert_uimm_bits!(IMM8, 8);
11079    static_assert_sae!(SAE);
11080    _mm512_mask_reduce_round_ph::<IMM8, SAE>(_mm512_setzero_ph(), k, a)
11081}
11082
11083/// Extract the reduced argument of the lower half-precision (16-bit) floating-point element in b by
11084/// the number of bits specified by imm8, store the result in the lower element of dst, and copy the
11085/// upper 7 packed elements from a to the upper elements of dst.
11086///
11087/// Rounding is done according to the imm8 parameter, which can be one of:
11088///
11089/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest
11090/// * [`_MM_FROUND_TO_NEG_INF`] : round down
11091/// * [`_MM_FROUND_TO_POS_INF`] : round up
11092/// * [`_MM_FROUND_TO_ZERO`] : truncate
11093/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
11094///
11095/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_reduce_sh)
11096#[inline]
11097#[target_feature(enable = "avx512fp16")]
11098#[cfg_attr(test, assert_instr(vreducesh, IMM8 = 0))]
11099#[rustc_legacy_const_generics(2)]
11100#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
11101pub fn _mm_reduce_sh<const IMM8: i32>(a: __m128h, b: __m128h) -> __m128h {
11102    static_assert_uimm_bits!(IMM8, 8);
11103    _mm_mask_reduce_sh::<IMM8>(f16x8::ZERO.as_m128h(), 0xff, a, b)
11104}
11105
11106/// Extract the reduced argument of the lower half-precision (16-bit) floating-point element in b by
11107/// the number of bits specified by imm8, store the result in the lower element of dst using writemask k
11108/// (the element is copied from src when mask bit 0 is not set), and copy the upper 7 packed elements from
11109/// a to the upper elements of dst.
11110///
11111/// Rounding is done according to the imm8 parameter, which can be one of:
11112///
11113/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest
11114/// * [`_MM_FROUND_TO_NEG_INF`] : round down
11115/// * [`_MM_FROUND_TO_POS_INF`] : round up
11116/// * [`_MM_FROUND_TO_ZERO`] : truncate
11117/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
11118///
11119/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_reduce_sh)
11120#[inline]
11121#[target_feature(enable = "avx512fp16")]
11122#[cfg_attr(test, assert_instr(vreducesh, IMM8 = 0))]
11123#[rustc_legacy_const_generics(4)]
11124#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
11125pub fn _mm_mask_reduce_sh<const IMM8: i32>(
11126    src: __m128h,
11127    k: __mmask8,
11128    a: __m128h,
11129    b: __m128h,
11130) -> __m128h {
11131    static_assert_uimm_bits!(IMM8, 8);
11132    _mm_mask_reduce_round_sh::<IMM8, _MM_FROUND_CUR_DIRECTION>(src, k, a, b)
11133}
11134
11135/// Extract the reduced argument of the lower half-precision (16-bit) floating-point element in b by
11136/// the number of bits specified by imm8, store the result in the lower element of dst using zeromask k
11137/// (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from a
11138/// to the upper elements of dst.
11139///
11140/// Rounding is done according to the imm8 parameter, which can be one of:
11141///
11142/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest
11143/// * [`_MM_FROUND_TO_NEG_INF`] : round down
11144/// * [`_MM_FROUND_TO_POS_INF`] : round up
11145/// * [`_MM_FROUND_TO_ZERO`] : truncate
11146/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
11147///
11148/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_reduce_sh)
11149#[inline]
11150#[target_feature(enable = "avx512fp16")]
11151#[cfg_attr(test, assert_instr(vreducesh, IMM8 = 0))]
11152#[rustc_legacy_const_generics(3)]
11153#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
11154pub fn _mm_maskz_reduce_sh<const IMM8: i32>(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
11155    static_assert_uimm_bits!(IMM8, 8);
11156    _mm_mask_reduce_sh::<IMM8>(f16x8::ZERO.as_m128h(), k, a, b)
11157}
11158
11159/// Extract the reduced argument of the lower half-precision (16-bit) floating-point element in b by
11160/// the number of bits specified by imm8, store the result in the lower element of dst, and copy the upper
11161/// 7 packed elements from a to the upper elements of dst.
11162///
11163/// Rounding is done according to the imm8 parameter, which can be one of:
11164///
11165/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest
11166/// * [`_MM_FROUND_TO_NEG_INF`] : round down
11167/// * [`_MM_FROUND_TO_POS_INF`] : round up
11168/// * [`_MM_FROUND_TO_ZERO`] : truncate
11169/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
11170///
11171/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
11172///
11173/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_reduce_round_sh)
11174#[inline]
11175#[target_feature(enable = "avx512fp16")]
11176#[cfg_attr(test, assert_instr(vreducesh, IMM8 = 0, SAE = 8))]
11177#[rustc_legacy_const_generics(2, 3)]
11178#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
11179pub fn _mm_reduce_round_sh<const IMM8: i32, const SAE: i32>(a: __m128h, b: __m128h) -> __m128h {
11180    static_assert_uimm_bits!(IMM8, 8);
11181    static_assert_sae!(SAE);
11182    _mm_mask_reduce_round_sh::<IMM8, SAE>(f16x8::ZERO.as_m128h(), 0xff, a, b)
11183}
11184
11185/// Extract the reduced argument of the lower half-precision (16-bit) floating-point element in b by
11186/// the number of bits specified by imm8, store the result in the lower element of dst using writemask k
11187/// (the element is copied from src when mask bit 0 is not set), and copy the upper 7 packed elements from a
11188/// to the upper elements of dst.
11189///
11190/// Rounding is done according to the imm8 parameter, which can be one of:
11191///
11192/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest
11193/// * [`_MM_FROUND_TO_NEG_INF`] : round down
11194/// * [`_MM_FROUND_TO_POS_INF`] : round up
11195/// * [`_MM_FROUND_TO_ZERO`] : truncate
11196/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
11197///
11198/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
11199///
11200/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_reduce_round_sh)
11201#[inline]
11202#[target_feature(enable = "avx512fp16")]
11203#[cfg_attr(test, assert_instr(vreducesh, IMM8 = 0, SAE = 8))]
11204#[rustc_legacy_const_generics(4, 5)]
11205#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
11206pub fn _mm_mask_reduce_round_sh<const IMM8: i32, const SAE: i32>(
11207    src: __m128h,
11208    k: __mmask8,
11209    a: __m128h,
11210    b: __m128h,
11211) -> __m128h {
11212    unsafe {
11213        static_assert_uimm_bits!(IMM8, 8);
11214        static_assert_sae!(SAE);
11215        vreducesh(a, b, src, k, IMM8, SAE)
11216    }
11217}
11218
11219/// Extract the reduced argument of the lower half-precision (16-bit) floating-point element in b by
11220/// the number of bits specified by imm8, store the result in the lower element of dst using zeromask k
11221/// (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from a
11222/// to the upper elements of dst.
11223///
11224/// Rounding is done according to the imm8 parameter, which can be one of:
11225///
11226/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest
11227/// * [`_MM_FROUND_TO_NEG_INF`] : round down
11228/// * [`_MM_FROUND_TO_POS_INF`] : round up
11229/// * [`_MM_FROUND_TO_ZERO`] : truncate
11230/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
11231///
11232/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
11233///
11234/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_reduce_round_sh)
11235#[inline]
11236#[target_feature(enable = "avx512fp16")]
11237#[cfg_attr(test, assert_instr(vreducesh, IMM8 = 0, SAE = 8))]
11238#[rustc_legacy_const_generics(3, 4)]
11239#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
11240pub fn _mm_maskz_reduce_round_sh<const IMM8: i32, const SAE: i32>(
11241    k: __mmask8,
11242    a: __m128h,
11243    b: __m128h,
11244) -> __m128h {
11245    static_assert_uimm_bits!(IMM8, 8);
11246    static_assert_sae!(SAE);
11247    _mm_mask_reduce_round_sh::<IMM8, SAE>(f16x8::ZERO.as_m128h(), k, a, b)
11248}
11249
11250/// Reduce the packed half-precision (16-bit) floating-point elements in a by addition. Returns the
11251/// sum of all elements in a.
11252///
11253/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_reduce_add_ph)
11254#[inline]
11255#[target_feature(enable = "avx512fp16,avx512vl")]
11256#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
11257#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
11258pub const fn _mm_reduce_add_ph(a: __m128h) -> f16 {
11259    unsafe {
11260        let b = simd_shuffle!(a, a, [4, 5, 6, 7, 0, 1, 2, 3]);
11261        let a = _mm_add_ph(a, b);
11262        let b = simd_shuffle!(a, a, [2, 3, 0, 1, 4, 5, 6, 7]);
11263        let a = _mm_add_ph(a, b);
11264        simd_extract!(a, 0, f16) + simd_extract!(a, 1, f16)
11265    }
11266}
11267
11268/// Reduce the packed half-precision (16-bit) floating-point elements in a by addition. Returns the
11269/// sum of all elements in a.
11270///
11271/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_reduce_add_ph)
11272#[inline]
11273#[target_feature(enable = "avx512fp16,avx512vl")]
11274#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
11275#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
11276pub const fn _mm256_reduce_add_ph(a: __m256h) -> f16 {
11277    unsafe {
11278        let p = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]);
11279        let q = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
11280        _mm_reduce_add_ph(_mm_add_ph(p, q))
11281    }
11282}
11283
11284/// Reduce the packed half-precision (16-bit) floating-point elements in a by addition. Returns the
11285/// sum of all elements in a.
11286///
11287/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_add_ph)
11288#[inline]
11289#[target_feature(enable = "avx512fp16")]
11290#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
11291#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
11292pub const fn _mm512_reduce_add_ph(a: __m512h) -> f16 {
11293    unsafe {
11294        let p = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]);
11295        let q = simd_shuffle!(
11296            a,
11297            a,
11298            [
11299                16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
11300            ]
11301        );
11302        _mm256_reduce_add_ph(_mm256_add_ph(p, q))
11303    }
11304}
11305
11306/// Reduce the packed half-precision (16-bit) floating-point elements in a by multiplication. Returns
11307/// the product of all elements in a.
11308///
11309/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_reduce_mul_ph)
11310#[inline]
11311#[target_feature(enable = "avx512fp16,avx512vl")]
11312#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
11313#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
11314pub const fn _mm_reduce_mul_ph(a: __m128h) -> f16 {
11315    unsafe {
11316        let b = simd_shuffle!(a, a, [4, 5, 6, 7, 0, 1, 2, 3]);
11317        let a = _mm_mul_ph(a, b);
11318        let b = simd_shuffle!(a, a, [2, 3, 0, 1, 4, 5, 6, 7]);
11319        let a = _mm_mul_ph(a, b);
11320        simd_extract!(a, 0, f16) * simd_extract!(a, 1, f16)
11321    }
11322}
11323
11324/// Reduce the packed half-precision (16-bit) floating-point elements in a by multiplication. Returns
11325/// the product of all elements in a.
11326///
11327/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_reduce_mul_ph)
11328#[inline]
11329#[target_feature(enable = "avx512fp16,avx512vl")]
11330#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
11331#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
11332pub const fn _mm256_reduce_mul_ph(a: __m256h) -> f16 {
11333    unsafe {
11334        let p = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]);
11335        let q = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
11336        _mm_reduce_mul_ph(_mm_mul_ph(p, q))
11337    }
11338}
11339
11340/// Reduce the packed half-precision (16-bit) floating-point elements in a by multiplication. Returns
11341/// the product of all elements in a.
11342///
11343/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_mul_ph)
11344#[inline]
11345#[target_feature(enable = "avx512fp16")]
11346#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
11347#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
11348pub const fn _mm512_reduce_mul_ph(a: __m512h) -> f16 {
11349    unsafe {
11350        let p = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]);
11351        let q = simd_shuffle!(
11352            a,
11353            a,
11354            [
11355                16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
11356            ]
11357        );
11358        _mm256_reduce_mul_ph(_mm256_mul_ph(p, q))
11359    }
11360}
11361
11362/// Reduce the packed half-precision (16-bit) floating-point elements in a by minimum. Returns the
11363/// minimum of all elements in a.
11364///
11365/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_reduce_min_ph)
11366#[inline]
11367#[target_feature(enable = "avx512fp16,avx512vl")]
11368#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
11369pub fn _mm_reduce_min_ph(a: __m128h) -> f16 {
11370    unsafe {
11371        let b = simd_shuffle!(a, a, [4, 5, 6, 7, 0, 1, 2, 3]);
11372        let a = _mm_min_ph(a, b);
11373        let b = simd_shuffle!(a, a, [2, 3, 0, 1, 4, 5, 6, 7]);
11374        let a = _mm_min_ph(a, b);
11375        let b = simd_shuffle!(a, a, [1, 0, 2, 3, 4, 5, 6, 7]);
11376        simd_extract!(_mm_min_sh(a, b), 0)
11377    }
11378}
11379
11380/// Reduce the packed half-precision (16-bit) floating-point elements in a by minimum. Returns the
11381/// minimum of all elements in a.
11382///
11383/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_reduce_min_ph)
11384#[inline]
11385#[target_feature(enable = "avx512fp16,avx512vl")]
11386#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
11387pub fn _mm256_reduce_min_ph(a: __m256h) -> f16 {
11388    unsafe {
11389        let p = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]);
11390        let q = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
11391        _mm_reduce_min_ph(_mm_min_ph(p, q))
11392    }
11393}
11394
11395/// Reduce the packed half-precision (16-bit) floating-point elements in a by minimum. Returns the
11396/// minimum of all elements in a.
11397///
11398/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_min_ph)
11399#[inline]
11400#[target_feature(enable = "avx512fp16")]
11401#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
11402pub fn _mm512_reduce_min_ph(a: __m512h) -> f16 {
11403    unsafe {
11404        let p = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]);
11405        let q = simd_shuffle!(
11406            a,
11407            a,
11408            [
11409                16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
11410            ]
11411        );
11412        _mm256_reduce_min_ph(_mm256_min_ph(p, q))
11413    }
11414}
11415
11416/// Reduce the packed half-precision (16-bit) floating-point elements in a by maximum. Returns the
11417/// maximum of all elements in a.
11418///
11419/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_reduce_max_ph)
11420#[inline]
11421#[target_feature(enable = "avx512fp16,avx512vl")]
11422#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
11423pub fn _mm_reduce_max_ph(a: __m128h) -> f16 {
11424    unsafe {
11425        let b = simd_shuffle!(a, a, [4, 5, 6, 7, 0, 1, 2, 3]);
11426        let a = _mm_max_ph(a, b);
11427        let b = simd_shuffle!(a, a, [2, 3, 0, 1, 4, 5, 6, 7]);
11428        let a = _mm_max_ph(a, b);
11429        let b = simd_shuffle!(a, a, [1, 0, 2, 3, 4, 5, 6, 7]);
11430        simd_extract!(_mm_max_sh(a, b), 0)
11431    }
11432}
11433
11434/// Reduce the packed half-precision (16-bit) floating-point elements in a by maximum. Returns the
11435/// maximum of all elements in a.
11436///
11437/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_reduce_max_ph)
11438#[inline]
11439#[target_feature(enable = "avx512fp16,avx512vl")]
11440#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
11441pub fn _mm256_reduce_max_ph(a: __m256h) -> f16 {
11442    unsafe {
11443        let p = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]);
11444        let q = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
11445        _mm_reduce_max_ph(_mm_max_ph(p, q))
11446    }
11447}
11448
11449/// Reduce the packed half-precision (16-bit) floating-point elements in a by maximum. Returns the
11450/// maximum of all elements in a.
11451///
11452/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_max_ph)
11453#[inline]
11454#[target_feature(enable = "avx512fp16")]
11455#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
11456pub fn _mm512_reduce_max_ph(a: __m512h) -> f16 {
11457    unsafe {
11458        let p = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]);
11459        let q = simd_shuffle!(
11460            a,
11461            a,
11462            [
11463                16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
11464            ]
11465        );
11466        _mm256_reduce_max_ph(_mm256_max_ph(p, q))
11467    }
11468}
11469
11470/// Test packed half-precision (16-bit) floating-point elements in a for special categories specified
11471/// by imm8, and store the results in mask vector k.
11472/// imm can be a combination of:
11473///
11474///     0x01 // QNaN
11475///     0x02 // Positive Zero
11476///     0x04 // Negative Zero
11477///     0x08 // Positive Infinity
11478///     0x10 // Negative Infinity
11479///     0x20 // Denormal
11480///     0x40 // Negative
11481///     0x80 // SNaN
11482///
11483/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fpclass_ph_mask)
11484#[inline]
11485#[target_feature(enable = "avx512fp16,avx512vl")]
11486#[cfg_attr(test, assert_instr(vfpclassph, IMM8 = 0))]
11487#[rustc_legacy_const_generics(1)]
11488#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
11489pub fn _mm_fpclass_ph_mask<const IMM8: i32>(a: __m128h) -> __mmask8 {
11490    unsafe {
11491        static_assert_uimm_bits!(IMM8, 8);
11492        vfpclassph_128(a, IMM8)
11493    }
11494}
11495
11496/// Test packed half-precision (16-bit) floating-point elements in a for special categories specified
11497/// by imm8, and store the results in mask vector k using zeromask k (elements are zeroed out when the
11498/// corresponding mask bit is not set).
11499/// imm can be a combination of:
11500///
11501///     0x01 // QNaN
11502///     0x02 // Positive Zero
11503///     0x04 // Negative Zero
11504///     0x08 // Positive Infinity
11505///     0x10 // Negative Infinity
11506///     0x20 // Denormal
11507///     0x40 // Negative
11508///     0x80 // SNaN
11509///
11510/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fpclass_ph_mask)
11511#[inline]
11512#[target_feature(enable = "avx512fp16,avx512vl")]
11513#[cfg_attr(test, assert_instr(vfpclassph, IMM8 = 0))]
11514#[rustc_legacy_const_generics(2)]
11515#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
11516pub fn _mm_mask_fpclass_ph_mask<const IMM8: i32>(k1: __mmask8, a: __m128h) -> __mmask8 {
11517    _mm_fpclass_ph_mask::<IMM8>(a) & k1
11518}
11519
11520/// Test packed half-precision (16-bit) floating-point elements in a for special categories specified
11521/// by imm8, and store the results in mask vector k.
11522/// imm can be a combination of:
11523///
11524///     0x01 // QNaN
11525///     0x02 // Positive Zero
11526///     0x04 // Negative Zero
11527///     0x08 // Positive Infinity
11528///     0x10 // Negative Infinity
11529///     0x20 // Denormal
11530///     0x40 // Negative
11531///     0x80 // SNaN
11532///
11533/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_fpclass_ph_mask)
11534#[inline]
11535#[target_feature(enable = "avx512fp16,avx512vl")]
11536#[cfg_attr(test, assert_instr(vfpclassph, IMM8 = 0))]
11537#[rustc_legacy_const_generics(1)]
11538#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
11539pub fn _mm256_fpclass_ph_mask<const IMM8: i32>(a: __m256h) -> __mmask16 {
11540    unsafe {
11541        static_assert_uimm_bits!(IMM8, 8);
11542        vfpclassph_256(a, IMM8)
11543    }
11544}
11545
11546/// Test packed half-precision (16-bit) floating-point elements in a for special categories specified
11547/// by imm8, and store the results in mask vector k using zeromask k (elements are zeroed out when the
11548/// corresponding mask bit is not set).
11549/// imm can be a combination of:
11550///
11551///     0x01 // QNaN
11552///     0x02 // Positive Zero
11553///     0x04 // Negative Zero
11554///     0x08 // Positive Infinity
11555///     0x10 // Negative Infinity
11556///     0x20 // Denormal
11557///     0x40 // Negative
11558///     0x80 // SNaN
11559///
11560/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_fpclass_ph_mask)
11561#[inline]
11562#[target_feature(enable = "avx512fp16,avx512vl")]
11563#[cfg_attr(test, assert_instr(vfpclassph, IMM8 = 0))]
11564#[rustc_legacy_const_generics(2)]
11565#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
11566pub fn _mm256_mask_fpclass_ph_mask<const IMM8: i32>(k1: __mmask16, a: __m256h) -> __mmask16 {
11567    _mm256_fpclass_ph_mask::<IMM8>(a) & k1
11568}
11569
11570/// Test packed half-precision (16-bit) floating-point elements in a for special categories specified
11571/// by imm8, and store the results in mask vector k.
11572/// imm can be a combination of:
11573///
11574///     0x01 // QNaN
11575///     0x02 // Positive Zero
11576///     0x04 // Negative Zero
11577///     0x08 // Positive Infinity
11578///     0x10 // Negative Infinity
11579///     0x20 // Denormal
11580///     0x40 // Negative
11581///     0x80 // SNaN
11582///
11583/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fpclass_ph_mask)
11584#[inline]
11585#[target_feature(enable = "avx512fp16")]
11586#[cfg_attr(test, assert_instr(vfpclassph, IMM8 = 0))]
11587#[rustc_legacy_const_generics(1)]
11588#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
11589pub fn _mm512_fpclass_ph_mask<const IMM8: i32>(a: __m512h) -> __mmask32 {
11590    unsafe {
11591        static_assert_uimm_bits!(IMM8, 8);
11592        vfpclassph_512(a, IMM8)
11593    }
11594}
11595
11596/// Test packed half-precision (16-bit) floating-point elements in a for special categories specified
11597/// by imm8, and store the results in mask vector k using zeromask k (elements are zeroed out when the
11598/// corresponding mask bit is not set).
11599/// imm can be a combination of:
11600///
11601///     0x01 // QNaN
11602///     0x02 // Positive Zero
11603///     0x04 // Negative Zero
11604///     0x08 // Positive Infinity
11605///     0x10 // Negative Infinity
11606///     0x20 // Denormal
11607///     0x40 // Negative
11608///     0x80 // SNaN
11609///
11610/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fpclass_ph_mask)
11611#[inline]
11612#[target_feature(enable = "avx512fp16")]
11613#[cfg_attr(test, assert_instr(vfpclassph, IMM8 = 0))]
11614#[rustc_legacy_const_generics(2)]
11615#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
11616pub fn _mm512_mask_fpclass_ph_mask<const IMM8: i32>(k1: __mmask32, a: __m512h) -> __mmask32 {
11617    _mm512_fpclass_ph_mask::<IMM8>(a) & k1
11618}
11619
11620/// Test the lower half-precision (16-bit) floating-point element in a for special categories specified
11621/// by imm8, and store the result in mask vector k.
11622/// imm can be a combination of:
11623///
11624///     0x01 // QNaN
11625///     0x02 // Positive Zero
11626///     0x04 // Negative Zero
11627///     0x08 // Positive Infinity
11628///     0x10 // Negative Infinity
11629///     0x20 // Denormal
11630///     0x40 // Negative
11631///     0x80 // SNaN
11632///
11633/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fpclass_sh_mask)
11634#[inline]
11635#[target_feature(enable = "avx512fp16")]
11636#[cfg_attr(test, assert_instr(vfpclasssh, IMM8 = 0))]
11637#[rustc_legacy_const_generics(1)]
11638#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
11639pub fn _mm_fpclass_sh_mask<const IMM8: i32>(a: __m128h) -> __mmask8 {
11640    _mm_mask_fpclass_sh_mask::<IMM8>(0xff, a)
11641}
11642
11643/// Test the lower half-precision (16-bit) floating-point element in a for special categories specified
11644/// by imm8, and store the result in mask vector k using zeromask k (elements are zeroed out when the
11645/// corresponding mask bit is not set).
11646/// imm can be a combination of:
11647///
11648///     0x01 // QNaN
11649///     0x02 // Positive Zero
11650///     0x04 // Negative Zero
11651///     0x08 // Positive Infinity
11652///     0x10 // Negative Infinity
11653///     0x20 // Denormal
11654///     0x40 // Negative
11655///     0x80 // SNaN
11656///
11657/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fpclass_sh_mask)
11658#[inline]
11659#[target_feature(enable = "avx512fp16")]
11660#[cfg_attr(test, assert_instr(vfpclasssh, IMM8 = 0))]
11661#[rustc_legacy_const_generics(2)]
11662#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
11663pub fn _mm_mask_fpclass_sh_mask<const IMM8: i32>(k1: __mmask8, a: __m128h) -> __mmask8 {
11664    unsafe {
11665        static_assert_uimm_bits!(IMM8, 8);
11666        vfpclasssh(a, IMM8, k1)
11667    }
11668}
11669
11670/// Blend packed half-precision (16-bit) floating-point elements from a and b using control mask k,
11671/// and store the results in dst.
11672///
11673/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_blend_ph)
11674#[inline]
11675#[target_feature(enable = "avx512fp16,avx512vl")]
11676#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
11677#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
11678pub const fn _mm_mask_blend_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
11679    unsafe { simd_select_bitmask(k, b, a) }
11680}
11681
11682/// Blend packed half-precision (16-bit) floating-point elements from a and b using control mask k,
11683/// and store the results in dst.
11684///
11685/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_blend_ph)
11686#[inline]
11687#[target_feature(enable = "avx512fp16,avx512vl")]
11688#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
11689#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
11690pub const fn _mm256_mask_blend_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
11691    unsafe { simd_select_bitmask(k, b, a) }
11692}
11693
11694/// Blend packed half-precision (16-bit) floating-point elements from a and b using control mask k,
11695/// and store the results in dst.
11696///
11697/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_blend_ph)
11698#[inline]
11699#[target_feature(enable = "avx512fp16")]
11700#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
11701#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
11702pub const fn _mm512_mask_blend_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
11703    unsafe { simd_select_bitmask(k, b, a) }
11704}
11705
11706/// Shuffle half-precision (16-bit) floating-point elements in a and b using the corresponding selector
11707/// and index in idx, and store the results in dst.
11708///
11709/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_permutex2var_ph)
11710#[inline]
11711#[target_feature(enable = "avx512fp16,avx512vl")]
11712#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
11713pub fn _mm_permutex2var_ph(a: __m128h, idx: __m128i, b: __m128h) -> __m128h {
11714    _mm_castsi128_ph(_mm_permutex2var_epi16(
11715        _mm_castph_si128(a),
11716        idx,
11717        _mm_castph_si128(b),
11718    ))
11719}
11720
11721/// Shuffle half-precision (16-bit) floating-point elements in a and b using the corresponding selector
11722/// and index in idx, and store the results in dst.
11723///
11724/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_permutex2var_ph)
11725#[inline]
11726#[target_feature(enable = "avx512fp16,avx512vl")]
11727#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
11728pub fn _mm256_permutex2var_ph(a: __m256h, idx: __m256i, b: __m256h) -> __m256h {
11729    _mm256_castsi256_ph(_mm256_permutex2var_epi16(
11730        _mm256_castph_si256(a),
11731        idx,
11732        _mm256_castph_si256(b),
11733    ))
11734}
11735
11736/// Shuffle half-precision (16-bit) floating-point elements in a and b using the corresponding selector
11737/// and index in idx, and store the results in dst.
11738///
11739/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_permutex2var_ph)
11740#[inline]
11741#[target_feature(enable = "avx512fp16")]
11742#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
11743pub fn _mm512_permutex2var_ph(a: __m512h, idx: __m512i, b: __m512h) -> __m512h {
11744    _mm512_castsi512_ph(_mm512_permutex2var_epi16(
11745        _mm512_castph_si512(a),
11746        idx,
11747        _mm512_castph_si512(b),
11748    ))
11749}
11750
11751/// Shuffle half-precision (16-bit) floating-point elements in a using the corresponding index in idx,
11752/// and store the results in dst.
11753///
11754/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_permutexvar_ph)
11755#[inline]
11756#[target_feature(enable = "avx512fp16,avx512vl")]
11757#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
11758pub fn _mm_permutexvar_ph(idx: __m128i, a: __m128h) -> __m128h {
11759    _mm_castsi128_ph(_mm_permutexvar_epi16(idx, _mm_castph_si128(a)))
11760}
11761
11762/// Shuffle half-precision (16-bit) floating-point elements in a using the corresponding index in idx,
11763/// and store the results in dst.
11764///
11765/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_permutexvar_ph)
11766#[inline]
11767#[target_feature(enable = "avx512fp16,avx512vl")]
11768#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
11769pub fn _mm256_permutexvar_ph(idx: __m256i, a: __m256h) -> __m256h {
11770    _mm256_castsi256_ph(_mm256_permutexvar_epi16(idx, _mm256_castph_si256(a)))
11771}
11772
11773/// Shuffle half-precision (16-bit) floating-point elements in a using the corresponding index in idx,
11774/// and store the results in dst.
11775///
11776/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_permutexvar_ph)
11777#[inline]
11778#[target_feature(enable = "avx512fp16")]
11779#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
11780pub fn _mm512_permutexvar_ph(idx: __m512i, a: __m512h) -> __m512h {
11781    _mm512_castsi512_ph(_mm512_permutexvar_epi16(idx, _mm512_castph_si512(a)))
11782}
11783
11784/// Convert packed signed 16-bit integers in a to packed half-precision (16-bit) floating-point elements,
11785/// and store the results in dst.
11786///
11787/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtepi16_ph)
11788#[inline]
11789#[target_feature(enable = "avx512fp16,avx512vl")]
11790#[cfg_attr(test, assert_instr(vcvtw2ph))]
11791#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
11792pub fn _mm_cvtepi16_ph(a: __m128i) -> __m128h {
11793    unsafe { vcvtw2ph_128(a.as_i16x8(), _MM_FROUND_CUR_DIRECTION) }
11794}
11795
11796/// Convert packed signed 16-bit integers in a to packed half-precision (16-bit) floating-point elements,
11797/// and store the results in dst using writemask k (elements are copied from src to dst when the corresponding
11798/// mask bit is not set).
11799///
11800/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cvtepi16_ph)
11801#[inline]
11802#[target_feature(enable = "avx512fp16,avx512vl")]
11803#[cfg_attr(test, assert_instr(vcvtw2ph))]
11804#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
11805pub fn _mm_mask_cvtepi16_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h {
11806    unsafe { simd_select_bitmask(k, _mm_cvtepi16_ph(a), src) }
11807}
11808
11809/// Convert packed signed 16-bit integers in a to packed half-precision (16-bit) floating-point elements,
11810/// and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
11811///
11812/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_cvtepi16_ph)
11813#[inline]
11814#[target_feature(enable = "avx512fp16,avx512vl")]
11815#[cfg_attr(test, assert_instr(vcvtw2ph))]
11816#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
11817pub fn _mm_maskz_cvtepi16_ph(k: __mmask8, a: __m128i) -> __m128h {
11818    _mm_mask_cvtepi16_ph(_mm_setzero_ph(), k, a)
11819}
11820
11821/// Convert packed signed 16-bit integers in a to packed half-precision (16-bit) floating-point elements,
11822/// and store the results in dst.
11823///
11824/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtepi16_ph)
11825#[inline]
11826#[target_feature(enable = "avx512fp16,avx512vl")]
11827#[cfg_attr(test, assert_instr(vcvtw2ph))]
11828#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
11829pub fn _mm256_cvtepi16_ph(a: __m256i) -> __m256h {
11830    unsafe { vcvtw2ph_256(a.as_i16x16(), _MM_FROUND_CUR_DIRECTION) }
11831}
11832
11833/// Convert packed signed 16-bit integers in a to packed half-precision (16-bit) floating-point elements,
11834/// and store the results in dst using writemask k (elements are copied from src to dst when the corresponding
11835/// mask bit is not set).
11836///
11837/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_cvtepi16_ph)
11838#[inline]
11839#[target_feature(enable = "avx512fp16,avx512vl")]
11840#[cfg_attr(test, assert_instr(vcvtw2ph))]
11841#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
11842pub fn _mm256_mask_cvtepi16_ph(src: __m256h, k: __mmask16, a: __m256i) -> __m256h {
11843    unsafe { simd_select_bitmask(k, _mm256_cvtepi16_ph(a), src) }
11844}
11845
11846/// Convert packed signed 16-bit integers in a to packed half-precision (16-bit) floating-point elements,
11847/// and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
11848///
11849/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_cvtepi16_ph)
11850#[inline]
11851#[target_feature(enable = "avx512fp16,avx512vl")]
11852#[cfg_attr(test, assert_instr(vcvtw2ph))]
11853#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
11854pub fn _mm256_maskz_cvtepi16_ph(k: __mmask16, a: __m256i) -> __m256h {
11855    _mm256_mask_cvtepi16_ph(_mm256_setzero_ph(), k, a)
11856}
11857
11858/// Convert packed signed 16-bit integers in a to packed half-precision (16-bit) floating-point elements,
11859/// and store the results in dst.
11860///
11861/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepi16_ph)
11862#[inline]
11863#[target_feature(enable = "avx512fp16")]
11864#[cfg_attr(test, assert_instr(vcvtw2ph))]
11865#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
11866pub fn _mm512_cvtepi16_ph(a: __m512i) -> __m512h {
11867    unsafe { vcvtw2ph_512(a.as_i16x32(), _MM_FROUND_CUR_DIRECTION) }
11868}
11869
11870/// Convert packed signed 16-bit integers in a to packed half-precision (16-bit) floating-point elements,
11871/// and store the results in dst using writemask k (elements are copied from src to dst when the corresponding
11872/// mask bit is not set).
11873///
11874/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepi16_ph)
11875#[inline]
11876#[target_feature(enable = "avx512fp16")]
11877#[cfg_attr(test, assert_instr(vcvtw2ph))]
11878#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
11879pub fn _mm512_mask_cvtepi16_ph(src: __m512h, k: __mmask32, a: __m512i) -> __m512h {
11880    unsafe { simd_select_bitmask(k, _mm512_cvtepi16_ph(a), src) }
11881}
11882
11883/// Convert packed signed 16-bit integers in a to packed half-precision (16-bit) floating-point elements,
11884/// and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
11885///
11886/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepi16_ph)
11887#[inline]
11888#[target_feature(enable = "avx512fp16")]
11889#[cfg_attr(test, assert_instr(vcvtw2ph))]
11890#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
11891pub fn _mm512_maskz_cvtepi16_ph(k: __mmask32, a: __m512i) -> __m512h {
11892    _mm512_mask_cvtepi16_ph(_mm512_setzero_ph(), k, a)
11893}
11894
11895/// Convert packed signed 16-bit integers in a to packed half-precision (16-bit) floating-point elements,
11896/// and store the results in dst.
11897///
11898/// Rounding is done according to the rounding parameter, which can be one of:
11899///
11900/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
11901/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
11902/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
11903/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
11904/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
11905///
11906/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvt_roundepi16_ph)
11907#[inline]
11908#[target_feature(enable = "avx512fp16")]
11909#[cfg_attr(test, assert_instr(vcvtw2ph, ROUNDING = 8))]
11910#[rustc_legacy_const_generics(1)]
11911#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
11912pub fn _mm512_cvt_roundepi16_ph<const ROUNDING: i32>(a: __m512i) -> __m512h {
11913    unsafe {
11914        static_assert_rounding!(ROUNDING);
11915        vcvtw2ph_512(a.as_i16x32(), ROUNDING)
11916    }
11917}
11918
11919/// Convert packed signed 16-bit integers in a to packed half-precision (16-bit) floating-point elements,
11920/// and store the results in dst using writemask k (elements are copied from src to dst when the corresponding
11921/// mask bit is not set).
11922///
11923/// Rounding is done according to the rounding parameter, which can be one of:
11924///
11925/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
11926/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
11927/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
11928/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
11929/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
11930///
11931/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvt_roundepi16_ph)
11932#[inline]
11933#[target_feature(enable = "avx512fp16")]
11934#[cfg_attr(test, assert_instr(vcvtw2ph, ROUNDING = 8))]
11935#[rustc_legacy_const_generics(3)]
11936#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
11937pub fn _mm512_mask_cvt_roundepi16_ph<const ROUNDING: i32>(
11938    src: __m512h,
11939    k: __mmask32,
11940    a: __m512i,
11941) -> __m512h {
11942    unsafe {
11943        static_assert_rounding!(ROUNDING);
11944        simd_select_bitmask(k, _mm512_cvt_roundepi16_ph::<ROUNDING>(a), src)
11945    }
11946}
11947
11948/// Convert packed signed 16-bit integers in a to packed half-precision (16-bit) floating-point elements,
11949/// and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
11950///
11951/// Rounding is done according to the rounding parameter, which can be one of:
11952///
11953/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
11954/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
11955/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
11956/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
11957/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
11958///
11959/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvt_roundepi16_ph)
11960#[inline]
11961#[target_feature(enable = "avx512fp16")]
11962#[cfg_attr(test, assert_instr(vcvtw2ph, ROUNDING = 8))]
11963#[rustc_legacy_const_generics(2)]
11964#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
11965pub fn _mm512_maskz_cvt_roundepi16_ph<const ROUNDING: i32>(k: __mmask32, a: __m512i) -> __m512h {
11966    static_assert_rounding!(ROUNDING);
11967    _mm512_mask_cvt_roundepi16_ph::<ROUNDING>(_mm512_setzero_ph(), k, a)
11968}
11969
11970/// Convert packed unsigned 16-bit integers in a to packed half-precision (16-bit) floating-point elements,
11971/// and store the results in dst.
11972///
11973/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtepu16_ph)
11974#[inline]
11975#[target_feature(enable = "avx512fp16,avx512vl")]
11976#[cfg_attr(test, assert_instr(vcvtuw2ph))]
11977#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
11978pub fn _mm_cvtepu16_ph(a: __m128i) -> __m128h {
11979    unsafe { vcvtuw2ph_128(a.as_u16x8(), _MM_FROUND_CUR_DIRECTION) }
11980}
11981
11982/// Convert packed unsigned 16-bit integers in a to packed half-precision (16-bit) floating-point elements,
11983/// and store the results in dst using writemask k (elements are copied from src to dst when the corresponding
11984/// mask bit is not set).
11985///
11986/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cvtepu16_ph)
11987#[inline]
11988#[target_feature(enable = "avx512fp16,avx512vl")]
11989#[cfg_attr(test, assert_instr(vcvtuw2ph))]
11990#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
11991pub fn _mm_mask_cvtepu16_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h {
11992    unsafe { simd_select_bitmask(k, _mm_cvtepu16_ph(a), src) }
11993}
11994
11995/// Convert packed unsigned 16-bit integers in a to packed half-precision (16-bit) floating-point elements,
11996/// and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
11997///
11998/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_cvtepu16_ph)
11999#[inline]
12000#[target_feature(enable = "avx512fp16,avx512vl")]
12001#[cfg_attr(test, assert_instr(vcvtuw2ph))]
12002#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12003pub fn _mm_maskz_cvtepu16_ph(k: __mmask8, a: __m128i) -> __m128h {
12004    _mm_mask_cvtepu16_ph(_mm_setzero_ph(), k, a)
12005}
12006
12007/// Convert packed unsigned 16-bit integers in a to packed half-precision (16-bit) floating-point elements,
12008/// and store the results in dst.
12009///
12010/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtepu16_ph)
12011#[inline]
12012#[target_feature(enable = "avx512fp16,avx512vl")]
12013#[cfg_attr(test, assert_instr(vcvtuw2ph))]
12014#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12015pub fn _mm256_cvtepu16_ph(a: __m256i) -> __m256h {
12016    unsafe { vcvtuw2ph_256(a.as_u16x16(), _MM_FROUND_CUR_DIRECTION) }
12017}
12018
12019/// Convert packed unsigned 16-bit integers in a to packed half-precision (16-bit) floating-point elements,
12020/// and store the results in dst using writemask k (elements are copied from src to dst when the corresponding
12021/// mask bit is not set).
12022///
12023/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_cvtepu16_ph)
12024#[inline]
12025#[target_feature(enable = "avx512fp16,avx512vl")]
12026#[cfg_attr(test, assert_instr(vcvtuw2ph))]
12027#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12028pub fn _mm256_mask_cvtepu16_ph(src: __m256h, k: __mmask16, a: __m256i) -> __m256h {
12029    unsafe { simd_select_bitmask(k, _mm256_cvtepu16_ph(a), src) }
12030}
12031
12032/// Convert packed unsigned 16-bit integers in a to packed half-precision (16-bit) floating-point elements,
12033/// and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
12034///
12035/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_cvtepu16_ph)
12036#[inline]
12037#[target_feature(enable = "avx512fp16,avx512vl")]
12038#[cfg_attr(test, assert_instr(vcvtuw2ph))]
12039#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12040pub fn _mm256_maskz_cvtepu16_ph(k: __mmask16, a: __m256i) -> __m256h {
12041    _mm256_mask_cvtepu16_ph(_mm256_setzero_ph(), k, a)
12042}
12043
12044/// Convert packed unsigned 16-bit integers in a to packed half-precision (16-bit) floating-point elements,
12045/// and store the results in dst.
12046///
12047/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepu16_ph)
12048#[inline]
12049#[target_feature(enable = "avx512fp16")]
12050#[cfg_attr(test, assert_instr(vcvtuw2ph))]
12051#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12052pub fn _mm512_cvtepu16_ph(a: __m512i) -> __m512h {
12053    unsafe { vcvtuw2ph_512(a.as_u16x32(), _MM_FROUND_CUR_DIRECTION) }
12054}
12055
12056/// Convert packed unsigned 16-bit integers in a to packed half-precision (16-bit) floating-point elements,
12057/// and store the results in dst using writemask k (elements are copied from src to dst when the corresponding
12058/// mask bit is not set).
12059///
12060/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepu16_ph)
12061#[inline]
12062#[target_feature(enable = "avx512fp16")]
12063#[cfg_attr(test, assert_instr(vcvtuw2ph))]
12064#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12065pub fn _mm512_mask_cvtepu16_ph(src: __m512h, k: __mmask32, a: __m512i) -> __m512h {
12066    unsafe { simd_select_bitmask(k, _mm512_cvtepu16_ph(a), src) }
12067}
12068
12069/// Convert packed unsigned 16-bit integers in a to packed half-precision (16-bit) floating-point elements,
12070/// and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
12071///
12072/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepu16_ph)
12073#[inline]
12074#[target_feature(enable = "avx512fp16")]
12075#[cfg_attr(test, assert_instr(vcvtuw2ph))]
12076#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12077pub fn _mm512_maskz_cvtepu16_ph(k: __mmask32, a: __m512i) -> __m512h {
12078    _mm512_mask_cvtepu16_ph(_mm512_setzero_ph(), k, a)
12079}
12080
12081/// Convert packed unsigned 16-bit integers in a to packed half-precision (16-bit) floating-point elements,
12082/// and store the results in dst.
12083///
12084/// Rounding is done according to the rounding parameter, which can be one of:
12085///
12086/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
12087/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
12088/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
12089/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
12090/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
12091///
12092/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvt_roundepu16_ph)
12093#[inline]
12094#[target_feature(enable = "avx512fp16")]
12095#[cfg_attr(test, assert_instr(vcvtuw2ph, ROUNDING = 8))]
12096#[rustc_legacy_const_generics(1)]
12097#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12098pub fn _mm512_cvt_roundepu16_ph<const ROUNDING: i32>(a: __m512i) -> __m512h {
12099    unsafe {
12100        static_assert_rounding!(ROUNDING);
12101        vcvtuw2ph_512(a.as_u16x32(), ROUNDING)
12102    }
12103}
12104
12105/// Convert packed unsigned 16-bit integers in a to packed half-precision (16-bit) floating-point elements,
12106/// and store the results in dst using writemask k (elements are copied from src to dst when the corresponding
12107/// mask bit is not set).
12108///
12109/// Rounding is done according to the rounding parameter, which can be one of:
12110///
12111/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
12112/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
12113/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
12114/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
12115/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
12116///
12117/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvt_roundepu16_ph)
12118#[inline]
12119#[target_feature(enable = "avx512fp16")]
12120#[cfg_attr(test, assert_instr(vcvtuw2ph, ROUNDING = 8))]
12121#[rustc_legacy_const_generics(3)]
12122#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12123pub fn _mm512_mask_cvt_roundepu16_ph<const ROUNDING: i32>(
12124    src: __m512h,
12125    k: __mmask32,
12126    a: __m512i,
12127) -> __m512h {
12128    unsafe {
12129        static_assert_rounding!(ROUNDING);
12130        simd_select_bitmask(k, _mm512_cvt_roundepu16_ph::<ROUNDING>(a), src)
12131    }
12132}
12133
12134/// Convert packed unsigned 16-bit integers in a to packed half-precision (16-bit) floating-point elements,
12135/// and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
12136///
12137/// Rounding is done according to the rounding parameter, which can be one of:
12138///
12139/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
12140/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
12141/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
12142/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
12143/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
12144///
12145/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvt_roundepu16_ph)
12146#[inline]
12147#[target_feature(enable = "avx512fp16")]
12148#[cfg_attr(test, assert_instr(vcvtuw2ph, ROUNDING = 8))]
12149#[rustc_legacy_const_generics(2)]
12150#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12151pub fn _mm512_maskz_cvt_roundepu16_ph<const ROUNDING: i32>(k: __mmask32, a: __m512i) -> __m512h {
12152    static_assert_rounding!(ROUNDING);
12153    _mm512_mask_cvt_roundepu16_ph::<ROUNDING>(_mm512_setzero_ph(), k, a)
12154}
12155
12156/// Convert packed signed 32-bit integers in a to packed half-precision (16-bit) floating-point elements,
12157/// and store the results in dst. The upper 64 bits of dst are zeroed out.
12158///
12159/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtepi32_ph)
12160#[inline]
12161#[target_feature(enable = "avx512fp16,avx512vl")]
12162#[cfg_attr(test, assert_instr(vcvtdq2ph))]
12163#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12164pub fn _mm_cvtepi32_ph(a: __m128i) -> __m128h {
12165    _mm_mask_cvtepi32_ph(_mm_setzero_ph(), 0xff, a)
12166}
12167
12168/// Convert packed signed 32-bit integers in a to packed half-precision (16-bit) floating-point elements,
12169/// and store the results in dst using writemask k (elements are copied from src to dst when the corresponding
12170/// mask bit is not set). The upper 64 bits of dst are zeroed out.
12171///
12172/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cvtepi32_ph)
12173#[inline]
12174#[target_feature(enable = "avx512fp16,avx512vl")]
12175#[cfg_attr(test, assert_instr(vcvtdq2ph))]
12176#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12177pub fn _mm_mask_cvtepi32_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h {
12178    unsafe { vcvtdq2ph_128(a.as_i32x4(), src, k) }
12179}
12180
12181/// Convert packed signed 32-bit integers in a to packed half-precision (16-bit) floating-point elements,
12182/// and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
12183/// The upper 64 bits of dst are zeroed out.
12184///
12185/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_cvtepi32_ph)
12186#[inline]
12187#[target_feature(enable = "avx512fp16,avx512vl")]
12188#[cfg_attr(test, assert_instr(vcvtdq2ph))]
12189#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12190pub fn _mm_maskz_cvtepi32_ph(k: __mmask8, a: __m128i) -> __m128h {
12191    _mm_mask_cvtepi32_ph(_mm_setzero_ph(), k, a)
12192}
12193
12194/// Convert packed signed 32-bit integers in a to packed half-precision (16-bit) floating-point elements,
12195/// and store the results in dst.
12196///
12197/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtepi32_ph)
12198#[inline]
12199#[target_feature(enable = "avx512fp16,avx512vl")]
12200#[cfg_attr(test, assert_instr(vcvtdq2ph))]
12201#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12202pub fn _mm256_cvtepi32_ph(a: __m256i) -> __m128h {
12203    unsafe { vcvtdq2ph_256(a.as_i32x8(), _MM_FROUND_CUR_DIRECTION) }
12204}
12205
12206/// Convert packed signed 32-bit integers in a to packed half-precision (16-bit) floating-point elements,
12207/// and store the results in dst using writemask k (elements are copied from src to dst when the corresponding
12208/// mask bit is not set).
12209///
12210/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_cvtepi32_ph)
12211#[inline]
12212#[target_feature(enable = "avx512fp16,avx512vl")]
12213#[cfg_attr(test, assert_instr(vcvtdq2ph))]
12214#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12215pub fn _mm256_mask_cvtepi32_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h {
12216    unsafe { simd_select_bitmask(k, _mm256_cvtepi32_ph(a), src) }
12217}
12218
12219/// Convert packed signed 32-bit integers in a to packed half-precision (16-bit) floating-point elements,
12220/// and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
12221///
12222/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_cvtepi32_ph)
12223#[inline]
12224#[target_feature(enable = "avx512fp16,avx512vl")]
12225#[cfg_attr(test, assert_instr(vcvtdq2ph))]
12226#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12227pub fn _mm256_maskz_cvtepi32_ph(k: __mmask8, a: __m256i) -> __m128h {
12228    _mm256_mask_cvtepi32_ph(_mm_setzero_ph(), k, a)
12229}
12230
12231/// Convert packed signed 32-bit integers in a to packed half-precision (16-bit) floating-point elements,
12232/// and store the results in dst.
12233///
12234/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepi32_ph)
12235#[inline]
12236#[target_feature(enable = "avx512fp16")]
12237#[cfg_attr(test, assert_instr(vcvtdq2ph))]
12238#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12239pub fn _mm512_cvtepi32_ph(a: __m512i) -> __m256h {
12240    unsafe { vcvtdq2ph_512(a.as_i32x16(), _MM_FROUND_CUR_DIRECTION) }
12241}
12242
12243/// Convert packed signed 32-bit integers in a to packed half-precision (16-bit) floating-point elements,
12244/// and store the results in dst using writemask k (elements are copied from src to dst when the corresponding
12245/// mask bit is not set).
12246///
12247/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepi32_ph)
12248#[inline]
12249#[target_feature(enable = "avx512fp16")]
12250#[cfg_attr(test, assert_instr(vcvtdq2ph))]
12251#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12252pub fn _mm512_mask_cvtepi32_ph(src: __m256h, k: __mmask16, a: __m512i) -> __m256h {
12253    unsafe { simd_select_bitmask(k, _mm512_cvtepi32_ph(a), src) }
12254}
12255
12256/// Convert packed signed 32-bit integers in a to packed half-precision (16-bit) floating-point elements,
12257/// and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
12258///
12259/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepi32_ph)
12260#[inline]
12261#[target_feature(enable = "avx512fp16")]
12262#[cfg_attr(test, assert_instr(vcvtdq2ph))]
12263#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12264pub fn _mm512_maskz_cvtepi32_ph(k: __mmask16, a: __m512i) -> __m256h {
12265    _mm512_mask_cvtepi32_ph(f16x16::ZERO.as_m256h(), k, a)
12266}
12267
12268/// Convert packed signed 32-bit integers in a to packed half-precision (16-bit) floating-point elements,
12269/// and store the results in dst.
12270///
12271/// Rounding is done according to the rounding parameter, which can be one of:
12272///
12273/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
12274/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
12275/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
12276/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
12277/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
12278///
12279/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvt_roundepi32_ph)
12280#[inline]
12281#[target_feature(enable = "avx512fp16")]
12282#[cfg_attr(test, assert_instr(vcvtdq2ph, ROUNDING = 8))]
12283#[rustc_legacy_const_generics(1)]
12284#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12285pub fn _mm512_cvt_roundepi32_ph<const ROUNDING: i32>(a: __m512i) -> __m256h {
12286    unsafe {
12287        static_assert_rounding!(ROUNDING);
12288        vcvtdq2ph_512(a.as_i32x16(), ROUNDING)
12289    }
12290}
12291
12292/// Convert packed signed 32-bit integers in a to packed half-precision (16-bit) floating-point elements,
12293/// and store the results in dst using writemask k (elements are copied from src to dst when the corresponding
12294/// mask bit is not set).
12295///
12296/// Rounding is done according to the rounding parameter, which can be one of:
12297///
12298/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
12299/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
12300/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
12301/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
12302/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
12303///
12304/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvt_roundepi32_ph)
12305#[inline]
12306#[target_feature(enable = "avx512fp16")]
12307#[cfg_attr(test, assert_instr(vcvtdq2ph, ROUNDING = 8))]
12308#[rustc_legacy_const_generics(3)]
12309#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12310pub fn _mm512_mask_cvt_roundepi32_ph<const ROUNDING: i32>(
12311    src: __m256h,
12312    k: __mmask16,
12313    a: __m512i,
12314) -> __m256h {
12315    unsafe {
12316        static_assert_rounding!(ROUNDING);
12317        simd_select_bitmask(k, _mm512_cvt_roundepi32_ph::<ROUNDING>(a), src)
12318    }
12319}
12320
12321/// Convert packed signed 32-bit integers in a to packed half-precision (16-bit) floating-point elements,
12322/// and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
12323///
12324/// Rounding is done according to the rounding parameter, which can be one of:
12325///
12326/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
12327/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
12328/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
12329/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
12330/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
12331///
12332/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvt_roundepi32_ph)
12333#[inline]
12334#[target_feature(enable = "avx512fp16")]
12335#[cfg_attr(test, assert_instr(vcvtdq2ph, ROUNDING = 8))]
12336#[rustc_legacy_const_generics(2)]
12337#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12338pub fn _mm512_maskz_cvt_roundepi32_ph<const ROUNDING: i32>(k: __mmask16, a: __m512i) -> __m256h {
12339    static_assert_rounding!(ROUNDING);
12340    _mm512_mask_cvt_roundepi32_ph::<ROUNDING>(f16x16::ZERO.as_m256h(), k, a)
12341}
12342
12343/// Convert the signed 32-bit integer b to a half-precision (16-bit) floating-point element, store the
12344/// result in the lower element of dst, and copy the upper 7 packed elements from a to the upper elements
12345/// of dst.
12346///
12347/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvti32_sh)
12348#[inline]
12349#[target_feature(enable = "avx512fp16")]
12350#[cfg_attr(test, assert_instr(vcvtsi2sh))]
12351#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12352pub fn _mm_cvti32_sh(a: __m128h, b: i32) -> __m128h {
12353    unsafe { vcvtsi2sh(a, b, _MM_FROUND_CUR_DIRECTION) }
12354}
12355
12356/// Convert the signed 32-bit integer b to a half-precision (16-bit) floating-point element, store the
12357/// result in the lower element of dst, and copy the upper 7 packed elements from a to the upper elements
12358/// of dst.
12359///
12360/// Rounding is done according to the rounding parameter, which can be one of:
12361///
12362/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
12363/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
12364/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
12365/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
12366/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
12367///
12368/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvt_roundi32_sh)
12369#[inline]
12370#[target_feature(enable = "avx512fp16")]
12371#[cfg_attr(test, assert_instr(vcvtsi2sh, ROUNDING = 8))]
12372#[rustc_legacy_const_generics(2)]
12373#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12374pub fn _mm_cvt_roundi32_sh<const ROUNDING: i32>(a: __m128h, b: i32) -> __m128h {
12375    unsafe {
12376        static_assert_rounding!(ROUNDING);
12377        vcvtsi2sh(a, b, ROUNDING)
12378    }
12379}
12380
12381/// Convert packed unsigned 32-bit integers in a to packed half-precision (16-bit) floating-point elements,
12382/// and store the results in dst. The upper 64 bits of dst are zeroed out.
12383///
12384/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtepu32_ph)
12385#[inline]
12386#[target_feature(enable = "avx512fp16,avx512vl")]
12387#[cfg_attr(test, assert_instr(vcvtudq2ph))]
12388#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12389pub fn _mm_cvtepu32_ph(a: __m128i) -> __m128h {
12390    _mm_mask_cvtepu32_ph(_mm_setzero_ph(), 0xff, a)
12391}
12392
12393/// Convert packed unsigned 32-bit integers in a to packed half-precision (16-bit) floating-point elements,
12394/// and store the results in dst using writemask k (elements are copied from src to dst when the corresponding
12395/// mask bit is not set). The upper 64 bits of dst are zeroed out.
12396///
12397/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cvtepu32_ph)
12398#[inline]
12399#[target_feature(enable = "avx512fp16,avx512vl")]
12400#[cfg_attr(test, assert_instr(vcvtudq2ph))]
12401#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12402pub fn _mm_mask_cvtepu32_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h {
12403    unsafe { vcvtudq2ph_128(a.as_u32x4(), src, k) }
12404}
12405
12406/// Convert packed unsigned 32-bit integers in a to packed half-precision (16-bit) floating-point elements,
12407/// and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
12408/// The upper 64 bits of dst are zeroed out.
12409///
12410/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_cvtepu32_ph)
12411#[inline]
12412#[target_feature(enable = "avx512fp16,avx512vl")]
12413#[cfg_attr(test, assert_instr(vcvtudq2ph))]
12414#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12415pub fn _mm_maskz_cvtepu32_ph(k: __mmask8, a: __m128i) -> __m128h {
12416    _mm_mask_cvtepu32_ph(_mm_setzero_ph(), k, a)
12417}
12418
12419/// Convert packed unsigned 32-bit integers in a to packed half-precision (16-bit) floating-point elements,
12420/// and store the results in dst.
12421///
12422/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtepu32_ph)
12423#[inline]
12424#[target_feature(enable = "avx512fp16,avx512vl")]
12425#[cfg_attr(test, assert_instr(vcvtudq2ph))]
12426#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12427pub fn _mm256_cvtepu32_ph(a: __m256i) -> __m128h {
12428    unsafe { vcvtudq2ph_256(a.as_u32x8(), _MM_FROUND_CUR_DIRECTION) }
12429}
12430
12431/// Convert packed unsigned 32-bit integers in a to packed half-precision (16-bit) floating-point elements,
12432/// and store the results in dst using writemask k (elements are copied from src to dst when the corresponding
12433/// mask bit is not set).
12434///
12435/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_cvtepu32_ph)
12436#[inline]
12437#[target_feature(enable = "avx512fp16,avx512vl")]
12438#[cfg_attr(test, assert_instr(vcvtudq2ph))]
12439#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12440pub fn _mm256_mask_cvtepu32_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h {
12441    unsafe { simd_select_bitmask(k, _mm256_cvtepu32_ph(a), src) }
12442}
12443
12444/// Convert packed unsigned 32-bit integers in a to packed half-precision (16-bit) floating-point elements,
12445/// and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
12446///
12447/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_cvtepu32_ph)
12448#[inline]
12449#[target_feature(enable = "avx512fp16,avx512vl")]
12450#[cfg_attr(test, assert_instr(vcvtudq2ph))]
12451#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12452pub fn _mm256_maskz_cvtepu32_ph(k: __mmask8, a: __m256i) -> __m128h {
12453    _mm256_mask_cvtepu32_ph(_mm_setzero_ph(), k, a)
12454}
12455
12456/// Convert packed unsigned 32-bit integers in a to packed half-precision (16-bit) floating-point elements,
12457/// and store the results in dst.
12458///
12459/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepu32_ph)
12460#[inline]
12461#[target_feature(enable = "avx512fp16")]
12462#[cfg_attr(test, assert_instr(vcvtudq2ph))]
12463#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12464pub fn _mm512_cvtepu32_ph(a: __m512i) -> __m256h {
12465    unsafe { vcvtudq2ph_512(a.as_u32x16(), _MM_FROUND_CUR_DIRECTION) }
12466}
12467
12468/// Convert packed unsigned 32-bit integers in a to packed half-precision (16-bit) floating-point elements,
12469/// and store the results in dst using writemask k (elements are copied from src to dst when the corresponding
12470/// mask bit is not set).
12471///
12472/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepu32_ph)
12473#[inline]
12474#[target_feature(enable = "avx512fp16")]
12475#[cfg_attr(test, assert_instr(vcvtudq2ph))]
12476#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12477pub fn _mm512_mask_cvtepu32_ph(src: __m256h, k: __mmask16, a: __m512i) -> __m256h {
12478    unsafe { simd_select_bitmask(k, _mm512_cvtepu32_ph(a), src) }
12479}
12480
12481/// Convert packed unsigned 32-bit integers in a to packed half-precision (16-bit) floating-point elements,
12482/// and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
12483///
12484/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepu32_ph)
12485#[inline]
12486#[target_feature(enable = "avx512fp16")]
12487#[cfg_attr(test, assert_instr(vcvtudq2ph))]
12488#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12489pub fn _mm512_maskz_cvtepu32_ph(k: __mmask16, a: __m512i) -> __m256h {
12490    _mm512_mask_cvtepu32_ph(f16x16::ZERO.as_m256h(), k, a)
12491}
12492
12493/// Convert packed unsigned 32-bit integers in a to packed half-precision (16-bit) floating-point elements,
12494/// and store the results in dst.
12495///
12496/// Rounding is done according to the rounding parameter, which can be one of:
12497///
12498/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
12499/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
12500/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
12501/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
12502/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
12503///
12504/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvt_roundepu32_ph)
12505#[inline]
12506#[target_feature(enable = "avx512fp16")]
12507#[cfg_attr(test, assert_instr(vcvtudq2ph, ROUNDING = 8))]
12508#[rustc_legacy_const_generics(1)]
12509#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12510pub fn _mm512_cvt_roundepu32_ph<const ROUNDING: i32>(a: __m512i) -> __m256h {
12511    unsafe {
12512        static_assert_rounding!(ROUNDING);
12513        vcvtudq2ph_512(a.as_u32x16(), ROUNDING)
12514    }
12515}
12516
12517/// Convert packed unsigned 32-bit integers in a to packed half-precision (16-bit) floating-point elements,
12518/// and store the results in dst using writemask k (elements are copied from src to dst when the corresponding
12519/// mask bit is not set).
12520///
12521/// Rounding is done according to the rounding parameter, which can be one of:
12522///
12523/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
12524/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
12525/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
12526/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
12527/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
12528///
12529/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvt_roundepu32_ph)
12530#[inline]
12531#[target_feature(enable = "avx512fp16")]
12532#[cfg_attr(test, assert_instr(vcvtudq2ph, ROUNDING = 8))]
12533#[rustc_legacy_const_generics(3)]
12534#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12535pub fn _mm512_mask_cvt_roundepu32_ph<const ROUNDING: i32>(
12536    src: __m256h,
12537    k: __mmask16,
12538    a: __m512i,
12539) -> __m256h {
12540    unsafe {
12541        static_assert_rounding!(ROUNDING);
12542        simd_select_bitmask(k, _mm512_cvt_roundepu32_ph::<ROUNDING>(a), src)
12543    }
12544}
12545
12546/// Convert packed unsigned 32-bit integers in a to packed half-precision (16-bit) floating-point elements,
12547/// and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
12548///
12549/// Rounding is done according to the rounding parameter, which can be one of:
12550///
12551/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
12552/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
12553/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
12554/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
12555/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
12556///
12557/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvt_roundepu32_ph)
12558#[inline]
12559#[target_feature(enable = "avx512fp16")]
12560#[cfg_attr(test, assert_instr(vcvtudq2ph, ROUNDING = 8))]
12561#[rustc_legacy_const_generics(2)]
12562#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12563pub fn _mm512_maskz_cvt_roundepu32_ph<const ROUNDING: i32>(k: __mmask16, a: __m512i) -> __m256h {
12564    static_assert_rounding!(ROUNDING);
12565    _mm512_mask_cvt_roundepu32_ph::<ROUNDING>(f16x16::ZERO.as_m256h(), k, a)
12566}
12567
12568/// Convert the unsigned 32-bit integer b to a half-precision (16-bit) floating-point element, store the
12569/// result in the lower element of dst, and copy the upper 7 packed elements from a to the upper elements
12570/// of dst.
12571///
12572/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtu32_sh)
12573#[inline]
12574#[target_feature(enable = "avx512fp16")]
12575#[cfg_attr(test, assert_instr(vcvtusi2sh))]
12576#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12577pub fn _mm_cvtu32_sh(a: __m128h, b: u32) -> __m128h {
12578    unsafe { vcvtusi2sh(a, b, _MM_FROUND_CUR_DIRECTION) }
12579}
12580
12581/// Convert the unsigned 32-bit integer b to a half-precision (16-bit) floating-point element, store the
12582/// result in the lower element of dst, and copy the upper 7 packed elements from a to the upper elements
12583/// of dst.
12584///
12585/// Rounding is done according to the rounding parameter, which can be one of:
12586///
12587/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
12588/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
12589/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
12590/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
12591/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
12592///
12593/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvt_roundu32_sh)
12594#[inline]
12595#[target_feature(enable = "avx512fp16")]
12596#[cfg_attr(test, assert_instr(vcvtusi2sh, ROUNDING = 8))]
12597#[rustc_legacy_const_generics(2)]
12598#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12599pub fn _mm_cvt_roundu32_sh<const ROUNDING: i32>(a: __m128h, b: u32) -> __m128h {
12600    unsafe {
12601        static_assert_rounding!(ROUNDING);
12602        vcvtusi2sh(a, b, ROUNDING)
12603    }
12604}
12605
12606/// Convert packed signed 64-bit integers in a to packed half-precision (16-bit) floating-point elements,
12607/// and store the results in dst. The upper 96 bits of dst are zeroed out.
12608///
12609/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtepi64_ph)
12610#[inline]
12611#[target_feature(enable = "avx512fp16,avx512vl")]
12612#[cfg_attr(test, assert_instr(vcvtqq2ph))]
12613#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12614pub fn _mm_cvtepi64_ph(a: __m128i) -> __m128h {
12615    _mm_mask_cvtepi64_ph(_mm_setzero_ph(), 0xff, a)
12616}
12617
12618/// Convert packed signed 64-bit integers in a to packed half-precision (16-bit) floating-point elements,
12619/// and store the results in dst using writemask k (elements are copied from src to dst when the corresponding
12620/// mask bit is not set). The upper 96 bits of dst are zeroed out.
12621///
12622/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cvtepi64_ph)
12623#[inline]
12624#[target_feature(enable = "avx512fp16,avx512vl")]
12625#[cfg_attr(test, assert_instr(vcvtqq2ph))]
12626#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12627pub fn _mm_mask_cvtepi64_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h {
12628    unsafe { vcvtqq2ph_128(a.as_i64x2(), src, k) }
12629}
12630
12631/// Convert packed signed 64-bit integers in a to packed half-precision (16-bit) floating-point elements,
12632/// and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
12633/// The upper 96 bits of dst are zeroed out.
12634///
12635/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_cvtepi64_ph)
12636#[inline]
12637#[target_feature(enable = "avx512fp16,avx512vl")]
12638#[cfg_attr(test, assert_instr(vcvtqq2ph))]
12639#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12640pub fn _mm_maskz_cvtepi64_ph(k: __mmask8, a: __m128i) -> __m128h {
12641    _mm_mask_cvtepi64_ph(_mm_setzero_ph(), k, a)
12642}
12643
12644/// Convert packed signed 64-bit integers in a to packed half-precision (16-bit) floating-point elements,
12645/// and store the results in dst. The upper 64 bits of dst are zeroed out.
12646///
12647/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtepi64_ph)
12648#[inline]
12649#[target_feature(enable = "avx512fp16,avx512vl")]
12650#[cfg_attr(test, assert_instr(vcvtqq2ph))]
12651#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12652pub fn _mm256_cvtepi64_ph(a: __m256i) -> __m128h {
12653    _mm256_mask_cvtepi64_ph(_mm_setzero_ph(), 0xff, a)
12654}
12655
12656/// Convert packed signed 64-bit integers in a to packed half-precision (16-bit) floating-point elements,
12657/// and store the results in dst using writemask k (elements are copied from src to dst when the corresponding
12658/// mask bit is not set). The upper 64 bits of dst are zeroed out.
12659///
12660/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_cvtepi64_ph)
12661#[inline]
12662#[target_feature(enable = "avx512fp16,avx512vl")]
12663#[cfg_attr(test, assert_instr(vcvtqq2ph))]
12664#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12665pub fn _mm256_mask_cvtepi64_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h {
12666    unsafe { vcvtqq2ph_256(a.as_i64x4(), src, k) }
12667}
12668
12669/// Convert packed signed 64-bit integers in a to packed half-precision (16-bit) floating-point elements,
12670/// and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
12671/// The upper 64 bits of dst are zeroed out.
12672///
12673/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_cvtepi64_ph)
12674#[inline]
12675#[target_feature(enable = "avx512fp16,avx512vl")]
12676#[cfg_attr(test, assert_instr(vcvtqq2ph))]
12677#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12678pub fn _mm256_maskz_cvtepi64_ph(k: __mmask8, a: __m256i) -> __m128h {
12679    _mm256_mask_cvtepi64_ph(_mm_setzero_ph(), k, a)
12680}
12681
12682/// Convert packed signed 64-bit integers in a to packed half-precision (16-bit) floating-point elements,
12683/// and store the results in dst.
12684///
12685/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepi64_ph)
12686#[inline]
12687#[target_feature(enable = "avx512fp16")]
12688#[cfg_attr(test, assert_instr(vcvtqq2ph))]
12689#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12690pub fn _mm512_cvtepi64_ph(a: __m512i) -> __m128h {
12691    unsafe { vcvtqq2ph_512(a.as_i64x8(), _MM_FROUND_CUR_DIRECTION) }
12692}
12693
12694/// Convert packed signed 64-bit integers in a to packed half-precision (16-bit) floating-point elements,
12695/// and store the results in dst using writemask k (elements are copied from src to dst when the corresponding
12696/// mask bit is not set).
12697///
12698/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepi64_ph)
12699#[inline]
12700#[target_feature(enable = "avx512fp16")]
12701#[cfg_attr(test, assert_instr(vcvtqq2ph))]
12702#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12703pub fn _mm512_mask_cvtepi64_ph(src: __m128h, k: __mmask8, a: __m512i) -> __m128h {
12704    unsafe { simd_select_bitmask(k, _mm512_cvtepi64_ph(a), src) }
12705}
12706
12707/// Convert packed signed 64-bit integers in a to packed half-precision (16-bit) floating-point elements,
12708/// and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
12709///
12710/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepi64_ph)
12711#[inline]
12712#[target_feature(enable = "avx512fp16")]
12713#[cfg_attr(test, assert_instr(vcvtqq2ph))]
12714#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12715pub fn _mm512_maskz_cvtepi64_ph(k: __mmask8, a: __m512i) -> __m128h {
12716    _mm512_mask_cvtepi64_ph(f16x8::ZERO.as_m128h(), k, a)
12717}
12718
12719/// Convert packed signed 64-bit integers in a to packed half-precision (16-bit) floating-point elements,
12720/// and store the results in dst.
12721///
12722/// Rounding is done according to the rounding parameter, which can be one of:
12723///
12724/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
12725/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
12726/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
12727/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
12728/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
12729///
12730/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvt_roundepi64_ph)
12731#[inline]
12732#[target_feature(enable = "avx512fp16")]
12733#[cfg_attr(test, assert_instr(vcvtqq2ph, ROUNDING = 8))]
12734#[rustc_legacy_const_generics(1)]
12735#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12736pub fn _mm512_cvt_roundepi64_ph<const ROUNDING: i32>(a: __m512i) -> __m128h {
12737    unsafe {
12738        static_assert_rounding!(ROUNDING);
12739        vcvtqq2ph_512(a.as_i64x8(), ROUNDING)
12740    }
12741}
12742
12743/// Convert packed signed 64-bit integers in a to packed half-precision (16-bit) floating-point elements,
12744/// and store the results in dst using writemask k (elements are copied from src to dst when the corresponding
12745/// mask bit is not set).
12746///
12747/// Rounding is done according to the rounding parameter, which can be one of:
12748///
12749/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
12750/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
12751/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
12752/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
12753/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
12754///
12755/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvt_roundepi64_ph)
12756#[inline]
12757#[target_feature(enable = "avx512fp16")]
12758#[cfg_attr(test, assert_instr(vcvtqq2ph, ROUNDING = 8))]
12759#[rustc_legacy_const_generics(3)]
12760#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12761pub fn _mm512_mask_cvt_roundepi64_ph<const ROUNDING: i32>(
12762    src: __m128h,
12763    k: __mmask8,
12764    a: __m512i,
12765) -> __m128h {
12766    unsafe {
12767        static_assert_rounding!(ROUNDING);
12768        simd_select_bitmask(k, _mm512_cvt_roundepi64_ph::<ROUNDING>(a), src)
12769    }
12770}
12771
12772/// Convert packed signed 64-bit integers in a to packed half-precision (16-bit) floating-point elements,
12773/// and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
12774///
12775/// Rounding is done according to the rounding parameter, which can be one of:
12776///
12777/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
12778/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
12779/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
12780/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
12781/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
12782///
12783/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvt_roundepi64_ph)
12784#[inline]
12785#[target_feature(enable = "avx512fp16")]
12786#[cfg_attr(test, assert_instr(vcvtqq2ph, ROUNDING = 8))]
12787#[rustc_legacy_const_generics(2)]
12788#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12789pub fn _mm512_maskz_cvt_roundepi64_ph<const ROUNDING: i32>(k: __mmask8, a: __m512i) -> __m128h {
12790    static_assert_rounding!(ROUNDING);
12791    _mm512_mask_cvt_roundepi64_ph::<ROUNDING>(f16x8::ZERO.as_m128h(), k, a)
12792}
12793
12794/// Convert packed unsigned 64-bit integers in a to packed half-precision (16-bit) floating-point elements,
12795/// and store the results in dst. The upper 96 bits of dst are zeroed out.
12796///
12797/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtepu64_ph)
12798#[inline]
12799#[target_feature(enable = "avx512fp16,avx512vl")]
12800#[cfg_attr(test, assert_instr(vcvtuqq2ph))]
12801#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12802pub fn _mm_cvtepu64_ph(a: __m128i) -> __m128h {
12803    _mm_mask_cvtepu64_ph(_mm_setzero_ph(), 0xff, a)
12804}
12805
12806/// Convert packed unsigned 64-bit integers in a to packed half-precision (16-bit) floating-point elements,
12807/// and store the results in dst using writemask k (elements are copied from src to dst when the corresponding
12808/// mask bit is not set). The upper 96 bits of dst are zeroed out.
12809///
12810/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cvtepu64_ph)
12811#[inline]
12812#[target_feature(enable = "avx512fp16,avx512vl")]
12813#[cfg_attr(test, assert_instr(vcvtuqq2ph))]
12814#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12815pub fn _mm_mask_cvtepu64_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h {
12816    unsafe { vcvtuqq2ph_128(a.as_u64x2(), src, k) }
12817}
12818
12819/// Convert packed unsigned 64-bit integers in a to packed half-precision (16-bit) floating-point elements,
12820/// and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
12821/// The upper 96 bits of dst are zeroed out.
12822///
12823/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_cvtepu64_ph)
12824#[inline]
12825#[target_feature(enable = "avx512fp16,avx512vl")]
12826#[cfg_attr(test, assert_instr(vcvtuqq2ph))]
12827#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12828pub fn _mm_maskz_cvtepu64_ph(k: __mmask8, a: __m128i) -> __m128h {
12829    _mm_mask_cvtepu64_ph(_mm_setzero_ph(), k, a)
12830}
12831
12832/// Convert packed unsigned 64-bit integers in a to packed half-precision (16-bit) floating-point elements,
12833/// and store the results in dst. The upper 64 bits of dst are zeroed out.
12834///
12835/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtepu64_ph)
12836#[inline]
12837#[target_feature(enable = "avx512fp16,avx512vl")]
12838#[cfg_attr(test, assert_instr(vcvtuqq2ph))]
12839#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12840pub fn _mm256_cvtepu64_ph(a: __m256i) -> __m128h {
12841    _mm256_mask_cvtepu64_ph(_mm_setzero_ph(), 0xff, a)
12842}
12843
12844/// Convert packed unsigned 64-bit integers in a to packed half-precision (16-bit) floating-point elements,
12845/// and store the results in dst using writemask k (elements are copied from src to dst when the corresponding
12846/// mask bit is not set). The upper 64 bits of dst are zeroed out.
12847///
12848/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_cvtepu64_ph)
12849#[inline]
12850#[target_feature(enable = "avx512fp16,avx512vl")]
12851#[cfg_attr(test, assert_instr(vcvtuqq2ph))]
12852#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12853pub fn _mm256_mask_cvtepu64_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h {
12854    unsafe { vcvtuqq2ph_256(a.as_u64x4(), src, k) }
12855}
12856
12857/// Convert packed unsigned 64-bit integers in a to packed half-precision (16-bit) floating-point elements,
12858/// and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
12859/// The upper 64 bits of dst are zeroed out.
12860///
12861/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_cvtepu64_ph)
12862#[inline]
12863#[target_feature(enable = "avx512fp16,avx512vl")]
12864#[cfg_attr(test, assert_instr(vcvtuqq2ph))]
12865#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12866pub fn _mm256_maskz_cvtepu64_ph(k: __mmask8, a: __m256i) -> __m128h {
12867    _mm256_mask_cvtepu64_ph(_mm_setzero_ph(), k, a)
12868}
12869
12870/// Convert packed unsigned 64-bit integers in a to packed half-precision (16-bit) floating-point elements,
12871/// and store the results in dst.
12872///
12873/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepu64_ph)
12874#[inline]
12875#[target_feature(enable = "avx512fp16")]
12876#[cfg_attr(test, assert_instr(vcvtuqq2ph))]
12877#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12878pub fn _mm512_cvtepu64_ph(a: __m512i) -> __m128h {
12879    unsafe { vcvtuqq2ph_512(a.as_u64x8(), _MM_FROUND_CUR_DIRECTION) }
12880}
12881
12882/// Convert packed unsigned 64-bit integers in a to packed half-precision (16-bit) floating-point elements,
12883/// and store the results in dst using writemask k (elements are copied from src to dst when the corresponding
12884/// mask bit is not set).
12885///
12886/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepu64_ph)
12887#[inline]
12888#[target_feature(enable = "avx512fp16")]
12889#[cfg_attr(test, assert_instr(vcvtuqq2ph))]
12890#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12891pub fn _mm512_mask_cvtepu64_ph(src: __m128h, k: __mmask8, a: __m512i) -> __m128h {
12892    unsafe { simd_select_bitmask(k, _mm512_cvtepu64_ph(a), src) }
12893}
12894
12895/// Convert packed unsigned 64-bit integers in a to packed half-precision (16-bit) floating-point elements,
12896/// and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
12897///
12898/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepu64_ph)
12899#[inline]
12900#[target_feature(enable = "avx512fp16")]
12901#[cfg_attr(test, assert_instr(vcvtuqq2ph))]
12902#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12903pub fn _mm512_maskz_cvtepu64_ph(k: __mmask8, a: __m512i) -> __m128h {
12904    _mm512_mask_cvtepu64_ph(f16x8::ZERO.as_m128h(), k, a)
12905}
12906
12907/// Convert packed unsigned 64-bit integers in a to packed half-precision (16-bit) floating-point elements,
12908/// and store the results in dst.
12909///
12910/// Rounding is done according to the rounding parameter, which can be one of:
12911///
12912/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
12913/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
12914/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
12915/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
12916/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
12917///
12918/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvt_roundepu64_ph)
12919#[inline]
12920#[target_feature(enable = "avx512fp16")]
12921#[cfg_attr(test, assert_instr(vcvtuqq2ph, ROUNDING = 8))]
12922#[rustc_legacy_const_generics(1)]
12923#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12924pub fn _mm512_cvt_roundepu64_ph<const ROUNDING: i32>(a: __m512i) -> __m128h {
12925    unsafe {
12926        static_assert_rounding!(ROUNDING);
12927        vcvtuqq2ph_512(a.as_u64x8(), ROUNDING)
12928    }
12929}
12930
12931/// Convert packed unsigned 64-bit integers in a to packed half-precision (16-bit) floating-point elements,
12932/// and store the results in dst using writemask k (elements are copied from src to dst when the corresponding
12933/// mask bit is not set).
12934///
12935/// Rounding is done according to the rounding parameter, which can be one of:
12936///
12937/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
12938/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
12939/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
12940/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
12941/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
12942///
12943/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvt_roundepu64_ph)
12944#[inline]
12945#[target_feature(enable = "avx512fp16")]
12946#[cfg_attr(test, assert_instr(vcvtuqq2ph, ROUNDING = 8))]
12947#[rustc_legacy_const_generics(3)]
12948#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12949pub fn _mm512_mask_cvt_roundepu64_ph<const ROUNDING: i32>(
12950    src: __m128h,
12951    k: __mmask8,
12952    a: __m512i,
12953) -> __m128h {
12954    unsafe {
12955        static_assert_rounding!(ROUNDING);
12956        simd_select_bitmask(k, _mm512_cvt_roundepu64_ph::<ROUNDING>(a), src)
12957    }
12958}
12959
12960/// Convert packed unsigned 64-bit integers in a to packed half-precision (16-bit) floating-point elements,
12961/// and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
12962///
12963/// Rounding is done according to the rounding parameter, which can be one of:
12964///
12965/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
12966/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
12967/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
12968/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
12969/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
12970///
12971/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvt_roundepu64_ph)
12972#[inline]
12973#[target_feature(enable = "avx512fp16")]
12974#[cfg_attr(test, assert_instr(vcvtuqq2ph, ROUNDING = 8))]
12975#[rustc_legacy_const_generics(2)]
12976#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12977pub fn _mm512_maskz_cvt_roundepu64_ph<const ROUNDING: i32>(k: __mmask8, a: __m512i) -> __m128h {
12978    static_assert_rounding!(ROUNDING);
12979    _mm512_mask_cvt_roundepu64_ph::<ROUNDING>(f16x8::ZERO.as_m128h(), k, a)
12980}
12981
12982/// Convert packed single-precision (32-bit) floating-point elements in a to packed half-precision (16-bit)
12983/// floating-point elements, and store the results in dst.
12984///
12985/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtxps_ph)
12986#[inline]
12987#[target_feature(enable = "avx512fp16,avx512vl")]
12988#[cfg_attr(test, assert_instr(vcvtps2phx))]
12989#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
12990pub fn _mm_cvtxps_ph(a: __m128) -> __m128h {
12991    _mm_mask_cvtxps_ph(_mm_setzero_ph(), 0xff, a)
12992}
12993
12994/// Convert packed single-precision (32-bit) floating-point elements in a to packed half-precision (16-bit)
12995/// floating-point elements, and store the results in dst using writemask k (elements are copied from src to dst
12996/// when the corresponding mask bit is not set). The upper 64 bits of dst are zeroed out.
12997///
12998/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cvtxps_ph)
12999#[inline]
13000#[target_feature(enable = "avx512fp16,avx512vl")]
13001#[cfg_attr(test, assert_instr(vcvtps2phx))]
13002#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13003pub fn _mm_mask_cvtxps_ph(src: __m128h, k: __mmask8, a: __m128) -> __m128h {
13004    unsafe { vcvtps2phx_128(a, src, k) }
13005}
13006
13007/// Convert packed single-precision (32-bit) floating-point elements in a to packed half-precision (16-bit)
13008/// floating-point elements, and store the results in dst using zeromask k (elements are zeroed out when the
13009/// corresponding mask bit is not set). The upper 64 bits of dst are zeroed out.
13010///
13011/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_cvtxps_ph)
13012#[inline]
13013#[target_feature(enable = "avx512fp16,avx512vl")]
13014#[cfg_attr(test, assert_instr(vcvtps2phx))]
13015#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13016pub fn _mm_maskz_cvtxps_ph(k: __mmask8, a: __m128) -> __m128h {
13017    _mm_mask_cvtxps_ph(_mm_setzero_ph(), k, a)
13018}
13019
13020/// Convert packed single-precision (32-bit) floating-point elements in a to packed half-precision (16-bit)
13021/// floating-point elements, and store the results in dst.
13022///
13023/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtxps_ph)
13024#[inline]
13025#[target_feature(enable = "avx512fp16,avx512vl")]
13026#[cfg_attr(test, assert_instr(vcvtps2phx))]
13027#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13028pub fn _mm256_cvtxps_ph(a: __m256) -> __m128h {
13029    _mm256_mask_cvtxps_ph(_mm_setzero_ph(), 0xff, a)
13030}
13031
13032/// Convert packed single-precision (32-bit) floating-point elements in a to packed half-precision (16-bit)
13033/// floating-point elements, and store the results in dst using writemask k (elements are copied from src to dst
13034/// when the corresponding mask bit is not set).
13035///
13036/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_cvtxps_ph)
13037#[inline]
13038#[target_feature(enable = "avx512fp16,avx512vl")]
13039#[cfg_attr(test, assert_instr(vcvtps2phx))]
13040#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13041pub fn _mm256_mask_cvtxps_ph(src: __m128h, k: __mmask8, a: __m256) -> __m128h {
13042    unsafe { vcvtps2phx_256(a, src, k) }
13043}
13044
13045/// Convert packed single-precision (32-bit) floating-point elements in a to packed half-precision (16-bit)
13046/// floating-point elements, and store the results in dst using zeromask k (elements are zeroed out when the
13047/// corresponding mask bit is not set).
13048///
13049/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_cvtxps_ph)
13050#[inline]
13051#[target_feature(enable = "avx512fp16,avx512vl")]
13052#[cfg_attr(test, assert_instr(vcvtps2phx))]
13053#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13054pub fn _mm256_maskz_cvtxps_ph(k: __mmask8, a: __m256) -> __m128h {
13055    _mm256_mask_cvtxps_ph(_mm_setzero_ph(), k, a)
13056}
13057
13058/// Convert packed single-precision (32-bit) floating-point elements in a to packed half-precision (16-bit)
13059/// floating-point elements, and store the results in dst.
13060///
13061/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtxps_ph)
13062#[inline]
13063#[target_feature(enable = "avx512fp16")]
13064#[cfg_attr(test, assert_instr(vcvtps2phx))]
13065#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13066pub fn _mm512_cvtxps_ph(a: __m512) -> __m256h {
13067    _mm512_mask_cvtxps_ph(f16x16::ZERO.as_m256h(), 0xffff, a)
13068}
13069
13070/// Convert packed single-precision (32-bit) floating-point elements in a to packed half-precision (16-bit)
13071/// floating-point elements, and store the results in dst using writemask k (elements are copied from src to dst
13072/// when the corresponding mask bit is not set).
13073///
13074/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtxps_ph)
13075#[inline]
13076#[target_feature(enable = "avx512fp16")]
13077#[cfg_attr(test, assert_instr(vcvtps2phx))]
13078#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13079pub fn _mm512_mask_cvtxps_ph(src: __m256h, k: __mmask16, a: __m512) -> __m256h {
13080    unsafe { vcvtps2phx_512(a, src, k, _MM_FROUND_CUR_DIRECTION) }
13081}
13082
13083/// Convert packed single-precision (32-bit) floating-point elements in a to packed half-precision (16-bit)
13084/// floating-point elements, and store the results in dst using zeromask k (elements are zeroed out when the
13085/// corresponding mask bit is not set).
13086///
13087/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtxps_ph)
13088#[inline]
13089#[target_feature(enable = "avx512fp16")]
13090#[cfg_attr(test, assert_instr(vcvtps2phx))]
13091#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13092pub fn _mm512_maskz_cvtxps_ph(k: __mmask16, a: __m512) -> __m256h {
13093    _mm512_mask_cvtxps_ph(f16x16::ZERO.as_m256h(), k, a)
13094}
13095
13096/// Convert packed single-precision (32-bit) floating-point elements in a to packed half-precision (16-bit)
13097/// floating-point elements, and store the results in dst.
13098///
13099/// Rounding is done according to the rounding parameter, which can be one of:
13100///
13101/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
13102/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
13103/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
13104/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
13105/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
13106///
13107/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtx_roundps_ph)
13108#[inline]
13109#[target_feature(enable = "avx512fp16")]
13110#[cfg_attr(test, assert_instr(vcvtps2phx, ROUNDING = 8))]
13111#[rustc_legacy_const_generics(1)]
13112#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13113pub fn _mm512_cvtx_roundps_ph<const ROUNDING: i32>(a: __m512) -> __m256h {
13114    static_assert_rounding!(ROUNDING);
13115    _mm512_mask_cvtx_roundps_ph::<ROUNDING>(f16x16::ZERO.as_m256h(), 0xffff, a)
13116}
13117
13118/// Convert packed single-precision (32-bit) floating-point elements in a to packed half-precision (16-bit)
13119/// floating-point elements, and store the results in dst using writemask k (elements are copied from src to dst
13120/// when the corresponding mask bit is not set).
13121///
13122/// Rounding is done according to the rounding parameter, which can be one of:
13123///
13124/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
13125/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
13126/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
13127/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
13128/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
13129///
13130/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtx_roundps_ph)
13131#[inline]
13132#[target_feature(enable = "avx512fp16")]
13133#[cfg_attr(test, assert_instr(vcvtps2phx, ROUNDING = 8))]
13134#[rustc_legacy_const_generics(3)]
13135#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13136pub fn _mm512_mask_cvtx_roundps_ph<const ROUNDING: i32>(
13137    src: __m256h,
13138    k: __mmask16,
13139    a: __m512,
13140) -> __m256h {
13141    unsafe {
13142        static_assert_rounding!(ROUNDING);
13143        vcvtps2phx_512(a, src, k, ROUNDING)
13144    }
13145}
13146
13147/// Convert packed single-precision (32-bit) floating-point elements in a to packed half-precision (16-bit)
13148/// floating-point elements, and store the results in dst using zeromask k (elements are zeroed out when the
13149/// corresponding mask bit is not set).
13150///
13151/// Rounding is done according to the rounding parameter, which can be one of:
13152///
13153/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
13154/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
13155/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
13156/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
13157/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
13158///
13159/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtx_roundps_ph)
13160#[inline]
13161#[target_feature(enable = "avx512fp16")]
13162#[cfg_attr(test, assert_instr(vcvtps2phx, ROUNDING = 8))]
13163#[rustc_legacy_const_generics(2)]
13164#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13165pub fn _mm512_maskz_cvtx_roundps_ph<const ROUNDING: i32>(k: __mmask16, a: __m512) -> __m256h {
13166    static_assert_rounding!(ROUNDING);
13167    _mm512_mask_cvtx_roundps_ph::<ROUNDING>(f16x16::ZERO.as_m256h(), k, a)
13168}
13169
13170/// Convert the lower single-precision (32-bit) floating-point element in b to a half-precision (16-bit)
13171/// floating-point elements, store the result in the lower element of dst, and copy the upper 7 packed
13172/// elements from a to the upper elements of dst.
13173///
13174/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtss_sh)
13175#[inline]
13176#[target_feature(enable = "avx512fp16")]
13177#[cfg_attr(test, assert_instr(vcvtss2sh))]
13178#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13179pub fn _mm_cvtss_sh(a: __m128h, b: __m128) -> __m128h {
13180    _mm_mask_cvtss_sh(f16x8::ZERO.as_m128h(), 0xff, a, b)
13181}
13182
13183/// Convert the lower single-precision (32-bit) floating-point element in b to a half-precision (16-bit)
13184/// floating-point elements, store the result in the lower element of dst using writemask k (the element
13185/// if copied from src when mask bit 0 is not set), and copy the upper 7 packed elements from a to the
13186/// upper elements of dst.
13187///
13188/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cvtss_sh)
13189#[inline]
13190#[target_feature(enable = "avx512fp16")]
13191#[cfg_attr(test, assert_instr(vcvtss2sh))]
13192#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13193pub fn _mm_mask_cvtss_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128) -> __m128h {
13194    unsafe { vcvtss2sh(a, b, src, k, _MM_FROUND_CUR_DIRECTION) }
13195}
13196
13197/// Convert the lower single-precision (32-bit) floating-point element in b to a half-precision (16-bit)
13198/// floating-point elements, store the result in the lower element of dst using zeromask k (the element
13199/// is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from a to the upper
13200/// elements of dst.
13201///
13202/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_cvtss_sh)
13203#[inline]
13204#[target_feature(enable = "avx512fp16")]
13205#[cfg_attr(test, assert_instr(vcvtss2sh))]
13206#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13207pub fn _mm_maskz_cvtss_sh(k: __mmask8, a: __m128h, b: __m128) -> __m128h {
13208    _mm_mask_cvtss_sh(f16x8::ZERO.as_m128h(), k, a, b)
13209}
13210
13211/// Convert the lower single-precision (32-bit) floating-point element in b to a half-precision (16-bit)
13212/// floating-point elements, store the result in the lower element of dst, and copy the upper 7 packed
13213/// elements from a to the upper elements of dst.
13214///
13215/// Rounding is done according to the rounding parameter, which can be one of:
13216///
13217/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
13218/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
13219/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
13220/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
13221/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
13222///
13223/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvt_roundss_sh)
13224#[inline]
13225#[target_feature(enable = "avx512fp16")]
13226#[cfg_attr(test, assert_instr(vcvtss2sh, ROUNDING = 8))]
13227#[rustc_legacy_const_generics(2)]
13228#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13229pub fn _mm_cvt_roundss_sh<const ROUNDING: i32>(a: __m128h, b: __m128) -> __m128h {
13230    static_assert_rounding!(ROUNDING);
13231    _mm_mask_cvt_roundss_sh::<ROUNDING>(f16x8::ZERO.as_m128h(), 0xff, a, b)
13232}
13233
13234/// Convert the lower single-precision (32-bit) floating-point element in b to a half-precision (16-bit)
13235/// floating-point elements, store the result in the lower element of dst using writemask k (the element
13236/// if copied from src when mask bit 0 is not set), and copy the upper 7 packed elements from a to the
13237/// upper elements of dst.
13238///
13239/// Rounding is done according to the rounding parameter, which can be one of:
13240///
13241/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
13242/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
13243/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
13244/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
13245/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
13246///
13247/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cvt_roundss_sh)
13248#[inline]
13249#[target_feature(enable = "avx512fp16")]
13250#[cfg_attr(test, assert_instr(vcvtss2sh, ROUNDING = 8))]
13251#[rustc_legacy_const_generics(4)]
13252#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13253pub fn _mm_mask_cvt_roundss_sh<const ROUNDING: i32>(
13254    src: __m128h,
13255    k: __mmask8,
13256    a: __m128h,
13257    b: __m128,
13258) -> __m128h {
13259    unsafe {
13260        static_assert_rounding!(ROUNDING);
13261        vcvtss2sh(a, b, src, k, ROUNDING)
13262    }
13263}
13264
13265/// Convert the lower single-precision (32-bit) floating-point element in b to a half-precision (16-bit)
13266/// floating-point elements, store the result in the lower element of dst using zeromask k (the element
13267/// is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from a to the upper
13268/// elements of dst.
13269///
13270/// Rounding is done according to the rounding parameter, which can be one of:
13271///
13272/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
13273/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
13274/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
13275/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
13276/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
13277///
13278/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_cvt_roundss_sh)
13279#[inline]
13280#[target_feature(enable = "avx512fp16")]
13281#[cfg_attr(test, assert_instr(vcvtss2sh, ROUNDING = 8))]
13282#[rustc_legacy_const_generics(3)]
13283#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13284pub fn _mm_maskz_cvt_roundss_sh<const ROUNDING: i32>(
13285    k: __mmask8,
13286    a: __m128h,
13287    b: __m128,
13288) -> __m128h {
13289    static_assert_rounding!(ROUNDING);
13290    _mm_mask_cvt_roundss_sh::<ROUNDING>(f16x8::ZERO.as_m128h(), k, a, b)
13291}
13292
13293/// Convert packed double-precision (64-bit) floating-point elements in a to packed half-precision (16-bit)
13294/// floating-point elements, and store the results in dst. The upper 96 bits of dst are zeroed out.
13295///
13296/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtpd_ph)
13297#[inline]
13298#[target_feature(enable = "avx512fp16,avx512vl")]
13299#[cfg_attr(test, assert_instr(vcvtpd2ph))]
13300#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13301pub fn _mm_cvtpd_ph(a: __m128d) -> __m128h {
13302    _mm_mask_cvtpd_ph(_mm_setzero_ph(), 0xff, a)
13303}
13304
13305/// Convert packed double-precision (64-bit) floating-point elements in a to packed half-precision (16-bit)
13306/// floating-point elements, and store the results in dst using writemask k (elements are copied from src to dst
13307/// when the corresponding mask bit is not set). The upper 96 bits of dst are zeroed out.
13308///
13309/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cvtpd_ph)
13310#[inline]
13311#[target_feature(enable = "avx512fp16,avx512vl")]
13312#[cfg_attr(test, assert_instr(vcvtpd2ph))]
13313#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13314pub fn _mm_mask_cvtpd_ph(src: __m128h, k: __mmask8, a: __m128d) -> __m128h {
13315    unsafe { vcvtpd2ph_128(a, src, k) }
13316}
13317
13318/// Convert packed double-precision (64-bit) floating-point elements in a to packed half-precision (16-bit)
13319/// floating-point elements, and store the results in dst using zeromask k (elements are zeroed out when the
13320/// corresponding mask bit is not set). The upper 96 bits of dst are zeroed out.
13321///
13322/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_cvtpd_ph)
13323#[inline]
13324#[target_feature(enable = "avx512fp16,avx512vl")]
13325#[cfg_attr(test, assert_instr(vcvtpd2ph))]
13326#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13327pub fn _mm_maskz_cvtpd_ph(k: __mmask8, a: __m128d) -> __m128h {
13328    _mm_mask_cvtpd_ph(_mm_setzero_ph(), k, a)
13329}
13330
13331/// Convert packed double-precision (64-bit) floating-point elements in a to packed half-precision (16-bit)
13332/// floating-point elements, and store the results in dst. The upper 64 bits of dst are zeroed out.
13333///
13334/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtpd_ph)
13335#[inline]
13336#[target_feature(enable = "avx512fp16,avx512vl")]
13337#[cfg_attr(test, assert_instr(vcvtpd2ph))]
13338#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13339pub fn _mm256_cvtpd_ph(a: __m256d) -> __m128h {
13340    _mm256_mask_cvtpd_ph(_mm_setzero_ph(), 0xff, a)
13341}
13342
13343/// Convert packed double-precision (64-bit) floating-point elements in a to packed half-precision (16-bit)
13344/// floating-point elements, and store the results in dst using writemask k (elements are copied from src to dst
13345/// when the corresponding mask bit is not set). The upper 64 bits of dst are zeroed out.
13346///
13347/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_cvtpd_ph)
13348#[inline]
13349#[target_feature(enable = "avx512fp16,avx512vl")]
13350#[cfg_attr(test, assert_instr(vcvtpd2ph))]
13351#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13352pub fn _mm256_mask_cvtpd_ph(src: __m128h, k: __mmask8, a: __m256d) -> __m128h {
13353    unsafe { vcvtpd2ph_256(a, src, k) }
13354}
13355
13356/// Convert packed double-precision (64-bit) floating-point elements in a to packed half-precision (16-bit)
13357/// floating-point elements, and store the results in dst using zeromask k (elements are zeroed out when the
13358/// corresponding mask bit is not set). The upper 64 bits of dst are zeroed out.
13359///
13360/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_cvtpd_ph)
13361#[inline]
13362#[target_feature(enable = "avx512fp16,avx512vl")]
13363#[cfg_attr(test, assert_instr(vcvtpd2ph))]
13364#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13365pub fn _mm256_maskz_cvtpd_ph(k: __mmask8, a: __m256d) -> __m128h {
13366    _mm256_mask_cvtpd_ph(_mm_setzero_ph(), k, a)
13367}
13368
13369/// Convert packed double-precision (64-bit) floating-point elements in a to packed half-precision (16-bit)
13370/// floating-point elements, and store the results in dst.
13371///
13372/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtpd_ph)
13373#[inline]
13374#[target_feature(enable = "avx512fp16")]
13375#[cfg_attr(test, assert_instr(vcvtpd2ph))]
13376#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13377pub fn _mm512_cvtpd_ph(a: __m512d) -> __m128h {
13378    _mm512_mask_cvtpd_ph(f16x8::ZERO.as_m128h(), 0xff, a)
13379}
13380
13381/// Convert packed double-precision (64-bit) floating-point elements in a to packed half-precision (16-bit)
13382/// floating-point elements, and store the results in dst using writemask k (elements are copied from src to dst
13383/// when the corresponding mask bit is not set).
13384///
13385/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtpd_ph)
13386#[inline]
13387#[target_feature(enable = "avx512fp16")]
13388#[cfg_attr(test, assert_instr(vcvtpd2ph))]
13389#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13390pub fn _mm512_mask_cvtpd_ph(src: __m128h, k: __mmask8, a: __m512d) -> __m128h {
13391    unsafe { vcvtpd2ph_512(a, src, k, _MM_FROUND_CUR_DIRECTION) }
13392}
13393
13394/// Convert packed double-precision (64-bit) floating-point elements in a to packed half-precision (16-bit)
13395/// floating-point elements, and store the results in dst using zeromask k (elements are zeroed out when the
13396/// corresponding mask bit is not set).
13397///
13398/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtpd_ph)
13399#[inline]
13400#[target_feature(enable = "avx512fp16")]
13401#[cfg_attr(test, assert_instr(vcvtpd2ph))]
13402#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13403pub fn _mm512_maskz_cvtpd_ph(k: __mmask8, a: __m512d) -> __m128h {
13404    _mm512_mask_cvtpd_ph(f16x8::ZERO.as_m128h(), k, a)
13405}
13406
13407/// Convert packed double-precision (64-bit) floating-point elements in a to packed half-precision (16-bit)
13408/// floating-point elements, and store the results in dst.
13409///
13410/// Rounding is done according to the rounding parameter, which can be one of:
13411///
13412/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
13413/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
13414/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
13415/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
13416/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
13417///
13418/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvt_roundpd_ph)
13419#[inline]
13420#[target_feature(enable = "avx512fp16")]
13421#[cfg_attr(test, assert_instr(vcvtpd2ph, ROUNDING = 8))]
13422#[rustc_legacy_const_generics(1)]
13423#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13424pub fn _mm512_cvt_roundpd_ph<const ROUNDING: i32>(a: __m512d) -> __m128h {
13425    static_assert_rounding!(ROUNDING);
13426    _mm512_mask_cvt_roundpd_ph::<ROUNDING>(f16x8::ZERO.as_m128h(), 0xff, a)
13427}
13428
13429/// Convert packed double-precision (64-bit) floating-point elements in a to packed half-precision (16-bit)
13430/// floating-point elements, and store the results in dst using writemask k (elements are copied from src to dst
13431/// when the corresponding mask bit is not set).
13432///
13433/// Rounding is done according to the rounding parameter, which can be one of:
13434///
13435/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
13436/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
13437/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
13438/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
13439/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
13440///
13441/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvt_roundpd_ph)
13442#[inline]
13443#[target_feature(enable = "avx512fp16")]
13444#[cfg_attr(test, assert_instr(vcvtpd2ph, ROUNDING = 8))]
13445#[rustc_legacy_const_generics(3)]
13446#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13447pub fn _mm512_mask_cvt_roundpd_ph<const ROUNDING: i32>(
13448    src: __m128h,
13449    k: __mmask8,
13450    a: __m512d,
13451) -> __m128h {
13452    unsafe {
13453        static_assert_rounding!(ROUNDING);
13454        vcvtpd2ph_512(a, src, k, ROUNDING)
13455    }
13456}
13457
13458/// Convert packed double-precision (64-bit) floating-point elements in a to packed half-precision (16-bit)
13459/// floating-point elements, and store the results in dst using zeromask k (elements are zeroed out when the
13460/// corresponding mask bit is not set).
13461///
13462/// Rounding is done according to the rounding parameter, which can be one of:
13463///
13464/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
13465/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
13466/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
13467/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
13468/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
13469///
13470/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvt_roundpd_ph)
13471#[inline]
13472#[target_feature(enable = "avx512fp16")]
13473#[cfg_attr(test, assert_instr(vcvtpd2ph, ROUNDING = 8))]
13474#[rustc_legacy_const_generics(2)]
13475#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13476pub fn _mm512_maskz_cvt_roundpd_ph<const ROUNDING: i32>(k: __mmask8, a: __m512d) -> __m128h {
13477    static_assert_rounding!(ROUNDING);
13478    _mm512_mask_cvt_roundpd_ph::<ROUNDING>(f16x8::ZERO.as_m128h(), k, a)
13479}
13480
13481/// Convert the lower double-precision (64-bit) floating-point element in b to a half-precision (16-bit)
13482/// floating-point elements, store the result in the lower element of dst, and copy the upper 7 packed
13483/// elements from a to the upper elements of dst.
13484///
13485/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsd_sh)
13486#[inline]
13487#[target_feature(enable = "avx512fp16")]
13488#[cfg_attr(test, assert_instr(vcvtsd2sh))]
13489#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13490pub fn _mm_cvtsd_sh(a: __m128h, b: __m128d) -> __m128h {
13491    _mm_mask_cvtsd_sh(f16x8::ZERO.as_m128h(), 0xff, a, b)
13492}
13493
13494/// Convert the lower double-precision (64-bit) floating-point element in b to a half-precision (16-bit)
13495/// floating-point elements, store the result in the lower element of dst using writemask k (the element
13496/// if copied from src when mask bit 0 is not set), and copy the upper 7 packed elements from a to the
13497/// upper elements of dst.
13498///
13499/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cvtsd_sh)
13500#[inline]
13501#[target_feature(enable = "avx512fp16")]
13502#[cfg_attr(test, assert_instr(vcvtsd2sh))]
13503#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13504pub fn _mm_mask_cvtsd_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128d) -> __m128h {
13505    unsafe { vcvtsd2sh(a, b, src, k, _MM_FROUND_CUR_DIRECTION) }
13506}
13507
13508/// Convert the lower double-precision (64-bit) floating-point element in b to a half-precision (16-bit)
13509/// floating-point elements, store the result in the lower element of dst using zeromask k (the element
13510/// is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from a to the upper
13511/// elements of dst.
13512///
13513/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_cvtsd_sh)
13514#[inline]
13515#[target_feature(enable = "avx512fp16")]
13516#[cfg_attr(test, assert_instr(vcvtsd2sh))]
13517#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13518pub fn _mm_maskz_cvtsd_sh(k: __mmask8, a: __m128h, b: __m128d) -> __m128h {
13519    _mm_mask_cvtsd_sh(f16x8::ZERO.as_m128h(), k, a, b)
13520}
13521
13522/// Convert the lower double-precision (64-bit) floating-point element in b to a half-precision (16-bit)
13523/// floating-point elements, store the result in the lower element of dst, and copy the upper 7 packed
13524/// elements from a to the upper elements of dst.
13525///
13526/// Rounding is done according to the rounding parameter, which can be one of:
13527///
13528/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
13529/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
13530/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
13531/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
13532/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
13533///
13534/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvt_roundsd_sh)
13535#[inline]
13536#[target_feature(enable = "avx512fp16")]
13537#[cfg_attr(test, assert_instr(vcvtsd2sh, ROUNDING = 8))]
13538#[rustc_legacy_const_generics(2)]
13539#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13540pub fn _mm_cvt_roundsd_sh<const ROUNDING: i32>(a: __m128h, b: __m128d) -> __m128h {
13541    static_assert_rounding!(ROUNDING);
13542    _mm_mask_cvt_roundsd_sh::<ROUNDING>(f16x8::ZERO.as_m128h(), 0xff, a, b)
13543}
13544
13545/// Convert the lower double-precision (64-bit) floating-point element in b to a half-precision (16-bit)
13546/// floating-point elements, store the result in the lower element of dst using writemask k (the element
13547/// if copied from src when mask bit 0 is not set), and copy the upper 7 packed elements from a to the
13548/// upper elements of dst.
13549///
13550/// Rounding is done according to the rounding parameter, which can be one of:
13551///
13552/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
13553/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
13554/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
13555/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
13556/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
13557///
13558/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cvt_roundsd_sh)
13559#[inline]
13560#[target_feature(enable = "avx512fp16")]
13561#[cfg_attr(test, assert_instr(vcvtsd2sh, ROUNDING = 8))]
13562#[rustc_legacy_const_generics(4)]
13563#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13564pub fn _mm_mask_cvt_roundsd_sh<const ROUNDING: i32>(
13565    src: __m128h,
13566    k: __mmask8,
13567    a: __m128h,
13568    b: __m128d,
13569) -> __m128h {
13570    unsafe {
13571        static_assert_rounding!(ROUNDING);
13572        vcvtsd2sh(a, b, src, k, ROUNDING)
13573    }
13574}
13575
13576/// Convert the lower double-precision (64-bit) floating-point element in b to a half-precision (16-bit)
13577/// floating-point elements, store the result in the lower element of dst using zeromask k (the element
13578/// is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from a to the upper
13579/// elements of dst.
13580///
13581/// Rounding is done according to the rounding parameter, which can be one of:
13582///
13583/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
13584/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
13585/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
13586/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
13587/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
13588///
13589/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_cvt_roundsd_sh)
13590#[inline]
13591#[target_feature(enable = "avx512fp16")]
13592#[cfg_attr(test, assert_instr(vcvtsd2sh, ROUNDING = 8))]
13593#[rustc_legacy_const_generics(3)]
13594#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13595pub fn _mm_maskz_cvt_roundsd_sh<const ROUNDING: i32>(
13596    k: __mmask8,
13597    a: __m128h,
13598    b: __m128d,
13599) -> __m128h {
13600    static_assert_rounding!(ROUNDING);
13601    _mm_mask_cvt_roundsd_sh::<ROUNDING>(f16x8::ZERO.as_m128h(), k, a, b)
13602}
13603
13604/// Convert packed half-precision (16-bit) floating-point elements in a to packed 16-bit integers, and
13605/// store the results in dst.
13606///
13607/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtph_epi16)
13608#[inline]
13609#[target_feature(enable = "avx512fp16,avx512vl")]
13610#[cfg_attr(test, assert_instr(vcvtph2w))]
13611#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13612pub fn _mm_cvtph_epi16(a: __m128h) -> __m128i {
13613    _mm_mask_cvtph_epi16(_mm_undefined_si128(), 0xff, a)
13614}
13615
13616/// Convert packed half-precision (16-bit) floating-point elements in a to packed 16-bit integers, and
13617/// store the results in dst using writemask k (elements are copied from src when the corresponding
13618/// mask bit is not set).
13619///
13620/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cvtph_epi16)
13621#[inline]
13622#[target_feature(enable = "avx512fp16,avx512vl")]
13623#[cfg_attr(test, assert_instr(vcvtph2w))]
13624#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13625pub fn _mm_mask_cvtph_epi16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
13626    unsafe { transmute(vcvtph2w_128(a, src.as_i16x8(), k)) }
13627}
13628
13629/// Convert packed half-precision (16-bit) floating-point elements in a to packed 16-bit integers, and
13630/// store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
13631///
13632/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_cvtph_epi16)
13633#[inline]
13634#[target_feature(enable = "avx512fp16,avx512vl")]
13635#[cfg_attr(test, assert_instr(vcvtph2w))]
13636#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13637pub fn _mm_maskz_cvtph_epi16(k: __mmask8, a: __m128h) -> __m128i {
13638    _mm_mask_cvtph_epi16(_mm_setzero_si128(), k, a)
13639}
13640
13641/// Convert packed half-precision (16-bit) floating-point elements in a to packed 16-bit integers, and
13642/// store the results in dst.
13643///
13644/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtph_epi16)
13645#[inline]
13646#[target_feature(enable = "avx512fp16,avx512vl")]
13647#[cfg_attr(test, assert_instr(vcvtph2w))]
13648#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13649pub fn _mm256_cvtph_epi16(a: __m256h) -> __m256i {
13650    _mm256_mask_cvtph_epi16(_mm256_undefined_si256(), 0xffff, a)
13651}
13652
13653/// Convert packed half-precision (16-bit) floating-point elements in a to packed 16-bit integers, and
13654/// store the results in dst using writemask k (elements are copied from src when the corresponding
13655/// mask bit is not set).
13656///
13657/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_cvtph_epi16)
13658#[inline]
13659#[target_feature(enable = "avx512fp16,avx512vl")]
13660#[cfg_attr(test, assert_instr(vcvtph2w))]
13661#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13662pub fn _mm256_mask_cvtph_epi16(src: __m256i, k: __mmask16, a: __m256h) -> __m256i {
13663    unsafe { transmute(vcvtph2w_256(a, src.as_i16x16(), k)) }
13664}
13665
13666/// Convert packed half-precision (16-bit) floating-point elements in a to packed 16-bit integers, and
13667/// store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
13668///
13669/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_cvtph_epi16)
13670#[inline]
13671#[target_feature(enable = "avx512fp16,avx512vl")]
13672#[cfg_attr(test, assert_instr(vcvtph2w))]
13673#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13674pub fn _mm256_maskz_cvtph_epi16(k: __mmask16, a: __m256h) -> __m256i {
13675    _mm256_mask_cvtph_epi16(_mm256_setzero_si256(), k, a)
13676}
13677
13678/// Convert packed half-precision (16-bit) floating-point elements in a to packed 16-bit integers, and
13679/// store the results in dst.
13680///
13681/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtph_epi16)
13682#[inline]
13683#[target_feature(enable = "avx512fp16")]
13684#[cfg_attr(test, assert_instr(vcvtph2w))]
13685#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13686pub fn _mm512_cvtph_epi16(a: __m512h) -> __m512i {
13687    _mm512_mask_cvtph_epi16(_mm512_undefined_epi32(), 0xffffffff, a)
13688}
13689
13690/// Convert packed half-precision (16-bit) floating-point elements in a to packed 16-bit integers, and
13691/// store the results in dst using writemask k (elements are copied from src when the corresponding
13692/// mask bit is not set).
13693///
13694/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtph_epi16)
13695#[inline]
13696#[target_feature(enable = "avx512fp16")]
13697#[cfg_attr(test, assert_instr(vcvtph2w))]
13698#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13699pub fn _mm512_mask_cvtph_epi16(src: __m512i, k: __mmask32, a: __m512h) -> __m512i {
13700    unsafe {
13701        transmute(vcvtph2w_512(
13702            a,
13703            src.as_i16x32(),
13704            k,
13705            _MM_FROUND_CUR_DIRECTION,
13706        ))
13707    }
13708}
13709
13710/// Convert packed half-precision (16-bit) floating-point elements in a to packed 16-bit integers, and
13711/// store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
13712///
13713/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtph_epi16)
13714#[inline]
13715#[target_feature(enable = "avx512fp16")]
13716#[cfg_attr(test, assert_instr(vcvtph2w))]
13717#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13718pub fn _mm512_maskz_cvtph_epi16(k: __mmask32, a: __m512h) -> __m512i {
13719    _mm512_mask_cvtph_epi16(_mm512_setzero_si512(), k, a)
13720}
13721
13722/// Convert packed half-precision (16-bit) floating-point elements in a to packed 16-bit integers, and
13723/// store the results in dst.
13724///
13725/// Rounding is done according to the rounding parameter, which can be one of:
13726///
13727/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
13728/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
13729/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
13730/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
13731/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
13732///
13733/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvt_roundph_epi16)
13734#[inline]
13735#[target_feature(enable = "avx512fp16")]
13736#[cfg_attr(test, assert_instr(vcvtph2w, ROUNDING = 8))]
13737#[rustc_legacy_const_generics(1)]
13738#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13739pub fn _mm512_cvt_roundph_epi16<const ROUNDING: i32>(a: __m512h) -> __m512i {
13740    static_assert_rounding!(ROUNDING);
13741    _mm512_mask_cvt_roundph_epi16::<ROUNDING>(_mm512_undefined_epi32(), 0xffffffff, a)
13742}
13743
13744/// Convert packed half-precision (16-bit) floating-point elements in a to packed 16-bit integers, and
13745/// store the results in dst using writemask k (elements are copied from src when the corresponding
13746/// mask bit is not set).
13747///
13748/// Rounding is done according to the rounding parameter, which can be one of:
13749///
13750/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
13751/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
13752/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
13753/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
13754/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
13755///
13756/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvt_roundph_epi16)
13757#[inline]
13758#[target_feature(enable = "avx512fp16")]
13759#[cfg_attr(test, assert_instr(vcvtph2w, ROUNDING = 8))]
13760#[rustc_legacy_const_generics(3)]
13761#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13762pub fn _mm512_mask_cvt_roundph_epi16<const ROUNDING: i32>(
13763    src: __m512i,
13764    k: __mmask32,
13765    a: __m512h,
13766) -> __m512i {
13767    unsafe {
13768        static_assert_rounding!(ROUNDING);
13769        transmute(vcvtph2w_512(a, src.as_i16x32(), k, ROUNDING))
13770    }
13771}
13772
13773/// Convert packed half-precision (16-bit) floating-point elements in a to packed 16-bit integers, and
13774/// store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
13775///
13776/// Rounding is done according to the rounding parameter, which can be one of:
13777///
13778/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
13779/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
13780/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
13781/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
13782/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
13783///
13784/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvt_roundph_epi16)
13785#[inline]
13786#[target_feature(enable = "avx512fp16")]
13787#[cfg_attr(test, assert_instr(vcvtph2w, ROUNDING = 8))]
13788#[rustc_legacy_const_generics(2)]
13789#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13790pub fn _mm512_maskz_cvt_roundph_epi16<const ROUNDING: i32>(k: __mmask32, a: __m512h) -> __m512i {
13791    static_assert_rounding!(ROUNDING);
13792    _mm512_mask_cvt_roundph_epi16::<ROUNDING>(_mm512_setzero_si512(), k, a)
13793}
13794
13795/// Convert packed half-precision (16-bit) floating-point elements in a to packed unsigned 16-bit integers,
13796/// and store the results in dst.
13797///
13798/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtph_epu16)
13799#[inline]
13800#[target_feature(enable = "avx512fp16,avx512vl")]
13801#[cfg_attr(test, assert_instr(vcvtph2uw))]
13802#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13803pub fn _mm_cvtph_epu16(a: __m128h) -> __m128i {
13804    _mm_mask_cvtph_epu16(_mm_undefined_si128(), 0xff, a)
13805}
13806
13807/// Convert packed half-precision (16-bit) floating-point elements in a to packed unsigned 16-bit integers,
13808/// and store the results in dst using writemask k (elements are copied from src when the corresponding
13809/// mask bit is not set).
13810///
13811/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cvtph_epu16)
13812#[inline]
13813#[target_feature(enable = "avx512fp16,avx512vl")]
13814#[cfg_attr(test, assert_instr(vcvtph2uw))]
13815#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13816pub fn _mm_mask_cvtph_epu16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
13817    unsafe { transmute(vcvtph2uw_128(a, src.as_u16x8(), k)) }
13818}
13819
13820/// Convert packed half-precision (16-bit) floating-point elements in a to packed unsigned 16-bit integers,
13821/// and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
13822///
13823/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_cvtph_epu16)
13824#[inline]
13825#[target_feature(enable = "avx512fp16,avx512vl")]
13826#[cfg_attr(test, assert_instr(vcvtph2uw))]
13827#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13828pub fn _mm_maskz_cvtph_epu16(k: __mmask8, a: __m128h) -> __m128i {
13829    _mm_mask_cvtph_epu16(_mm_setzero_si128(), k, a)
13830}
13831
13832/// Convert packed half-precision (16-bit) floating-point elements in a to packed unsigned 16-bit integers,
13833/// and store the results in dst.
13834///
13835/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtph_epu16)
13836#[inline]
13837#[target_feature(enable = "avx512fp16,avx512vl")]
13838#[cfg_attr(test, assert_instr(vcvtph2uw))]
13839#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13840pub fn _mm256_cvtph_epu16(a: __m256h) -> __m256i {
13841    _mm256_mask_cvtph_epu16(_mm256_undefined_si256(), 0xffff, a)
13842}
13843
13844/// Convert packed half-precision (16-bit) floating-point elements in a to packed unsigned 16-bit integers,
13845/// and store the results in dst using writemask k (elements are copied from src when the corresponding
13846/// mask bit is not set).
13847///
13848/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_cvtph_epu16)
13849#[inline]
13850#[target_feature(enable = "avx512fp16,avx512vl")]
13851#[cfg_attr(test, assert_instr(vcvtph2uw))]
13852#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13853pub fn _mm256_mask_cvtph_epu16(src: __m256i, k: __mmask16, a: __m256h) -> __m256i {
13854    unsafe { transmute(vcvtph2uw_256(a, src.as_u16x16(), k)) }
13855}
13856
13857/// Convert packed half-precision (16-bit) floating-point elements in a to packed unsigned 16-bit integers,
13858/// and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
13859///
13860/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_cvtph_epu16)
13861#[inline]
13862#[target_feature(enable = "avx512fp16,avx512vl")]
13863#[cfg_attr(test, assert_instr(vcvtph2uw))]
13864#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13865pub fn _mm256_maskz_cvtph_epu16(k: __mmask16, a: __m256h) -> __m256i {
13866    _mm256_mask_cvtph_epu16(_mm256_setzero_si256(), k, a)
13867}
13868
13869/// Convert packed half-precision (16-bit) floating-point elements in a to packed unsigned 16-bit integers,
13870/// and store the results in dst.
13871///
13872/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtph_epu16)
13873#[inline]
13874#[target_feature(enable = "avx512fp16")]
13875#[cfg_attr(test, assert_instr(vcvtph2uw))]
13876#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13877pub fn _mm512_cvtph_epu16(a: __m512h) -> __m512i {
13878    _mm512_mask_cvtph_epu16(_mm512_undefined_epi32(), 0xffffffff, a)
13879}
13880
13881/// Convert packed half-precision (16-bit) floating-point elements in a to packed unsigned 16-bit integers,
13882/// and store the results in dst using writemask k (elements are copied from src when the corresponding
13883/// mask bit is not set).
13884///
13885/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtph_epu16)
13886#[inline]
13887#[target_feature(enable = "avx512fp16")]
13888#[cfg_attr(test, assert_instr(vcvtph2uw))]
13889#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13890pub fn _mm512_mask_cvtph_epu16(src: __m512i, k: __mmask32, a: __m512h) -> __m512i {
13891    unsafe {
13892        transmute(vcvtph2uw_512(
13893            a,
13894            src.as_u16x32(),
13895            k,
13896            _MM_FROUND_CUR_DIRECTION,
13897        ))
13898    }
13899}
13900
13901/// Convert packed half-precision (16-bit) floating-point elements in a to packed unsigned 16-bit integers,
13902/// and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
13903///
13904/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtph_epu16)
13905#[inline]
13906#[target_feature(enable = "avx512fp16")]
13907#[cfg_attr(test, assert_instr(vcvtph2uw))]
13908#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13909pub fn _mm512_maskz_cvtph_epu16(k: __mmask32, a: __m512h) -> __m512i {
13910    _mm512_mask_cvtph_epu16(_mm512_setzero_si512(), k, a)
13911}
13912
13913/// Convert packed half-precision (16-bit) floating-point elements in a to packed unsigned 16-bit integers,
13914/// and store the results in dst.
13915///
13916/// Exceptions can be suppressed by passing [`_MM_FROUND_NO_EXC`] in the sae parameter.
13917///
13918/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvt_roundph_epu16)
13919#[inline]
13920#[target_feature(enable = "avx512fp16")]
13921#[cfg_attr(test, assert_instr(vcvtph2uw, SAE = 8))]
13922#[rustc_legacy_const_generics(1)]
13923#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13924pub fn _mm512_cvt_roundph_epu16<const SAE: i32>(a: __m512h) -> __m512i {
13925    static_assert_sae!(SAE);
13926    _mm512_mask_cvt_roundph_epu16::<SAE>(_mm512_undefined_epi32(), 0xffffffff, a)
13927}
13928
13929/// Convert packed half-precision (16-bit) floating-point elements in a to packed unsigned 16-bit integers,
13930/// and store the results in dst using writemask k (elements are copied from src when the corresponding
13931/// mask bit is not set).
13932///
13933/// Exceptions can be suppressed by passing [`_MM_FROUND_NO_EXC`] in the sae parameter.
13934///
13935/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvt_roundph_epu16)
13936#[inline]
13937#[target_feature(enable = "avx512fp16")]
13938#[cfg_attr(test, assert_instr(vcvtph2uw, SAE = 8))]
13939#[rustc_legacy_const_generics(3)]
13940#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13941pub fn _mm512_mask_cvt_roundph_epu16<const SAE: i32>(
13942    src: __m512i,
13943    k: __mmask32,
13944    a: __m512h,
13945) -> __m512i {
13946    unsafe {
13947        static_assert_sae!(SAE);
13948        transmute(vcvtph2uw_512(a, src.as_u16x32(), k, SAE))
13949    }
13950}
13951
13952/// Convert packed half-precision (16-bit) floating-point elements in a to packed unsigned 16-bit integers,
13953/// and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
13954///
13955/// Exceptions can be suppressed by passing [`_MM_FROUND_NO_EXC`] in the sae parameter.
13956///
13957/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvt_roundph_epu16)
13958#[inline]
13959#[target_feature(enable = "avx512fp16")]
13960#[cfg_attr(test, assert_instr(vcvtph2uw, SAE = 8))]
13961#[rustc_legacy_const_generics(2)]
13962#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13963pub fn _mm512_maskz_cvt_roundph_epu16<const SAE: i32>(k: __mmask32, a: __m512h) -> __m512i {
13964    static_assert_sae!(SAE);
13965    _mm512_mask_cvt_roundph_epu16::<SAE>(_mm512_setzero_si512(), k, a)
13966}
13967
13968/// Convert packed half-precision (16-bit) floating-point elements in a to packed 16-bit integers with
13969/// truncation, and store the results in dst.
13970///
13971/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvttph_epi16)
13972#[inline]
13973#[target_feature(enable = "avx512fp16,avx512vl")]
13974#[cfg_attr(test, assert_instr(vcvttph2w))]
13975#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13976pub fn _mm_cvttph_epi16(a: __m128h) -> __m128i {
13977    _mm_mask_cvttph_epi16(_mm_undefined_si128(), 0xff, a)
13978}
13979
13980/// Convert packed half-precision (16-bit) floating-point elements in a to packed 16-bit integers with
13981/// truncation, and store the results in dst using writemask k (elements are copied from src when the corresponding
13982/// mask bit is not set).
13983///
13984/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cvttph_epi16)
13985#[inline]
13986#[target_feature(enable = "avx512fp16,avx512vl")]
13987#[cfg_attr(test, assert_instr(vcvttph2w))]
13988#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
13989pub fn _mm_mask_cvttph_epi16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
13990    unsafe { transmute(vcvttph2w_128(a, src.as_i16x8(), k)) }
13991}
13992
13993/// Convert packed half-precision (16-bit) floating-point elements in a to packed 16-bit integers with
13994/// truncation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding
13995/// mask bit is not set).
13996///
13997/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_cvttph_epi16)
13998#[inline]
13999#[target_feature(enable = "avx512fp16,avx512vl")]
14000#[cfg_attr(test, assert_instr(vcvttph2w))]
14001#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14002pub fn _mm_maskz_cvttph_epi16(k: __mmask8, a: __m128h) -> __m128i {
14003    _mm_mask_cvttph_epi16(_mm_setzero_si128(), k, a)
14004}
14005
14006/// Convert packed half-precision (16-bit) floating-point elements in a to packed 16-bit integers with
14007/// truncation, and store the results in dst.
14008///
14009/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvttph_epi16)
14010#[inline]
14011#[target_feature(enable = "avx512fp16,avx512vl")]
14012#[cfg_attr(test, assert_instr(vcvttph2w))]
14013#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14014pub fn _mm256_cvttph_epi16(a: __m256h) -> __m256i {
14015    _mm256_mask_cvttph_epi16(_mm256_undefined_si256(), 0xffff, a)
14016}
14017
14018/// Convert packed half-precision (16-bit) floating-point elements in a to packed 16-bit integers with
14019/// truncation, and store the results in dst using writemask k (elements are copied from src when the corresponding
14020/// mask bit is not set).
14021///
14022/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_cvttph_epi16)
14023#[inline]
14024#[target_feature(enable = "avx512fp16,avx512vl")]
14025#[cfg_attr(test, assert_instr(vcvttph2w))]
14026#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14027pub fn _mm256_mask_cvttph_epi16(src: __m256i, k: __mmask16, a: __m256h) -> __m256i {
14028    unsafe { transmute(vcvttph2w_256(a, src.as_i16x16(), k)) }
14029}
14030
14031/// Convert packed half-precision (16-bit) floating-point elements in a to packed 16-bit integers with
14032/// truncation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding
14033/// mask bit is not set).
14034///
14035/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_cvttph_epi16)
14036#[inline]
14037#[target_feature(enable = "avx512fp16,avx512vl")]
14038#[cfg_attr(test, assert_instr(vcvttph2w))]
14039#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14040pub fn _mm256_maskz_cvttph_epi16(k: __mmask16, a: __m256h) -> __m256i {
14041    _mm256_mask_cvttph_epi16(_mm256_setzero_si256(), k, a)
14042}
14043
14044/// Convert packed half-precision (16-bit) floating-point elements in a to packed 16-bit integers with
14045/// truncation, and store the results in dst.
14046///
14047/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvttph_epi16)
14048#[inline]
14049#[target_feature(enable = "avx512fp16")]
14050#[cfg_attr(test, assert_instr(vcvttph2w))]
14051#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14052pub fn _mm512_cvttph_epi16(a: __m512h) -> __m512i {
14053    _mm512_mask_cvttph_epi16(_mm512_undefined_epi32(), 0xffffffff, a)
14054}
14055
14056/// Convert packed half-precision (16-bit) floating-point elements in a to packed 16-bit integers with
14057/// truncation, and store the results in dst using writemask k (elements are copied from src when the corresponding
14058/// mask bit is not set).
14059///
14060/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvttph_epi16)
14061#[inline]
14062#[target_feature(enable = "avx512fp16")]
14063#[cfg_attr(test, assert_instr(vcvttph2w))]
14064#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14065pub fn _mm512_mask_cvttph_epi16(src: __m512i, k: __mmask32, a: __m512h) -> __m512i {
14066    unsafe {
14067        transmute(vcvttph2w_512(
14068            a,
14069            src.as_i16x32(),
14070            k,
14071            _MM_FROUND_CUR_DIRECTION,
14072        ))
14073    }
14074}
14075
14076/// Convert packed half-precision (16-bit) floating-point elements in a to packed 16-bit integers with
14077/// truncation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding
14078/// mask bit is not set).
14079///
14080/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvttph_epi16)
14081#[inline]
14082#[target_feature(enable = "avx512fp16")]
14083#[cfg_attr(test, assert_instr(vcvttph2w))]
14084#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14085pub fn _mm512_maskz_cvttph_epi16(k: __mmask32, a: __m512h) -> __m512i {
14086    _mm512_mask_cvttph_epi16(_mm512_setzero_si512(), k, a)
14087}
14088
14089/// Convert packed half-precision (16-bit) floating-point elements in a to packed 16-bit integers with
14090/// truncation, and store the results in dst.
14091///
14092/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
14093///
14094/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtt_roundph_epi16)
14095#[inline]
14096#[target_feature(enable = "avx512fp16")]
14097#[cfg_attr(test, assert_instr(vcvttph2w, SAE = 8))]
14098#[rustc_legacy_const_generics(1)]
14099#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14100pub fn _mm512_cvtt_roundph_epi16<const SAE: i32>(a: __m512h) -> __m512i {
14101    static_assert_sae!(SAE);
14102    _mm512_mask_cvtt_roundph_epi16::<SAE>(_mm512_undefined_epi32(), 0xffffffff, a)
14103}
14104
14105/// Convert packed half-precision (16-bit) floating-point elements in a to packed 16-bit integers with
14106/// truncation, and store the results in dst using writemask k (elements are copied from src when the corresponding
14107/// mask bit is not set).
14108///
14109/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
14110///
14111/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtt_roundph_epi16)
14112#[inline]
14113#[target_feature(enable = "avx512fp16")]
14114#[cfg_attr(test, assert_instr(vcvttph2w, SAE = 8))]
14115#[rustc_legacy_const_generics(3)]
14116#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14117pub fn _mm512_mask_cvtt_roundph_epi16<const SAE: i32>(
14118    src: __m512i,
14119    k: __mmask32,
14120    a: __m512h,
14121) -> __m512i {
14122    unsafe {
14123        static_assert_sae!(SAE);
14124        transmute(vcvttph2w_512(a, src.as_i16x32(), k, SAE))
14125    }
14126}
14127
14128/// Convert packed half-precision (16-bit) floating-point elements in a to packed 16-bit integers with
14129/// truncation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding
14130/// mask bit is not set).
14131///
14132/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
14133///
14134/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtt_roundph_epi16)
14135#[inline]
14136#[target_feature(enable = "avx512fp16")]
14137#[cfg_attr(test, assert_instr(vcvttph2w, SAE = 8))]
14138#[rustc_legacy_const_generics(2)]
14139#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14140pub fn _mm512_maskz_cvtt_roundph_epi16<const SAE: i32>(k: __mmask32, a: __m512h) -> __m512i {
14141    static_assert_sae!(SAE);
14142    _mm512_mask_cvtt_roundph_epi16::<SAE>(_mm512_setzero_si512(), k, a)
14143}
14144
14145/// Convert packed half-precision (16-bit) floating-point elements in a to packed unsigned 16-bit integers with
14146/// truncation, and store the results in dst.
14147///
14148/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvttph_epu16)
14149#[inline]
14150#[target_feature(enable = "avx512fp16,avx512vl")]
14151#[cfg_attr(test, assert_instr(vcvttph2uw))]
14152#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14153pub fn _mm_cvttph_epu16(a: __m128h) -> __m128i {
14154    _mm_mask_cvttph_epu16(_mm_undefined_si128(), 0xff, a)
14155}
14156
14157/// Convert packed half-precision (16-bit) floating-point elements in a to packed unsigned 16-bit integers with
14158/// truncation, and store the results in dst using writemask k (elements are copied from src when the corresponding
14159/// mask bit is not set).
14160///
14161/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cvttph_epu16)
14162#[inline]
14163#[target_feature(enable = "avx512fp16,avx512vl")]
14164#[cfg_attr(test, assert_instr(vcvttph2uw))]
14165#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14166pub fn _mm_mask_cvttph_epu16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
14167    unsafe { transmute(vcvttph2uw_128(a, src.as_u16x8(), k)) }
14168}
14169
14170/// Convert packed half-precision (16-bit) floating-point elements in a to packed unsigned 16-bit integers with
14171/// truncation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding
14172/// mask bit is not set).
14173///
14174/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_cvttph_epu16)
14175#[inline]
14176#[target_feature(enable = "avx512fp16,avx512vl")]
14177#[cfg_attr(test, assert_instr(vcvttph2uw))]
14178#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14179pub fn _mm_maskz_cvttph_epu16(k: __mmask8, a: __m128h) -> __m128i {
14180    _mm_mask_cvttph_epu16(_mm_setzero_si128(), k, a)
14181}
14182
14183/// Convert packed half-precision (16-bit) floating-point elements in a to packed unsigned 16-bit integers with
14184/// truncation, and store the results in dst.
14185///
14186/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvttph_epu16)
14187#[inline]
14188#[target_feature(enable = "avx512fp16,avx512vl")]
14189#[cfg_attr(test, assert_instr(vcvttph2uw))]
14190#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14191pub fn _mm256_cvttph_epu16(a: __m256h) -> __m256i {
14192    _mm256_mask_cvttph_epu16(_mm256_undefined_si256(), 0xffff, a)
14193}
14194
14195/// Convert packed half-precision (16-bit) floating-point elements in a to packed unsigned 16-bit integers with
14196/// truncation, and store the results in dst using writemask k (elements are copied from src when the corresponding
14197/// mask bit is not set).
14198///
14199/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_cvttph_epu16)
14200#[inline]
14201#[target_feature(enable = "avx512fp16,avx512vl")]
14202#[cfg_attr(test, assert_instr(vcvttph2uw))]
14203#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14204pub fn _mm256_mask_cvttph_epu16(src: __m256i, k: __mmask16, a: __m256h) -> __m256i {
14205    unsafe { transmute(vcvttph2uw_256(a, src.as_u16x16(), k)) }
14206}
14207
14208/// Convert packed half-precision (16-bit) floating-point elements in a to packed unsigned 16-bit integers with
14209/// truncation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding
14210/// mask bit is not set).
14211///
14212/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_cvttph_epu16)
14213#[inline]
14214#[target_feature(enable = "avx512fp16,avx512vl")]
14215#[cfg_attr(test, assert_instr(vcvttph2uw))]
14216#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14217pub fn _mm256_maskz_cvttph_epu16(k: __mmask16, a: __m256h) -> __m256i {
14218    _mm256_mask_cvttph_epu16(_mm256_setzero_si256(), k, a)
14219}
14220
14221/// Convert packed half-precision (16-bit) floating-point elements in a to packed unsigned 16-bit integers with
14222/// truncation, and store the results in dst.
14223///
14224/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvttph_epu16)
14225#[inline]
14226#[target_feature(enable = "avx512fp16")]
14227#[cfg_attr(test, assert_instr(vcvttph2uw))]
14228#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14229pub fn _mm512_cvttph_epu16(a: __m512h) -> __m512i {
14230    _mm512_mask_cvttph_epu16(_mm512_undefined_epi32(), 0xffffffff, a)
14231}
14232
14233/// Convert packed half-precision (16-bit) floating-point elements in a to packed unsigned 16-bit integers with
14234/// truncation, and store the results in dst using writemask k (elements are copied from src when the corresponding
14235/// mask bit is not set).
14236///
14237/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvttph_epu16)
14238#[inline]
14239#[target_feature(enable = "avx512fp16")]
14240#[cfg_attr(test, assert_instr(vcvttph2uw))]
14241#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14242pub fn _mm512_mask_cvttph_epu16(src: __m512i, k: __mmask32, a: __m512h) -> __m512i {
14243    unsafe {
14244        transmute(vcvttph2uw_512(
14245            a,
14246            src.as_u16x32(),
14247            k,
14248            _MM_FROUND_CUR_DIRECTION,
14249        ))
14250    }
14251}
14252
14253/// Convert packed half-precision (16-bit) floating-point elements in a to packed unsigned 16-bit integers with
14254/// truncation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding
14255/// mask bit is not set).
14256///
14257/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvttph_epu16)
14258#[inline]
14259#[target_feature(enable = "avx512fp16")]
14260#[cfg_attr(test, assert_instr(vcvttph2uw))]
14261#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14262pub fn _mm512_maskz_cvttph_epu16(k: __mmask32, a: __m512h) -> __m512i {
14263    _mm512_mask_cvttph_epu16(_mm512_setzero_si512(), k, a)
14264}
14265
14266/// Convert packed half-precision (16-bit) floating-point elements in a to packed unsigned 16-bit integers with
14267/// truncation, and store the results in dst.
14268///
14269/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
14270///
14271/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtt_roundph_epu16)
14272#[inline]
14273#[target_feature(enable = "avx512fp16")]
14274#[cfg_attr(test, assert_instr(vcvttph2uw, SAE = 8))]
14275#[rustc_legacy_const_generics(1)]
14276#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14277pub fn _mm512_cvtt_roundph_epu16<const SAE: i32>(a: __m512h) -> __m512i {
14278    static_assert_sae!(SAE);
14279    _mm512_mask_cvtt_roundph_epu16::<SAE>(_mm512_undefined_epi32(), 0xffffffff, a)
14280}
14281
14282/// Convert packed half-precision (16-bit) floating-point elements in a to packed unsigned 16-bit integers with
14283/// truncation, and store the results in dst using writemask k (elements are copied from src when the corresponding
14284/// mask bit is not set).
14285///
14286/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
14287///
14288/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtt_roundph_epu16)
14289#[inline]
14290#[target_feature(enable = "avx512fp16")]
14291#[cfg_attr(test, assert_instr(vcvttph2uw, SAE = 8))]
14292#[rustc_legacy_const_generics(3)]
14293#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14294pub fn _mm512_mask_cvtt_roundph_epu16<const SAE: i32>(
14295    src: __m512i,
14296    k: __mmask32,
14297    a: __m512h,
14298) -> __m512i {
14299    unsafe {
14300        static_assert_sae!(SAE);
14301        transmute(vcvttph2uw_512(a, src.as_u16x32(), k, SAE))
14302    }
14303}
14304
14305/// Convert packed half-precision (16-bit) floating-point elements in a to packed unsigned 16-bit integers with
14306/// truncation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding
14307/// mask bit is not set).
14308///
14309/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
14310///
14311/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtt_roundph_epu16)
14312#[inline]
14313#[target_feature(enable = "avx512fp16")]
14314#[cfg_attr(test, assert_instr(vcvttph2uw, SAE = 8))]
14315#[rustc_legacy_const_generics(2)]
14316#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14317pub fn _mm512_maskz_cvtt_roundph_epu16<const SAE: i32>(k: __mmask32, a: __m512h) -> __m512i {
14318    static_assert_sae!(SAE);
14319    _mm512_mask_cvtt_roundph_epu16::<SAE>(_mm512_setzero_si512(), k, a)
14320}
14321
14322/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit integers, and store the
14323/// results in dst.
14324///
14325/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtph_epi32)
14326#[inline]
14327#[target_feature(enable = "avx512fp16,avx512vl")]
14328#[cfg_attr(test, assert_instr(vcvtph2dq))]
14329#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14330pub fn _mm_cvtph_epi32(a: __m128h) -> __m128i {
14331    _mm_mask_cvtph_epi32(_mm_undefined_si128(), 0xff, a)
14332}
14333
14334/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit integers, and store the
14335/// results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
14336///
14337/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cvtph_epi32)
14338#[inline]
14339#[target_feature(enable = "avx512fp16,avx512vl")]
14340#[cfg_attr(test, assert_instr(vcvtph2dq))]
14341#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14342pub fn _mm_mask_cvtph_epi32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
14343    unsafe { transmute(vcvtph2dq_128(a, src.as_i32x4(), k)) }
14344}
14345
14346/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit integers, and store the
14347/// results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
14348///
14349/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_cvtph_epi32)
14350#[inline]
14351#[target_feature(enable = "avx512fp16,avx512vl")]
14352#[cfg_attr(test, assert_instr(vcvtph2dq))]
14353#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14354pub fn _mm_maskz_cvtph_epi32(k: __mmask8, a: __m128h) -> __m128i {
14355    _mm_mask_cvtph_epi32(_mm_setzero_si128(), k, a)
14356}
14357
14358/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit integers, and store the
14359/// results in dst.
14360///
14361/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtph_epi32)
14362#[inline]
14363#[target_feature(enable = "avx512fp16,avx512vl")]
14364#[cfg_attr(test, assert_instr(vcvtph2dq))]
14365#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14366pub fn _mm256_cvtph_epi32(a: __m128h) -> __m256i {
14367    _mm256_mask_cvtph_epi32(_mm256_undefined_si256(), 0xff, a)
14368}
14369
14370/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit integers, and store the
14371/// results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
14372///
14373/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_cvtph_epi32)
14374#[inline]
14375#[target_feature(enable = "avx512fp16,avx512vl")]
14376#[cfg_attr(test, assert_instr(vcvtph2dq))]
14377#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14378pub fn _mm256_mask_cvtph_epi32(src: __m256i, k: __mmask8, a: __m128h) -> __m256i {
14379    unsafe { transmute(vcvtph2dq_256(a, src.as_i32x8(), k)) }
14380}
14381
14382/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit integers, and store the
14383/// results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
14384///
14385/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_cvtph_epi32)
14386#[inline]
14387#[target_feature(enable = "avx512fp16,avx512vl")]
14388#[cfg_attr(test, assert_instr(vcvtph2dq))]
14389#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14390pub fn _mm256_maskz_cvtph_epi32(k: __mmask8, a: __m128h) -> __m256i {
14391    _mm256_mask_cvtph_epi32(_mm256_setzero_si256(), k, a)
14392}
14393
14394/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit integers, and store the
14395/// results in dst.
14396///
14397/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtph_epi32)
14398#[inline]
14399#[target_feature(enable = "avx512fp16")]
14400#[cfg_attr(test, assert_instr(vcvtph2dq))]
14401#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14402pub fn _mm512_cvtph_epi32(a: __m256h) -> __m512i {
14403    _mm512_mask_cvtph_epi32(_mm512_undefined_epi32(), 0xffff, a)
14404}
14405
14406/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit integers, and store the
14407/// results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
14408///
14409/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtph_epi32)
14410#[inline]
14411#[target_feature(enable = "avx512fp16")]
14412#[cfg_attr(test, assert_instr(vcvtph2dq))]
14413#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14414pub fn _mm512_mask_cvtph_epi32(src: __m512i, k: __mmask16, a: __m256h) -> __m512i {
14415    unsafe {
14416        transmute(vcvtph2dq_512(
14417            a,
14418            src.as_i32x16(),
14419            k,
14420            _MM_FROUND_CUR_DIRECTION,
14421        ))
14422    }
14423}
14424
14425/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit integers, and store the
14426/// results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
14427///
14428/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtph_epi32)
14429#[inline]
14430#[target_feature(enable = "avx512fp16")]
14431#[cfg_attr(test, assert_instr(vcvtph2dq))]
14432#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14433pub fn _mm512_maskz_cvtph_epi32(k: __mmask16, a: __m256h) -> __m512i {
14434    _mm512_mask_cvtph_epi32(_mm512_setzero_si512(), k, a)
14435}
14436
14437/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit integers, and store the
14438/// results in dst.
14439///
14440/// Rounding is done according to the rounding parameter, which can be one of:
14441///
14442/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
14443/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
14444/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
14445/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
14446/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
14447///
14448/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvt_roundph_epi32)
14449#[inline]
14450#[target_feature(enable = "avx512fp16")]
14451#[cfg_attr(test, assert_instr(vcvtph2dq, ROUNDING = 8))]
14452#[rustc_legacy_const_generics(1)]
14453#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14454pub fn _mm512_cvt_roundph_epi32<const ROUNDING: i32>(a: __m256h) -> __m512i {
14455    static_assert_rounding!(ROUNDING);
14456    _mm512_mask_cvt_roundph_epi32::<ROUNDING>(_mm512_undefined_epi32(), 0xffff, a)
14457}
14458
14459/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit integers, and store the
14460/// results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
14461///
14462/// Rounding is done according to the rounding parameter, which can be one of:
14463///
14464/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
14465/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
14466/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
14467/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
14468/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
14469///
14470/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvt_roundph_epi32)
14471#[inline]
14472#[target_feature(enable = "avx512fp16")]
14473#[cfg_attr(test, assert_instr(vcvtph2dq, ROUNDING = 8))]
14474#[rustc_legacy_const_generics(3)]
14475#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14476pub fn _mm512_mask_cvt_roundph_epi32<const ROUNDING: i32>(
14477    src: __m512i,
14478    k: __mmask16,
14479    a: __m256h,
14480) -> __m512i {
14481    unsafe {
14482        static_assert_rounding!(ROUNDING);
14483        transmute(vcvtph2dq_512(a, src.as_i32x16(), k, ROUNDING))
14484    }
14485}
14486
14487/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit integers, and store the
14488/// results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
14489///
14490/// Rounding is done according to the rounding parameter, which can be one of:
14491///
14492/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
14493/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
14494/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
14495/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
14496/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
14497///
14498/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvt_roundph_epi32)
14499#[inline]
14500#[target_feature(enable = "avx512fp16")]
14501#[cfg_attr(test, assert_instr(vcvtph2dq, ROUNDING = 8))]
14502#[rustc_legacy_const_generics(2)]
14503#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14504pub fn _mm512_maskz_cvt_roundph_epi32<const ROUNDING: i32>(k: __mmask16, a: __m256h) -> __m512i {
14505    static_assert_rounding!(ROUNDING);
14506    _mm512_mask_cvt_roundph_epi32::<ROUNDING>(_mm512_setzero_si512(), k, a)
14507}
14508
14509/// Convert the lower half-precision (16-bit) floating-point element in a to a 32-bit integer, and store
14510/// the result in dst.
14511///
14512/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsh_i32)
14513#[inline]
14514#[target_feature(enable = "avx512fp16")]
14515#[cfg_attr(test, assert_instr(vcvtsh2si))]
14516#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14517pub fn _mm_cvtsh_i32(a: __m128h) -> i32 {
14518    unsafe { vcvtsh2si32(a, _MM_FROUND_CUR_DIRECTION) }
14519}
14520
14521/// Convert the lower half-precision (16-bit) floating-point element in a to a 32-bit integer, and store
14522/// the result in dst.
14523///
14524/// Rounding is done according to the rounding parameter, which can be one of:
14525///
14526/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
14527/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
14528/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
14529/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
14530/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
14531///
14532/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvt_roundsh_i32)
14533#[inline]
14534#[target_feature(enable = "avx512fp16")]
14535#[cfg_attr(test, assert_instr(vcvtsh2si, ROUNDING = 8))]
14536#[rustc_legacy_const_generics(1)]
14537#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14538pub fn _mm_cvt_roundsh_i32<const ROUNDING: i32>(a: __m128h) -> i32 {
14539    unsafe {
14540        static_assert_rounding!(ROUNDING);
14541        vcvtsh2si32(a, ROUNDING)
14542    }
14543}
14544
14545/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit integers, and store the
14546/// results in dst.
14547///
14548/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtph_epu32)
14549#[inline]
14550#[target_feature(enable = "avx512fp16,avx512vl")]
14551#[cfg_attr(test, assert_instr(vcvtph2udq))]
14552#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14553pub fn _mm_cvtph_epu32(a: __m128h) -> __m128i {
14554    _mm_mask_cvtph_epu32(_mm_undefined_si128(), 0xff, a)
14555}
14556
14557/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit unsigned integers, and store
14558/// the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
14559///
14560/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cvtph_epu32)
14561#[inline]
14562#[target_feature(enable = "avx512fp16,avx512vl")]
14563#[cfg_attr(test, assert_instr(vcvtph2udq))]
14564#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14565pub fn _mm_mask_cvtph_epu32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
14566    unsafe { transmute(vcvtph2udq_128(a, src.as_u32x4(), k)) }
14567}
14568
14569/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit unsigned integers, and store
14570/// the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
14571///
14572/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_cvtph_epu32)
14573#[inline]
14574#[target_feature(enable = "avx512fp16,avx512vl")]
14575#[cfg_attr(test, assert_instr(vcvtph2udq))]
14576#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14577pub fn _mm_maskz_cvtph_epu32(k: __mmask8, a: __m128h) -> __m128i {
14578    _mm_mask_cvtph_epu32(_mm_setzero_si128(), k, a)
14579}
14580
14581/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit unsigned integers, and store
14582/// the results in dst.
14583///
14584/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtph_epu32)
14585#[inline]
14586#[target_feature(enable = "avx512fp16,avx512vl")]
14587#[cfg_attr(test, assert_instr(vcvtph2udq))]
14588#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14589pub fn _mm256_cvtph_epu32(a: __m128h) -> __m256i {
14590    _mm256_mask_cvtph_epu32(_mm256_undefined_si256(), 0xff, a)
14591}
14592
14593/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit unsigned integers, and store
14594/// the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
14595///
14596/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_cvtph_epu32)
14597#[inline]
14598#[target_feature(enable = "avx512fp16,avx512vl")]
14599#[cfg_attr(test, assert_instr(vcvtph2udq))]
14600#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14601pub fn _mm256_mask_cvtph_epu32(src: __m256i, k: __mmask8, a: __m128h) -> __m256i {
14602    unsafe { transmute(vcvtph2udq_256(a, src.as_u32x8(), k)) }
14603}
14604
14605/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit unsigned integers, and store
14606/// the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
14607///
14608/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_cvtph_epu32)
14609#[inline]
14610#[target_feature(enable = "avx512fp16,avx512vl")]
14611#[cfg_attr(test, assert_instr(vcvtph2udq))]
14612#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14613pub fn _mm256_maskz_cvtph_epu32(k: __mmask8, a: __m128h) -> __m256i {
14614    _mm256_mask_cvtph_epu32(_mm256_setzero_si256(), k, a)
14615}
14616
14617/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit unsigned integers, and store
14618/// the results in dst.
14619///
14620/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtph_epu32)
14621#[inline]
14622#[target_feature(enable = "avx512fp16")]
14623#[cfg_attr(test, assert_instr(vcvtph2udq))]
14624#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14625pub fn _mm512_cvtph_epu32(a: __m256h) -> __m512i {
14626    _mm512_mask_cvtph_epu32(_mm512_undefined_epi32(), 0xffff, a)
14627}
14628
14629/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit unsigned integers, and store
14630/// the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
14631///
14632/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtph_epu32)
14633#[inline]
14634#[target_feature(enable = "avx512fp16")]
14635#[cfg_attr(test, assert_instr(vcvtph2udq))]
14636#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14637pub fn _mm512_mask_cvtph_epu32(src: __m512i, k: __mmask16, a: __m256h) -> __m512i {
14638    unsafe {
14639        transmute(vcvtph2udq_512(
14640            a,
14641            src.as_u32x16(),
14642            k,
14643            _MM_FROUND_CUR_DIRECTION,
14644        ))
14645    }
14646}
14647
14648/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit unsigned integers, and store
14649/// the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
14650///
14651/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtph_epu32)
14652#[inline]
14653#[target_feature(enable = "avx512fp16")]
14654#[cfg_attr(test, assert_instr(vcvtph2udq))]
14655#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14656pub fn _mm512_maskz_cvtph_epu32(k: __mmask16, a: __m256h) -> __m512i {
14657    _mm512_mask_cvtph_epu32(_mm512_setzero_si512(), k, a)
14658}
14659
14660/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit unsigned integers, and store
14661/// the results in dst.
14662///
14663/// Rounding is done according to the rounding parameter, which can be one of:
14664///
14665/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
14666/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
14667/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
14668/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
14669/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
14670///
14671/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvt_roundph_epu32)
14672#[inline]
14673#[target_feature(enable = "avx512fp16")]
14674#[cfg_attr(test, assert_instr(vcvtph2udq, ROUNDING = 8))]
14675#[rustc_legacy_const_generics(1)]
14676#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14677pub fn _mm512_cvt_roundph_epu32<const ROUNDING: i32>(a: __m256h) -> __m512i {
14678    static_assert_rounding!(ROUNDING);
14679    _mm512_mask_cvt_roundph_epu32::<ROUNDING>(_mm512_undefined_epi32(), 0xffff, a)
14680}
14681
14682/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit unsigned integers, and store
14683/// the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
14684///
14685/// Rounding is done according to the rounding parameter, which can be one of:
14686///
14687/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
14688/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
14689/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
14690/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
14691/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
14692///
14693/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvt_roundph_epu32)
14694#[inline]
14695#[target_feature(enable = "avx512fp16")]
14696#[cfg_attr(test, assert_instr(vcvtph2udq, ROUNDING = 8))]
14697#[rustc_legacy_const_generics(3)]
14698#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14699pub fn _mm512_mask_cvt_roundph_epu32<const ROUNDING: i32>(
14700    src: __m512i,
14701    k: __mmask16,
14702    a: __m256h,
14703) -> __m512i {
14704    unsafe {
14705        static_assert_rounding!(ROUNDING);
14706        transmute(vcvtph2udq_512(a, src.as_u32x16(), k, ROUNDING))
14707    }
14708}
14709
14710/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit unsigned integers, and store
14711/// the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
14712///
14713/// Rounding is done according to the rounding parameter, which can be one of:
14714///
14715/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
14716/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
14717/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
14718/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
14719/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
14720///
14721/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvt_roundph_epu32)
14722#[inline]
14723#[target_feature(enable = "avx512fp16")]
14724#[cfg_attr(test, assert_instr(vcvtph2udq, ROUNDING = 8))]
14725#[rustc_legacy_const_generics(2)]
14726#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14727pub fn _mm512_maskz_cvt_roundph_epu32<const ROUNDING: i32>(k: __mmask16, a: __m256h) -> __m512i {
14728    static_assert_rounding!(ROUNDING);
14729    _mm512_mask_cvt_roundph_epu32::<ROUNDING>(_mm512_setzero_si512(), k, a)
14730}
14731
14732/// Convert the lower half-precision (16-bit) floating-point element in a to a 32-bit unsigned integer, and store
14733/// the result in dst.
14734///
14735/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsh_u32)
14736#[inline]
14737#[target_feature(enable = "avx512fp16")]
14738#[cfg_attr(test, assert_instr(vcvtsh2usi))]
14739#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14740pub fn _mm_cvtsh_u32(a: __m128h) -> u32 {
14741    unsafe { vcvtsh2usi32(a, _MM_FROUND_CUR_DIRECTION) }
14742}
14743
14744/// Convert the lower half-precision (16-bit) floating-point element in a to a 32-bit unsigned integer, and store
14745/// the result in dst.
14746///
14747/// Exceptions can be suppressed by passing [`_MM_FROUND_NO_EXC`] in the sae parameter.
14748///
14749/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvt_roundsh_u32)
14750#[inline]
14751#[target_feature(enable = "avx512fp16")]
14752#[cfg_attr(test, assert_instr(vcvtsh2usi, SAE = 8))]
14753#[rustc_legacy_const_generics(1)]
14754#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14755pub fn _mm_cvt_roundsh_u32<const SAE: i32>(a: __m128h) -> u32 {
14756    unsafe {
14757        static_assert_rounding!(SAE);
14758        vcvtsh2usi32(a, SAE)
14759    }
14760}
14761
14762/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit integers with truncation, and
14763/// store the results in dst.
14764///
14765/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvttph_epi32)
14766#[inline]
14767#[target_feature(enable = "avx512fp16,avx512vl")]
14768#[cfg_attr(test, assert_instr(vcvttph2dq))]
14769#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14770pub fn _mm_cvttph_epi32(a: __m128h) -> __m128i {
14771    _mm_mask_cvttph_epi32(_mm_undefined_si128(), 0xff, a)
14772}
14773
14774/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit integers with truncation, and
14775/// store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
14776///
14777/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cvttph_epi32)
14778#[inline]
14779#[target_feature(enable = "avx512fp16,avx512vl")]
14780#[cfg_attr(test, assert_instr(vcvttph2dq))]
14781#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14782pub fn _mm_mask_cvttph_epi32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
14783    unsafe { transmute(vcvttph2dq_128(a, src.as_i32x4(), k)) }
14784}
14785
14786/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit integers with truncation, and
14787/// store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
14788///
14789/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_cvttph_epi32)
14790#[inline]
14791#[target_feature(enable = "avx512fp16,avx512vl")]
14792#[cfg_attr(test, assert_instr(vcvttph2dq))]
14793#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14794pub fn _mm_maskz_cvttph_epi32(k: __mmask8, a: __m128h) -> __m128i {
14795    _mm_mask_cvttph_epi32(_mm_setzero_si128(), k, a)
14796}
14797
14798/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit integers with truncation, and
14799/// store the results in dst.
14800///
14801/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvttph_epi32)
14802#[inline]
14803#[target_feature(enable = "avx512fp16,avx512vl")]
14804#[cfg_attr(test, assert_instr(vcvttph2dq))]
14805#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14806pub fn _mm256_cvttph_epi32(a: __m128h) -> __m256i {
14807    _mm256_mask_cvttph_epi32(_mm256_undefined_si256(), 0xff, a)
14808}
14809
14810/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit integers with truncation, and
14811/// store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
14812///
14813/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_cvttph_epi32)
14814#[inline]
14815#[target_feature(enable = "avx512fp16,avx512vl")]
14816#[cfg_attr(test, assert_instr(vcvttph2dq))]
14817#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14818pub fn _mm256_mask_cvttph_epi32(src: __m256i, k: __mmask8, a: __m128h) -> __m256i {
14819    unsafe { transmute(vcvttph2dq_256(a, src.as_i32x8(), k)) }
14820}
14821
14822/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit integers with truncation, and
14823/// store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
14824///
14825/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_cvttph_epi32)
14826#[inline]
14827#[target_feature(enable = "avx512fp16,avx512vl")]
14828#[cfg_attr(test, assert_instr(vcvttph2dq))]
14829#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14830pub fn _mm256_maskz_cvttph_epi32(k: __mmask8, a: __m128h) -> __m256i {
14831    _mm256_mask_cvttph_epi32(_mm256_setzero_si256(), k, a)
14832}
14833
14834/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit integers with truncation, and
14835/// store the results in dst.
14836///
14837/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvttph_epi32)
14838#[inline]
14839#[target_feature(enable = "avx512fp16")]
14840#[cfg_attr(test, assert_instr(vcvttph2dq))]
14841#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14842pub fn _mm512_cvttph_epi32(a: __m256h) -> __m512i {
14843    _mm512_mask_cvttph_epi32(_mm512_undefined_epi32(), 0xffff, a)
14844}
14845
14846/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit integers with truncation, and
14847/// store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
14848///
14849/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvttph_epi32)
14850#[inline]
14851#[target_feature(enable = "avx512fp16")]
14852#[cfg_attr(test, assert_instr(vcvttph2dq))]
14853#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14854pub fn _mm512_mask_cvttph_epi32(src: __m512i, k: __mmask16, a: __m256h) -> __m512i {
14855    unsafe {
14856        transmute(vcvttph2dq_512(
14857            a,
14858            src.as_i32x16(),
14859            k,
14860            _MM_FROUND_CUR_DIRECTION,
14861        ))
14862    }
14863}
14864
14865/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit integers with truncation, and
14866/// store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
14867///
14868/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvttph_epi32)
14869#[inline]
14870#[target_feature(enable = "avx512fp16")]
14871#[cfg_attr(test, assert_instr(vcvttph2dq))]
14872#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14873pub fn _mm512_maskz_cvttph_epi32(k: __mmask16, a: __m256h) -> __m512i {
14874    _mm512_mask_cvttph_epi32(_mm512_setzero_si512(), k, a)
14875}
14876
14877/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit integers with truncation, and
14878/// store the results in dst.
14879///
14880/// Exceptions can be suppressed by passing `_MM_FROUND_NO_EXC` in the `sae` parameter.
14881///
14882/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtt_roundph_epi32)
14883#[inline]
14884#[target_feature(enable = "avx512fp16")]
14885#[cfg_attr(test, assert_instr(vcvttph2dq, SAE = 8))]
14886#[rustc_legacy_const_generics(1)]
14887#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14888pub fn _mm512_cvtt_roundph_epi32<const SAE: i32>(a: __m256h) -> __m512i {
14889    static_assert_sae!(SAE);
14890    _mm512_mask_cvtt_roundph_epi32::<SAE>(_mm512_undefined_epi32(), 0xffff, a)
14891}
14892
14893/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit integers with truncation, and
14894/// store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
14895///
14896/// Exceptions can be suppressed by passing `_MM_FROUND_NO_EXC` in the `sae` parameter.
14897///
14898/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtt_roundph_epi32)
14899#[inline]
14900#[target_feature(enable = "avx512fp16")]
14901#[cfg_attr(test, assert_instr(vcvttph2dq, SAE = 8))]
14902#[rustc_legacy_const_generics(3)]
14903#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14904pub fn _mm512_mask_cvtt_roundph_epi32<const SAE: i32>(
14905    src: __m512i,
14906    k: __mmask16,
14907    a: __m256h,
14908) -> __m512i {
14909    unsafe {
14910        static_assert_sae!(SAE);
14911        transmute(vcvttph2dq_512(a, src.as_i32x16(), k, SAE))
14912    }
14913}
14914
14915/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit integers with truncation, and
14916/// store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
14917///
14918/// Exceptions can be suppressed by passing `_MM_FROUND_NO_EXC` in the `sae` parameter.
14919///
14920/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtt_roundph_epi32)
14921#[inline]
14922#[target_feature(enable = "avx512fp16")]
14923#[cfg_attr(test, assert_instr(vcvttph2dq, SAE = 8))]
14924#[rustc_legacy_const_generics(2)]
14925#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14926pub fn _mm512_maskz_cvtt_roundph_epi32<const SAE: i32>(k: __mmask16, a: __m256h) -> __m512i {
14927    static_assert_sae!(SAE);
14928    _mm512_mask_cvtt_roundph_epi32::<SAE>(_mm512_setzero_si512(), k, a)
14929}
14930
14931/// Convert the lower half-precision (16-bit) floating-point element in a to a 32-bit integer with truncation, and store
14932/// the result in dst.
14933///
14934/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvttsh_i32)
14935#[inline]
14936#[target_feature(enable = "avx512fp16")]
14937#[cfg_attr(test, assert_instr(vcvttsh2si))]
14938#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14939pub fn _mm_cvttsh_i32(a: __m128h) -> i32 {
14940    unsafe { vcvttsh2si32(a, _MM_FROUND_CUR_DIRECTION) }
14941}
14942
14943/// Convert the lower half-precision (16-bit) floating-point element in a to a 32-bit integer with truncation, and store
14944/// the result in dst.
14945///
14946/// Exceptions can be suppressed by passing `_MM_FROUND_NO_EXC` in the `sae` parameter.
14947///
14948/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtt_roundsh_i32)
14949#[inline]
14950#[target_feature(enable = "avx512fp16")]
14951#[cfg_attr(test, assert_instr(vcvttsh2si, SAE = 8))]
14952#[rustc_legacy_const_generics(1)]
14953#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14954pub fn _mm_cvtt_roundsh_i32<const SAE: i32>(a: __m128h) -> i32 {
14955    unsafe {
14956        static_assert_sae!(SAE);
14957        vcvttsh2si32(a, SAE)
14958    }
14959}
14960
14961/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit unsigned integers with truncation, and
14962/// store the results in dst.
14963///
14964/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvttph_epu32)
14965#[inline]
14966#[target_feature(enable = "avx512fp16,avx512vl")]
14967#[cfg_attr(test, assert_instr(vcvttph2udq))]
14968#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14969pub fn _mm_cvttph_epu32(a: __m128h) -> __m128i {
14970    _mm_mask_cvttph_epu32(_mm_undefined_si128(), 0xff, a)
14971}
14972
14973/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit unsigned integers with truncation, and
14974/// store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
14975///
14976/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cvttph_epu32)
14977#[inline]
14978#[target_feature(enable = "avx512fp16,avx512vl")]
14979#[cfg_attr(test, assert_instr(vcvttph2udq))]
14980#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14981pub fn _mm_mask_cvttph_epu32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
14982    unsafe { transmute(vcvttph2udq_128(a, src.as_u32x4(), k)) }
14983}
14984
14985/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit unsigned integers with truncation, and
14986/// store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
14987///
14988/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_cvttph_epu32)
14989#[inline]
14990#[target_feature(enable = "avx512fp16,avx512vl")]
14991#[cfg_attr(test, assert_instr(vcvttph2udq))]
14992#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
14993pub fn _mm_maskz_cvttph_epu32(k: __mmask8, a: __m128h) -> __m128i {
14994    _mm_mask_cvttph_epu32(_mm_setzero_si128(), k, a)
14995}
14996
14997/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit unsigned integers with truncation, and
14998/// store the results in dst.
14999///
15000/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvttph_epu32)
15001#[inline]
15002#[target_feature(enable = "avx512fp16,avx512vl")]
15003#[cfg_attr(test, assert_instr(vcvttph2udq))]
15004#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15005pub fn _mm256_cvttph_epu32(a: __m128h) -> __m256i {
15006    _mm256_mask_cvttph_epu32(_mm256_undefined_si256(), 0xff, a)
15007}
15008
15009/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit unsigned integers with truncation, and
15010/// store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
15011///
15012/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_cvttph_epu32)
15013#[inline]
15014#[target_feature(enable = "avx512fp16,avx512vl")]
15015#[cfg_attr(test, assert_instr(vcvttph2udq))]
15016#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15017pub fn _mm256_mask_cvttph_epu32(src: __m256i, k: __mmask8, a: __m128h) -> __m256i {
15018    unsafe { transmute(vcvttph2udq_256(a, src.as_u32x8(), k)) }
15019}
15020
15021/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit unsigned integers with truncation, and
15022/// store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
15023///
15024/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_cvttph_epu32)
15025#[inline]
15026#[target_feature(enable = "avx512fp16,avx512vl")]
15027#[cfg_attr(test, assert_instr(vcvttph2udq))]
15028#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15029pub fn _mm256_maskz_cvttph_epu32(k: __mmask8, a: __m128h) -> __m256i {
15030    _mm256_mask_cvttph_epu32(_mm256_setzero_si256(), k, a)
15031}
15032
15033/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit unsigned integers with truncation, and
15034/// store the results in dst.
15035///
15036/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvttph_epu32)
15037#[inline]
15038#[target_feature(enable = "avx512fp16")]
15039#[cfg_attr(test, assert_instr(vcvttph2udq))]
15040#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15041pub fn _mm512_cvttph_epu32(a: __m256h) -> __m512i {
15042    _mm512_mask_cvttph_epu32(_mm512_undefined_epi32(), 0xffff, a)
15043}
15044
15045/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit unsigned integers with truncation, and
15046/// store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
15047///
15048/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvttph_epu32)
15049#[inline]
15050#[target_feature(enable = "avx512fp16")]
15051#[cfg_attr(test, assert_instr(vcvttph2udq))]
15052#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15053pub fn _mm512_mask_cvttph_epu32(src: __m512i, k: __mmask16, a: __m256h) -> __m512i {
15054    unsafe {
15055        transmute(vcvttph2udq_512(
15056            a,
15057            src.as_u32x16(),
15058            k,
15059            _MM_FROUND_CUR_DIRECTION,
15060        ))
15061    }
15062}
15063
15064/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit unsigned integers with truncation, and
15065/// store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
15066///
15067/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvttph_epu32)
15068#[inline]
15069#[target_feature(enable = "avx512fp16")]
15070#[cfg_attr(test, assert_instr(vcvttph2udq))]
15071#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15072pub fn _mm512_maskz_cvttph_epu32(k: __mmask16, a: __m256h) -> __m512i {
15073    _mm512_mask_cvttph_epu32(_mm512_setzero_si512(), k, a)
15074}
15075
15076/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit unsigned integers with truncation, and
15077/// store the results in dst.
15078///
15079/// Exceptions can be suppressed by passing `_MM_FROUND_NO_EXC` in the `sae` parameter.
15080///
15081/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtt_roundph_epu32)
15082#[inline]
15083#[target_feature(enable = "avx512fp16")]
15084#[cfg_attr(test, assert_instr(vcvttph2udq, SAE = 8))]
15085#[rustc_legacy_const_generics(1)]
15086#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15087pub fn _mm512_cvtt_roundph_epu32<const SAE: i32>(a: __m256h) -> __m512i {
15088    static_assert_sae!(SAE);
15089    _mm512_mask_cvtt_roundph_epu32::<SAE>(_mm512_undefined_epi32(), 0xffff, a)
15090}
15091
15092/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit unsigned integers with truncation, and
15093/// store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
15094///
15095/// Exceptions can be suppressed by passing `_MM_FROUND_NO_EXC` in the `sae` parameter.
15096///
15097/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtt_roundph_epu32)
15098#[inline]
15099#[target_feature(enable = "avx512fp16")]
15100#[cfg_attr(test, assert_instr(vcvttph2udq, SAE = 8))]
15101#[rustc_legacy_const_generics(3)]
15102#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15103pub fn _mm512_mask_cvtt_roundph_epu32<const SAE: i32>(
15104    src: __m512i,
15105    k: __mmask16,
15106    a: __m256h,
15107) -> __m512i {
15108    unsafe {
15109        static_assert_sae!(SAE);
15110        transmute(vcvttph2udq_512(a, src.as_u32x16(), k, SAE))
15111    }
15112}
15113
15114/// Convert packed half-precision (16-bit) floating-point elements in a to packed 32-bit unsigned integers with truncation, and
15115/// store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
15116///
15117/// Exceptions can be suppressed by passing `_MM_FROUND_NO_EXC` in the `sae` parameter.
15118///
15119/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtt_roundph_epu32)
15120#[inline]
15121#[target_feature(enable = "avx512fp16")]
15122#[cfg_attr(test, assert_instr(vcvttph2udq, SAE = 8))]
15123#[rustc_legacy_const_generics(2)]
15124#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15125pub fn _mm512_maskz_cvtt_roundph_epu32<const SAE: i32>(k: __mmask16, a: __m256h) -> __m512i {
15126    static_assert_sae!(SAE);
15127    _mm512_mask_cvtt_roundph_epu32::<SAE>(_mm512_setzero_si512(), k, a)
15128}
15129
15130/// Convert the lower half-precision (16-bit) floating-point element in a to a 32-bit unsigned integer with truncation, and store
15131/// the result in dst.
15132///
15133/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvttsh_u32)
15134#[inline]
15135#[target_feature(enable = "avx512fp16")]
15136#[cfg_attr(test, assert_instr(vcvttsh2usi))]
15137#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15138pub fn _mm_cvttsh_u32(a: __m128h) -> u32 {
15139    unsafe { vcvttsh2usi32(a, _MM_FROUND_CUR_DIRECTION) }
15140}
15141
15142/// Convert the lower half-precision (16-bit) floating-point element in a to a 32-bit unsigned integer with truncation, and store
15143/// the result in dst.
15144///
15145/// Exceptions can be suppressed by passing `_MM_FROUND_NO_EXC` in the `sae` parameter.
15146///
15147/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtt_roundsh_u32)
15148#[inline]
15149#[target_feature(enable = "avx512fp16")]
15150#[cfg_attr(test, assert_instr(vcvttsh2usi, SAE = 8))]
15151#[rustc_legacy_const_generics(1)]
15152#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15153pub fn _mm_cvtt_roundsh_u32<const SAE: i32>(a: __m128h) -> u32 {
15154    unsafe {
15155        static_assert_sae!(SAE);
15156        vcvttsh2usi32(a, SAE)
15157    }
15158}
15159
15160/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit integers, and
15161/// store the results in dst.
15162///
15163/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtph_epi64)
15164#[inline]
15165#[target_feature(enable = "avx512fp16,avx512vl")]
15166#[cfg_attr(test, assert_instr(vcvtph2qq))]
15167#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15168pub fn _mm_cvtph_epi64(a: __m128h) -> __m128i {
15169    _mm_mask_cvtph_epi64(_mm_undefined_si128(), 0xff, a)
15170}
15171
15172/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit integers, and
15173/// store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
15174///
15175/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cvtph_epi64)
15176#[inline]
15177#[target_feature(enable = "avx512fp16,avx512vl")]
15178#[cfg_attr(test, assert_instr(vcvtph2qq))]
15179#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15180pub fn _mm_mask_cvtph_epi64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
15181    unsafe { transmute(vcvtph2qq_128(a, src.as_i64x2(), k)) }
15182}
15183
15184/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit integers, and
15185/// store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
15186///
15187/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_cvtph_epi64)
15188#[inline]
15189#[target_feature(enable = "avx512fp16,avx512vl")]
15190#[cfg_attr(test, assert_instr(vcvtph2qq))]
15191#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15192pub fn _mm_maskz_cvtph_epi64(k: __mmask8, a: __m128h) -> __m128i {
15193    _mm_mask_cvtph_epi64(_mm_setzero_si128(), k, a)
15194}
15195
15196/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit integers, and
15197/// store the results in dst.
15198///
15199/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtph_epi64)
15200#[inline]
15201#[target_feature(enable = "avx512fp16,avx512vl")]
15202#[cfg_attr(test, assert_instr(vcvtph2qq))]
15203#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15204pub fn _mm256_cvtph_epi64(a: __m128h) -> __m256i {
15205    _mm256_mask_cvtph_epi64(_mm256_undefined_si256(), 0xff, a)
15206}
15207
15208/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit integers, and
15209/// store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
15210///
15211/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_cvtph_epi64)
15212#[inline]
15213#[target_feature(enable = "avx512fp16,avx512vl")]
15214#[cfg_attr(test, assert_instr(vcvtph2qq))]
15215#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15216pub fn _mm256_mask_cvtph_epi64(src: __m256i, k: __mmask8, a: __m128h) -> __m256i {
15217    unsafe { transmute(vcvtph2qq_256(a, src.as_i64x4(), k)) }
15218}
15219
15220/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit integers, and
15221/// store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
15222///
15223/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_cvtph_epi64)
15224#[inline]
15225#[target_feature(enable = "avx512fp16,avx512vl")]
15226#[cfg_attr(test, assert_instr(vcvtph2qq))]
15227#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15228pub fn _mm256_maskz_cvtph_epi64(k: __mmask8, a: __m128h) -> __m256i {
15229    _mm256_mask_cvtph_epi64(_mm256_setzero_si256(), k, a)
15230}
15231
15232/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit integers, and
15233/// store the results in dst.
15234///
15235/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtph_epi64)
15236#[inline]
15237#[target_feature(enable = "avx512fp16")]
15238#[cfg_attr(test, assert_instr(vcvtph2qq))]
15239#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15240pub fn _mm512_cvtph_epi64(a: __m128h) -> __m512i {
15241    _mm512_mask_cvtph_epi64(_mm512_undefined_epi32(), 0xff, a)
15242}
15243
15244/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit integers, and
15245/// store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
15246///
15247/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtph_epi64)
15248#[inline]
15249#[target_feature(enable = "avx512fp16")]
15250#[cfg_attr(test, assert_instr(vcvtph2qq))]
15251#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15252pub fn _mm512_mask_cvtph_epi64(src: __m512i, k: __mmask8, a: __m128h) -> __m512i {
15253    unsafe {
15254        transmute(vcvtph2qq_512(
15255            a,
15256            src.as_i64x8(),
15257            k,
15258            _MM_FROUND_CUR_DIRECTION,
15259        ))
15260    }
15261}
15262
15263/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit integers, and
15264/// store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
15265///
15266/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtph_epi64)
15267#[inline]
15268#[target_feature(enable = "avx512fp16")]
15269#[cfg_attr(test, assert_instr(vcvtph2qq))]
15270#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15271pub fn _mm512_maskz_cvtph_epi64(k: __mmask8, a: __m128h) -> __m512i {
15272    _mm512_mask_cvtph_epi64(_mm512_setzero_si512(), k, a)
15273}
15274
15275/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit integers, and
15276/// store the results in dst.
15277///
15278/// Rounding is done according to the rounding parameter, which can be one of:
15279///
15280/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
15281/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
15282/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
15283/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
15284/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
15285///
15286/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvt_roundph_epi64)
15287#[inline]
15288#[target_feature(enable = "avx512fp16")]
15289#[cfg_attr(test, assert_instr(vcvtph2qq, ROUNDING = 8))]
15290#[rustc_legacy_const_generics(1)]
15291#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15292pub fn _mm512_cvt_roundph_epi64<const ROUNDING: i32>(a: __m128h) -> __m512i {
15293    static_assert_rounding!(ROUNDING);
15294    _mm512_mask_cvt_roundph_epi64::<ROUNDING>(_mm512_undefined_epi32(), 0xff, a)
15295}
15296
15297/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit integers, and
15298/// store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
15299///
15300/// Rounding is done according to the rounding parameter, which can be one of:
15301///
15302/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
15303/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
15304/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
15305/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
15306/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
15307///
15308/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvt_roundph_epi64)
15309#[inline]
15310#[target_feature(enable = "avx512fp16")]
15311#[cfg_attr(test, assert_instr(vcvtph2qq, ROUNDING = 8))]
15312#[rustc_legacy_const_generics(3)]
15313#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15314pub fn _mm512_mask_cvt_roundph_epi64<const ROUNDING: i32>(
15315    src: __m512i,
15316    k: __mmask8,
15317    a: __m128h,
15318) -> __m512i {
15319    unsafe {
15320        static_assert_rounding!(ROUNDING);
15321        transmute(vcvtph2qq_512(a, src.as_i64x8(), k, ROUNDING))
15322    }
15323}
15324
15325/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit integers, and
15326/// store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
15327///
15328/// Rounding is done according to the rounding parameter, which can be one of:
15329///
15330/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
15331/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
15332/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
15333/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
15334/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
15335///
15336/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvt_roundph_epi64)
15337#[inline]
15338#[target_feature(enable = "avx512fp16")]
15339#[cfg_attr(test, assert_instr(vcvtph2qq, ROUNDING = 8))]
15340#[rustc_legacy_const_generics(2)]
15341#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15342pub fn _mm512_maskz_cvt_roundph_epi64<const ROUNDING: i32>(k: __mmask8, a: __m128h) -> __m512i {
15343    static_assert_rounding!(ROUNDING);
15344    _mm512_mask_cvt_roundph_epi64::<ROUNDING>(_mm512_setzero_si512(), k, a)
15345}
15346
15347/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit unsigned integers, and
15348/// store the results in dst.
15349///
15350/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtph_epu64)
15351#[inline]
15352#[target_feature(enable = "avx512fp16,avx512vl")]
15353#[cfg_attr(test, assert_instr(vcvtph2uqq))]
15354#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15355pub fn _mm_cvtph_epu64(a: __m128h) -> __m128i {
15356    _mm_mask_cvtph_epu64(_mm_undefined_si128(), 0xff, a)
15357}
15358
15359/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit unsigned integers, and
15360/// store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
15361///
15362/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cvtph_epu64)
15363#[inline]
15364#[target_feature(enable = "avx512fp16,avx512vl")]
15365#[cfg_attr(test, assert_instr(vcvtph2uqq))]
15366#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15367pub fn _mm_mask_cvtph_epu64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
15368    unsafe { transmute(vcvtph2uqq_128(a, src.as_u64x2(), k)) }
15369}
15370
15371/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit unsigned integers, and
15372/// store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
15373///
15374/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_cvtph_epu64)
15375#[inline]
15376#[target_feature(enable = "avx512fp16,avx512vl")]
15377#[cfg_attr(test, assert_instr(vcvtph2uqq))]
15378#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15379pub fn _mm_maskz_cvtph_epu64(k: __mmask8, a: __m128h) -> __m128i {
15380    _mm_mask_cvtph_epu64(_mm_setzero_si128(), k, a)
15381}
15382
15383/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit unsigned integers, and
15384/// store the results in dst.
15385///
15386/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtph_epu64)
15387#[inline]
15388#[target_feature(enable = "avx512fp16,avx512vl")]
15389#[cfg_attr(test, assert_instr(vcvtph2uqq))]
15390#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15391pub fn _mm256_cvtph_epu64(a: __m128h) -> __m256i {
15392    _mm256_mask_cvtph_epu64(_mm256_undefined_si256(), 0xff, a)
15393}
15394
15395/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit unsigned integers, and
15396/// store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
15397///
15398/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_cvtph_epu64)
15399#[inline]
15400#[target_feature(enable = "avx512fp16,avx512vl")]
15401#[cfg_attr(test, assert_instr(vcvtph2uqq))]
15402#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15403pub fn _mm256_mask_cvtph_epu64(src: __m256i, k: __mmask8, a: __m128h) -> __m256i {
15404    unsafe { transmute(vcvtph2uqq_256(a, src.as_u64x4(), k)) }
15405}
15406
15407/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit unsigned integers, and
15408/// store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
15409///
15410/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_cvtph_epu64)
15411#[inline]
15412#[target_feature(enable = "avx512fp16,avx512vl")]
15413#[cfg_attr(test, assert_instr(vcvtph2uqq))]
15414#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15415pub fn _mm256_maskz_cvtph_epu64(k: __mmask8, a: __m128h) -> __m256i {
15416    _mm256_mask_cvtph_epu64(_mm256_setzero_si256(), k, a)
15417}
15418
15419/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit unsigned integers, and
15420/// store the results in dst.
15421///
15422/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtph_epu64)
15423#[inline]
15424#[target_feature(enable = "avx512fp16")]
15425#[cfg_attr(test, assert_instr(vcvtph2uqq))]
15426#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15427pub fn _mm512_cvtph_epu64(a: __m128h) -> __m512i {
15428    _mm512_mask_cvtph_epu64(_mm512_undefined_epi32(), 0xff, a)
15429}
15430
15431/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit unsigned integers, and
15432/// store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
15433///
15434/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtph_epu64)
15435#[inline]
15436#[target_feature(enable = "avx512fp16")]
15437#[cfg_attr(test, assert_instr(vcvtph2uqq))]
15438#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15439pub fn _mm512_mask_cvtph_epu64(src: __m512i, k: __mmask8, a: __m128h) -> __m512i {
15440    unsafe {
15441        transmute(vcvtph2uqq_512(
15442            a,
15443            src.as_u64x8(),
15444            k,
15445            _MM_FROUND_CUR_DIRECTION,
15446        ))
15447    }
15448}
15449
15450/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit unsigned integers, and
15451/// store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
15452///
15453/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtph_epu64)
15454#[inline]
15455#[target_feature(enable = "avx512fp16")]
15456#[cfg_attr(test, assert_instr(vcvtph2uqq))]
15457#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15458pub fn _mm512_maskz_cvtph_epu64(k: __mmask8, a: __m128h) -> __m512i {
15459    _mm512_mask_cvtph_epu64(_mm512_setzero_si512(), k, a)
15460}
15461
15462/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit unsigned integers, and
15463/// store the results in dst.
15464///
15465/// Rounding is done according to the rounding parameter, which can be one of:
15466///
15467/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
15468/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
15469/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
15470/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
15471/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
15472///
15473/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvt_roundph_epu64)
15474#[inline]
15475#[target_feature(enable = "avx512fp16")]
15476#[cfg_attr(test, assert_instr(vcvtph2uqq, ROUNDING = 8))]
15477#[rustc_legacy_const_generics(1)]
15478#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15479pub fn _mm512_cvt_roundph_epu64<const ROUNDING: i32>(a: __m128h) -> __m512i {
15480    static_assert_rounding!(ROUNDING);
15481    _mm512_mask_cvt_roundph_epu64::<ROUNDING>(_mm512_undefined_epi32(), 0xff, a)
15482}
15483
15484/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit unsigned integers, and
15485/// store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
15486///
15487/// Rounding is done according to the rounding parameter, which can be one of:
15488///
15489/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
15490/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
15491/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
15492/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
15493/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
15494///
15495/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvt_roundph_epu64)
15496#[inline]
15497#[target_feature(enable = "avx512fp16")]
15498#[cfg_attr(test, assert_instr(vcvtph2uqq, ROUNDING = 8))]
15499#[rustc_legacy_const_generics(3)]
15500#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15501pub fn _mm512_mask_cvt_roundph_epu64<const ROUNDING: i32>(
15502    src: __m512i,
15503    k: __mmask8,
15504    a: __m128h,
15505) -> __m512i {
15506    unsafe {
15507        static_assert_rounding!(ROUNDING);
15508        transmute(vcvtph2uqq_512(a, src.as_u64x8(), k, ROUNDING))
15509    }
15510}
15511
15512/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit unsigned integers, and
15513/// store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
15514///
15515/// Rounding is done according to the rounding parameter, which can be one of:
15516///
15517/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
15518/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
15519/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
15520/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
15521/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
15522///
15523/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvt_roundph_epu64)
15524#[inline]
15525#[target_feature(enable = "avx512fp16")]
15526#[cfg_attr(test, assert_instr(vcvtph2uqq, ROUNDING = 8))]
15527#[rustc_legacy_const_generics(2)]
15528#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15529pub fn _mm512_maskz_cvt_roundph_epu64<const ROUNDING: i32>(k: __mmask8, a: __m128h) -> __m512i {
15530    static_assert_rounding!(ROUNDING);
15531    _mm512_mask_cvt_roundph_epu64::<ROUNDING>(_mm512_setzero_si512(), k, a)
15532}
15533
15534/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit integers with truncation, and
15535/// store the results in dst.
15536///
15537/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvttph_epi64)
15538#[inline]
15539#[target_feature(enable = "avx512fp16,avx512vl")]
15540#[cfg_attr(test, assert_instr(vcvttph2qq))]
15541#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15542pub fn _mm_cvttph_epi64(a: __m128h) -> __m128i {
15543    _mm_mask_cvttph_epi64(_mm_undefined_si128(), 0xff, a)
15544}
15545
15546/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit integers with truncation, and
15547/// store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
15548///
15549/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cvttph_epi64)
15550#[inline]
15551#[target_feature(enable = "avx512fp16,avx512vl")]
15552#[cfg_attr(test, assert_instr(vcvttph2qq))]
15553#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15554pub fn _mm_mask_cvttph_epi64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
15555    unsafe { transmute(vcvttph2qq_128(a, src.as_i64x2(), k)) }
15556}
15557
15558/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit integers with truncation, and
15559/// store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
15560///
15561/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_cvttph_epi64)
15562#[inline]
15563#[target_feature(enable = "avx512fp16,avx512vl")]
15564#[cfg_attr(test, assert_instr(vcvttph2qq))]
15565#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15566pub fn _mm_maskz_cvttph_epi64(k: __mmask8, a: __m128h) -> __m128i {
15567    _mm_mask_cvttph_epi64(_mm_setzero_si128(), k, a)
15568}
15569
15570/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit integers with truncation, and
15571/// store the results in dst.
15572///
15573/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvttph_epi64)
15574#[inline]
15575#[target_feature(enable = "avx512fp16,avx512vl")]
15576#[cfg_attr(test, assert_instr(vcvttph2qq))]
15577#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15578pub fn _mm256_cvttph_epi64(a: __m128h) -> __m256i {
15579    _mm256_mask_cvttph_epi64(_mm256_undefined_si256(), 0xff, a)
15580}
15581
15582/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit integers with truncation, and
15583/// store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
15584///
15585/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_cvttph_epi64)
15586#[inline]
15587#[target_feature(enable = "avx512fp16,avx512vl")]
15588#[cfg_attr(test, assert_instr(vcvttph2qq))]
15589#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15590pub fn _mm256_mask_cvttph_epi64(src: __m256i, k: __mmask8, a: __m128h) -> __m256i {
15591    unsafe { transmute(vcvttph2qq_256(a, src.as_i64x4(), k)) }
15592}
15593
15594/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit integers with truncation, and
15595/// store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
15596///
15597/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_cvttph_epi64)
15598#[inline]
15599#[target_feature(enable = "avx512fp16,avx512vl")]
15600#[cfg_attr(test, assert_instr(vcvttph2qq))]
15601#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15602pub fn _mm256_maskz_cvttph_epi64(k: __mmask8, a: __m128h) -> __m256i {
15603    _mm256_mask_cvttph_epi64(_mm256_setzero_si256(), k, a)
15604}
15605
15606/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit integers with truncation, and
15607/// store the results in dst.
15608///
15609/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvttph_epi64)
15610#[inline]
15611#[target_feature(enable = "avx512fp16")]
15612#[cfg_attr(test, assert_instr(vcvttph2qq))]
15613#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15614pub fn _mm512_cvttph_epi64(a: __m128h) -> __m512i {
15615    _mm512_mask_cvttph_epi64(_mm512_undefined_epi32(), 0xff, a)
15616}
15617
15618/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit integers with truncation, and
15619/// store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
15620///
15621/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvttph_epi64)
15622#[inline]
15623#[target_feature(enable = "avx512fp16")]
15624#[cfg_attr(test, assert_instr(vcvttph2qq))]
15625#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15626pub fn _mm512_mask_cvttph_epi64(src: __m512i, k: __mmask8, a: __m128h) -> __m512i {
15627    unsafe {
15628        transmute(vcvttph2qq_512(
15629            a,
15630            src.as_i64x8(),
15631            k,
15632            _MM_FROUND_CUR_DIRECTION,
15633        ))
15634    }
15635}
15636
15637/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit integers with truncation, and
15638/// store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
15639///
15640/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvttph_epi64)
15641#[inline]
15642#[target_feature(enable = "avx512fp16")]
15643#[cfg_attr(test, assert_instr(vcvttph2qq))]
15644#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15645pub fn _mm512_maskz_cvttph_epi64(k: __mmask8, a: __m128h) -> __m512i {
15646    _mm512_mask_cvttph_epi64(_mm512_setzero_si512(), k, a)
15647}
15648
15649/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit integers with truncation, and
15650/// store the results in dst.
15651///
15652/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
15653///
15654/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtt_roundph_epi64)
15655#[inline]
15656#[target_feature(enable = "avx512fp16")]
15657#[cfg_attr(test, assert_instr(vcvttph2qq, SAE = 8))]
15658#[rustc_legacy_const_generics(1)]
15659#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15660pub fn _mm512_cvtt_roundph_epi64<const SAE: i32>(a: __m128h) -> __m512i {
15661    static_assert_sae!(SAE);
15662    _mm512_mask_cvtt_roundph_epi64::<SAE>(_mm512_undefined_epi32(), 0xff, a)
15663}
15664
15665/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit integers with truncation, and
15666/// store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
15667///
15668/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
15669///
15670/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtt_roundph_epi64)
15671#[inline]
15672#[target_feature(enable = "avx512fp16")]
15673#[cfg_attr(test, assert_instr(vcvttph2qq, SAE = 8))]
15674#[rustc_legacy_const_generics(3)]
15675#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15676pub fn _mm512_mask_cvtt_roundph_epi64<const SAE: i32>(
15677    src: __m512i,
15678    k: __mmask8,
15679    a: __m128h,
15680) -> __m512i {
15681    unsafe {
15682        static_assert_sae!(SAE);
15683        transmute(vcvttph2qq_512(a, src.as_i64x8(), k, SAE))
15684    }
15685}
15686
15687/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit integers with truncation, and
15688/// store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
15689///
15690/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
15691///
15692/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtt_roundph_epi64)
15693#[inline]
15694#[target_feature(enable = "avx512fp16")]
15695#[cfg_attr(test, assert_instr(vcvttph2qq, SAE = 8))]
15696#[rustc_legacy_const_generics(2)]
15697#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15698pub fn _mm512_maskz_cvtt_roundph_epi64<const SAE: i32>(k: __mmask8, a: __m128h) -> __m512i {
15699    static_assert_sae!(SAE);
15700    _mm512_mask_cvtt_roundph_epi64::<SAE>(_mm512_setzero_si512(), k, a)
15701}
15702
15703/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit unsigned integers with truncation, and
15704/// store the results in dst.
15705///
15706/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvttph_epu64)
15707#[inline]
15708#[target_feature(enable = "avx512fp16,avx512vl")]
15709#[cfg_attr(test, assert_instr(vcvttph2uqq))]
15710#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15711pub fn _mm_cvttph_epu64(a: __m128h) -> __m128i {
15712    _mm_mask_cvttph_epu64(_mm_undefined_si128(), 0xff, a)
15713}
15714
15715/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit unsigned integers with truncation, and
15716/// store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
15717///
15718/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cvttph_epu64)
15719#[inline]
15720#[target_feature(enable = "avx512fp16,avx512vl")]
15721#[cfg_attr(test, assert_instr(vcvttph2uqq))]
15722#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15723pub fn _mm_mask_cvttph_epu64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
15724    unsafe { transmute(vcvttph2uqq_128(a, src.as_u64x2(), k)) }
15725}
15726
15727/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit unsigned integers with truncation, and
15728/// store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
15729///
15730/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_cvttph_epu64)
15731#[inline]
15732#[target_feature(enable = "avx512fp16,avx512vl")]
15733#[cfg_attr(test, assert_instr(vcvttph2uqq))]
15734#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15735pub fn _mm_maskz_cvttph_epu64(k: __mmask8, a: __m128h) -> __m128i {
15736    _mm_mask_cvttph_epu64(_mm_setzero_si128(), k, a)
15737}
15738
15739/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit unsigned integers with truncation, and
15740/// store the results in dst.
15741///
15742/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvttph_epu64)
15743#[inline]
15744#[target_feature(enable = "avx512fp16,avx512vl")]
15745#[cfg_attr(test, assert_instr(vcvttph2uqq))]
15746#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15747pub fn _mm256_cvttph_epu64(a: __m128h) -> __m256i {
15748    _mm256_mask_cvttph_epu64(_mm256_undefined_si256(), 0xff, a)
15749}
15750
15751/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit unsigned integers with truncation, and
15752/// store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
15753///
15754/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_cvttph_epu64)
15755#[inline]
15756#[target_feature(enable = "avx512fp16,avx512vl")]
15757#[cfg_attr(test, assert_instr(vcvttph2uqq))]
15758#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15759pub fn _mm256_mask_cvttph_epu64(src: __m256i, k: __mmask8, a: __m128h) -> __m256i {
15760    unsafe { transmute(vcvttph2uqq_256(a, src.as_u64x4(), k)) }
15761}
15762
15763/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit unsigned integers with truncation, and
15764/// store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
15765///
15766/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_cvttph_epu64)
15767#[inline]
15768#[target_feature(enable = "avx512fp16,avx512vl")]
15769#[cfg_attr(test, assert_instr(vcvttph2uqq))]
15770#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15771pub fn _mm256_maskz_cvttph_epu64(k: __mmask8, a: __m128h) -> __m256i {
15772    _mm256_mask_cvttph_epu64(_mm256_setzero_si256(), k, a)
15773}
15774
15775/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit unsigned integers with truncation, and
15776/// store the results in dst.
15777///
15778/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvttph_epu64)
15779#[inline]
15780#[target_feature(enable = "avx512fp16")]
15781#[cfg_attr(test, assert_instr(vcvttph2uqq))]
15782#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15783pub fn _mm512_cvttph_epu64(a: __m128h) -> __m512i {
15784    _mm512_mask_cvttph_epu64(_mm512_undefined_epi32(), 0xff, a)
15785}
15786
15787/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit unsigned integers with truncation, and
15788/// store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
15789///
15790/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvttph_epu64)
15791#[inline]
15792#[target_feature(enable = "avx512fp16")]
15793#[cfg_attr(test, assert_instr(vcvttph2uqq))]
15794#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15795pub fn _mm512_mask_cvttph_epu64(src: __m512i, k: __mmask8, a: __m128h) -> __m512i {
15796    unsafe {
15797        transmute(vcvttph2uqq_512(
15798            a,
15799            src.as_u64x8(),
15800            k,
15801            _MM_FROUND_CUR_DIRECTION,
15802        ))
15803    }
15804}
15805
15806/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit unsigned integers with truncation, and
15807/// store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
15808///
15809/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvttph_epu64)
15810#[inline]
15811#[target_feature(enable = "avx512fp16")]
15812#[cfg_attr(test, assert_instr(vcvttph2uqq))]
15813#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15814pub fn _mm512_maskz_cvttph_epu64(k: __mmask8, a: __m128h) -> __m512i {
15815    _mm512_mask_cvttph_epu64(_mm512_setzero_si512(), k, a)
15816}
15817
15818/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit unsigned integers with truncation, and
15819/// store the results in dst.
15820///
15821/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
15822///
15823/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtt_roundph_epu64)
15824#[inline]
15825#[target_feature(enable = "avx512fp16")]
15826#[cfg_attr(test, assert_instr(vcvttph2uqq, SAE = 8))]
15827#[rustc_legacy_const_generics(1)]
15828#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15829pub fn _mm512_cvtt_roundph_epu64<const SAE: i32>(a: __m128h) -> __m512i {
15830    static_assert_sae!(SAE);
15831    _mm512_mask_cvtt_roundph_epu64::<SAE>(_mm512_undefined_epi32(), 0xff, a)
15832}
15833
15834/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit unsigned integers with truncation, and
15835/// store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
15836///
15837/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
15838///
15839/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtt_roundph_epu64)
15840#[inline]
15841#[target_feature(enable = "avx512fp16")]
15842#[cfg_attr(test, assert_instr(vcvttph2uqq, SAE = 8))]
15843#[rustc_legacy_const_generics(3)]
15844#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15845pub fn _mm512_mask_cvtt_roundph_epu64<const SAE: i32>(
15846    src: __m512i,
15847    k: __mmask8,
15848    a: __m128h,
15849) -> __m512i {
15850    unsafe {
15851        static_assert_sae!(SAE);
15852        transmute(vcvttph2uqq_512(a, src.as_u64x8(), k, SAE))
15853    }
15854}
15855
15856/// Convert packed half-precision (16-bit) floating-point elements in a to packed 64-bit unsigned integers with truncation, and
15857/// store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
15858///
15859/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
15860///
15861/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtt_roundph_epu64)
15862#[inline]
15863#[target_feature(enable = "avx512fp16")]
15864#[cfg_attr(test, assert_instr(vcvttph2uqq, SAE = 8))]
15865#[rustc_legacy_const_generics(2)]
15866#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15867pub fn _mm512_maskz_cvtt_roundph_epu64<const SAE: i32>(k: __mmask8, a: __m128h) -> __m512i {
15868    static_assert_sae!(SAE);
15869    _mm512_mask_cvtt_roundph_epu64::<SAE>(_mm512_setzero_si512(), k, a)
15870}
15871
15872/// Convert packed half-precision (16-bit) floating-point elements in a to packed single-precision (32-bit)
15873/// floating-point elements, and store the results in dst.
15874///
15875/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtxph_ps)
15876#[inline]
15877#[target_feature(enable = "avx512fp16,avx512vl")]
15878#[cfg_attr(test, assert_instr(vcvtph2psx))]
15879#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15880pub fn _mm_cvtxph_ps(a: __m128h) -> __m128 {
15881    _mm_mask_cvtxph_ps(_mm_setzero_ps(), 0xff, a)
15882}
15883
15884/// Convert packed half-precision (16-bit) floating-point elements in a to packed single-precision (32-bit)
15885/// floating-point elements, and store the results in dst using writemask k (elements are copied from src to
15886/// dst when the corresponding mask bit is not set).
15887///
15888/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cvtxph_ps)
15889#[inline]
15890#[target_feature(enable = "avx512fp16,avx512vl")]
15891#[cfg_attr(test, assert_instr(vcvtph2psx))]
15892#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15893pub fn _mm_mask_cvtxph_ps(src: __m128, k: __mmask8, a: __m128h) -> __m128 {
15894    unsafe { vcvtph2psx_128(a, src, k) }
15895}
15896
15897/// Convert packed half-precision (16-bit) floating-point elements in a to packed single-precision (32-bit)
15898/// floating-point elements, and store the results in dst using zeromask k (elements are zeroed out when the
15899/// corresponding mask bit is not set).
15900///
15901/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_cvtxph_ps)
15902#[inline]
15903#[target_feature(enable = "avx512fp16,avx512vl")]
15904#[cfg_attr(test, assert_instr(vcvtph2psx))]
15905#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15906pub fn _mm_maskz_cvtxph_ps(k: __mmask8, a: __m128h) -> __m128 {
15907    _mm_mask_cvtxph_ps(_mm_setzero_ps(), k, a)
15908}
15909
15910/// Convert packed half-precision (16-bit) floating-point elements in a to packed single-precision (32-bit)
15911/// floating-point elements, and store the results in dst.
15912///
15913/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtxph_ps)
15914#[inline]
15915#[target_feature(enable = "avx512fp16,avx512vl")]
15916#[cfg_attr(test, assert_instr(vcvtph2psx))]
15917#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15918pub fn _mm256_cvtxph_ps(a: __m128h) -> __m256 {
15919    _mm256_mask_cvtxph_ps(_mm256_setzero_ps(), 0xff, a)
15920}
15921
15922/// Convert packed half-precision (16-bit) floating-point elements in a to packed single-precision (32-bit)
15923/// floating-point elements, and store the results in dst using writemask k (elements are copied from src to
15924/// dst when the corresponding mask bit is not set).
15925///
15926/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_cvtxph_ps)
15927#[inline]
15928#[target_feature(enable = "avx512fp16,avx512vl")]
15929#[cfg_attr(test, assert_instr(vcvtph2psx))]
15930#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15931pub fn _mm256_mask_cvtxph_ps(src: __m256, k: __mmask8, a: __m128h) -> __m256 {
15932    unsafe { vcvtph2psx_256(a, src, k) }
15933}
15934
15935/// Convert packed half-precision (16-bit) floating-point elements in a to packed single-precision (32-bit)
15936/// floating-point elements, and store the results in dst using zeromask k (elements are zeroed out when the
15937/// corresponding mask bit is not set).
15938///
15939/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_cvtxph_ps)
15940#[inline]
15941#[target_feature(enable = "avx512fp16,avx512vl")]
15942#[cfg_attr(test, assert_instr(vcvtph2psx))]
15943#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15944pub fn _mm256_maskz_cvtxph_ps(k: __mmask8, a: __m128h) -> __m256 {
15945    _mm256_mask_cvtxph_ps(_mm256_setzero_ps(), k, a)
15946}
15947
15948/// Convert packed half-precision (16-bit) floating-point elements in a to packed single-precision (32-bit)
15949/// floating-point elements, and store the results in dst.
15950///
15951/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtxph_ps)
15952#[inline]
15953#[target_feature(enable = "avx512fp16")]
15954#[cfg_attr(test, assert_instr(vcvtph2psx))]
15955#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15956pub fn _mm512_cvtxph_ps(a: __m256h) -> __m512 {
15957    _mm512_mask_cvtxph_ps(_mm512_setzero_ps(), 0xffff, a)
15958}
15959
15960/// Convert packed half-precision (16-bit) floating-point elements in a to packed single-precision (32-bit)
15961/// floating-point elements, and store the results in dst using writemask k (elements are copied from src to
15962/// dst when the corresponding mask bit is not set).
15963///
15964/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtxph_ps)
15965#[inline]
15966#[target_feature(enable = "avx512fp16")]
15967#[cfg_attr(test, assert_instr(vcvtph2psx))]
15968#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15969pub fn _mm512_mask_cvtxph_ps(src: __m512, k: __mmask16, a: __m256h) -> __m512 {
15970    unsafe { vcvtph2psx_512(a, src, k, _MM_FROUND_CUR_DIRECTION) }
15971}
15972
15973/// Convert packed half-precision (16-bit) floating-point elements in a to packed single-precision (32-bit)
15974/// floating-point elements, and store the results in dst using zeromask k (elements are zeroed out when the
15975/// corresponding mask bit is not set).
15976///
15977/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtxph_ps)
15978#[inline]
15979#[target_feature(enable = "avx512fp16")]
15980#[cfg_attr(test, assert_instr(vcvtph2psx))]
15981#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15982pub fn _mm512_maskz_cvtxph_ps(k: __mmask16, a: __m256h) -> __m512 {
15983    _mm512_mask_cvtxph_ps(_mm512_setzero_ps(), k, a)
15984}
15985
15986/// Convert packed half-precision (16-bit) floating-point elements in a to packed single-precision (32-bit)
15987/// floating-point elements, and store the results in dst.
15988///
15989/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
15990///
15991/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtx_roundph_ps)
15992#[inline]
15993#[target_feature(enable = "avx512fp16")]
15994#[cfg_attr(test, assert_instr(vcvtph2psx, SAE = 8))]
15995#[rustc_legacy_const_generics(1)]
15996#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
15997pub fn _mm512_cvtx_roundph_ps<const SAE: i32>(a: __m256h) -> __m512 {
15998    static_assert_sae!(SAE);
15999    _mm512_mask_cvtx_roundph_ps::<SAE>(_mm512_setzero_ps(), 0xffff, a)
16000}
16001
16002/// Convert packed half-precision (16-bit) floating-point elements in a to packed single-precision (32-bit)
16003/// floating-point elements, and store the results in dst using writemask k (elements are copied from src to
16004/// dst when the corresponding mask bit is not set).
16005///
16006/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
16007///
16008/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtx_roundph_ps)
16009#[inline]
16010#[target_feature(enable = "avx512fp16")]
16011#[cfg_attr(test, assert_instr(vcvtph2psx, SAE = 8))]
16012#[rustc_legacy_const_generics(3)]
16013#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
16014pub fn _mm512_mask_cvtx_roundph_ps<const SAE: i32>(
16015    src: __m512,
16016    k: __mmask16,
16017    a: __m256h,
16018) -> __m512 {
16019    unsafe {
16020        static_assert_sae!(SAE);
16021        vcvtph2psx_512(a, src, k, SAE)
16022    }
16023}
16024
16025/// Convert packed half-precision (16-bit) floating-point elements in a to packed single-precision (32-bit)
16026/// floating-point elements, and store the results in dst using zeromask k (elements are zeroed out when the
16027/// corresponding mask bit is not set).
16028///
16029/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
16030///
16031/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtx_roundph_ps)
16032#[inline]
16033#[target_feature(enable = "avx512fp16")]
16034#[cfg_attr(test, assert_instr(vcvtph2psx, SAE = 8))]
16035#[rustc_legacy_const_generics(2)]
16036#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
16037pub fn _mm512_maskz_cvtx_roundph_ps<const SAE: i32>(k: __mmask16, a: __m256h) -> __m512 {
16038    static_assert_sae!(SAE);
16039    _mm512_mask_cvtx_roundph_ps::<SAE>(_mm512_setzero_ps(), k, a)
16040}
16041
16042/// Convert the lower half-precision (16-bit) floating-point element in b to a single-precision (32-bit)
16043/// floating-point element, store the result in the lower element of dst, and copy the upper 3 packed
16044/// elements from a to the upper elements of dst.
16045///
16046/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsh_ss)
16047#[inline]
16048#[target_feature(enable = "avx512fp16")]
16049#[cfg_attr(test, assert_instr(vcvtsh2ss))]
16050#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
16051pub fn _mm_cvtsh_ss(a: __m128, b: __m128h) -> __m128 {
16052    _mm_mask_cvtsh_ss(a, 0xff, a, b)
16053}
16054
16055/// Convert the lower half-precision (16-bit) floating-point element in b to a single-precision (32-bit)
16056/// floating-point element, store the result in the lower element of dst using writemask k (the element is
16057/// copied from src to dst when mask bit 0 is not set), and copy the upper 3 packed elements from a to the
16058/// upper elements of dst.
16059///
16060/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cvtsh_ss)
16061#[inline]
16062#[target_feature(enable = "avx512fp16")]
16063#[cfg_attr(test, assert_instr(vcvtsh2ss))]
16064#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
16065pub fn _mm_mask_cvtsh_ss(src: __m128, k: __mmask8, a: __m128, b: __m128h) -> __m128 {
16066    unsafe { vcvtsh2ss(a, b, src, k, _MM_FROUND_CUR_DIRECTION) }
16067}
16068
16069/// Convert the lower half-precision (16-bit) floating-point element in b to a single-precision (32-bit)
16070/// floating-point element, store the result in the lower element of dst using zeromask k (the element is
16071/// zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from a to the upper elements
16072/// of dst.
16073///
16074/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_cvtsh_ss)
16075#[inline]
16076#[target_feature(enable = "avx512fp16")]
16077#[cfg_attr(test, assert_instr(vcvtsh2ss))]
16078#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
16079pub fn _mm_maskz_cvtsh_ss(k: __mmask8, a: __m128, b: __m128h) -> __m128 {
16080    _mm_mask_cvtsh_ss(_mm_set_ss(0.0), k, a, b)
16081}
16082
16083/// Convert the lower half-precision (16-bit) floating-point element in b to a single-precision (32-bit)
16084/// floating-point element, store the result in the lower element of dst, and copy the upper 3 packed elements
16085/// from a to the upper elements of dst.
16086///
16087/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
16088///
16089/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvt_roundsh_ss)
16090#[inline]
16091#[target_feature(enable = "avx512fp16")]
16092#[cfg_attr(test, assert_instr(vcvtsh2ss, SAE = 8))]
16093#[rustc_legacy_const_generics(2)]
16094#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
16095pub fn _mm_cvt_roundsh_ss<const SAE: i32>(a: __m128, b: __m128h) -> __m128 {
16096    static_assert_sae!(SAE);
16097    _mm_mask_cvt_roundsh_ss::<SAE>(_mm_undefined_ps(), 0xff, a, b)
16098}
16099
16100/// Convert the lower half-precision (16-bit) floating-point element in b to a single-precision (32-bit)
16101/// floating-point element, store the result in the lower element of dst using writemask k (the element is
16102/// copied from src to dst when mask bit 0 is not set), and copy the upper 3 packed elements from a to the
16103/// upper elements of dst.
16104///
16105/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
16106///
16107/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cvt_roundsh_ss)
16108#[inline]
16109#[target_feature(enable = "avx512fp16")]
16110#[cfg_attr(test, assert_instr(vcvtsh2ss, SAE = 8))]
16111#[rustc_legacy_const_generics(4)]
16112#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
16113pub fn _mm_mask_cvt_roundsh_ss<const SAE: i32>(
16114    src: __m128,
16115    k: __mmask8,
16116    a: __m128,
16117    b: __m128h,
16118) -> __m128 {
16119    unsafe {
16120        static_assert_sae!(SAE);
16121        vcvtsh2ss(a, b, src, k, SAE)
16122    }
16123}
16124
16125/// Convert the lower half-precision (16-bit) floating-point element in b to a single-precision (32-bit)
16126/// floating-point element, store the result in the lower element of dst using zeromask k (the element is
16127/// zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from a to the upper elements
16128/// of dst.
16129///
16130/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
16131///
16132/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_cvt_roundsh_ss)
16133#[inline]
16134#[target_feature(enable = "avx512fp16")]
16135#[cfg_attr(test, assert_instr(vcvtsh2ss, SAE = 8))]
16136#[rustc_legacy_const_generics(3)]
16137#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
16138pub fn _mm_maskz_cvt_roundsh_ss<const SAE: i32>(k: __mmask8, a: __m128, b: __m128h) -> __m128 {
16139    static_assert_sae!(SAE);
16140    _mm_mask_cvt_roundsh_ss::<SAE>(_mm_set_ss(0.0), k, a, b)
16141}
16142
16143/// Convert packed half-precision (16-bit) floating-point elements in a to packed double-precision (64-bit)
16144/// floating-point elements, and store the results in dst.
16145///
16146/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtph_pd)
16147#[inline]
16148#[target_feature(enable = "avx512fp16,avx512vl")]
16149#[cfg_attr(test, assert_instr(vcvtph2pd))]
16150#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
16151pub fn _mm_cvtph_pd(a: __m128h) -> __m128d {
16152    _mm_mask_cvtph_pd(_mm_setzero_pd(), 0xff, a)
16153}
16154
16155/// Convert packed half-precision (16-bit) floating-point elements in a to packed double-precision (64-bit)
16156/// floating-point elements, and store the results in dst using writemask k (elements are copied from src to
16157/// dst when the corresponding mask bit is not set).
16158///
16159/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cvtph_pd)
16160#[inline]
16161#[target_feature(enable = "avx512fp16,avx512vl")]
16162#[cfg_attr(test, assert_instr(vcvtph2pd))]
16163#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
16164pub fn _mm_mask_cvtph_pd(src: __m128d, k: __mmask8, a: __m128h) -> __m128d {
16165    unsafe { vcvtph2pd_128(a, src, k) }
16166}
16167
16168/// Convert packed half-precision (16-bit) floating-point elements in a to packed double-precision (64-bit)
16169/// floating-point elements, and store the results in dst using zeromask k (elements are zeroed out when the
16170/// corresponding mask bit is not set).
16171///
16172/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_cvtph_pd)
16173#[inline]
16174#[target_feature(enable = "avx512fp16,avx512vl")]
16175#[cfg_attr(test, assert_instr(vcvtph2pd))]
16176#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
16177pub fn _mm_maskz_cvtph_pd(k: __mmask8, a: __m128h) -> __m128d {
16178    _mm_mask_cvtph_pd(_mm_setzero_pd(), k, a)
16179}
16180
16181/// Convert packed half-precision (16-bit) floating-point elements in a to packed double-precision (64-bit)
16182/// floating-point elements, and store the results in dst.
16183///
16184/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtph_pd)
16185#[inline]
16186#[target_feature(enable = "avx512fp16,avx512vl")]
16187#[cfg_attr(test, assert_instr(vcvtph2pd))]
16188#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
16189pub fn _mm256_cvtph_pd(a: __m128h) -> __m256d {
16190    _mm256_mask_cvtph_pd(_mm256_setzero_pd(), 0xff, a)
16191}
16192
16193/// Convert packed half-precision (16-bit) floating-point elements in a to packed double-precision (64-bit)
16194/// floating-point elements, and store the results in dst using writemask k (elements are copied from src to
16195/// dst when the corresponding mask bit is not set).
16196///
16197/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_cvtph_pd)
16198#[inline]
16199#[target_feature(enable = "avx512fp16,avx512vl")]
16200#[cfg_attr(test, assert_instr(vcvtph2pd))]
16201#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
16202pub fn _mm256_mask_cvtph_pd(src: __m256d, k: __mmask8, a: __m128h) -> __m256d {
16203    unsafe { vcvtph2pd_256(a, src, k) }
16204}
16205
16206/// Convert packed half-precision (16-bit) floating-point elements in a to packed double-precision (64-bit)
16207/// floating-point elements, and store the results in dst using zeromask k (elements are zeroed out when the
16208/// corresponding mask bit is not set).
16209///
16210/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_cvtph_pd)
16211#[inline]
16212#[target_feature(enable = "avx512fp16,avx512vl")]
16213#[cfg_attr(test, assert_instr(vcvtph2pd))]
16214#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
16215pub fn _mm256_maskz_cvtph_pd(k: __mmask8, a: __m128h) -> __m256d {
16216    _mm256_mask_cvtph_pd(_mm256_setzero_pd(), k, a)
16217}
16218
16219/// Convert packed half-precision (16-bit) floating-point elements in a to packed double-precision (64-bit)
16220/// floating-point elements, and store the results in dst.
16221///
16222/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtph_pd)
16223#[inline]
16224#[target_feature(enable = "avx512fp16")]
16225#[cfg_attr(test, assert_instr(vcvtph2pd))]
16226#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
16227pub fn _mm512_cvtph_pd(a: __m128h) -> __m512d {
16228    _mm512_mask_cvtph_pd(_mm512_setzero_pd(), 0xff, a)
16229}
16230
16231/// Convert packed half-precision (16-bit) floating-point elements in a to packed double-precision (64-bit)
16232/// floating-point elements, and store the results in dst using writemask k (elements are copied from src to
16233/// dst when the corresponding mask bit is not set).
16234///
16235/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtph_pd)
16236#[inline]
16237#[target_feature(enable = "avx512fp16")]
16238#[cfg_attr(test, assert_instr(vcvtph2pd))]
16239#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
16240pub fn _mm512_mask_cvtph_pd(src: __m512d, k: __mmask8, a: __m128h) -> __m512d {
16241    unsafe { vcvtph2pd_512(a, src, k, _MM_FROUND_CUR_DIRECTION) }
16242}
16243
16244/// Convert packed half-precision (16-bit) floating-point elements in a to packed double-precision (64-bit)
16245/// floating-point elements, and store the results in dst using zeromask k (elements are zeroed out when the
16246/// corresponding mask bit is not set).
16247///
16248/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtph_pd)
16249#[inline]
16250#[target_feature(enable = "avx512fp16")]
16251#[cfg_attr(test, assert_instr(vcvtph2pd))]
16252#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
16253pub fn _mm512_maskz_cvtph_pd(k: __mmask8, a: __m128h) -> __m512d {
16254    _mm512_mask_cvtph_pd(_mm512_setzero_pd(), k, a)
16255}
16256
16257/// Convert packed half-precision (16-bit) floating-point elements in a to packed double-precision (64-bit)
16258/// floating-point elements, and store the results in dst.
16259///
16260/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
16261///
16262/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvt_roundph_pd)
16263#[inline]
16264#[target_feature(enable = "avx512fp16")]
16265#[cfg_attr(test, assert_instr(vcvtph2pd, SAE = 8))]
16266#[rustc_legacy_const_generics(1)]
16267#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
16268pub fn _mm512_cvt_roundph_pd<const SAE: i32>(a: __m128h) -> __m512d {
16269    static_assert_sae!(SAE);
16270    _mm512_mask_cvt_roundph_pd::<SAE>(_mm512_setzero_pd(), 0xff, a)
16271}
16272
16273/// Convert packed half-precision (16-bit) floating-point elements in a to packed double-precision (64-bit)
16274/// floating-point elements, and store the results in dst using writemask k (elements are copied from src to
16275/// dst when the corresponding mask bit is not set).
16276///
16277/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
16278///
16279/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvt_roundph_pd)
16280#[inline]
16281#[target_feature(enable = "avx512fp16")]
16282#[cfg_attr(test, assert_instr(vcvtph2pd, SAE = 8))]
16283#[rustc_legacy_const_generics(3)]
16284#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
16285pub fn _mm512_mask_cvt_roundph_pd<const SAE: i32>(
16286    src: __m512d,
16287    k: __mmask8,
16288    a: __m128h,
16289) -> __m512d {
16290    unsafe {
16291        static_assert_sae!(SAE);
16292        vcvtph2pd_512(a, src, k, SAE)
16293    }
16294}
16295
16296/// Convert packed half-precision (16-bit) floating-point elements in a to packed double-precision (64-bit)
16297/// floating-point elements, and store the results in dst using zeromask k (elements are zeroed out when the
16298/// corresponding mask bit is not set).
16299///
16300/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
16301///
16302/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvt_roundph_pd)
16303#[inline]
16304#[target_feature(enable = "avx512fp16")]
16305#[cfg_attr(test, assert_instr(vcvtph2pd, SAE = 8))]
16306#[rustc_legacy_const_generics(2)]
16307#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
16308pub fn _mm512_maskz_cvt_roundph_pd<const SAE: i32>(k: __mmask8, a: __m128h) -> __m512d {
16309    static_assert_sae!(SAE);
16310    _mm512_mask_cvt_roundph_pd::<SAE>(_mm512_setzero_pd(), k, a)
16311}
16312
16313/// Convert the lower half-precision (16-bit) floating-point element in b to a double-precision (64-bit)
16314/// floating-point element, store the result in the lower element of dst, and copy the upper element
16315/// from a to the upper element of dst.
16316///
16317/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsh_sd)
16318#[inline]
16319#[target_feature(enable = "avx512fp16")]
16320#[cfg_attr(test, assert_instr(vcvtsh2sd))]
16321#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
16322pub fn _mm_cvtsh_sd(a: __m128d, b: __m128h) -> __m128d {
16323    _mm_mask_cvtsh_sd(a, 0xff, a, b)
16324}
16325
16326/// Convert the lower half-precision (16-bit) floating-point element in b to a double-precision (64-bit)
16327/// floating-point element, store the result in the lower element of dst using writemask k (the element is
16328/// copied from src to dst when mask bit 0 is not set), and copy the upper element from a to the upper element
16329/// of dst.
16330///
16331/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cvtsh_sd)
16332#[inline]
16333#[target_feature(enable = "avx512fp16")]
16334#[cfg_attr(test, assert_instr(vcvtsh2sd))]
16335#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
16336pub fn _mm_mask_cvtsh_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128h) -> __m128d {
16337    unsafe { vcvtsh2sd(a, b, src, k, _MM_FROUND_CUR_DIRECTION) }
16338}
16339
16340/// Convert the lower half-precision (16-bit) floating-point element in b to a double-precision (64-bit)
16341/// floating-point element, store the result in the lower element of dst using zeromask k (the element is
16342/// zeroed out when mask bit 0 is not set), and copy the upper element from a to the upper element of dst.
16343///
16344/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_cvtsh_sd)
16345#[inline]
16346#[target_feature(enable = "avx512fp16")]
16347#[cfg_attr(test, assert_instr(vcvtsh2sd))]
16348#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
16349pub fn _mm_maskz_cvtsh_sd(k: __mmask8, a: __m128d, b: __m128h) -> __m128d {
16350    _mm_mask_cvtsh_sd(_mm_set_sd(0.0), k, a, b)
16351}
16352
16353/// Convert the lower half-precision (16-bit) floating-point element in b to a double-precision (64-bit)
16354/// floating-point element, store the result in the lower element of dst, and copy the upper element from a
16355/// to the upper element of dst.
16356///
16357/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
16358///
16359/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvt_roundsh_sd)
16360#[inline]
16361#[target_feature(enable = "avx512fp16")]
16362#[cfg_attr(test, assert_instr(vcvtsh2sd, SAE = 8))]
16363#[rustc_legacy_const_generics(2)]
16364#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
16365pub fn _mm_cvt_roundsh_sd<const SAE: i32>(a: __m128d, b: __m128h) -> __m128d {
16366    static_assert_sae!(SAE);
16367    _mm_mask_cvt_roundsh_sd::<SAE>(a, 0xff, a, b)
16368}
16369
16370/// Convert the lower half-precision (16-bit) floating-point element in b to a double-precision (64-bit)
16371/// floating-point element, store the result in the lower element of dst using writemask k (the element is
16372/// copied from src to dst when mask bit 0 is not set), and copy the upper element from a to the upper element
16373/// of dst.
16374///
16375/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
16376///
16377/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cvt_roundsh_sd)
16378#[inline]
16379#[target_feature(enable = "avx512fp16")]
16380#[cfg_attr(test, assert_instr(vcvtsh2sd, SAE = 8))]
16381#[rustc_legacy_const_generics(4)]
16382#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
16383pub fn _mm_mask_cvt_roundsh_sd<const SAE: i32>(
16384    src: __m128d,
16385    k: __mmask8,
16386    a: __m128d,
16387    b: __m128h,
16388) -> __m128d {
16389    unsafe {
16390        static_assert_sae!(SAE);
16391        vcvtsh2sd(a, b, src, k, SAE)
16392    }
16393}
16394
16395/// Convert the lower half-precision (16-bit) floating-point element in b to a double-precision (64-bit)
16396/// floating-point element, store the result in the lower element of dst using zeromask k (the element is
16397/// zeroed out when mask bit 0 is not set), and copy the upper element from a to the upper element of dst.
16398///
16399/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
16400///
16401/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_cvt_roundsh_sd)
16402#[inline]
16403#[target_feature(enable = "avx512fp16")]
16404#[cfg_attr(test, assert_instr(vcvtsh2sd, SAE = 8))]
16405#[rustc_legacy_const_generics(3)]
16406#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
16407pub fn _mm_maskz_cvt_roundsh_sd<const SAE: i32>(k: __mmask8, a: __m128d, b: __m128h) -> __m128d {
16408    static_assert_sae!(SAE);
16409    _mm_mask_cvt_roundsh_sd::<SAE>(_mm_set_sd(0.0), k, a, b)
16410}
16411
16412/// Copy the lower half-precision (16-bit) floating-point element from `a` to `dst`.
16413///
16414/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsh_h)
16415#[inline]
16416#[target_feature(enable = "avx512fp16")]
16417#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
16418#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
16419pub const fn _mm_cvtsh_h(a: __m128h) -> f16 {
16420    unsafe { simd_extract!(a, 0) }
16421}
16422
16423/// Copy the lower half-precision (16-bit) floating-point element from `a` to `dst`.
16424///
16425/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtsh_h)
16426#[inline]
16427#[target_feature(enable = "avx512fp16")]
16428#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
16429#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
16430pub const fn _mm256_cvtsh_h(a: __m256h) -> f16 {
16431    unsafe { simd_extract!(a, 0) }
16432}
16433
16434/// Copy the lower half-precision (16-bit) floating-point element from `a` to `dst`.
16435///
16436/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtsh_h)
16437#[inline]
16438#[target_feature(enable = "avx512fp16")]
16439#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
16440#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
16441pub const fn _mm512_cvtsh_h(a: __m512h) -> f16 {
16442    unsafe { simd_extract!(a, 0) }
16443}
16444
16445/// Copy the lower 16-bit integer in a to dst.
16446///
16447/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsi128_si16)
16448#[inline]
16449#[target_feature(enable = "avx512fp16")]
16450#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
16451#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
16452pub const fn _mm_cvtsi128_si16(a: __m128i) -> i16 {
16453    unsafe { simd_extract!(a.as_i16x8(), 0) }
16454}
16455
16456/// Copy 16-bit integer a to the lower elements of dst, and zero the upper elements of dst.
16457///
16458/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsi16_si128)
16459#[inline]
16460#[target_feature(enable = "avx512fp16")]
16461#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
16462#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
16463pub const fn _mm_cvtsi16_si128(a: i16) -> __m128i {
16464    unsafe { transmute(simd_insert!(i16x8::ZERO, 0, a)) }
16465}
16466
16467#[allow(improper_ctypes)]
16468unsafe extern "llvm-intrinsic" {
16469    #[link_name = "llvm.x86.avx512fp16.mask.cmp.ph.128"]
16470    fn vcmpph_128(a: __m128h, b: __m128h, imm5: i32, mask: __mmask8) -> __mmask8;
16471    #[link_name = "llvm.x86.avx512fp16.mask.cmp.ph.256"]
16472    fn vcmpph_256(a: __m256h, b: __m256h, imm5: i32, mask: __mmask16) -> __mmask16;
16473    #[link_name = "llvm.x86.avx512fp16.mask.cmp.ph.512"]
16474    fn vcmpph_512(a: __m512h, b: __m512h, imm5: i32, mask: __mmask32, sae: i32) -> __mmask32;
16475
16476    #[link_name = "llvm.x86.avx512fp16.mask.cmp.sh"]
16477    fn vcmpsh(a: __m128h, b: __m128h, imm5: i32, mask: __mmask8, sae: i32) -> __mmask8;
16478    #[link_name = "llvm.x86.avx512fp16.vcomi.sh"]
16479    fn vcomish(a: __m128h, b: __m128h, imm5: i32, sae: i32) -> i32;
16480
16481    #[link_name = "llvm.x86.avx512fp16.add.ph.512"]
16482    fn vaddph(a: __m512h, b: __m512h, rounding: i32) -> __m512h;
16483    #[link_name = "llvm.x86.avx512fp16.sub.ph.512"]
16484    fn vsubph(a: __m512h, b: __m512h, rounding: i32) -> __m512h;
16485    #[link_name = "llvm.x86.avx512fp16.mul.ph.512"]
16486    fn vmulph(a: __m512h, b: __m512h, rounding: i32) -> __m512h;
16487    #[link_name = "llvm.x86.avx512fp16.div.ph.512"]
16488    fn vdivph(a: __m512h, b: __m512h, rounding: i32) -> __m512h;
16489
16490    #[link_name = "llvm.x86.avx512fp16.mask.add.sh.round"]
16491    fn vaddsh(a: __m128h, b: __m128h, src: __m128h, k: __mmask8, rounding: i32) -> __m128h;
16492    #[link_name = "llvm.x86.avx512fp16.mask.sub.sh.round"]
16493    fn vsubsh(a: __m128h, b: __m128h, src: __m128h, k: __mmask8, rounding: i32) -> __m128h;
16494    #[link_name = "llvm.x86.avx512fp16.mask.mul.sh.round"]
16495    fn vmulsh(a: __m128h, b: __m128h, src: __m128h, k: __mmask8, rounding: i32) -> __m128h;
16496    #[link_name = "llvm.x86.avx512fp16.mask.div.sh.round"]
16497    fn vdivsh(a: __m128h, b: __m128h, src: __m128h, k: __mmask8, rounding: i32) -> __m128h;
16498
16499    #[link_name = "llvm.x86.avx512fp16.mask.vfmul.cph.128"]
16500    fn vfmulcph_128(a: __m128, b: __m128, src: __m128, k: __mmask8) -> __m128;
16501    #[link_name = "llvm.x86.avx512fp16.mask.vfmul.cph.256"]
16502    fn vfmulcph_256(a: __m256, b: __m256, src: __m256, k: __mmask8) -> __m256;
16503    #[link_name = "llvm.x86.avx512fp16.mask.vfmul.cph.512"]
16504    fn vfmulcph_512(a: __m512, b: __m512, src: __m512, k: __mmask16, rounding: i32) -> __m512;
16505    #[link_name = "llvm.x86.avx512fp16.mask.vfmul.csh"]
16506    fn vfmulcsh(a: __m128, b: __m128, src: __m128, k: __mmask8, rounding: i32) -> __m128;
16507
16508    #[link_name = "llvm.x86.avx512fp16.mask.vfcmul.cph.128"]
16509    fn vfcmulcph_128(a: __m128, b: __m128, src: __m128, k: __mmask8) -> __m128;
16510    #[link_name = "llvm.x86.avx512fp16.mask.vfcmul.cph.256"]
16511    fn vfcmulcph_256(a: __m256, b: __m256, src: __m256, k: __mmask8) -> __m256;
16512    #[link_name = "llvm.x86.avx512fp16.mask.vfcmul.cph.512"]
16513    fn vfcmulcph_512(a: __m512, b: __m512, src: __m512, k: __mmask16, rounding: i32) -> __m512;
16514    #[link_name = "llvm.x86.avx512fp16.mask.vfcmul.csh"]
16515    fn vfcmulcsh(a: __m128, b: __m128, src: __m128, k: __mmask8, rounding: i32) -> __m128;
16516
16517    #[link_name = "llvm.x86.avx512fp16.mask.vfmadd.cph.128"]
16518    fn vfmaddcph_mask3_128(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m128;
16519    #[link_name = "llvm.x86.avx512fp16.maskz.vfmadd.cph.128"]
16520    fn vfmaddcph_maskz_128(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m128;
16521    #[link_name = "llvm.x86.avx512fp16.mask.vfmadd.cph.256"]
16522    fn vfmaddcph_mask3_256(a: __m256, b: __m256, c: __m256, k: __mmask8) -> __m256;
16523    #[link_name = "llvm.x86.avx512fp16.maskz.vfmadd.cph.256"]
16524    fn vfmaddcph_maskz_256(a: __m256, b: __m256, c: __m256, k: __mmask8) -> __m256;
16525    #[link_name = "llvm.x86.avx512fp16.mask.vfmadd.cph.512"]
16526    fn vfmaddcph_mask3_512(a: __m512, b: __m512, c: __m512, k: __mmask16, rounding: i32) -> __m512;
16527    #[link_name = "llvm.x86.avx512fp16.maskz.vfmadd.cph.512"]
16528    fn vfmaddcph_maskz_512(a: __m512, b: __m512, c: __m512, k: __mmask16, rounding: i32) -> __m512;
16529    #[link_name = "llvm.x86.avx512fp16.mask.vfmadd.csh"]
16530    fn vfmaddcsh_mask(a: __m128, b: __m128, c: __m128, k: __mmask8, rounding: i32) -> __m128;
16531    #[link_name = "llvm.x86.avx512fp16.maskz.vfmadd.csh"]
16532    fn vfmaddcsh_maskz(a: __m128, b: __m128, c: __m128, k: __mmask8, rounding: i32) -> __m128;
16533
16534    #[link_name = "llvm.x86.avx512fp16.mask.vfcmadd.cph.128"]
16535    fn vfcmaddcph_mask3_128(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m128;
16536    #[link_name = "llvm.x86.avx512fp16.maskz.vfcmadd.cph.128"]
16537    fn vfcmaddcph_maskz_128(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m128;
16538    #[link_name = "llvm.x86.avx512fp16.mask.vfcmadd.cph.256"]
16539    fn vfcmaddcph_mask3_256(a: __m256, b: __m256, c: __m256, k: __mmask8) -> __m256;
16540    #[link_name = "llvm.x86.avx512fp16.maskz.vfcmadd.cph.256"]
16541    fn vfcmaddcph_maskz_256(a: __m256, b: __m256, c: __m256, k: __mmask8) -> __m256;
16542    #[link_name = "llvm.x86.avx512fp16.mask.vfcmadd.cph.512"]
16543    fn vfcmaddcph_mask3_512(a: __m512, b: __m512, c: __m512, k: __mmask16, rounding: i32)
16544    -> __m512;
16545    #[link_name = "llvm.x86.avx512fp16.maskz.vfcmadd.cph.512"]
16546    fn vfcmaddcph_maskz_512(a: __m512, b: __m512, c: __m512, k: __mmask16, rounding: i32)
16547    -> __m512;
16548    #[link_name = "llvm.x86.avx512fp16.mask.vfcmadd.csh"]
16549    fn vfcmaddcsh_mask(a: __m128, b: __m128, c: __m128, k: __mmask8, rounding: i32) -> __m128;
16550    #[link_name = "llvm.x86.avx512fp16.maskz.vfcmadd.csh"]
16551    fn vfcmaddcsh_maskz(a: __m128, b: __m128, c: __m128, k: __mmask8, rounding: i32) -> __m128;
16552
16553    #[link_name = "llvm.x86.avx512fp16.vfmadd.ph.512"]
16554    fn vfmaddph_512(a: __m512h, b: __m512h, c: __m512h, rounding: i32) -> __m512h;
16555    #[link_name = "llvm.x86.avx512fp16.vfmadd.f16"]
16556    fn vfmaddsh(a: f16, b: f16, c: f16, rounding: i32) -> f16;
16557
16558    #[link_name = "llvm.x86.avx512fp16.vfmaddsub.ph.512"]
16559    fn vfmaddsubph_512(a: __m512h, b: __m512h, c: __m512h, rounding: i32) -> __m512h;
16560
16561    #[link_name = "llvm.x86.avx512fp16.mask.rcp.ph.128"]
16562    fn vrcpph_128(a: __m128h, src: __m128h, k: __mmask8) -> __m128h;
16563    #[link_name = "llvm.x86.avx512fp16.mask.rcp.ph.256"]
16564    fn vrcpph_256(a: __m256h, src: __m256h, k: __mmask16) -> __m256h;
16565    #[link_name = "llvm.x86.avx512fp16.mask.rcp.ph.512"]
16566    fn vrcpph_512(a: __m512h, src: __m512h, k: __mmask32) -> __m512h;
16567    #[link_name = "llvm.x86.avx512fp16.mask.rcp.sh"]
16568    fn vrcpsh(a: __m128h, b: __m128h, src: __m128h, k: __mmask8) -> __m128h;
16569
16570    #[link_name = "llvm.x86.avx512fp16.mask.rsqrt.ph.128"]
16571    fn vrsqrtph_128(a: __m128h, src: __m128h, k: __mmask8) -> __m128h;
16572    #[link_name = "llvm.x86.avx512fp16.mask.rsqrt.ph.256"]
16573    fn vrsqrtph_256(a: __m256h, src: __m256h, k: __mmask16) -> __m256h;
16574    #[link_name = "llvm.x86.avx512fp16.mask.rsqrt.ph.512"]
16575    fn vrsqrtph_512(a: __m512h, src: __m512h, k: __mmask32) -> __m512h;
16576    #[link_name = "llvm.x86.avx512fp16.mask.rsqrt.sh"]
16577    fn vrsqrtsh(a: __m128h, b: __m128h, src: __m128h, k: __mmask8) -> __m128h;
16578
16579    #[link_name = "llvm.x86.avx512fp16.sqrt.ph.512"]
16580    fn vsqrtph_512(a: __m512h, rounding: i32) -> __m512h;
16581    #[link_name = "llvm.x86.avx512fp16.mask.sqrt.sh"]
16582    fn vsqrtsh(a: __m128h, b: __m128h, src: __m128h, k: __mmask8, rounding: i32) -> __m128h;
16583
16584    #[link_name = "llvm.x86.avx512fp16.max.ph.128"]
16585    fn vmaxph_128(a: __m128h, b: __m128h) -> __m128h;
16586    #[link_name = "llvm.x86.avx512fp16.max.ph.256"]
16587    fn vmaxph_256(a: __m256h, b: __m256h) -> __m256h;
16588    #[link_name = "llvm.x86.avx512fp16.max.ph.512"]
16589    fn vmaxph_512(a: __m512h, b: __m512h, sae: i32) -> __m512h;
16590    #[link_name = "llvm.x86.avx512fp16.mask.max.sh.round"]
16591    fn vmaxsh(a: __m128h, b: __m128h, src: __m128h, k: __mmask8, sae: i32) -> __m128h;
16592
16593    #[link_name = "llvm.x86.avx512fp16.min.ph.128"]
16594    fn vminph_128(a: __m128h, b: __m128h) -> __m128h;
16595    #[link_name = "llvm.x86.avx512fp16.min.ph.256"]
16596    fn vminph_256(a: __m256h, b: __m256h) -> __m256h;
16597    #[link_name = "llvm.x86.avx512fp16.min.ph.512"]
16598    fn vminph_512(a: __m512h, b: __m512h, sae: i32) -> __m512h;
16599    #[link_name = "llvm.x86.avx512fp16.mask.min.sh.round"]
16600    fn vminsh(a: __m128h, b: __m128h, src: __m128h, k: __mmask8, sae: i32) -> __m128h;
16601
16602    #[link_name = "llvm.x86.avx512fp16.mask.getexp.ph.128"]
16603    fn vgetexpph_128(a: __m128h, src: __m128h, k: __mmask8) -> __m128h;
16604    #[link_name = "llvm.x86.avx512fp16.mask.getexp.ph.256"]
16605    fn vgetexpph_256(a: __m256h, src: __m256h, k: __mmask16) -> __m256h;
16606    #[link_name = "llvm.x86.avx512fp16.mask.getexp.ph.512"]
16607    fn vgetexpph_512(a: __m512h, src: __m512h, k: __mmask32, sae: i32) -> __m512h;
16608    #[link_name = "llvm.x86.avx512fp16.mask.getexp.sh"]
16609    fn vgetexpsh(a: __m128h, b: __m128h, src: __m128h, k: __mmask8, sae: i32) -> __m128h;
16610
16611    #[link_name = "llvm.x86.avx512fp16.mask.getmant.ph.128"]
16612    fn vgetmantph_128(a: __m128h, imm8: i32, src: __m128h, k: __mmask8) -> __m128h;
16613    #[link_name = "llvm.x86.avx512fp16.mask.getmant.ph.256"]
16614    fn vgetmantph_256(a: __m256h, imm8: i32, src: __m256h, k: __mmask16) -> __m256h;
16615    #[link_name = "llvm.x86.avx512fp16.mask.getmant.ph.512"]
16616    fn vgetmantph_512(a: __m512h, imm8: i32, src: __m512h, k: __mmask32, sae: i32) -> __m512h;
16617    #[link_name = "llvm.x86.avx512fp16.mask.getmant.sh"]
16618    fn vgetmantsh(
16619        a: __m128h,
16620        b: __m128h,
16621        imm8: i32,
16622        src: __m128h,
16623        k: __mmask8,
16624        sae: i32,
16625    ) -> __m128h;
16626
16627    #[link_name = "llvm.x86.avx512fp16.mask.rndscale.ph.128"]
16628    fn vrndscaleph_128(a: __m128h, imm8: i32, src: __m128h, k: __mmask8) -> __m128h;
16629    #[link_name = "llvm.x86.avx512fp16.mask.rndscale.ph.256"]
16630    fn vrndscaleph_256(a: __m256h, imm8: i32, src: __m256h, k: __mmask16) -> __m256h;
16631    #[link_name = "llvm.x86.avx512fp16.mask.rndscale.ph.512"]
16632    fn vrndscaleph_512(a: __m512h, imm8: i32, src: __m512h, k: __mmask32, sae: i32) -> __m512h;
16633    #[link_name = "llvm.x86.avx512fp16.mask.rndscale.sh"]
16634    fn vrndscalesh(
16635        a: __m128h,
16636        b: __m128h,
16637        src: __m128h,
16638        k: __mmask8,
16639        imm8: i32,
16640        sae: i32,
16641    ) -> __m128h;
16642
16643    #[link_name = "llvm.x86.avx512fp16.mask.scalef.ph.128"]
16644    fn vscalefph_128(a: __m128h, b: __m128h, src: __m128h, k: __mmask8) -> __m128h;
16645    #[link_name = "llvm.x86.avx512fp16.mask.scalef.ph.256"]
16646    fn vscalefph_256(a: __m256h, b: __m256h, src: __m256h, k: __mmask16) -> __m256h;
16647    #[link_name = "llvm.x86.avx512fp16.mask.scalef.ph.512"]
16648    fn vscalefph_512(a: __m512h, b: __m512h, src: __m512h, k: __mmask32, rounding: i32) -> __m512h;
16649    #[link_name = "llvm.x86.avx512fp16.mask.scalef.sh"]
16650    fn vscalefsh(a: __m128h, b: __m128h, src: __m128h, k: __mmask8, rounding: i32) -> __m128h;
16651
16652    #[link_name = "llvm.x86.avx512fp16.mask.reduce.ph.128"]
16653    fn vreduceph_128(a: __m128h, imm8: i32, src: __m128h, k: __mmask8) -> __m128h;
16654    #[link_name = "llvm.x86.avx512fp16.mask.reduce.ph.256"]
16655    fn vreduceph_256(a: __m256h, imm8: i32, src: __m256h, k: __mmask16) -> __m256h;
16656    #[link_name = "llvm.x86.avx512fp16.mask.reduce.ph.512"]
16657    fn vreduceph_512(a: __m512h, imm8: i32, src: __m512h, k: __mmask32, sae: i32) -> __m512h;
16658    #[link_name = "llvm.x86.avx512fp16.mask.reduce.sh"]
16659    fn vreducesh(a: __m128h, b: __m128h, src: __m128h, k: __mmask8, imm8: i32, sae: i32)
16660    -> __m128h;
16661
16662    #[link_name = "llvm.x86.avx512fp16.fpclass.ph.128"]
16663    fn vfpclassph_128(a: __m128h, imm8: i32) -> __mmask8;
16664    #[link_name = "llvm.x86.avx512fp16.fpclass.ph.256"]
16665    fn vfpclassph_256(a: __m256h, imm8: i32) -> __mmask16;
16666    #[link_name = "llvm.x86.avx512fp16.fpclass.ph.512"]
16667    fn vfpclassph_512(a: __m512h, imm8: i32) -> __mmask32;
16668
16669    #[link_name = "llvm.x86.avx512fp16.mask.fpclass.sh"]
16670    fn vfpclasssh(a: __m128h, imm8: i32, k: __mmask8) -> __mmask8;
16671
16672    #[link_name = "llvm.x86.avx512.sitofp.round.v8f16.v8i16"]
16673    fn vcvtw2ph_128(a: i16x8, rounding: i32) -> __m128h;
16674    #[link_name = "llvm.x86.avx512.sitofp.round.v16f16.v16i16"]
16675    fn vcvtw2ph_256(a: i16x16, rounding: i32) -> __m256h;
16676    #[link_name = "llvm.x86.avx512.sitofp.round.v32f16.v32i16"]
16677    fn vcvtw2ph_512(a: i16x32, rounding: i32) -> __m512h;
16678    #[link_name = "llvm.x86.avx512.uitofp.round.v8f16.v8i16"]
16679    fn vcvtuw2ph_128(a: u16x8, rounding: i32) -> __m128h;
16680    #[link_name = "llvm.x86.avx512.uitofp.round.v16f16.v16i16"]
16681    fn vcvtuw2ph_256(a: u16x16, rounding: i32) -> __m256h;
16682    #[link_name = "llvm.x86.avx512.uitofp.round.v32f16.v32i16"]
16683    fn vcvtuw2ph_512(a: u16x32, rounding: i32) -> __m512h;
16684
16685    #[link_name = "llvm.x86.avx512fp16.mask.vcvtdq2ph.128"]
16686    fn vcvtdq2ph_128(a: i32x4, src: __m128h, k: __mmask8) -> __m128h;
16687    #[link_name = "llvm.x86.avx512.sitofp.round.v8f16.v8i32"]
16688    fn vcvtdq2ph_256(a: i32x8, rounding: i32) -> __m128h;
16689    #[link_name = "llvm.x86.avx512.sitofp.round.v16f16.v16i32"]
16690    fn vcvtdq2ph_512(a: i32x16, rounding: i32) -> __m256h;
16691    #[link_name = "llvm.x86.avx512fp16.vcvtsi2sh"]
16692    fn vcvtsi2sh(a: __m128h, b: i32, rounding: i32) -> __m128h;
16693    #[link_name = "llvm.x86.avx512fp16.mask.vcvtudq2ph.128"]
16694    fn vcvtudq2ph_128(a: u32x4, src: __m128h, k: __mmask8) -> __m128h;
16695    #[link_name = "llvm.x86.avx512.uitofp.round.v8f16.v8i32"]
16696    fn vcvtudq2ph_256(a: u32x8, rounding: i32) -> __m128h;
16697    #[link_name = "llvm.x86.avx512.uitofp.round.v16f16.v16i32"]
16698    fn vcvtudq2ph_512(a: u32x16, rounding: i32) -> __m256h;
16699    #[link_name = "llvm.x86.avx512fp16.vcvtusi2sh"]
16700    fn vcvtusi2sh(a: __m128h, b: u32, rounding: i32) -> __m128h;
16701
16702    #[link_name = "llvm.x86.avx512fp16.mask.vcvtqq2ph.128"]
16703    fn vcvtqq2ph_128(a: i64x2, src: __m128h, k: __mmask8) -> __m128h;
16704    #[link_name = "llvm.x86.avx512fp16.mask.vcvtqq2ph.256"]
16705    fn vcvtqq2ph_256(a: i64x4, src: __m128h, k: __mmask8) -> __m128h;
16706    #[link_name = "llvm.x86.avx512.sitofp.round.v8f16.v8i64"]
16707    fn vcvtqq2ph_512(a: i64x8, rounding: i32) -> __m128h;
16708    #[link_name = "llvm.x86.avx512fp16.mask.vcvtuqq2ph.128"]
16709    fn vcvtuqq2ph_128(a: u64x2, src: __m128h, k: __mmask8) -> __m128h;
16710    #[link_name = "llvm.x86.avx512fp16.mask.vcvtuqq2ph.256"]
16711    fn vcvtuqq2ph_256(a: u64x4, src: __m128h, k: __mmask8) -> __m128h;
16712    #[link_name = "llvm.x86.avx512.uitofp.round.v8f16.v8i64"]
16713    fn vcvtuqq2ph_512(a: u64x8, rounding: i32) -> __m128h;
16714
16715    #[link_name = "llvm.x86.avx512fp16.mask.vcvtps2phx.128"]
16716    fn vcvtps2phx_128(a: __m128, src: __m128h, k: __mmask8) -> __m128h;
16717    #[link_name = "llvm.x86.avx512fp16.mask.vcvtps2phx.256"]
16718    fn vcvtps2phx_256(a: __m256, src: __m128h, k: __mmask8) -> __m128h;
16719    #[link_name = "llvm.x86.avx512fp16.mask.vcvtps2phx.512"]
16720    fn vcvtps2phx_512(a: __m512, src: __m256h, k: __mmask16, rounding: i32) -> __m256h;
16721    #[link_name = "llvm.x86.avx512fp16.mask.vcvtss2sh.round"]
16722    fn vcvtss2sh(a: __m128h, b: __m128, src: __m128h, k: __mmask8, rounding: i32) -> __m128h;
16723
16724    #[link_name = "llvm.x86.avx512fp16.mask.vcvtpd2ph.128"]
16725    fn vcvtpd2ph_128(a: __m128d, src: __m128h, k: __mmask8) -> __m128h;
16726    #[link_name = "llvm.x86.avx512fp16.mask.vcvtpd2ph.256"]
16727    fn vcvtpd2ph_256(a: __m256d, src: __m128h, k: __mmask8) -> __m128h;
16728    #[link_name = "llvm.x86.avx512fp16.mask.vcvtpd2ph.512"]
16729    fn vcvtpd2ph_512(a: __m512d, src: __m128h, k: __mmask8, rounding: i32) -> __m128h;
16730    #[link_name = "llvm.x86.avx512fp16.mask.vcvtsd2sh.round"]
16731    fn vcvtsd2sh(a: __m128h, b: __m128d, src: __m128h, k: __mmask8, rounding: i32) -> __m128h;
16732
16733    #[link_name = "llvm.x86.avx512fp16.mask.vcvtph2w.128"]
16734    fn vcvtph2w_128(a: __m128h, src: i16x8, k: __mmask8) -> i16x8;
16735    #[link_name = "llvm.x86.avx512fp16.mask.vcvtph2w.256"]
16736    fn vcvtph2w_256(a: __m256h, src: i16x16, k: __mmask16) -> i16x16;
16737    #[link_name = "llvm.x86.avx512fp16.mask.vcvtph2w.512"]
16738    fn vcvtph2w_512(a: __m512h, src: i16x32, k: __mmask32, rounding: i32) -> i16x32;
16739    #[link_name = "llvm.x86.avx512fp16.mask.vcvtph2uw.128"]
16740    fn vcvtph2uw_128(a: __m128h, src: u16x8, k: __mmask8) -> u16x8;
16741    #[link_name = "llvm.x86.avx512fp16.mask.vcvtph2uw.256"]
16742    fn vcvtph2uw_256(a: __m256h, src: u16x16, k: __mmask16) -> u16x16;
16743    #[link_name = "llvm.x86.avx512fp16.mask.vcvtph2uw.512"]
16744    fn vcvtph2uw_512(a: __m512h, src: u16x32, k: __mmask32, sae: i32) -> u16x32;
16745
16746    #[link_name = "llvm.x86.avx512fp16.mask.vcvttph2w.128"]
16747    fn vcvttph2w_128(a: __m128h, src: i16x8, k: __mmask8) -> i16x8;
16748    #[link_name = "llvm.x86.avx512fp16.mask.vcvttph2w.256"]
16749    fn vcvttph2w_256(a: __m256h, src: i16x16, k: __mmask16) -> i16x16;
16750    #[link_name = "llvm.x86.avx512fp16.mask.vcvttph2w.512"]
16751    fn vcvttph2w_512(a: __m512h, src: i16x32, k: __mmask32, sae: i32) -> i16x32;
16752    #[link_name = "llvm.x86.avx512fp16.mask.vcvttph2uw.128"]
16753    fn vcvttph2uw_128(a: __m128h, src: u16x8, k: __mmask8) -> u16x8;
16754    #[link_name = "llvm.x86.avx512fp16.mask.vcvttph2uw.256"]
16755    fn vcvttph2uw_256(a: __m256h, src: u16x16, k: __mmask16) -> u16x16;
16756    #[link_name = "llvm.x86.avx512fp16.mask.vcvttph2uw.512"]
16757    fn vcvttph2uw_512(a: __m512h, src: u16x32, k: __mmask32, sae: i32) -> u16x32;
16758
16759    #[link_name = "llvm.x86.avx512fp16.mask.vcvtph2dq.128"]
16760    fn vcvtph2dq_128(a: __m128h, src: i32x4, k: __mmask8) -> i32x4;
16761    #[link_name = "llvm.x86.avx512fp16.mask.vcvtph2dq.256"]
16762    fn vcvtph2dq_256(a: __m128h, src: i32x8, k: __mmask8) -> i32x8;
16763    #[link_name = "llvm.x86.avx512fp16.mask.vcvtph2dq.512"]
16764    fn vcvtph2dq_512(a: __m256h, src: i32x16, k: __mmask16, rounding: i32) -> i32x16;
16765    #[link_name = "llvm.x86.avx512fp16.vcvtsh2si32"]
16766    fn vcvtsh2si32(a: __m128h, rounding: i32) -> i32;
16767    #[link_name = "llvm.x86.avx512fp16.mask.vcvtph2udq.128"]
16768    fn vcvtph2udq_128(a: __m128h, src: u32x4, k: __mmask8) -> u32x4;
16769    #[link_name = "llvm.x86.avx512fp16.mask.vcvtph2udq.256"]
16770    fn vcvtph2udq_256(a: __m128h, src: u32x8, k: __mmask8) -> u32x8;
16771    #[link_name = "llvm.x86.avx512fp16.mask.vcvtph2udq.512"]
16772    fn vcvtph2udq_512(a: __m256h, src: u32x16, k: __mmask16, rounding: i32) -> u32x16;
16773    #[link_name = "llvm.x86.avx512fp16.vcvtsh2usi32"]
16774    fn vcvtsh2usi32(a: __m128h, sae: i32) -> u32;
16775
16776    #[link_name = "llvm.x86.avx512fp16.mask.vcvttph2dq.128"]
16777    fn vcvttph2dq_128(a: __m128h, src: i32x4, k: __mmask8) -> i32x4;
16778    #[link_name = "llvm.x86.avx512fp16.mask.vcvttph2dq.256"]
16779    fn vcvttph2dq_256(a: __m128h, src: i32x8, k: __mmask8) -> i32x8;
16780    #[link_name = "llvm.x86.avx512fp16.mask.vcvttph2dq.512"]
16781    fn vcvttph2dq_512(a: __m256h, src: i32x16, k: __mmask16, sae: i32) -> i32x16;
16782    #[link_name = "llvm.x86.avx512fp16.vcvttsh2si32"]
16783    fn vcvttsh2si32(a: __m128h, sae: i32) -> i32;
16784    #[link_name = "llvm.x86.avx512fp16.mask.vcvttph2udq.128"]
16785    fn vcvttph2udq_128(a: __m128h, src: u32x4, k: __mmask8) -> u32x4;
16786    #[link_name = "llvm.x86.avx512fp16.mask.vcvttph2udq.256"]
16787    fn vcvttph2udq_256(a: __m128h, src: u32x8, k: __mmask8) -> u32x8;
16788    #[link_name = "llvm.x86.avx512fp16.mask.vcvttph2udq.512"]
16789    fn vcvttph2udq_512(a: __m256h, src: u32x16, k: __mmask16, sae: i32) -> u32x16;
16790    #[link_name = "llvm.x86.avx512fp16.vcvttsh2usi32"]
16791    fn vcvttsh2usi32(a: __m128h, sae: i32) -> u32;
16792
16793    #[link_name = "llvm.x86.avx512fp16.mask.vcvtph2qq.128"]
16794    fn vcvtph2qq_128(a: __m128h, src: i64x2, k: __mmask8) -> i64x2;
16795    #[link_name = "llvm.x86.avx512fp16.mask.vcvtph2qq.256"]
16796    fn vcvtph2qq_256(a: __m128h, src: i64x4, k: __mmask8) -> i64x4;
16797    #[link_name = "llvm.x86.avx512fp16.mask.vcvtph2qq.512"]
16798    fn vcvtph2qq_512(a: __m128h, src: i64x8, k: __mmask8, rounding: i32) -> i64x8;
16799    #[link_name = "llvm.x86.avx512fp16.mask.vcvtph2uqq.128"]
16800    fn vcvtph2uqq_128(a: __m128h, src: u64x2, k: __mmask8) -> u64x2;
16801    #[link_name = "llvm.x86.avx512fp16.mask.vcvtph2uqq.256"]
16802    fn vcvtph2uqq_256(a: __m128h, src: u64x4, k: __mmask8) -> u64x4;
16803    #[link_name = "llvm.x86.avx512fp16.mask.vcvtph2uqq.512"]
16804    fn vcvtph2uqq_512(a: __m128h, src: u64x8, k: __mmask8, rounding: i32) -> u64x8;
16805
16806    #[link_name = "llvm.x86.avx512fp16.mask.vcvttph2qq.128"]
16807    fn vcvttph2qq_128(a: __m128h, src: i64x2, k: __mmask8) -> i64x2;
16808    #[link_name = "llvm.x86.avx512fp16.mask.vcvttph2qq.256"]
16809    fn vcvttph2qq_256(a: __m128h, src: i64x4, k: __mmask8) -> i64x4;
16810    #[link_name = "llvm.x86.avx512fp16.mask.vcvttph2qq.512"]
16811    fn vcvttph2qq_512(a: __m128h, src: i64x8, k: __mmask8, sae: i32) -> i64x8;
16812    #[link_name = "llvm.x86.avx512fp16.mask.vcvttph2uqq.128"]
16813    fn vcvttph2uqq_128(a: __m128h, src: u64x2, k: __mmask8) -> u64x2;
16814    #[link_name = "llvm.x86.avx512fp16.mask.vcvttph2uqq.256"]
16815    fn vcvttph2uqq_256(a: __m128h, src: u64x4, k: __mmask8) -> u64x4;
16816    #[link_name = "llvm.x86.avx512fp16.mask.vcvttph2uqq.512"]
16817    fn vcvttph2uqq_512(a: __m128h, src: u64x8, k: __mmask8, sae: i32) -> u64x8;
16818
16819    #[link_name = "llvm.x86.avx512fp16.mask.vcvtph2psx.128"]
16820    fn vcvtph2psx_128(a: __m128h, src: __m128, k: __mmask8) -> __m128;
16821    #[link_name = "llvm.x86.avx512fp16.mask.vcvtph2psx.256"]
16822    fn vcvtph2psx_256(a: __m128h, src: __m256, k: __mmask8) -> __m256;
16823    #[link_name = "llvm.x86.avx512fp16.mask.vcvtph2psx.512"]
16824    fn vcvtph2psx_512(a: __m256h, src: __m512, k: __mmask16, sae: i32) -> __m512;
16825    #[link_name = "llvm.x86.avx512fp16.mask.vcvtsh2ss.round"]
16826    fn vcvtsh2ss(a: __m128, b: __m128h, src: __m128, k: __mmask8, sae: i32) -> __m128;
16827
16828    #[link_name = "llvm.x86.avx512fp16.mask.vcvtph2pd.128"]
16829    fn vcvtph2pd_128(a: __m128h, src: __m128d, k: __mmask8) -> __m128d;
16830    #[link_name = "llvm.x86.avx512fp16.mask.vcvtph2pd.256"]
16831    fn vcvtph2pd_256(a: __m128h, src: __m256d, k: __mmask8) -> __m256d;
16832    #[link_name = "llvm.x86.avx512fp16.mask.vcvtph2pd.512"]
16833    fn vcvtph2pd_512(a: __m128h, src: __m512d, k: __mmask8, sae: i32) -> __m512d;
16834    #[link_name = "llvm.x86.avx512fp16.mask.vcvtsh2sd.round"]
16835    fn vcvtsh2sd(a: __m128d, b: __m128h, src: __m128d, k: __mmask8, sae: i32) -> __m128d;
16836
16837}
16838
16839#[cfg(test)]
16840#[cfg(target_has_reliable_f16)]
16841mod tests {
16842    use crate::core_arch::assert_eq_const as assert_eq;
16843    use crate::core_arch::x86::*;
16844    use crate::ptr::{addr_of, addr_of_mut};
16845    use stdarch_test::simd_test;
16846
16847    #[target_feature(enable = "avx512fp16")]
16848    #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
16849    const fn _mm_set1_pch(re: f16, im: f16) -> __m128h {
16850        _mm_setr_ph(re, im, re, im, re, im, re, im)
16851    }
16852
16853    #[target_feature(enable = "avx512fp16")]
16854    #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
16855    const fn _mm256_set1_pch(re: f16, im: f16) -> __m256h {
16856        _mm256_setr_ph(
16857            re, im, re, im, re, im, re, im, re, im, re, im, re, im, re, im,
16858        )
16859    }
16860
16861    #[target_feature(enable = "avx512fp16")]
16862    #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
16863    const fn _mm512_set1_pch(re: f16, im: f16) -> __m512h {
16864        _mm512_setr_ph(
16865            re, im, re, im, re, im, re, im, re, im, re, im, re, im, re, im, re, im, re, im, re, im,
16866            re, im, re, im, re, im, re, im, re, im,
16867        )
16868    }
16869
16870    #[simd_test(enable = "avx512fp16,avx512vl")]
16871    const fn test_mm_set_ph() {
16872        let r = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
16873        let e = _mm_setr_ph(8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0);
16874        assert_eq_m128h(r, e);
16875    }
16876
16877    #[simd_test(enable = "avx512fp16,avx512vl")]
16878    const fn test_mm256_set_ph() {
16879        let r = _mm256_set_ph(
16880            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
16881        );
16882        let e = _mm256_setr_ph(
16883            16.0, 15.0, 14.0, 13.0, 12.0, 11.0, 10.0, 9.0, 8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0,
16884        );
16885        assert_eq_m256h(r, e);
16886    }
16887
16888    #[simd_test(enable = "avx512fp16")]
16889    const fn test_mm512_set_ph() {
16890        let r = _mm512_set_ph(
16891            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
16892            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
16893            31.0, 32.0,
16894        );
16895        let e = _mm512_setr_ph(
16896            32.0, 31.0, 30.0, 29.0, 28.0, 27.0, 26.0, 25.0, 24.0, 23.0, 22.0, 21.0, 20.0, 19.0,
16897            18.0, 17.0, 16.0, 15.0, 14.0, 13.0, 12.0, 11.0, 10.0, 9.0, 8.0, 7.0, 6.0, 5.0, 4.0,
16898            3.0, 2.0, 1.0,
16899        );
16900        assert_eq_m512h(r, e);
16901    }
16902
16903    #[simd_test(enable = "avx512fp16,avx512vl")]
16904    const fn test_mm_set_sh() {
16905        let r = _mm_set_sh(1.0);
16906        let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0);
16907        assert_eq_m128h(r, e);
16908    }
16909
16910    #[simd_test(enable = "avx512fp16,avx512vl")]
16911    const fn test_mm_set1_ph() {
16912        let r = _mm_set1_ph(1.0);
16913        let e = _mm_set_ph(1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0);
16914        assert_eq_m128h(r, e);
16915    }
16916
16917    #[simd_test(enable = "avx512fp16,avx512vl")]
16918    const fn test_mm256_set1_ph() {
16919        let r = _mm256_set1_ph(1.0);
16920        let e = _mm256_set_ph(
16921            1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0,
16922        );
16923        assert_eq_m256h(r, e);
16924    }
16925
16926    #[simd_test(enable = "avx512fp16")]
16927    const fn test_mm512_set1_ph() {
16928        let r = _mm512_set1_ph(1.0);
16929        let e = _mm512_set_ph(
16930            1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0,
16931            1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0,
16932        );
16933        assert_eq_m512h(r, e);
16934    }
16935
16936    #[simd_test(enable = "avx512fp16,avx512vl")]
16937    const fn test_mm_setr_ph() {
16938        let r = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
16939        let e = _mm_set_ph(8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0);
16940        assert_eq_m128h(r, e);
16941    }
16942
16943    #[simd_test(enable = "avx512fp16,avx512vl")]
16944    const fn test_mm256_setr_ph() {
16945        let r = _mm256_setr_ph(
16946            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
16947        );
16948        let e = _mm256_set_ph(
16949            16.0, 15.0, 14.0, 13.0, 12.0, 11.0, 10.0, 9.0, 8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0,
16950        );
16951        assert_eq_m256h(r, e);
16952    }
16953
16954    #[simd_test(enable = "avx512fp16")]
16955    const fn test_mm512_setr_ph() {
16956        let r = _mm512_setr_ph(
16957            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
16958            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
16959            31.0, 32.0,
16960        );
16961        let e = _mm512_set_ph(
16962            32.0, 31.0, 30.0, 29.0, 28.0, 27.0, 26.0, 25.0, 24.0, 23.0, 22.0, 21.0, 20.0, 19.0,
16963            18.0, 17.0, 16.0, 15.0, 14.0, 13.0, 12.0, 11.0, 10.0, 9.0, 8.0, 7.0, 6.0, 5.0, 4.0,
16964            3.0, 2.0, 1.0,
16965        );
16966        assert_eq_m512h(r, e);
16967    }
16968
16969    #[simd_test(enable = "avx512fp16,avx512vl")]
16970    const fn test_mm_setzero_ph() {
16971        let r = _mm_setzero_ph();
16972        let e = _mm_set1_ph(0.0);
16973        assert_eq_m128h(r, e);
16974    }
16975
16976    #[simd_test(enable = "avx512fp16,avx512vl")]
16977    const fn test_mm256_setzero_ph() {
16978        let r = _mm256_setzero_ph();
16979        let e = _mm256_set1_ph(0.0);
16980        assert_eq_m256h(r, e);
16981    }
16982
16983    #[simd_test(enable = "avx512fp16")]
16984    const fn test_mm512_setzero_ph() {
16985        let r = _mm512_setzero_ph();
16986        let e = _mm512_set1_ph(0.0);
16987        assert_eq_m512h(r, e);
16988    }
16989
16990    #[simd_test(enable = "avx512fp16,avx512vl")]
16991    const fn test_mm_castsi128_ph() {
16992        let a = _mm_set1_epi16(0x3c00);
16993        let r = _mm_castsi128_ph(a);
16994        let e = _mm_set1_ph(1.0);
16995        assert_eq_m128h(r, e);
16996    }
16997
16998    #[simd_test(enable = "avx512fp16,avx512vl")]
16999    const fn test_mm256_castsi256_ph() {
17000        let a = _mm256_set1_epi16(0x3c00);
17001        let r = _mm256_castsi256_ph(a);
17002        let e = _mm256_set1_ph(1.0);
17003        assert_eq_m256h(r, e);
17004    }
17005
17006    #[simd_test(enable = "avx512fp16")]
17007    const fn test_mm512_castsi512_ph() {
17008        let a = _mm512_set1_epi16(0x3c00);
17009        let r = _mm512_castsi512_ph(a);
17010        let e = _mm512_set1_ph(1.0);
17011        assert_eq_m512h(r, e);
17012    }
17013
17014    #[simd_test(enable = "avx512fp16")]
17015    const fn test_mm_castph_si128() {
17016        let a = _mm_set1_ph(1.0);
17017        let r = _mm_castph_si128(a);
17018        let e = _mm_set1_epi16(0x3c00);
17019        assert_eq_m128i(r, e);
17020    }
17021
17022    #[simd_test(enable = "avx512fp16")]
17023    const fn test_mm256_castph_si256() {
17024        let a = _mm256_set1_ph(1.0);
17025        let r = _mm256_castph_si256(a);
17026        let e = _mm256_set1_epi16(0x3c00);
17027        assert_eq_m256i(r, e);
17028    }
17029
17030    #[simd_test(enable = "avx512fp16")]
17031    const fn test_mm512_castph_si512() {
17032        let a = _mm512_set1_ph(1.0);
17033        let r = _mm512_castph_si512(a);
17034        let e = _mm512_set1_epi16(0x3c00);
17035        assert_eq_m512i(r, e);
17036    }
17037
17038    #[simd_test(enable = "avx512fp16,avx512vl")]
17039    const fn test_mm_castps_ph() {
17040        let a = _mm_castsi128_ps(_mm_set1_epi16(0x3c00));
17041        let r = _mm_castps_ph(a);
17042        let e = _mm_set1_ph(1.0);
17043        assert_eq_m128h(r, e);
17044    }
17045
17046    #[simd_test(enable = "avx512fp16,avx512vl")]
17047    const fn test_mm256_castps_ph() {
17048        let a = _mm256_castsi256_ps(_mm256_set1_epi16(0x3c00));
17049        let r = _mm256_castps_ph(a);
17050        let e = _mm256_set1_ph(1.0);
17051        assert_eq_m256h(r, e);
17052    }
17053
17054    #[simd_test(enable = "avx512fp16")]
17055    const fn test_mm512_castps_ph() {
17056        let a = _mm512_castsi512_ps(_mm512_set1_epi16(0x3c00));
17057        let r = _mm512_castps_ph(a);
17058        let e = _mm512_set1_ph(1.0);
17059        assert_eq_m512h(r, e);
17060    }
17061
17062    #[simd_test(enable = "avx512fp16")]
17063    const fn test_mm_castph_ps() {
17064        let a = _mm_castsi128_ph(_mm_set1_epi32(0x3f800000));
17065        let r = _mm_castph_ps(a);
17066        let e = _mm_set1_ps(1.0);
17067        assert_eq_m128(r, e);
17068    }
17069
17070    #[simd_test(enable = "avx512fp16")]
17071    const fn test_mm256_castph_ps() {
17072        let a = _mm256_castsi256_ph(_mm256_set1_epi32(0x3f800000));
17073        let r = _mm256_castph_ps(a);
17074        let e = _mm256_set1_ps(1.0);
17075        assert_eq_m256(r, e);
17076    }
17077
17078    #[simd_test(enable = "avx512fp16")]
17079    const fn test_mm512_castph_ps() {
17080        let a = _mm512_castsi512_ph(_mm512_set1_epi32(0x3f800000));
17081        let r = _mm512_castph_ps(a);
17082        let e = _mm512_set1_ps(1.0);
17083        assert_eq_m512(r, e);
17084    }
17085
17086    #[simd_test(enable = "avx512fp16,avx512vl")]
17087    const fn test_mm_castpd_ph() {
17088        let a = _mm_castsi128_pd(_mm_set1_epi16(0x3c00));
17089        let r = _mm_castpd_ph(a);
17090        let e = _mm_set1_ph(1.0);
17091        assert_eq_m128h(r, e);
17092    }
17093
17094    #[simd_test(enable = "avx512fp16,avx512vl")]
17095    const fn test_mm256_castpd_ph() {
17096        let a = _mm256_castsi256_pd(_mm256_set1_epi16(0x3c00));
17097        let r = _mm256_castpd_ph(a);
17098        let e = _mm256_set1_ph(1.0);
17099        assert_eq_m256h(r, e);
17100    }
17101
17102    #[simd_test(enable = "avx512fp16")]
17103    const fn test_mm512_castpd_ph() {
17104        let a = _mm512_castsi512_pd(_mm512_set1_epi16(0x3c00));
17105        let r = _mm512_castpd_ph(a);
17106        let e = _mm512_set1_ph(1.0);
17107        assert_eq_m512h(r, e);
17108    }
17109
17110    #[simd_test(enable = "avx512fp16")]
17111    const fn test_mm_castph_pd() {
17112        let a = _mm_castsi128_ph(_mm_set1_epi64x(0x3ff0000000000000));
17113        let r = _mm_castph_pd(a);
17114        let e = _mm_set1_pd(1.0);
17115        assert_eq_m128d(r, e);
17116    }
17117
17118    #[simd_test(enable = "avx512fp16")]
17119    const fn test_mm256_castph_pd() {
17120        let a = _mm256_castsi256_ph(_mm256_set1_epi64x(0x3ff0000000000000));
17121        let r = _mm256_castph_pd(a);
17122        let e = _mm256_set1_pd(1.0);
17123        assert_eq_m256d(r, e);
17124    }
17125
17126    #[simd_test(enable = "avx512fp16")]
17127    const fn test_mm512_castph_pd() {
17128        let a = _mm512_castsi512_ph(_mm512_set1_epi64(0x3ff0000000000000));
17129        let r = _mm512_castph_pd(a);
17130        let e = _mm512_set1_pd(1.0);
17131        assert_eq_m512d(r, e);
17132    }
17133
17134    #[simd_test(enable = "avx512fp16,avx512vl")]
17135    const fn test_mm256_castph256_ph128() {
17136        let a = _mm256_setr_ph(
17137            1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
17138        );
17139        let r = _mm256_castph256_ph128(a);
17140        let e = _mm_setr_ph(1., 2., 3., 4., 5., 6., 7., 8.);
17141        assert_eq_m128h(r, e);
17142    }
17143
17144    #[simd_test(enable = "avx512fp16,avx512vl")]
17145    const fn test_mm512_castph512_ph128() {
17146        let a = _mm512_setr_ph(
17147            1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16., 17., 18., 19.,
17148            20., 21., 22., 23., 24., 25., 26., 27., 28., 29., 30., 31., 32.,
17149        );
17150        let r = _mm512_castph512_ph128(a);
17151        let e = _mm_setr_ph(1., 2., 3., 4., 5., 6., 7., 8.);
17152        assert_eq_m128h(r, e);
17153    }
17154
17155    #[simd_test(enable = "avx512fp16,avx512vl")]
17156    const fn test_mm512_castph512_ph256() {
17157        let a = _mm512_setr_ph(
17158            1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16., 17., 18., 19.,
17159            20., 21., 22., 23., 24., 25., 26., 27., 28., 29., 30., 31., 32.,
17160        );
17161        let r = _mm512_castph512_ph256(a);
17162        let e = _mm256_setr_ph(
17163            1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
17164        );
17165        assert_eq_m256h(r, e);
17166    }
17167
17168    #[simd_test(enable = "avx512fp16,avx512vl")]
17169    const fn test_mm256_castph128_ph256() {
17170        let a = _mm_setr_ph(1., 2., 3., 4., 5., 6., 7., 8.);
17171        let r = _mm256_castph128_ph256(a);
17172        assert_eq_m128h(_mm256_castph256_ph128(r), a);
17173    }
17174
17175    #[simd_test(enable = "avx512fp16,avx512vl")]
17176    const fn test_mm512_castph128_ph512() {
17177        let a = _mm_setr_ph(1., 2., 3., 4., 5., 6., 7., 8.);
17178        let r = _mm512_castph128_ph512(a);
17179        assert_eq_m128h(_mm512_castph512_ph128(r), a);
17180    }
17181
17182    #[simd_test(enable = "avx512fp16,avx512vl")]
17183    const fn test_mm512_castph256_ph512() {
17184        let a = _mm256_setr_ph(
17185            1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
17186        );
17187        let r = _mm512_castph256_ph512(a);
17188        assert_eq_m256h(_mm512_castph512_ph256(r), a);
17189    }
17190
17191    #[simd_test(enable = "avx512fp16,avx512vl")]
17192    const fn test_mm256_zextph128_ph256() {
17193        let a = _mm_setr_ph(1., 2., 3., 4., 5., 6., 7., 8.);
17194        let r = _mm256_zextph128_ph256(a);
17195        let e = _mm256_setr_ph(
17196            1., 2., 3., 4., 5., 6., 7., 8., 0., 0., 0., 0., 0., 0., 0., 0.,
17197        );
17198        assert_eq_m256h(r, e);
17199    }
17200
17201    #[simd_test(enable = "avx512fp16")]
17202    const fn test_mm512_zextph128_ph512() {
17203        let a = _mm_setr_ph(1., 2., 3., 4., 5., 6., 7., 8.);
17204        let r = _mm512_zextph128_ph512(a);
17205        let e = _mm512_setr_ph(
17206            1., 2., 3., 4., 5., 6., 7., 8., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0.,
17207            0., 0., 0., 0., 0., 0., 0., 0., 0., 0.,
17208        );
17209        assert_eq_m512h(r, e);
17210    }
17211
17212    #[simd_test(enable = "avx512fp16")]
17213    const fn test_mm512_zextph256_ph512() {
17214        let a = _mm256_setr_ph(
17215            1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
17216        );
17217        let r = _mm512_zextph256_ph512(a);
17218        let e = _mm512_setr_ph(
17219            1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16., 0., 0., 0., 0.,
17220            0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0.,
17221        );
17222        assert_eq_m512h(r, e);
17223    }
17224
17225    #[simd_test(enable = "avx512fp16,avx512vl")]
17226    fn test_mm_cmp_ph_mask() {
17227        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
17228        let b = _mm_set_ph(1.0, 2.0, 3.0, 4.0, -5.0, -6.0, -7.0, -8.0);
17229        let r = _mm_cmp_ph_mask::<_CMP_EQ_OQ>(a, b);
17230        assert_eq!(r, 0b11110000);
17231    }
17232
17233    #[simd_test(enable = "avx512fp16,avx512vl")]
17234    fn test_mm_mask_cmp_ph_mask() {
17235        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
17236        let b = _mm_set_ph(1.0, 2.0, 3.0, 4.0, -5.0, -6.0, -7.0, -8.0);
17237        let r = _mm_mask_cmp_ph_mask::<_CMP_EQ_OQ>(0b01010101, a, b);
17238        assert_eq!(r, 0b01010000);
17239    }
17240
17241    #[simd_test(enable = "avx512fp16,avx512vl")]
17242    fn test_mm256_cmp_ph_mask() {
17243        let a = _mm256_set_ph(
17244            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
17245        );
17246        let b = _mm256_set_ph(
17247            1.0, 2.0, 3.0, 4.0, -5.0, -6.0, -7.0, -8.0, 9.0, 10.0, 11.0, 12.0, -13.0, -14.0, -15.0,
17248            -16.0,
17249        );
17250        let r = _mm256_cmp_ph_mask::<_CMP_EQ_OQ>(a, b);
17251        assert_eq!(r, 0b1111000011110000);
17252    }
17253
17254    #[simd_test(enable = "avx512fp16,avx512vl")]
17255    fn test_mm256_mask_cmp_ph_mask() {
17256        let a = _mm256_set_ph(
17257            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
17258        );
17259        let b = _mm256_set_ph(
17260            1.0, 2.0, 3.0, 4.0, -5.0, -6.0, -7.0, -8.0, 9.0, 10.0, 11.0, 12.0, -13.0, -14.0, -15.0,
17261            -16.0,
17262        );
17263        let r = _mm256_mask_cmp_ph_mask::<_CMP_EQ_OQ>(0b0101010101010101, a, b);
17264        assert_eq!(r, 0b0101000001010000);
17265    }
17266
17267    #[simd_test(enable = "avx512fp16")]
17268    fn test_mm512_cmp_ph_mask() {
17269        let a = _mm512_set_ph(
17270            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
17271            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
17272            31.0, 32.0,
17273        );
17274        let b = _mm512_set_ph(
17275            1.0, 2.0, 3.0, 4.0, -5.0, -6.0, -7.0, -8.0, 9.0, 10.0, 11.0, 12.0, -13.0, -14.0, -15.0,
17276            -16.0, 17.0, 18.0, 19.0, 20.0, -21.0, -22.0, -23.0, -24.0, 25.0, 26.0, 27.0, 28.0,
17277            -29.0, -30.0, -31.0, -32.0,
17278        );
17279        let r = _mm512_cmp_ph_mask::<_CMP_EQ_OQ>(a, b);
17280        assert_eq!(r, 0b11110000111100001111000011110000);
17281    }
17282
17283    #[simd_test(enable = "avx512fp16")]
17284    fn test_mm512_mask_cmp_ph_mask() {
17285        let a = _mm512_set_ph(
17286            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
17287            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
17288            31.0, 32.0,
17289        );
17290        let b = _mm512_set_ph(
17291            1.0, 2.0, 3.0, 4.0, -5.0, -6.0, -7.0, -8.0, 9.0, 10.0, 11.0, 12.0, -13.0, -14.0, -15.0,
17292            -16.0, 17.0, 18.0, 19.0, 20.0, -21.0, -22.0, -23.0, -24.0, 25.0, 26.0, 27.0, 28.0,
17293            -29.0, -30.0, -31.0, -32.0,
17294        );
17295        let r = _mm512_mask_cmp_ph_mask::<_CMP_EQ_OQ>(0b01010101010101010101010101010101, a, b);
17296        assert_eq!(r, 0b01010000010100000101000001010000);
17297    }
17298
17299    #[simd_test(enable = "avx512fp16")]
17300    fn test_mm512_cmp_round_ph_mask() {
17301        let a = _mm512_set_ph(
17302            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
17303            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
17304            31.0, 32.0,
17305        );
17306        let b = _mm512_set_ph(
17307            1.0, 2.0, 3.0, 4.0, -5.0, -6.0, -7.0, -8.0, 9.0, 10.0, 11.0, 12.0, -13.0, -14.0, -15.0,
17308            -16.0, 17.0, 18.0, 19.0, 20.0, -21.0, -22.0, -23.0, -24.0, 25.0, 26.0, 27.0, 28.0,
17309            -29.0, -30.0, -31.0, -32.0,
17310        );
17311        let r = _mm512_cmp_round_ph_mask::<_CMP_EQ_OQ, _MM_FROUND_NO_EXC>(a, b);
17312        assert_eq!(r, 0b11110000111100001111000011110000);
17313    }
17314
17315    #[simd_test(enable = "avx512fp16")]
17316    fn test_mm512_mask_cmp_round_ph_mask() {
17317        let a = _mm512_set_ph(
17318            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
17319            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
17320            31.0, 32.0,
17321        );
17322        let b = _mm512_set_ph(
17323            1.0, 2.0, 3.0, 4.0, -5.0, -6.0, -7.0, -8.0, 9.0, 10.0, 11.0, 12.0, -13.0, -14.0, -15.0,
17324            -16.0, 17.0, 18.0, 19.0, 20.0, -21.0, -22.0, -23.0, -24.0, 25.0, 26.0, 27.0, 28.0,
17325            -29.0, -30.0, -31.0, -32.0,
17326        );
17327        let r = _mm512_mask_cmp_round_ph_mask::<_CMP_EQ_OQ, _MM_FROUND_NO_EXC>(
17328            0b01010101010101010101010101010101,
17329            a,
17330            b,
17331        );
17332        assert_eq!(r, 0b01010000010100000101000001010000);
17333    }
17334
17335    #[simd_test(enable = "avx512fp16")]
17336    fn test_mm_cmp_round_sh_mask() {
17337        let a = _mm_set_sh(1.0);
17338        let b = _mm_set_sh(1.0);
17339        let r = _mm_cmp_round_sh_mask::<_CMP_EQ_OQ, _MM_FROUND_NO_EXC>(a, b);
17340        assert_eq!(r, 1);
17341    }
17342
17343    #[simd_test(enable = "avx512fp16")]
17344    fn test_mm_mask_cmp_round_sh_mask() {
17345        let a = _mm_set_sh(1.0);
17346        let b = _mm_set_sh(1.0);
17347        let r = _mm_mask_cmp_round_sh_mask::<_CMP_EQ_OQ, _MM_FROUND_NO_EXC>(0, a, b);
17348        assert_eq!(r, 0);
17349    }
17350
17351    #[simd_test(enable = "avx512fp16")]
17352    fn test_mm_cmp_sh_mask() {
17353        let a = _mm_set_sh(1.0);
17354        let b = _mm_set_sh(1.0);
17355        let r = _mm_cmp_sh_mask::<_CMP_EQ_OQ>(a, b);
17356        assert_eq!(r, 1);
17357    }
17358
17359    #[simd_test(enable = "avx512fp16")]
17360    fn test_mm_mask_cmp_sh_mask() {
17361        let a = _mm_set_sh(1.0);
17362        let b = _mm_set_sh(1.0);
17363        let r = _mm_mask_cmp_sh_mask::<_CMP_EQ_OQ>(0, a, b);
17364        assert_eq!(r, 0);
17365    }
17366
17367    #[simd_test(enable = "avx512fp16")]
17368    fn test_mm_comi_round_sh() {
17369        let a = _mm_set_sh(1.0);
17370        let b = _mm_set_sh(1.0);
17371        let r = _mm_comi_round_sh::<_CMP_EQ_OQ, _MM_FROUND_NO_EXC>(a, b);
17372        assert_eq!(r, 1);
17373    }
17374
17375    #[simd_test(enable = "avx512fp16")]
17376    fn test_mm_comi_sh() {
17377        let a = _mm_set_sh(1.0);
17378        let b = _mm_set_sh(1.0);
17379        let r = _mm_comi_sh::<_CMP_EQ_OQ>(a, b);
17380        assert_eq!(r, 1);
17381    }
17382
17383    #[simd_test(enable = "avx512fp16")]
17384    fn test_mm_comieq_sh() {
17385        let a = _mm_set_sh(1.0);
17386        let b = _mm_set_sh(1.0);
17387        let r = _mm_comieq_sh(a, b);
17388        assert_eq!(r, 1);
17389    }
17390
17391    #[simd_test(enable = "avx512fp16")]
17392    fn test_mm_comige_sh() {
17393        let a = _mm_set_sh(2.0);
17394        let b = _mm_set_sh(1.0);
17395        let r = _mm_comige_sh(a, b);
17396        assert_eq!(r, 1);
17397    }
17398
17399    #[simd_test(enable = "avx512fp16")]
17400    fn test_mm_comigt_sh() {
17401        let a = _mm_set_sh(2.0);
17402        let b = _mm_set_sh(1.0);
17403        let r = _mm_comigt_sh(a, b);
17404        assert_eq!(r, 1);
17405    }
17406
17407    #[simd_test(enable = "avx512fp16")]
17408    fn test_mm_comile_sh() {
17409        let a = _mm_set_sh(1.0);
17410        let b = _mm_set_sh(2.0);
17411        let r = _mm_comile_sh(a, b);
17412        assert_eq!(r, 1);
17413    }
17414
17415    #[simd_test(enable = "avx512fp16")]
17416    fn test_mm_comilt_sh() {
17417        let a = _mm_set_sh(1.0);
17418        let b = _mm_set_sh(2.0);
17419        let r = _mm_comilt_sh(a, b);
17420        assert_eq!(r, 1);
17421    }
17422
17423    #[simd_test(enable = "avx512fp16")]
17424    fn test_mm_comineq_sh() {
17425        let a = _mm_set_sh(1.0);
17426        let b = _mm_set_sh(2.0);
17427        let r = _mm_comineq_sh(a, b);
17428        assert_eq!(r, 1);
17429    }
17430
17431    #[simd_test(enable = "avx512fp16")]
17432    fn test_mm_ucomieq_sh() {
17433        let a = _mm_set_sh(1.0);
17434        let b = _mm_set_sh(1.0);
17435        let r = _mm_ucomieq_sh(a, b);
17436        assert_eq!(r, 1);
17437    }
17438
17439    #[simd_test(enable = "avx512fp16")]
17440    fn test_mm_ucomige_sh() {
17441        let a = _mm_set_sh(2.0);
17442        let b = _mm_set_sh(1.0);
17443        let r = _mm_ucomige_sh(a, b);
17444        assert_eq!(r, 1);
17445    }
17446
17447    #[simd_test(enable = "avx512fp16")]
17448    fn test_mm_ucomigt_sh() {
17449        let a = _mm_set_sh(2.0);
17450        let b = _mm_set_sh(1.0);
17451        let r = _mm_ucomigt_sh(a, b);
17452        assert_eq!(r, 1);
17453    }
17454
17455    #[simd_test(enable = "avx512fp16")]
17456    fn test_mm_ucomile_sh() {
17457        let a = _mm_set_sh(1.0);
17458        let b = _mm_set_sh(2.0);
17459        let r = _mm_ucomile_sh(a, b);
17460        assert_eq!(r, 1);
17461    }
17462
17463    #[simd_test(enable = "avx512fp16")]
17464    fn test_mm_ucomilt_sh() {
17465        let a = _mm_set_sh(1.0);
17466        let b = _mm_set_sh(2.0);
17467        let r = _mm_ucomilt_sh(a, b);
17468        assert_eq!(r, 1);
17469    }
17470
17471    #[simd_test(enable = "avx512fp16")]
17472    fn test_mm_ucomineq_sh() {
17473        let a = _mm_set_sh(1.0);
17474        let b = _mm_set_sh(2.0);
17475        let r = _mm_ucomineq_sh(a, b);
17476        assert_eq!(r, 1);
17477    }
17478
17479    #[simd_test(enable = "avx512fp16,avx512vl")]
17480    const fn test_mm_load_ph() {
17481        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
17482        let b = unsafe { _mm_load_ph(addr_of!(a).cast()) };
17483        assert_eq_m128h(a, b);
17484    }
17485
17486    #[simd_test(enable = "avx512fp16,avx512vl")]
17487    const fn test_mm256_load_ph() {
17488        let a = _mm256_set_ph(
17489            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
17490        );
17491        let b = unsafe { _mm256_load_ph(addr_of!(a).cast()) };
17492        assert_eq_m256h(a, b);
17493    }
17494
17495    #[simd_test(enable = "avx512fp16")]
17496    const fn test_mm512_load_ph() {
17497        let a = _mm512_set_ph(
17498            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
17499            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
17500            31.0, 32.0,
17501        );
17502        let b = unsafe { _mm512_load_ph(addr_of!(a).cast()) };
17503        assert_eq_m512h(a, b);
17504    }
17505
17506    #[simd_test(enable = "avx512fp16,avx512vl")]
17507    const fn test_mm_load_sh() {
17508        let a = _mm_set_sh(1.0);
17509        let b = unsafe { _mm_load_sh(addr_of!(a).cast()) };
17510        assert_eq_m128h(a, b);
17511    }
17512
17513    #[simd_test(enable = "avx512fp16,avx512vl")]
17514    fn test_mm_mask_load_sh() {
17515        let a = _mm_set_sh(1.0);
17516        let src = _mm_set_sh(2.);
17517        let b = unsafe { _mm_mask_load_sh(src, 1, addr_of!(a).cast()) };
17518        assert_eq_m128h(a, b);
17519        let b = unsafe { _mm_mask_load_sh(src, 0, addr_of!(a).cast()) };
17520        assert_eq_m128h(src, b);
17521    }
17522
17523    #[simd_test(enable = "avx512fp16,avx512vl")]
17524    fn test_mm_maskz_load_sh() {
17525        let a = _mm_set_sh(1.0);
17526        let b = unsafe { _mm_maskz_load_sh(1, addr_of!(a).cast()) };
17527        assert_eq_m128h(a, b);
17528        let b = unsafe { _mm_maskz_load_sh(0, addr_of!(a).cast()) };
17529        assert_eq_m128h(_mm_setzero_ph(), b);
17530    }
17531
17532    #[simd_test(enable = "avx512fp16,avx512vl")]
17533    const fn test_mm_loadu_ph() {
17534        let array = [1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0];
17535        let r = unsafe { _mm_loadu_ph(array.as_ptr()) };
17536        let e = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
17537        assert_eq_m128h(r, e);
17538    }
17539
17540    #[simd_test(enable = "avx512fp16,avx512vl")]
17541    const fn test_mm256_loadu_ph() {
17542        let array = [
17543            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
17544        ];
17545        let r = unsafe { _mm256_loadu_ph(array.as_ptr()) };
17546        let e = _mm256_setr_ph(
17547            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
17548        );
17549        assert_eq_m256h(r, e);
17550    }
17551
17552    #[simd_test(enable = "avx512fp16")]
17553    const fn test_mm512_loadu_ph() {
17554        let array = [
17555            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
17556            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
17557            31.0, 32.0,
17558        ];
17559        let r = unsafe { _mm512_loadu_ph(array.as_ptr()) };
17560        let e = _mm512_setr_ph(
17561            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
17562            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
17563            31.0, 32.0,
17564        );
17565        assert_eq_m512h(r, e);
17566    }
17567
17568    #[simd_test(enable = "avx512fp16,avx512vl")]
17569    const fn test_mm_move_sh() {
17570        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
17571        let b = _mm_set_sh(9.0);
17572        let r = _mm_move_sh(a, b);
17573        let e = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 9.0);
17574        assert_eq_m128h(r, e);
17575    }
17576
17577    #[simd_test(enable = "avx512fp16,avx512vl")]
17578    const fn test_mm_mask_move_sh() {
17579        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
17580        let b = _mm_set_sh(9.0);
17581        let src = _mm_set_sh(10.0);
17582        let r = _mm_mask_move_sh(src, 0, a, b);
17583        let e = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 10.0);
17584        assert_eq_m128h(r, e);
17585    }
17586
17587    #[simd_test(enable = "avx512fp16,avx512vl")]
17588    const fn test_mm_maskz_move_sh() {
17589        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
17590        let b = _mm_set_sh(9.0);
17591        let r = _mm_maskz_move_sh(0, a, b);
17592        let e = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 0.0);
17593        assert_eq_m128h(r, e);
17594    }
17595
17596    #[simd_test(enable = "avx512fp16,avx512vl")]
17597    const fn test_mm_store_ph() {
17598        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
17599        let mut b = _mm_setzero_ph();
17600        unsafe {
17601            _mm_store_ph(addr_of_mut!(b).cast(), a);
17602        }
17603        assert_eq_m128h(a, b);
17604    }
17605
17606    #[simd_test(enable = "avx512fp16,avx512vl")]
17607    const fn test_mm256_store_ph() {
17608        let a = _mm256_set_ph(
17609            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
17610        );
17611        let mut b = _mm256_setzero_ph();
17612        unsafe {
17613            _mm256_store_ph(addr_of_mut!(b).cast(), a);
17614        }
17615        assert_eq_m256h(a, b);
17616    }
17617
17618    #[simd_test(enable = "avx512fp16")]
17619    const fn test_mm512_store_ph() {
17620        let a = _mm512_set_ph(
17621            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
17622            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
17623            31.0, 32.0,
17624        );
17625        let mut b = _mm512_setzero_ph();
17626        unsafe {
17627            _mm512_store_ph(addr_of_mut!(b).cast(), a);
17628        }
17629        assert_eq_m512h(a, b);
17630    }
17631
17632    #[simd_test(enable = "avx512fp16,avx512vl")]
17633    const fn test_mm_store_sh() {
17634        let a = _mm_set_sh(1.0);
17635        let mut b = _mm_setzero_ph();
17636        unsafe {
17637            _mm_store_sh(addr_of_mut!(b).cast(), a);
17638        }
17639        assert_eq_m128h(a, b);
17640    }
17641
17642    #[simd_test(enable = "avx512fp16,avx512vl")]
17643    fn test_mm_mask_store_sh() {
17644        let a = _mm_set_sh(1.0);
17645        let mut b = _mm_setzero_ph();
17646        unsafe {
17647            _mm_mask_store_sh(addr_of_mut!(b).cast(), 0, a);
17648        }
17649        assert_eq_m128h(_mm_setzero_ph(), b);
17650        unsafe {
17651            _mm_mask_store_sh(addr_of_mut!(b).cast(), 1, a);
17652        }
17653        assert_eq_m128h(a, b);
17654    }
17655
17656    #[simd_test(enable = "avx512fp16,avx512vl")]
17657    const fn test_mm_storeu_ph() {
17658        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
17659        let mut array = [0.0; 8];
17660        unsafe {
17661            _mm_storeu_ph(array.as_mut_ptr(), a);
17662        }
17663        assert_eq_m128h(a, unsafe { _mm_loadu_ph(array.as_ptr()) });
17664    }
17665
17666    #[simd_test(enable = "avx512fp16,avx512vl")]
17667    const fn test_mm256_storeu_ph() {
17668        let a = _mm256_set_ph(
17669            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
17670        );
17671        let mut array = [0.0; 16];
17672        unsafe {
17673            _mm256_storeu_ph(array.as_mut_ptr(), a);
17674        }
17675        assert_eq_m256h(a, unsafe { _mm256_loadu_ph(array.as_ptr()) });
17676    }
17677
17678    #[simd_test(enable = "avx512fp16")]
17679    const fn test_mm512_storeu_ph() {
17680        let a = _mm512_set_ph(
17681            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
17682            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
17683            31.0, 32.0,
17684        );
17685        let mut array = [0.0; 32];
17686        unsafe {
17687            _mm512_storeu_ph(array.as_mut_ptr(), a);
17688        }
17689        assert_eq_m512h(a, unsafe { _mm512_loadu_ph(array.as_ptr()) });
17690    }
17691
17692    #[simd_test(enable = "avx512fp16,avx512vl")]
17693    const fn test_mm_add_ph() {
17694        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
17695        let b = _mm_set_ph(8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0);
17696        let r = _mm_add_ph(a, b);
17697        let e = _mm_set1_ph(9.0);
17698        assert_eq_m128h(r, e);
17699    }
17700
17701    #[simd_test(enable = "avx512fp16,avx512vl")]
17702    const fn test_mm_mask_add_ph() {
17703        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
17704        let b = _mm_set_ph(8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0);
17705        let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
17706        let r = _mm_mask_add_ph(src, 0b01010101, a, b);
17707        let e = _mm_set_ph(10., 9., 12., 9., 14., 9., 16., 9.);
17708        assert_eq_m128h(r, e);
17709    }
17710
17711    #[simd_test(enable = "avx512fp16,avx512vl")]
17712    const fn test_mm_maskz_add_ph() {
17713        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
17714        let b = _mm_set_ph(8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0);
17715        let r = _mm_maskz_add_ph(0b01010101, a, b);
17716        let e = _mm_set_ph(0., 9., 0., 9., 0., 9., 0., 9.);
17717        assert_eq_m128h(r, e);
17718    }
17719
17720    #[simd_test(enable = "avx512fp16,avx512vl")]
17721    const fn test_mm256_add_ph() {
17722        let a = _mm256_set_ph(
17723            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
17724        );
17725        let b = _mm256_set_ph(
17726            16.0, 15.0, 14.0, 13.0, 12.0, 11.0, 10.0, 9.0, 8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0,
17727        );
17728        let r = _mm256_add_ph(a, b);
17729        let e = _mm256_set1_ph(17.0);
17730        assert_eq_m256h(r, e);
17731    }
17732
17733    #[simd_test(enable = "avx512fp16,avx512vl")]
17734    const fn test_mm256_mask_add_ph() {
17735        let a = _mm256_set_ph(
17736            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
17737        );
17738        let b = _mm256_set_ph(
17739            16.0, 15.0, 14.0, 13.0, 12.0, 11.0, 10.0, 9.0, 8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0,
17740        );
17741        let src = _mm256_set_ph(
17742            18., 19., 20., 21., 22., 23., 24., 25., 26., 27., 28., 29., 30., 31., 32., 33.,
17743        );
17744        let r = _mm256_mask_add_ph(src, 0b0101010101010101, a, b);
17745        let e = _mm256_set_ph(
17746            18., 17., 20., 17., 22., 17., 24., 17., 26., 17., 28., 17., 30., 17., 32., 17.,
17747        );
17748        assert_eq_m256h(r, e);
17749    }
17750
17751    #[simd_test(enable = "avx512fp16,avx512vl")]
17752    const fn test_mm256_maskz_add_ph() {
17753        let a = _mm256_set_ph(
17754            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
17755        );
17756        let b = _mm256_set_ph(
17757            16.0, 15.0, 14.0, 13.0, 12.0, 11.0, 10.0, 9.0, 8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0,
17758        );
17759        let r = _mm256_maskz_add_ph(0b0101010101010101, a, b);
17760        let e = _mm256_set_ph(
17761            0., 17., 0., 17., 0., 17., 0., 17., 0., 17., 0., 17., 0., 17., 0., 17.,
17762        );
17763        assert_eq_m256h(r, e);
17764    }
17765
17766    #[simd_test(enable = "avx512fp16")]
17767    const fn test_mm512_add_ph() {
17768        let a = _mm512_set_ph(
17769            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
17770            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
17771            31.0, 32.0,
17772        );
17773        let b = _mm512_set_ph(
17774            32.0, 31.0, 30.0, 29.0, 28.0, 27.0, 26.0, 25.0, 24.0, 23.0, 22.0, 21.0, 20.0, 19.0,
17775            18.0, 17.0, 16.0, 15.0, 14.0, 13.0, 12.0, 11.0, 10.0, 9.0, 8.0, 7.0, 6.0, 5.0, 4.0,
17776            3.0, 2.0, 1.0,
17777        );
17778        let r = _mm512_add_ph(a, b);
17779        let e = _mm512_set1_ph(33.0);
17780        assert_eq_m512h(r, e);
17781    }
17782
17783    #[simd_test(enable = "avx512fp16")]
17784    const fn test_mm512_mask_add_ph() {
17785        let a = _mm512_set_ph(
17786            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
17787            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
17788            31.0, 32.0,
17789        );
17790        let b = _mm512_set_ph(
17791            32.0, 31.0, 30.0, 29.0, 28.0, 27.0, 26.0, 25.0, 24.0, 23.0, 22.0, 21.0, 20.0, 19.0,
17792            18.0, 17.0, 16.0, 15.0, 14.0, 13.0, 12.0, 11.0, 10.0, 9.0, 8.0, 7.0, 6.0, 5.0, 4.0,
17793            3.0, 2.0, 1.0,
17794        );
17795        let src = _mm512_set_ph(
17796            34., 35., 36., 37., 38., 39., 40., 41., 42., 43., 44., 45., 46., 47., 48., 49., 50.,
17797            51., 52., 53., 54., 55., 56., 57., 58., 59., 60., 61., 62., 63., 64., 65.,
17798        );
17799        let r = _mm512_mask_add_ph(src, 0b01010101010101010101010101010101, a, b);
17800        let e = _mm512_set_ph(
17801            34., 33., 36., 33., 38., 33., 40., 33., 42., 33., 44., 33., 46., 33., 48., 33., 50.,
17802            33., 52., 33., 54., 33., 56., 33., 58., 33., 60., 33., 62., 33., 64., 33.,
17803        );
17804        assert_eq_m512h(r, e);
17805    }
17806
17807    #[simd_test(enable = "avx512fp16")]
17808    const fn test_mm512_maskz_add_ph() {
17809        let a = _mm512_set_ph(
17810            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
17811            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
17812            31.0, 32.0,
17813        );
17814        let b = _mm512_set_ph(
17815            32.0, 31.0, 30.0, 29.0, 28.0, 27.0, 26.0, 25.0, 24.0, 23.0, 22.0, 21.0, 20.0, 19.0,
17816            18.0, 17.0, 16.0, 15.0, 14.0, 13.0, 12.0, 11.0, 10.0, 9.0, 8.0, 7.0, 6.0, 5.0, 4.0,
17817            3.0, 2.0, 1.0,
17818        );
17819        let r = _mm512_maskz_add_ph(0b01010101010101010101010101010101, a, b);
17820        let e = _mm512_set_ph(
17821            0., 33., 0., 33., 0., 33., 0., 33., 0., 33., 0., 33., 0., 33., 0., 33., 0., 33., 0.,
17822            33., 0., 33., 0., 33., 0., 33., 0., 33., 0., 33., 0., 33.,
17823        );
17824        assert_eq_m512h(r, e);
17825    }
17826
17827    #[simd_test(enable = "avx512fp16")]
17828    fn test_mm512_add_round_ph() {
17829        let a = _mm512_set_ph(
17830            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
17831            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
17832            31.0, 32.0,
17833        );
17834        let b = _mm512_set_ph(
17835            32.0, 31.0, 30.0, 29.0, 28.0, 27.0, 26.0, 25.0, 24.0, 23.0, 22.0, 21.0, 20.0, 19.0,
17836            18.0, 17.0, 16.0, 15.0, 14.0, 13.0, 12.0, 11.0, 10.0, 9.0, 8.0, 7.0, 6.0, 5.0, 4.0,
17837            3.0, 2.0, 1.0,
17838        );
17839        let r = _mm512_add_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
17840        let e = _mm512_set1_ph(33.0);
17841        assert_eq_m512h(r, e);
17842    }
17843
17844    #[simd_test(enable = "avx512fp16")]
17845    fn test_mm512_mask_add_round_ph() {
17846        let a = _mm512_set_ph(
17847            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
17848            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
17849            31.0, 32.0,
17850        );
17851        let b = _mm512_set_ph(
17852            32.0, 31.0, 30.0, 29.0, 28.0, 27.0, 26.0, 25.0, 24.0, 23.0, 22.0, 21.0, 20.0, 19.0,
17853            18.0, 17.0, 16.0, 15.0, 14.0, 13.0, 12.0, 11.0, 10.0, 9.0, 8.0, 7.0, 6.0, 5.0, 4.0,
17854            3.0, 2.0, 1.0,
17855        );
17856        let src = _mm512_set_ph(
17857            34., 35., 36., 37., 38., 39., 40., 41., 42., 43., 44., 45., 46., 47., 48., 49., 50.,
17858            51., 52., 53., 54., 55., 56., 57., 58., 59., 60., 61., 62., 63., 64., 65.,
17859        );
17860        let r = _mm512_mask_add_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
17861            src,
17862            0b01010101010101010101010101010101,
17863            a,
17864            b,
17865        );
17866        let e = _mm512_set_ph(
17867            34., 33., 36., 33., 38., 33., 40., 33., 42., 33., 44., 33., 46., 33., 48., 33., 50.,
17868            33., 52., 33., 54., 33., 56., 33., 58., 33., 60., 33., 62., 33., 64., 33.,
17869        );
17870        assert_eq_m512h(r, e);
17871    }
17872
17873    #[simd_test(enable = "avx512fp16")]
17874    fn test_mm512_maskz_add_round_ph() {
17875        let a = _mm512_set_ph(
17876            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
17877            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
17878            31.0, 32.0,
17879        );
17880        let b = _mm512_set_ph(
17881            32.0, 31.0, 30.0, 29.0, 28.0, 27.0, 26.0, 25.0, 24.0, 23.0, 22.0, 21.0, 20.0, 19.0,
17882            18.0, 17.0, 16.0, 15.0, 14.0, 13.0, 12.0, 11.0, 10.0, 9.0, 8.0, 7.0, 6.0, 5.0, 4.0,
17883            3.0, 2.0, 1.0,
17884        );
17885        let r = _mm512_maskz_add_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
17886            0b01010101010101010101010101010101,
17887            a,
17888            b,
17889        );
17890        let e = _mm512_set_ph(
17891            0., 33., 0., 33., 0., 33., 0., 33., 0., 33., 0., 33., 0., 33., 0., 33., 0., 33., 0.,
17892            33., 0., 33., 0., 33., 0., 33., 0., 33., 0., 33., 0., 33.,
17893        );
17894        assert_eq_m512h(r, e);
17895    }
17896
17897    #[simd_test(enable = "avx512fp16,avx512vl")]
17898    fn test_mm_add_round_sh() {
17899        let a = _mm_set_sh(1.0);
17900        let b = _mm_set_sh(2.0);
17901        let r = _mm_add_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
17902        let e = _mm_set_sh(3.0);
17903        assert_eq_m128h(r, e);
17904    }
17905
17906    #[simd_test(enable = "avx512fp16,avx512vl")]
17907    fn test_mm_mask_add_round_sh() {
17908        let a = _mm_set_sh(1.0);
17909        let b = _mm_set_sh(2.0);
17910        let src = _mm_set_sh(4.0);
17911        let r = _mm_mask_add_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
17912            src, 0, a, b,
17913        );
17914        let e = _mm_set_sh(4.0);
17915        assert_eq_m128h(r, e);
17916        let r = _mm_mask_add_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
17917            src, 1, a, b,
17918        );
17919        let e = _mm_set_sh(3.0);
17920        assert_eq_m128h(r, e);
17921    }
17922
17923    #[simd_test(enable = "avx512fp16,avx512vl")]
17924    fn test_mm_maskz_add_round_sh() {
17925        let a = _mm_set_sh(1.0);
17926        let b = _mm_set_sh(2.0);
17927        let r =
17928            _mm_maskz_add_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
17929        let e = _mm_set_sh(0.0);
17930        assert_eq_m128h(r, e);
17931        let r =
17932            _mm_maskz_add_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(1, a, b);
17933        let e = _mm_set_sh(3.0);
17934        assert_eq_m128h(r, e);
17935    }
17936
17937    #[simd_test(enable = "avx512fp16,avx512vl")]
17938    const fn test_mm_add_sh() {
17939        let a = _mm_set_sh(1.0);
17940        let b = _mm_set_sh(2.0);
17941        let r = _mm_add_sh(a, b);
17942        let e = _mm_set_sh(3.0);
17943        assert_eq_m128h(r, e);
17944    }
17945
17946    #[simd_test(enable = "avx512fp16,avx512vl")]
17947    const fn test_mm_mask_add_sh() {
17948        let a = _mm_set_sh(1.0);
17949        let b = _mm_set_sh(2.0);
17950        let src = _mm_set_sh(4.0);
17951        let r = _mm_mask_add_sh(src, 0, a, b);
17952        let e = _mm_set_sh(4.0);
17953        assert_eq_m128h(r, e);
17954        let r = _mm_mask_add_sh(src, 1, a, b);
17955        let e = _mm_set_sh(3.0);
17956        assert_eq_m128h(r, e);
17957    }
17958
17959    #[simd_test(enable = "avx512fp16,avx512vl")]
17960    const fn test_mm_maskz_add_sh() {
17961        let a = _mm_set_sh(1.0);
17962        let b = _mm_set_sh(2.0);
17963        let r = _mm_maskz_add_sh(0, a, b);
17964        let e = _mm_set_sh(0.0);
17965        assert_eq_m128h(r, e);
17966        let r = _mm_maskz_add_sh(1, a, b);
17967        let e = _mm_set_sh(3.0);
17968        assert_eq_m128h(r, e);
17969    }
17970
17971    #[simd_test(enable = "avx512fp16,avx512vl")]
17972    const fn test_mm_sub_ph() {
17973        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
17974        let b = _mm_set_ph(8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0);
17975        let r = _mm_sub_ph(a, b);
17976        let e = _mm_set_ph(-7.0, -5.0, -3.0, -1.0, 1.0, 3.0, 5.0, 7.0);
17977        assert_eq_m128h(r, e);
17978    }
17979
17980    #[simd_test(enable = "avx512fp16,avx512vl")]
17981    const fn test_mm_mask_sub_ph() {
17982        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
17983        let b = _mm_set_ph(8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0);
17984        let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
17985        let r = _mm_mask_sub_ph(src, 0b01010101, a, b);
17986        let e = _mm_set_ph(10., -5., 12., -1., 14., 3., 16., 7.);
17987        assert_eq_m128h(r, e);
17988    }
17989
17990    #[simd_test(enable = "avx512fp16,avx512vl")]
17991    const fn test_mm_maskz_sub_ph() {
17992        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
17993        let b = _mm_set_ph(8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0);
17994        let r = _mm_maskz_sub_ph(0b01010101, a, b);
17995        let e = _mm_set_ph(0., -5., 0., -1., 0., 3., 0., 7.);
17996        assert_eq_m128h(r, e);
17997    }
17998
17999    #[simd_test(enable = "avx512fp16,avx512vl")]
18000    const fn test_mm256_sub_ph() {
18001        let a = _mm256_set_ph(
18002            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
18003        );
18004        let b = _mm256_set_ph(
18005            16.0, 15.0, 14.0, 13.0, 12.0, 11.0, 10.0, 9.0, 8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0,
18006        );
18007        let r = _mm256_sub_ph(a, b);
18008        let e = _mm256_set_ph(
18009            -15.0, -13.0, -11.0, -9.0, -7.0, -5.0, -3.0, -1.0, 1.0, 3.0, 5.0, 7.0, 9.0, 11.0, 13.0,
18010            15.0,
18011        );
18012        assert_eq_m256h(r, e);
18013    }
18014
18015    #[simd_test(enable = "avx512fp16,avx512vl")]
18016    const fn test_mm256_mask_sub_ph() {
18017        let a = _mm256_set_ph(
18018            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
18019        );
18020        let b = _mm256_set_ph(
18021            16.0, 15.0, 14.0, 13.0, 12.0, 11.0, 10.0, 9.0, 8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0,
18022        );
18023        let src = _mm256_set_ph(
18024            18., 19., 20., 21., 22., 23., 24., 25., 26., 27., 28., 29., 30., 31., 32., 33.,
18025        );
18026        let r = _mm256_mask_sub_ph(src, 0b0101010101010101, a, b);
18027        let e = _mm256_set_ph(
18028            18., -13., 20., -9., 22., -5., 24., -1., 26., 3., 28., 7., 30., 11., 32., 15.,
18029        );
18030        assert_eq_m256h(r, e);
18031    }
18032
18033    #[simd_test(enable = "avx512fp16,avx512vl")]
18034    const fn test_mm256_maskz_sub_ph() {
18035        let a = _mm256_set_ph(
18036            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
18037        );
18038        let b = _mm256_set_ph(
18039            16.0, 15.0, 14.0, 13.0, 12.0, 11.0, 10.0, 9.0, 8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0,
18040        );
18041        let r = _mm256_maskz_sub_ph(0b0101010101010101, a, b);
18042        let e = _mm256_set_ph(
18043            0., -13., 0., -9., 0., -5., 0., -1., 0., 3., 0., 7., 0., 11., 0., 15.,
18044        );
18045        assert_eq_m256h(r, e);
18046    }
18047
18048    #[simd_test(enable = "avx512fp16")]
18049    const fn test_mm512_sub_ph() {
18050        let a = _mm512_set_ph(
18051            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
18052            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
18053            31.0, 32.0,
18054        );
18055        let b = _mm512_set_ph(
18056            32.0, 31.0, 30.0, 29.0, 28.0, 27.0, 26.0, 25.0, 24.0, 23.0, 22.0, 21.0, 20.0, 19.0,
18057            18.0, 17.0, 16.0, 15.0, 14.0, 13.0, 12.0, 11.0, 10.0, 9.0, 8.0, 7.0, 6.0, 5.0, 4.0,
18058            3.0, 2.0, 1.0,
18059        );
18060        let r = _mm512_sub_ph(a, b);
18061        let e = _mm512_set_ph(
18062            -31.0, -29.0, -27.0, -25.0, -23.0, -21.0, -19.0, -17.0, -15.0, -13.0, -11.0, -9.0,
18063            -7.0, -5.0, -3.0, -1.0, 1.0, 3.0, 5.0, 7.0, 9.0, 11.0, 13.0, 15.0, 17.0, 19.0, 21.0,
18064            23.0, 25.0, 27.0, 29.0, 31.0,
18065        );
18066        assert_eq_m512h(r, e);
18067    }
18068
18069    #[simd_test(enable = "avx512fp16")]
18070    const fn test_mm512_mask_sub_ph() {
18071        let a = _mm512_set_ph(
18072            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
18073            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
18074            31.0, 32.0,
18075        );
18076        let b = _mm512_set_ph(
18077            32.0, 31.0, 30.0, 29.0, 28.0, 27.0, 26.0, 25.0, 24.0, 23.0, 22.0, 21.0, 20.0, 19.0,
18078            18.0, 17.0, 16.0, 15.0, 14.0, 13.0, 12.0, 11.0, 10.0, 9.0, 8.0, 7.0, 6.0, 5.0, 4.0,
18079            3.0, 2.0, 1.0,
18080        );
18081        let src = _mm512_set_ph(
18082            34., 35., 36., 37., 38., 39., 40., 41., 42., 43., 44., 45., 46., 47., 48., 49., 50.,
18083            51., 52., 53., 54., 55., 56., 57., 58., 59., 60., 61., 62., 63., 64., 65.,
18084        );
18085        let r = _mm512_mask_sub_ph(src, 0b01010101010101010101010101010101, a, b);
18086        let e = _mm512_set_ph(
18087            34., -29., 36., -25., 38., -21., 40., -17., 42., -13., 44., -9., 46., -5., 48., -1.,
18088            50., 3., 52., 7., 54., 11., 56., 15., 58., 19., 60., 23., 62., 27., 64., 31.,
18089        );
18090        assert_eq_m512h(r, e);
18091    }
18092
18093    #[simd_test(enable = "avx512fp16")]
18094    const fn test_mm512_maskz_sub_ph() {
18095        let a = _mm512_set_ph(
18096            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
18097            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
18098            31.0, 32.0,
18099        );
18100        let b = _mm512_set_ph(
18101            32.0, 31.0, 30.0, 29.0, 28.0, 27.0, 26.0, 25.0, 24.0, 23.0, 22.0, 21.0, 20.0, 19.0,
18102            18.0, 17.0, 16.0, 15.0, 14.0, 13.0, 12.0, 11.0, 10.0, 9.0, 8.0, 7.0, 6.0, 5.0, 4.0,
18103            3.0, 2.0, 1.0,
18104        );
18105        let r = _mm512_maskz_sub_ph(0b01010101010101010101010101010101, a, b);
18106        let e = _mm512_set_ph(
18107            0., -29., 0., -25., 0., -21., 0., -17., 0., -13., 0., -9., 0., -5., 0., -1., 0., 3.,
18108            0., 7., 0., 11., 0., 15., 0., 19., 0., 23., 0., 27., 0., 31.,
18109        );
18110        assert_eq_m512h(r, e);
18111    }
18112
18113    #[simd_test(enable = "avx512fp16")]
18114    fn test_mm512_sub_round_ph() {
18115        let a = _mm512_set_ph(
18116            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
18117            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
18118            31.0, 32.0,
18119        );
18120        let b = _mm512_set_ph(
18121            32.0, 31.0, 30.0, 29.0, 28.0, 27.0, 26.0, 25.0, 24.0, 23.0, 22.0, 21.0, 20.0, 19.0,
18122            18.0, 17.0, 16.0, 15.0, 14.0, 13.0, 12.0, 11.0, 10.0, 9.0, 8.0, 7.0, 6.0, 5.0, 4.0,
18123            3.0, 2.0, 1.0,
18124        );
18125        let r = _mm512_sub_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
18126        let e = _mm512_set_ph(
18127            -31.0, -29.0, -27.0, -25.0, -23.0, -21.0, -19.0, -17.0, -15.0, -13.0, -11.0, -9.0,
18128            -7.0, -5.0, -3.0, -1.0, 1.0, 3.0, 5.0, 7.0, 9.0, 11.0, 13.0, 15.0, 17.0, 19.0, 21.0,
18129            23.0, 25.0, 27.0, 29.0, 31.0,
18130        );
18131        assert_eq_m512h(r, e);
18132    }
18133
18134    #[simd_test(enable = "avx512fp16")]
18135    fn test_mm512_mask_sub_round_ph() {
18136        let a = _mm512_set_ph(
18137            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
18138            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
18139            31.0, 32.0,
18140        );
18141        let b = _mm512_set_ph(
18142            32.0, 31.0, 30.0, 29.0, 28.0, 27.0, 26.0, 25.0, 24.0, 23.0, 22.0, 21.0, 20.0, 19.0,
18143            18.0, 17.0, 16.0, 15.0, 14.0, 13.0, 12.0, 11.0, 10.0, 9.0, 8.0, 7.0, 6.0, 5.0, 4.0,
18144            3.0, 2.0, 1.0,
18145        );
18146        let src = _mm512_set_ph(
18147            34., 35., 36., 37., 38., 39., 40., 41., 42., 43., 44., 45., 46., 47., 48., 49., 50.,
18148            51., 52., 53., 54., 55., 56., 57., 58., 59., 60., 61., 62., 63., 64., 65.,
18149        );
18150        let r = _mm512_mask_sub_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
18151            src,
18152            0b01010101010101010101010101010101,
18153            a,
18154            b,
18155        );
18156        let e = _mm512_set_ph(
18157            34., -29., 36., -25., 38., -21., 40., -17., 42., -13., 44., -9., 46., -5., 48., -1.,
18158            50., 3., 52., 7., 54., 11., 56., 15., 58., 19., 60., 23., 62., 27., 64., 31.,
18159        );
18160        assert_eq_m512h(r, e);
18161    }
18162
18163    #[simd_test(enable = "avx512fp16")]
18164    fn test_mm512_maskz_sub_round_ph() {
18165        let a = _mm512_set_ph(
18166            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
18167            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
18168            31.0, 32.0,
18169        );
18170        let b = _mm512_set_ph(
18171            32.0, 31.0, 30.0, 29.0, 28.0, 27.0, 26.0, 25.0, 24.0, 23.0, 22.0, 21.0, 20.0, 19.0,
18172            18.0, 17.0, 16.0, 15.0, 14.0, 13.0, 12.0, 11.0, 10.0, 9.0, 8.0, 7.0, 6.0, 5.0, 4.0,
18173            3.0, 2.0, 1.0,
18174        );
18175        let r = _mm512_maskz_sub_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
18176            0b01010101010101010101010101010101,
18177            a,
18178            b,
18179        );
18180        let e = _mm512_set_ph(
18181            0., -29., 0., -25., 0., -21., 0., -17., 0., -13., 0., -9., 0., -5., 0., -1., 0., 3.,
18182            0., 7., 0., 11., 0., 15., 0., 19., 0., 23., 0., 27., 0., 31.,
18183        );
18184        assert_eq_m512h(r, e);
18185    }
18186
18187    #[simd_test(enable = "avx512fp16,avx512vl")]
18188    fn test_mm_sub_round_sh() {
18189        let a = _mm_set_sh(1.0);
18190        let b = _mm_set_sh(2.0);
18191        let r = _mm_sub_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
18192        let e = _mm_set_sh(-1.0);
18193        assert_eq_m128h(r, e);
18194    }
18195
18196    #[simd_test(enable = "avx512fp16,avx512vl")]
18197    fn test_mm_mask_sub_round_sh() {
18198        let a = _mm_set_sh(1.0);
18199        let b = _mm_set_sh(2.0);
18200        let src = _mm_set_sh(4.0);
18201        let r = _mm_mask_sub_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
18202            src, 0, a, b,
18203        );
18204        let e = _mm_set_sh(4.0);
18205        assert_eq_m128h(r, e);
18206        let r = _mm_mask_sub_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
18207            src, 1, a, b,
18208        );
18209        let e = _mm_set_sh(-1.0);
18210        assert_eq_m128h(r, e);
18211    }
18212
18213    #[simd_test(enable = "avx512fp16,avx512vl")]
18214    fn test_mm_maskz_sub_round_sh() {
18215        let a = _mm_set_sh(1.0);
18216        let b = _mm_set_sh(2.0);
18217        let r =
18218            _mm_maskz_sub_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
18219        let e = _mm_set_sh(0.0);
18220        assert_eq_m128h(r, e);
18221        let r =
18222            _mm_maskz_sub_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(1, a, b);
18223        let e = _mm_set_sh(-1.0);
18224        assert_eq_m128h(r, e);
18225    }
18226
18227    #[simd_test(enable = "avx512fp16,avx512vl")]
18228    const fn test_mm_sub_sh() {
18229        let a = _mm_set_sh(1.0);
18230        let b = _mm_set_sh(2.0);
18231        let r = _mm_sub_sh(a, b);
18232        let e = _mm_set_sh(-1.0);
18233        assert_eq_m128h(r, e);
18234    }
18235
18236    #[simd_test(enable = "avx512fp16,avx512vl")]
18237    const fn test_mm_mask_sub_sh() {
18238        let a = _mm_set_sh(1.0);
18239        let b = _mm_set_sh(2.0);
18240        let src = _mm_set_sh(4.0);
18241        let r = _mm_mask_sub_sh(src, 0, a, b);
18242        let e = _mm_set_sh(4.0);
18243        assert_eq_m128h(r, e);
18244        let r = _mm_mask_sub_sh(src, 1, a, b);
18245        let e = _mm_set_sh(-1.0);
18246        assert_eq_m128h(r, e);
18247    }
18248
18249    #[simd_test(enable = "avx512fp16,avx512vl")]
18250    const fn test_mm_maskz_sub_sh() {
18251        let a = _mm_set_sh(1.0);
18252        let b = _mm_set_sh(2.0);
18253        let r = _mm_maskz_sub_sh(0, a, b);
18254        let e = _mm_set_sh(0.0);
18255        assert_eq_m128h(r, e);
18256        let r = _mm_maskz_sub_sh(1, a, b);
18257        let e = _mm_set_sh(-1.0);
18258        assert_eq_m128h(r, e);
18259    }
18260
18261    #[simd_test(enable = "avx512fp16,avx512vl")]
18262    const fn test_mm_mul_ph() {
18263        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
18264        let b = _mm_set_ph(8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0);
18265        let r = _mm_mul_ph(a, b);
18266        let e = _mm_set_ph(8.0, 14.0, 18.0, 20.0, 20.0, 18.0, 14.0, 8.0);
18267        assert_eq_m128h(r, e);
18268    }
18269
18270    #[simd_test(enable = "avx512fp16,avx512vl")]
18271    const fn test_mm_mask_mul_ph() {
18272        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
18273        let b = _mm_set_ph(8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0);
18274        let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
18275        let r = _mm_mask_mul_ph(src, 0b01010101, a, b);
18276        let e = _mm_set_ph(10., 14., 12., 20., 14., 18., 16., 8.);
18277        assert_eq_m128h(r, e);
18278    }
18279
18280    #[simd_test(enable = "avx512fp16,avx512vl")]
18281    const fn test_mm_maskz_mul_ph() {
18282        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
18283        let b = _mm_set_ph(8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0);
18284        let r = _mm_maskz_mul_ph(0b01010101, a, b);
18285        let e = _mm_set_ph(0., 14., 0., 20., 0., 18., 0., 8.);
18286        assert_eq_m128h(r, e);
18287    }
18288
18289    #[simd_test(enable = "avx512fp16,avx512vl")]
18290    const fn test_mm256_mul_ph() {
18291        let a = _mm256_set_ph(
18292            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
18293        );
18294        let b = _mm256_set_ph(
18295            16.0, 15.0, 14.0, 13.0, 12.0, 11.0, 10.0, 9.0, 8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0,
18296        );
18297        let r = _mm256_mul_ph(a, b);
18298        let e = _mm256_set_ph(
18299            16.0, 30.0, 42.0, 52.0, 60.0, 66.0, 70.0, 72.0, 72.0, 70.0, 66.0, 60.0, 52.0, 42.0,
18300            30.0, 16.0,
18301        );
18302        assert_eq_m256h(r, e);
18303    }
18304
18305    #[simd_test(enable = "avx512fp16,avx512vl")]
18306    const fn test_mm256_mask_mul_ph() {
18307        let a = _mm256_set_ph(
18308            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
18309        );
18310        let b = _mm256_set_ph(
18311            16.0, 15.0, 14.0, 13.0, 12.0, 11.0, 10.0, 9.0, 8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0,
18312        );
18313        let src = _mm256_set_ph(
18314            18., 19., 20., 21., 22., 23., 24., 25., 26., 27., 28., 29., 30., 31., 32., 33.,
18315        );
18316        let r = _mm256_mask_mul_ph(src, 0b0101010101010101, a, b);
18317        let e = _mm256_set_ph(
18318            18., 30., 20., 52., 22., 66., 24., 72., 26., 70., 28., 60., 30., 42., 32., 16.,
18319        );
18320        assert_eq_m256h(r, e);
18321    }
18322
18323    #[simd_test(enable = "avx512fp16,avx512vl")]
18324    const fn test_mm256_maskz_mul_ph() {
18325        let a = _mm256_set_ph(
18326            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
18327        );
18328        let b = _mm256_set_ph(
18329            16.0, 15.0, 14.0, 13.0, 12.0, 11.0, 10.0, 9.0, 8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0,
18330        );
18331        let r = _mm256_maskz_mul_ph(0b0101010101010101, a, b);
18332        let e = _mm256_set_ph(
18333            0., 30., 0., 52., 0., 66., 0., 72., 0., 70., 0., 60., 0., 42., 0., 16.,
18334        );
18335        assert_eq_m256h(r, e);
18336    }
18337
18338    #[simd_test(enable = "avx512fp16")]
18339    const fn test_mm512_mul_ph() {
18340        let a = _mm512_set_ph(
18341            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
18342            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
18343            31.0, 32.0,
18344        );
18345        let b = _mm512_set_ph(
18346            32.0, 31.0, 30.0, 29.0, 28.0, 27.0, 26.0, 25.0, 24.0, 23.0, 22.0, 21.0, 20.0, 19.0,
18347            18.0, 17.0, 16.0, 15.0, 14.0, 13.0, 12.0, 11.0, 10.0, 9.0, 8.0, 7.0, 6.0, 5.0, 4.0,
18348            3.0, 2.0, 1.0,
18349        );
18350        let r = _mm512_mul_ph(a, b);
18351        let e = _mm512_set_ph(
18352            32.0, 62.0, 90.0, 116.0, 140.0, 162.0, 182.0, 200.0, 216.0, 230.0, 242.0, 252.0, 260.0,
18353            266.0, 270.0, 272.0, 272.0, 270.0, 266.0, 260.0, 252.0, 242.0, 230.0, 216.0, 200.0,
18354            182.0, 162.0, 140.0, 116.0, 90.0, 62.0, 32.0,
18355        );
18356        assert_eq_m512h(r, e);
18357    }
18358
18359    #[simd_test(enable = "avx512fp16")]
18360    const fn test_mm512_mask_mul_ph() {
18361        let a = _mm512_set_ph(
18362            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
18363            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
18364            31.0, 32.0,
18365        );
18366        let b = _mm512_set_ph(
18367            32.0, 31.0, 30.0, 29.0, 28.0, 27.0, 26.0, 25.0, 24.0, 23.0, 22.0, 21.0, 20.0, 19.0,
18368            18.0, 17.0, 16.0, 15.0, 14.0, 13.0, 12.0, 11.0, 10.0, 9.0, 8.0, 7.0, 6.0, 5.0, 4.0,
18369            3.0, 2.0, 1.0,
18370        );
18371        let src = _mm512_set_ph(
18372            34., 35., 36., 37., 38., 39., 40., 41., 42., 43., 44., 45., 46., 47., 48., 49., 50.,
18373            51., 52., 53., 54., 55., 56., 57., 58., 59., 60., 61., 62., 63., 64., 65.,
18374        );
18375        let r = _mm512_mask_mul_ph(src, 0b01010101010101010101010101010101, a, b);
18376        let e = _mm512_set_ph(
18377            34., 62., 36., 116., 38., 162., 40., 200., 42., 230., 44., 252., 46., 266., 48., 272.,
18378            50., 270., 52., 260., 54., 242., 56., 216., 58., 182., 60., 140., 62., 90., 64., 32.,
18379        );
18380        assert_eq_m512h(r, e);
18381    }
18382
18383    #[simd_test(enable = "avx512fp16")]
18384    const fn test_mm512_maskz_mul_ph() {
18385        let a = _mm512_set_ph(
18386            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
18387            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
18388            31.0, 32.0,
18389        );
18390        let b = _mm512_set_ph(
18391            32.0, 31.0, 30.0, 29.0, 28.0, 27.0, 26.0, 25.0, 24.0, 23.0, 22.0, 21.0, 20.0, 19.0,
18392            18.0, 17.0, 16.0, 15.0, 14.0, 13.0, 12.0, 11.0, 10.0, 9.0, 8.0, 7.0, 6.0, 5.0, 4.0,
18393            3.0, 2.0, 1.0,
18394        );
18395        let r = _mm512_maskz_mul_ph(0b01010101010101010101010101010101, a, b);
18396        let e = _mm512_set_ph(
18397            0., 62., 0., 116., 0., 162., 0., 200., 0., 230., 0., 252., 0., 266., 0., 272., 0.,
18398            270., 0., 260., 0., 242., 0., 216., 0., 182., 0., 140., 0., 90., 0., 32.,
18399        );
18400        assert_eq_m512h(r, e);
18401    }
18402
18403    #[simd_test(enable = "avx512fp16")]
18404    fn test_mm512_mul_round_ph() {
18405        let a = _mm512_set_ph(
18406            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
18407            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
18408            31.0, 32.0,
18409        );
18410        let b = _mm512_set_ph(
18411            32.0, 31.0, 30.0, 29.0, 28.0, 27.0, 26.0, 25.0, 24.0, 23.0, 22.0, 21.0, 20.0, 19.0,
18412            18.0, 17.0, 16.0, 15.0, 14.0, 13.0, 12.0, 11.0, 10.0, 9.0, 8.0, 7.0, 6.0, 5.0, 4.0,
18413            3.0, 2.0, 1.0,
18414        );
18415        let r = _mm512_mul_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
18416        let e = _mm512_set_ph(
18417            32.0, 62.0, 90.0, 116.0, 140.0, 162.0, 182.0, 200.0, 216.0, 230.0, 242.0, 252.0, 260.0,
18418            266.0, 270.0, 272.0, 272.0, 270.0, 266.0, 260.0, 252.0, 242.0, 230.0, 216.0, 200.0,
18419            182.0, 162.0, 140.0, 116.0, 90.0, 62.0, 32.0,
18420        );
18421        assert_eq_m512h(r, e);
18422    }
18423
18424    #[simd_test(enable = "avx512fp16")]
18425    fn test_mm512_mask_mul_round_ph() {
18426        let a = _mm512_set_ph(
18427            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
18428            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
18429            31.0, 32.0,
18430        );
18431        let b = _mm512_set_ph(
18432            32.0, 31.0, 30.0, 29.0, 28.0, 27.0, 26.0, 25.0, 24.0, 23.0, 22.0, 21.0, 20.0, 19.0,
18433            18.0, 17.0, 16.0, 15.0, 14.0, 13.0, 12.0, 11.0, 10.0, 9.0, 8.0, 7.0, 6.0, 5.0, 4.0,
18434            3.0, 2.0, 1.0,
18435        );
18436        let src = _mm512_set_ph(
18437            34., 35., 36., 37., 38., 39., 40., 41., 42., 43., 44., 45., 46., 47., 48., 49., 50.,
18438            51., 52., 53., 54., 55., 56., 57., 58., 59., 60., 61., 62., 63., 64., 65.,
18439        );
18440        let r = _mm512_mask_mul_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
18441            src,
18442            0b01010101010101010101010101010101,
18443            a,
18444            b,
18445        );
18446        let e = _mm512_set_ph(
18447            34., 62., 36., 116., 38., 162., 40., 200., 42., 230., 44., 252., 46., 266., 48., 272.,
18448            50., 270., 52., 260., 54., 242., 56., 216., 58., 182., 60., 140., 62., 90., 64., 32.,
18449        );
18450        assert_eq_m512h(r, e);
18451    }
18452
18453    #[simd_test(enable = "avx512fp16")]
18454    fn test_mm512_maskz_mul_round_ph() {
18455        let a = _mm512_set_ph(
18456            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
18457            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
18458            31.0, 32.0,
18459        );
18460        let b = _mm512_set_ph(
18461            32.0, 31.0, 30.0, 29.0, 28.0, 27.0, 26.0, 25.0, 24.0, 23.0, 22.0, 21.0, 20.0, 19.0,
18462            18.0, 17.0, 16.0, 15.0, 14.0, 13.0, 12.0, 11.0, 10.0, 9.0, 8.0, 7.0, 6.0, 5.0, 4.0,
18463            3.0, 2.0, 1.0,
18464        );
18465        let r = _mm512_maskz_mul_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
18466            0b01010101010101010101010101010101,
18467            a,
18468            b,
18469        );
18470        let e = _mm512_set_ph(
18471            0., 62., 0., 116., 0., 162., 0., 200., 0., 230., 0., 252., 0., 266., 0., 272., 0.,
18472            270., 0., 260., 0., 242., 0., 216., 0., 182., 0., 140., 0., 90., 0., 32.,
18473        );
18474        assert_eq_m512h(r, e);
18475    }
18476
18477    #[simd_test(enable = "avx512fp16,avx512vl")]
18478    fn test_mm_mul_round_sh() {
18479        let a = _mm_set_sh(1.0);
18480        let b = _mm_set_sh(2.0);
18481        let r = _mm_mul_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
18482        let e = _mm_set_sh(2.0);
18483        assert_eq_m128h(r, e);
18484    }
18485
18486    #[simd_test(enable = "avx512fp16,avx512vl")]
18487    fn test_mm_mask_mul_round_sh() {
18488        let a = _mm_set_sh(1.0);
18489        let b = _mm_set_sh(2.0);
18490        let src = _mm_set_sh(4.0);
18491        let r = _mm_mask_mul_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
18492            src, 0, a, b,
18493        );
18494        let e = _mm_set_sh(4.0);
18495        assert_eq_m128h(r, e);
18496        let r = _mm_mask_mul_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
18497            src, 1, a, b,
18498        );
18499        let e = _mm_set_sh(2.0);
18500        assert_eq_m128h(r, e);
18501    }
18502
18503    #[simd_test(enable = "avx512fp16,avx512vl")]
18504    fn test_mm_maskz_mul_round_sh() {
18505        let a = _mm_set_sh(1.0);
18506        let b = _mm_set_sh(2.0);
18507        let r =
18508            _mm_maskz_mul_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
18509        let e = _mm_set_sh(0.0);
18510        assert_eq_m128h(r, e);
18511        let r =
18512            _mm_maskz_mul_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(1, a, b);
18513        let e = _mm_set_sh(2.0);
18514        assert_eq_m128h(r, e);
18515    }
18516
18517    #[simd_test(enable = "avx512fp16,avx512vl")]
18518    const fn test_mm_mul_sh() {
18519        let a = _mm_set_sh(1.0);
18520        let b = _mm_set_sh(2.0);
18521        let r = _mm_mul_sh(a, b);
18522        let e = _mm_set_sh(2.0);
18523        assert_eq_m128h(r, e);
18524    }
18525
18526    #[simd_test(enable = "avx512fp16,avx512vl")]
18527    const fn test_mm_mask_mul_sh() {
18528        let a = _mm_set_sh(1.0);
18529        let b = _mm_set_sh(2.0);
18530        let src = _mm_set_sh(4.0);
18531        let r = _mm_mask_mul_sh(src, 0, a, b);
18532        let e = _mm_set_sh(4.0);
18533        assert_eq_m128h(r, e);
18534        let r = _mm_mask_mul_sh(src, 1, a, b);
18535        let e = _mm_set_sh(2.0);
18536        assert_eq_m128h(r, e);
18537    }
18538
18539    #[simd_test(enable = "avx512fp16,avx512vl")]
18540    const fn test_mm_maskz_mul_sh() {
18541        let a = _mm_set_sh(1.0);
18542        let b = _mm_set_sh(2.0);
18543        let r = _mm_maskz_mul_sh(0, a, b);
18544        let e = _mm_set_sh(0.0);
18545        assert_eq_m128h(r, e);
18546        let r = _mm_maskz_mul_sh(1, a, b);
18547        let e = _mm_set_sh(2.0);
18548        assert_eq_m128h(r, e);
18549    }
18550
18551    #[simd_test(enable = "avx512fp16,avx512vl")]
18552    const fn test_mm_div_ph() {
18553        let a = _mm_set1_ph(1.0);
18554        let b = _mm_set1_ph(2.0);
18555        let r = _mm_div_ph(a, b);
18556        let e = _mm_set1_ph(0.5);
18557        assert_eq_m128h(r, e);
18558    }
18559
18560    #[simd_test(enable = "avx512fp16,avx512vl")]
18561    const fn test_mm_mask_div_ph() {
18562        let a = _mm_set1_ph(1.0);
18563        let b = _mm_set1_ph(2.0);
18564        let src = _mm_set_ph(4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0);
18565        let r = _mm_mask_div_ph(src, 0b01010101, a, b);
18566        let e = _mm_set_ph(4.0, 0.5, 6.0, 0.5, 8.0, 0.5, 10.0, 0.5);
18567        assert_eq_m128h(r, e);
18568    }
18569
18570    #[simd_test(enable = "avx512fp16,avx512vl")]
18571    const fn test_mm_maskz_div_ph() {
18572        let a = _mm_set1_ph(1.0);
18573        let b = _mm_set1_ph(2.0);
18574        let r = _mm_maskz_div_ph(0b01010101, a, b);
18575        let e = _mm_set_ph(0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5);
18576        assert_eq_m128h(r, e);
18577    }
18578
18579    #[simd_test(enable = "avx512fp16,avx512vl")]
18580    const fn test_mm256_div_ph() {
18581        let a = _mm256_set1_ph(1.0);
18582        let b = _mm256_set1_ph(2.0);
18583        let r = _mm256_div_ph(a, b);
18584        let e = _mm256_set1_ph(0.5);
18585        assert_eq_m256h(r, e);
18586    }
18587
18588    #[simd_test(enable = "avx512fp16,avx512vl")]
18589    const fn test_mm256_mask_div_ph() {
18590        let a = _mm256_set1_ph(1.0);
18591        let b = _mm256_set1_ph(2.0);
18592        let src = _mm256_set_ph(
18593            4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0, 18.0,
18594            19.0,
18595        );
18596        let r = _mm256_mask_div_ph(src, 0b0101010101010101, a, b);
18597        let e = _mm256_set_ph(
18598            4.0, 0.5, 6.0, 0.5, 8.0, 0.5, 10.0, 0.5, 12.0, 0.5, 14.0, 0.5, 16.0, 0.5, 18.0, 0.5,
18599        );
18600        assert_eq_m256h(r, e);
18601    }
18602
18603    #[simd_test(enable = "avx512fp16,avx512vl")]
18604    const fn test_mm256_maskz_div_ph() {
18605        let a = _mm256_set1_ph(1.0);
18606        let b = _mm256_set1_ph(2.0);
18607        let r = _mm256_maskz_div_ph(0b0101010101010101, a, b);
18608        let e = _mm256_set_ph(
18609            0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5,
18610        );
18611        assert_eq_m256h(r, e);
18612    }
18613
18614    #[simd_test(enable = "avx512fp16")]
18615    const fn test_mm512_div_ph() {
18616        let a = _mm512_set1_ph(1.0);
18617        let b = _mm512_set1_ph(2.0);
18618        let r = _mm512_div_ph(a, b);
18619        let e = _mm512_set1_ph(0.5);
18620        assert_eq_m512h(r, e);
18621    }
18622
18623    #[simd_test(enable = "avx512fp16")]
18624    const fn test_mm512_mask_div_ph() {
18625        let a = _mm512_set1_ph(1.0);
18626        let b = _mm512_set1_ph(2.0);
18627        let src = _mm512_set_ph(
18628            4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0, 18.0,
18629            19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0, 31.0, 32.0,
18630            33.0, 34.0, 35.0,
18631        );
18632        let r = _mm512_mask_div_ph(src, 0b01010101010101010101010101010101, a, b);
18633        let e = _mm512_set_ph(
18634            4.0, 0.5, 6.0, 0.5, 8.0, 0.5, 10.0, 0.5, 12.0, 0.5, 14.0, 0.5, 16.0, 0.5, 18.0, 0.5,
18635            20.0, 0.5, 22.0, 0.5, 24.0, 0.5, 26.0, 0.5, 28.0, 0.5, 30.0, 0.5, 32.0, 0.5, 34.0, 0.5,
18636        );
18637        assert_eq_m512h(r, e);
18638    }
18639
18640    #[simd_test(enable = "avx512fp16")]
18641    const fn test_mm512_maskz_div_ph() {
18642        let a = _mm512_set1_ph(1.0);
18643        let b = _mm512_set1_ph(2.0);
18644        let r = _mm512_maskz_div_ph(0b01010101010101010101010101010101, a, b);
18645        let e = _mm512_set_ph(
18646            0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0,
18647            0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5,
18648        );
18649        assert_eq_m512h(r, e);
18650    }
18651
18652    #[simd_test(enable = "avx512fp16")]
18653    fn test_mm512_div_round_ph() {
18654        let a = _mm512_set1_ph(1.0);
18655        let b = _mm512_set1_ph(2.0);
18656        let r = _mm512_div_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
18657        let e = _mm512_set1_ph(0.5);
18658        assert_eq_m512h(r, e);
18659    }
18660
18661    #[simd_test(enable = "avx512fp16")]
18662    fn test_mm512_mask_div_round_ph() {
18663        let a = _mm512_set1_ph(1.0);
18664        let b = _mm512_set1_ph(2.0);
18665        let src = _mm512_set_ph(
18666            4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0, 18.0,
18667            19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0, 31.0, 32.0,
18668            33.0, 34.0, 35.0,
18669        );
18670        let r = _mm512_mask_div_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
18671            src,
18672            0b01010101010101010101010101010101,
18673            a,
18674            b,
18675        );
18676        let e = _mm512_set_ph(
18677            4.0, 0.5, 6.0, 0.5, 8.0, 0.5, 10.0, 0.5, 12.0, 0.5, 14.0, 0.5, 16.0, 0.5, 18.0, 0.5,
18678            20.0, 0.5, 22.0, 0.5, 24.0, 0.5, 26.0, 0.5, 28.0, 0.5, 30.0, 0.5, 32.0, 0.5, 34.0, 0.5,
18679        );
18680        assert_eq_m512h(r, e);
18681    }
18682
18683    #[simd_test(enable = "avx512fp16")]
18684    fn test_mm512_maskz_div_round_ph() {
18685        let a = _mm512_set1_ph(1.0);
18686        let b = _mm512_set1_ph(2.0);
18687        let r = _mm512_maskz_div_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
18688            0b01010101010101010101010101010101,
18689            a,
18690            b,
18691        );
18692        let e = _mm512_set_ph(
18693            0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0,
18694            0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5,
18695        );
18696        assert_eq_m512h(r, e);
18697    }
18698
18699    #[simd_test(enable = "avx512fp16,avx512vl")]
18700    fn test_mm_div_round_sh() {
18701        let a = _mm_set_sh(1.0);
18702        let b = _mm_set_sh(2.0);
18703        let r = _mm_div_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
18704        let e = _mm_set_sh(0.5);
18705        assert_eq_m128h(r, e);
18706    }
18707
18708    #[simd_test(enable = "avx512fp16,avx512vl")]
18709    fn test_mm_mask_div_round_sh() {
18710        let a = _mm_set_sh(1.0);
18711        let b = _mm_set_sh(2.0);
18712        let src = _mm_set_sh(4.0);
18713        let r = _mm_mask_div_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
18714            src, 0, a, b,
18715        );
18716        let e = _mm_set_sh(4.0);
18717        assert_eq_m128h(r, e);
18718        let r = _mm_mask_div_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
18719            src, 1, a, b,
18720        );
18721        let e = _mm_set_sh(0.5);
18722        assert_eq_m128h(r, e);
18723    }
18724
18725    #[simd_test(enable = "avx512fp16,avx512vl")]
18726    fn test_mm_maskz_div_round_sh() {
18727        let a = _mm_set_sh(1.0);
18728        let b = _mm_set_sh(2.0);
18729        let r =
18730            _mm_maskz_div_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
18731        let e = _mm_set_sh(0.0);
18732        assert_eq_m128h(r, e);
18733        let r =
18734            _mm_maskz_div_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(1, a, b);
18735        let e = _mm_set_sh(0.5);
18736        assert_eq_m128h(r, e);
18737    }
18738
18739    #[simd_test(enable = "avx512fp16,avx512vl")]
18740    const fn test_mm_div_sh() {
18741        let a = _mm_set_sh(1.0);
18742        let b = _mm_set_sh(2.0);
18743        let r = _mm_div_sh(a, b);
18744        let e = _mm_set_sh(0.5);
18745        assert_eq_m128h(r, e);
18746    }
18747
18748    #[simd_test(enable = "avx512fp16,avx512vl")]
18749    const fn test_mm_mask_div_sh() {
18750        let a = _mm_set_sh(1.0);
18751        let b = _mm_set_sh(2.0);
18752        let src = _mm_set_sh(4.0);
18753        let r = _mm_mask_div_sh(src, 0, a, b);
18754        let e = _mm_set_sh(4.0);
18755        assert_eq_m128h(r, e);
18756        let r = _mm_mask_div_sh(src, 1, a, b);
18757        let e = _mm_set_sh(0.5);
18758        assert_eq_m128h(r, e);
18759    }
18760
18761    #[simd_test(enable = "avx512fp16,avx512vl")]
18762    const fn test_mm_maskz_div_sh() {
18763        let a = _mm_set_sh(1.0);
18764        let b = _mm_set_sh(2.0);
18765        let r = _mm_maskz_div_sh(0, a, b);
18766        let e = _mm_set_sh(0.0);
18767        assert_eq_m128h(r, e);
18768        let r = _mm_maskz_div_sh(1, a, b);
18769        let e = _mm_set_sh(0.5);
18770        assert_eq_m128h(r, e);
18771    }
18772
18773    #[simd_test(enable = "avx512fp16,avx512vl")]
18774    fn test_mm_mul_pch() {
18775        let a = _mm_set1_pch(0.0, 1.0);
18776        let b = _mm_set1_pch(0.0, 1.0);
18777        let r = _mm_mul_pch(a, b);
18778        let e = _mm_set1_pch(-1.0, 0.0);
18779        assert_eq_m128h(r, e);
18780    }
18781
18782    #[simd_test(enable = "avx512fp16,avx512vl")]
18783    fn test_mm_mask_mul_pch() {
18784        let a = _mm_set1_pch(0.0, 1.0);
18785        let b = _mm_set1_pch(0.0, 1.0);
18786        let src = _mm_setr_ph(2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0);
18787        let r = _mm_mask_mul_pch(src, 0b0101, a, b);
18788        let e = _mm_setr_ph(-1.0, 0.0, 4.0, 5.0, -1.0, 0.0, 8.0, 9.0);
18789        assert_eq_m128h(r, e);
18790    }
18791
18792    #[simd_test(enable = "avx512fp16,avx512vl")]
18793    fn test_mm_maskz_mul_pch() {
18794        let a = _mm_set1_pch(0.0, 1.0);
18795        let b = _mm_set1_pch(0.0, 1.0);
18796        let r = _mm_maskz_mul_pch(0b0101, a, b);
18797        let e = _mm_setr_ph(-1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0);
18798        assert_eq_m128h(r, e);
18799    }
18800
18801    #[simd_test(enable = "avx512fp16,avx512vl")]
18802    fn test_mm256_mul_pch() {
18803        let a = _mm256_set1_pch(0.0, 1.0);
18804        let b = _mm256_set1_pch(0.0, 1.0);
18805        let r = _mm256_mul_pch(a, b);
18806        let e = _mm256_set1_pch(-1.0, 0.0);
18807        assert_eq_m256h(r, e);
18808    }
18809
18810    #[simd_test(enable = "avx512fp16,avx512vl")]
18811    fn test_mm256_mask_mul_pch() {
18812        let a = _mm256_set1_pch(0.0, 1.0);
18813        let b = _mm256_set1_pch(0.0, 1.0);
18814        let src = _mm256_setr_ph(
18815            2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0,
18816        );
18817        let r = _mm256_mask_mul_pch(src, 0b01010101, a, b);
18818        let e = _mm256_setr_ph(
18819            -1.0, 0.0, 4.0, 5.0, -1.0, 0.0, 8.0, 9.0, -1.0, 0.0, 12.0, 13.0, -1.0, 0.0, 16.0, 17.0,
18820        );
18821        assert_eq_m256h(r, e);
18822    }
18823
18824    #[simd_test(enable = "avx512fp16,avx512vl")]
18825    fn test_mm256_maskz_mul_pch() {
18826        let a = _mm256_set1_pch(0.0, 1.0);
18827        let b = _mm256_set1_pch(0.0, 1.0);
18828        let r = _mm256_maskz_mul_pch(0b01010101, a, b);
18829        let e = _mm256_setr_ph(
18830            -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0,
18831        );
18832        assert_eq_m256h(r, e);
18833    }
18834
18835    #[simd_test(enable = "avx512fp16")]
18836    fn test_mm512_mul_pch() {
18837        let a = _mm512_set1_pch(0.0, 1.0);
18838        let b = _mm512_set1_pch(0.0, 1.0);
18839        let r = _mm512_mul_pch(a, b);
18840        let e = _mm512_set1_pch(-1.0, 0.0);
18841        assert_eq_m512h(r, e);
18842    }
18843
18844    #[simd_test(enable = "avx512fp16")]
18845    fn test_mm512_mask_mul_pch() {
18846        let a = _mm512_set1_pch(0.0, 1.0);
18847        let b = _mm512_set1_pch(0.0, 1.0);
18848        let src = _mm512_setr_ph(
18849            2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0,
18850            18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0, 31.0,
18851            32.0, 33.0,
18852        );
18853        let r = _mm512_mask_mul_pch(src, 0b0101010101010101, a, b);
18854        let e = _mm512_setr_ph(
18855            -1.0, 0.0, 4.0, 5.0, -1.0, 0.0, 8.0, 9.0, -1.0, 0.0, 12.0, 13.0, -1.0, 0.0, 16.0, 17.0,
18856            -1.0, 0.0, 20.0, 21.0, -1.0, 0.0, 24.0, 25.0, -1.0, 0.0, 28.0, 29.0, -1.0, 0.0, 32.0,
18857            33.0,
18858        );
18859        assert_eq_m512h(r, e);
18860    }
18861
18862    #[simd_test(enable = "avx512fp16")]
18863    fn test_mm512_maskz_mul_pch() {
18864        let a = _mm512_set1_pch(0.0, 1.0);
18865        let b = _mm512_set1_pch(0.0, 1.0);
18866        let r = _mm512_maskz_mul_pch(0b0101010101010101, a, b);
18867        let e = _mm512_setr_ph(
18868            -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0,
18869            -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0,
18870        );
18871        assert_eq_m512h(r, e);
18872    }
18873
18874    #[simd_test(enable = "avx512fp16")]
18875    fn test_mm512_mul_round_pch() {
18876        let a = _mm512_set1_pch(0.0, 1.0);
18877        let b = _mm512_set1_pch(0.0, 1.0);
18878        let r = _mm512_mul_round_pch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
18879        let e = _mm512_set1_pch(-1.0, 0.0);
18880        assert_eq_m512h(r, e);
18881    }
18882
18883    #[simd_test(enable = "avx512fp16")]
18884    fn test_mm512_mask_mul_round_pch() {
18885        let a = _mm512_set1_pch(0.0, 1.0);
18886        let b = _mm512_set1_pch(0.0, 1.0);
18887        let src = _mm512_setr_ph(
18888            2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0,
18889            18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0, 31.0,
18890            32.0, 33.0,
18891        );
18892        let r = _mm512_mask_mul_round_pch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
18893            src,
18894            0b0101010101010101,
18895            a,
18896            b,
18897        );
18898        let e = _mm512_setr_ph(
18899            -1.0, 0.0, 4.0, 5.0, -1.0, 0.0, 8.0, 9.0, -1.0, 0.0, 12.0, 13.0, -1.0, 0.0, 16.0, 17.0,
18900            -1.0, 0.0, 20.0, 21.0, -1.0, 0.0, 24.0, 25.0, -1.0, 0.0, 28.0, 29.0, -1.0, 0.0, 32.0,
18901            33.0,
18902        );
18903        assert_eq_m512h(r, e);
18904    }
18905
18906    #[simd_test(enable = "avx512fp16")]
18907    fn test_mm512_maskz_mul_round_pch() {
18908        let a = _mm512_set1_pch(0.0, 1.0);
18909        let b = _mm512_set1_pch(0.0, 1.0);
18910        let r = _mm512_maskz_mul_round_pch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
18911            0b0101010101010101,
18912            a,
18913            b,
18914        );
18915        let e = _mm512_setr_ph(
18916            -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0,
18917            -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0,
18918        );
18919        assert_eq_m512h(r, e);
18920    }
18921
18922    #[simd_test(enable = "avx512fp16,avx512vl")]
18923    fn test_mm_mul_round_sch() {
18924        let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
18925        let b = _mm_setr_ph(0.0, 1.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
18926        let r = _mm_mul_round_sch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
18927        let e = _mm_setr_ph(-1.0, 0.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
18928        assert_eq_m128h(r, e);
18929    }
18930
18931    #[simd_test(enable = "avx512fp16,avx512vl")]
18932    fn test_mm_mask_mul_round_sch() {
18933        let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
18934        let b = _mm_setr_ph(0.0, 1.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
18935        let src = _mm_setr_ph(14.0, 15.0, 16.0, 17.0, 18.0, 19.0, 20.0, 21.0);
18936        let r = _mm_mask_mul_round_sch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
18937            src, 0, a, b,
18938        );
18939        let e = _mm_setr_ph(14.0, 15.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
18940        assert_eq_m128h(r, e);
18941    }
18942
18943    #[simd_test(enable = "avx512fp16,avx512vl")]
18944    fn test_mm_maskz_mul_round_sch() {
18945        let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
18946        let b = _mm_setr_ph(0.0, 1.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
18947        let r =
18948            _mm_maskz_mul_round_sch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
18949        let e = _mm_setr_ph(0.0, 0.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
18950        assert_eq_m128h(r, e);
18951    }
18952
18953    #[simd_test(enable = "avx512fp16,avx512vl")]
18954    fn test_mm_mul_sch() {
18955        let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
18956        let b = _mm_setr_ph(0.0, 1.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
18957        let r = _mm_mul_sch(a, b);
18958        let e = _mm_setr_ph(-1.0, 0.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
18959        assert_eq_m128h(r, e);
18960    }
18961
18962    #[simd_test(enable = "avx512fp16,avx512vl")]
18963    fn test_mm_mask_mul_sch() {
18964        let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
18965        let b = _mm_setr_ph(0.0, 1.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
18966        let src = _mm_setr_ph(14.0, 15.0, 16.0, 17.0, 18.0, 19.0, 20.0, 21.0);
18967        let r = _mm_mask_mul_sch(src, 0, a, b);
18968        let e = _mm_setr_ph(14.0, 15.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
18969        assert_eq_m128h(r, e);
18970    }
18971
18972    #[simd_test(enable = "avx512fp16,avx512vl")]
18973    fn test_mm_maskz_mul_sch() {
18974        let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
18975        let b = _mm_setr_ph(0.0, 1.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
18976        let r = _mm_maskz_mul_sch(0, a, b);
18977        let e = _mm_setr_ph(0.0, 0.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
18978        assert_eq_m128h(r, e);
18979    }
18980
18981    #[simd_test(enable = "avx512fp16,avx512vl")]
18982    fn test_mm_fmul_pch() {
18983        let a = _mm_set1_pch(0.0, 1.0);
18984        let b = _mm_set1_pch(0.0, 1.0);
18985        let r = _mm_fmul_pch(a, b);
18986        let e = _mm_set1_pch(-1.0, 0.0);
18987        assert_eq_m128h(r, e);
18988    }
18989
18990    #[simd_test(enable = "avx512fp16,avx512vl")]
18991    fn test_mm_mask_fmul_pch() {
18992        let a = _mm_set1_pch(0.0, 1.0);
18993        let b = _mm_set1_pch(0.0, 1.0);
18994        let src = _mm_setr_ph(2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0);
18995        let r = _mm_mask_fmul_pch(src, 0b0101, a, b);
18996        let e = _mm_setr_ph(-1.0, 0.0, 4.0, 5.0, -1.0, 0.0, 8.0, 9.0);
18997        assert_eq_m128h(r, e);
18998    }
18999
19000    #[simd_test(enable = "avx512fp16,avx512vl")]
19001    fn test_mm_maskz_fmul_pch() {
19002        let a = _mm_set1_pch(0.0, 1.0);
19003        let b = _mm_set1_pch(0.0, 1.0);
19004        let r = _mm_maskz_fmul_pch(0b0101, a, b);
19005        let e = _mm_setr_ph(-1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0);
19006        assert_eq_m128h(r, e);
19007    }
19008
19009    #[simd_test(enable = "avx512fp16,avx512vl")]
19010    fn test_mm256_fmul_pch() {
19011        let a = _mm256_set1_pch(0.0, 1.0);
19012        let b = _mm256_set1_pch(0.0, 1.0);
19013        let r = _mm256_fmul_pch(a, b);
19014        let e = _mm256_set1_pch(-1.0, 0.0);
19015        assert_eq_m256h(r, e);
19016    }
19017
19018    #[simd_test(enable = "avx512fp16,avx512vl")]
19019    fn test_mm256_mask_fmul_pch() {
19020        let a = _mm256_set1_pch(0.0, 1.0);
19021        let b = _mm256_set1_pch(0.0, 1.0);
19022        let src = _mm256_setr_ph(
19023            2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0,
19024        );
19025        let r = _mm256_mask_fmul_pch(src, 0b01010101, a, b);
19026        let e = _mm256_setr_ph(
19027            -1.0, 0.0, 4.0, 5.0, -1.0, 0.0, 8.0, 9.0, -1.0, 0.0, 12.0, 13.0, -1.0, 0.0, 16.0, 17.0,
19028        );
19029        assert_eq_m256h(r, e);
19030    }
19031
19032    #[simd_test(enable = "avx512fp16,avx512vl")]
19033    fn test_mm256_maskz_fmul_pch() {
19034        let a = _mm256_set1_pch(0.0, 1.0);
19035        let b = _mm256_set1_pch(0.0, 1.0);
19036        let r = _mm256_maskz_fmul_pch(0b01010101, a, b);
19037        let e = _mm256_setr_ph(
19038            -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0,
19039        );
19040        assert_eq_m256h(r, e);
19041    }
19042
19043    #[simd_test(enable = "avx512fp16")]
19044    fn test_mm512_fmul_pch() {
19045        let a = _mm512_set1_pch(0.0, 1.0);
19046        let b = _mm512_set1_pch(0.0, 1.0);
19047        let r = _mm512_fmul_pch(a, b);
19048        let e = _mm512_set1_pch(-1.0, 0.0);
19049        assert_eq_m512h(r, e);
19050    }
19051
19052    #[simd_test(enable = "avx512fp16")]
19053    fn test_mm512_mask_fmul_pch() {
19054        let a = _mm512_set1_pch(0.0, 1.0);
19055        let b = _mm512_set1_pch(0.0, 1.0);
19056        let src = _mm512_setr_ph(
19057            2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0,
19058            18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0, 31.0,
19059            32.0, 33.0,
19060        );
19061        let r = _mm512_mask_fmul_pch(src, 0b0101010101010101, a, b);
19062        let e = _mm512_setr_ph(
19063            -1.0, 0.0, 4.0, 5.0, -1.0, 0.0, 8.0, 9.0, -1.0, 0.0, 12.0, 13.0, -1.0, 0.0, 16.0, 17.0,
19064            -1.0, 0.0, 20.0, 21.0, -1.0, 0.0, 24.0, 25.0, -1.0, 0.0, 28.0, 29.0, -1.0, 0.0, 32.0,
19065            33.0,
19066        );
19067        assert_eq_m512h(r, e);
19068    }
19069
19070    #[simd_test(enable = "avx512fp16")]
19071    fn test_mm512_maskz_fmul_pch() {
19072        let a = _mm512_set1_pch(0.0, 1.0);
19073        let b = _mm512_set1_pch(0.0, 1.0);
19074        let r = _mm512_maskz_fmul_pch(0b0101010101010101, a, b);
19075        let e = _mm512_setr_ph(
19076            -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0,
19077            -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0,
19078        );
19079        assert_eq_m512h(r, e);
19080    }
19081
19082    #[simd_test(enable = "avx512fp16")]
19083    fn test_mm512_fmul_round_pch() {
19084        let a = _mm512_set1_pch(0.0, 1.0);
19085        let b = _mm512_set1_pch(0.0, 1.0);
19086        let r = _mm512_fmul_round_pch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
19087        let e = _mm512_set1_pch(-1.0, 0.0);
19088        assert_eq_m512h(r, e);
19089    }
19090
19091    #[simd_test(enable = "avx512fp16")]
19092    fn test_mm512_mask_fmul_round_pch() {
19093        let a = _mm512_set1_pch(0.0, 1.0);
19094        let b = _mm512_set1_pch(0.0, 1.0);
19095        let src = _mm512_setr_ph(
19096            2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0,
19097            18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0, 31.0,
19098            32.0, 33.0,
19099        );
19100        let r = _mm512_mask_fmul_round_pch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
19101            src,
19102            0b0101010101010101,
19103            a,
19104            b,
19105        );
19106        let e = _mm512_setr_ph(
19107            -1.0, 0.0, 4.0, 5.0, -1.0, 0.0, 8.0, 9.0, -1.0, 0.0, 12.0, 13.0, -1.0, 0.0, 16.0, 17.0,
19108            -1.0, 0.0, 20.0, 21.0, -1.0, 0.0, 24.0, 25.0, -1.0, 0.0, 28.0, 29.0, -1.0, 0.0, 32.0,
19109            33.0,
19110        );
19111        assert_eq_m512h(r, e);
19112    }
19113
19114    #[simd_test(enable = "avx512fp16")]
19115    fn test_mm512_maskz_fmul_round_pch() {
19116        let a = _mm512_set1_pch(0.0, 1.0);
19117        let b = _mm512_set1_pch(0.0, 1.0);
19118        let r = _mm512_maskz_fmul_round_pch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
19119            0b0101010101010101,
19120            a,
19121            b,
19122        );
19123        let e = _mm512_setr_ph(
19124            -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0,
19125            -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0,
19126        );
19127        assert_eq_m512h(r, e);
19128    }
19129
19130    #[simd_test(enable = "avx512fp16,avx512vl")]
19131    fn test_mm_fmul_round_sch() {
19132        let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19133        let b = _mm_setr_ph(0.0, 1.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
19134        let r = _mm_fmul_round_sch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
19135        let e = _mm_setr_ph(-1.0, 0.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19136        assert_eq_m128h(r, e);
19137    }
19138
19139    #[simd_test(enable = "avx512fp16,avx512vl")]
19140    fn test_mm_mask_fmul_round_sch() {
19141        let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19142        let b = _mm_setr_ph(0.0, 1.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
19143        let src = _mm_setr_ph(14.0, 15.0, 16.0, 17.0, 18.0, 19.0, 20.0, 21.0);
19144        let r = _mm_mask_fmul_round_sch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
19145            src, 0, a, b,
19146        );
19147        let e = _mm_setr_ph(14.0, 15.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19148        assert_eq_m128h(r, e);
19149    }
19150
19151    #[simd_test(enable = "avx512fp16,avx512vl")]
19152    fn test_mm_maskz_fmul_round_sch() {
19153        let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19154        let b = _mm_setr_ph(0.0, 1.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
19155        let r =
19156            _mm_maskz_fmul_round_sch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
19157        let e = _mm_setr_ph(0.0, 0.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19158        assert_eq_m128h(r, e);
19159    }
19160
19161    #[simd_test(enable = "avx512fp16,avx512vl")]
19162    fn test_mm_fmul_sch() {
19163        let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19164        let b = _mm_setr_ph(0.0, 1.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
19165        let r = _mm_fmul_sch(a, b);
19166        let e = _mm_setr_ph(-1.0, 0.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19167        assert_eq_m128h(r, e);
19168    }
19169
19170    #[simd_test(enable = "avx512fp16,avx512vl")]
19171    fn test_mm_mask_fmul_sch() {
19172        let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19173        let b = _mm_setr_ph(0.0, 1.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
19174        let src = _mm_setr_ph(14.0, 15.0, 16.0, 17.0, 18.0, 19.0, 20.0, 21.0);
19175        let r = _mm_mask_fmul_sch(src, 0, a, b);
19176        let e = _mm_setr_ph(14.0, 15.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19177        assert_eq_m128h(r, e);
19178    }
19179
19180    #[simd_test(enable = "avx512fp16,avx512vl")]
19181    fn test_mm_maskz_fmul_sch() {
19182        let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19183        let b = _mm_setr_ph(0.0, 1.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
19184        let r = _mm_maskz_fmul_sch(0, a, b);
19185        let e = _mm_setr_ph(0.0, 0.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19186        assert_eq_m128h(r, e);
19187    }
19188
19189    #[simd_test(enable = "avx512fp16,avx512vl")]
19190    fn test_mm_cmul_pch() {
19191        let a = _mm_set1_pch(0.0, 1.0);
19192        let b = _mm_set1_pch(0.0, -1.0);
19193        let r = _mm_cmul_pch(a, b);
19194        let e = _mm_set1_pch(-1.0, 0.0);
19195        assert_eq_m128h(r, e);
19196    }
19197
19198    #[simd_test(enable = "avx512fp16,avx512vl")]
19199    fn test_mm_mask_cmul_pch() {
19200        let a = _mm_set1_pch(0.0, 1.0);
19201        let b = _mm_set1_pch(0.0, -1.0);
19202        let src = _mm_setr_ph(2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0);
19203        let r = _mm_mask_cmul_pch(src, 0b0101, a, b);
19204        let e = _mm_setr_ph(-1.0, 0.0, 4.0, 5.0, -1.0, 0.0, 8.0, 9.0);
19205        assert_eq_m128h(r, e);
19206    }
19207
19208    #[simd_test(enable = "avx512fp16,avx512vl")]
19209    fn test_mm_maskz_cmul_pch() {
19210        let a = _mm_set1_pch(0.0, 1.0);
19211        let b = _mm_set1_pch(0.0, -1.0);
19212        let r = _mm_maskz_cmul_pch(0b0101, a, b);
19213        let e = _mm_setr_ph(-1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0);
19214        assert_eq_m128h(r, e);
19215    }
19216
19217    #[simd_test(enable = "avx512fp16,avx512vl")]
19218    fn test_mm256_cmul_pch() {
19219        let a = _mm256_set1_pch(0.0, 1.0);
19220        let b = _mm256_set1_pch(0.0, -1.0);
19221        let r = _mm256_cmul_pch(a, b);
19222        let e = _mm256_set1_pch(-1.0, 0.0);
19223        assert_eq_m256h(r, e);
19224    }
19225
19226    #[simd_test(enable = "avx512fp16,avx512vl")]
19227    fn test_mm256_mask_cmul_pch() {
19228        let a = _mm256_set1_pch(0.0, 1.0);
19229        let b = _mm256_set1_pch(0.0, -1.0);
19230        let src = _mm256_setr_ph(
19231            2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0,
19232        );
19233        let r = _mm256_mask_cmul_pch(src, 0b01010101, a, b);
19234        let e = _mm256_setr_ph(
19235            -1.0, 0.0, 4.0, 5.0, -1.0, 0.0, 8.0, 9.0, -1.0, 0.0, 12.0, 13.0, -1.0, 0.0, 16.0, 17.0,
19236        );
19237        assert_eq_m256h(r, e);
19238    }
19239
19240    #[simd_test(enable = "avx512fp16,avx512vl")]
19241    fn test_mm256_maskz_cmul_pch() {
19242        let a = _mm256_set1_pch(0.0, 1.0);
19243        let b = _mm256_set1_pch(0.0, -1.0);
19244        let r = _mm256_maskz_cmul_pch(0b01010101, a, b);
19245        let e = _mm256_setr_ph(
19246            -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0,
19247        );
19248        assert_eq_m256h(r, e);
19249    }
19250
19251    #[simd_test(enable = "avx512fp16")]
19252    fn test_mm512_cmul_pch() {
19253        let a = _mm512_set1_pch(0.0, 1.0);
19254        let b = _mm512_set1_pch(0.0, -1.0);
19255        let r = _mm512_cmul_pch(a, b);
19256        let e = _mm512_set1_pch(-1.0, 0.0);
19257        assert_eq_m512h(r, e);
19258    }
19259
19260    #[simd_test(enable = "avx512fp16")]
19261    fn test_mm512_mask_cmul_pch() {
19262        let a = _mm512_set1_pch(0.0, 1.0);
19263        let b = _mm512_set1_pch(0.0, -1.0);
19264        let src = _mm512_setr_ph(
19265            2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0,
19266            18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0, 31.0,
19267            32.0, 33.0,
19268        );
19269        let r = _mm512_mask_cmul_pch(src, 0b0101010101010101, a, b);
19270        let e = _mm512_setr_ph(
19271            -1.0, 0.0, 4.0, 5.0, -1.0, 0.0, 8.0, 9.0, -1.0, 0.0, 12.0, 13.0, -1.0, 0.0, 16.0, 17.0,
19272            -1.0, 0.0, 20.0, 21.0, -1.0, 0.0, 24.0, 25.0, -1.0, 0.0, 28.0, 29.0, -1.0, 0.0, 32.0,
19273            33.0,
19274        );
19275        assert_eq_m512h(r, e);
19276    }
19277
19278    #[simd_test(enable = "avx512fp16")]
19279    fn test_mm512_maskz_cmul_pch() {
19280        let a = _mm512_set1_pch(0.0, 1.0);
19281        let b = _mm512_set1_pch(0.0, -1.0);
19282        let r = _mm512_maskz_cmul_pch(0b0101010101010101, a, b);
19283        let e = _mm512_setr_ph(
19284            -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0,
19285            -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0,
19286        );
19287        assert_eq_m512h(r, e);
19288    }
19289
19290    #[simd_test(enable = "avx512fp16")]
19291    fn test_mm512_cmul_round_pch() {
19292        let a = _mm512_set1_pch(0.0, 1.0);
19293        let b = _mm512_set1_pch(0.0, -1.0);
19294        let r = _mm512_cmul_round_pch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
19295        let e = _mm512_set1_pch(-1.0, 0.0);
19296        assert_eq_m512h(r, e);
19297    }
19298
19299    #[simd_test(enable = "avx512fp16")]
19300    fn test_mm512_mask_cmul_round_pch() {
19301        let a = _mm512_set1_pch(0.0, 1.0);
19302        let b = _mm512_set1_pch(0.0, -1.0);
19303        let src = _mm512_setr_ph(
19304            2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0,
19305            18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0, 31.0,
19306            32.0, 33.0,
19307        );
19308        let r = _mm512_mask_cmul_round_pch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
19309            src,
19310            0b0101010101010101,
19311            a,
19312            b,
19313        );
19314        let e = _mm512_setr_ph(
19315            -1.0, 0.0, 4.0, 5.0, -1.0, 0.0, 8.0, 9.0, -1.0, 0.0, 12.0, 13.0, -1.0, 0.0, 16.0, 17.0,
19316            -1.0, 0.0, 20.0, 21.0, -1.0, 0.0, 24.0, 25.0, -1.0, 0.0, 28.0, 29.0, -1.0, 0.0, 32.0,
19317            33.0,
19318        );
19319        assert_eq_m512h(r, e);
19320    }
19321
19322    #[simd_test(enable = "avx512fp16")]
19323    fn test_mm512_maskz_cmul_round_pch() {
19324        let a = _mm512_set1_pch(0.0, 1.0);
19325        let b = _mm512_set1_pch(0.0, -1.0);
19326        let r = _mm512_maskz_cmul_round_pch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
19327            0b0101010101010101,
19328            a,
19329            b,
19330        );
19331        let e = _mm512_setr_ph(
19332            -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0,
19333            -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0,
19334        );
19335        assert_eq_m512h(r, e);
19336    }
19337
19338    #[simd_test(enable = "avx512fp16,avx512vl")]
19339    fn test_mm_cmul_sch() {
19340        let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19341        let b = _mm_setr_ph(0.0, -1.0, 8.0, -9.0, 10.0, -11.0, 12.0, -13.0);
19342        let r = _mm_cmul_sch(a, b);
19343        let e = _mm_setr_ph(-1.0, 0.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19344        assert_eq_m128h(r, e);
19345    }
19346
19347    #[simd_test(enable = "avx512fp16,avx512vl")]
19348    fn test_mm_mask_cmul_sch() {
19349        let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19350        let b = _mm_setr_ph(0.0, -1.0, 8.0, -9.0, 10.0, -11.0, 12.0, -13.0);
19351        let src = _mm_setr_ph(14.0, 15.0, 16.0, 17.0, 18.0, 19.0, 20.0, 21.0);
19352        let r = _mm_mask_cmul_sch(src, 0, a, b);
19353        let e = _mm_setr_ph(14.0, 15.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19354        assert_eq_m128h(r, e);
19355    }
19356
19357    #[simd_test(enable = "avx512fp16,avx512vl")]
19358    fn test_mm_maskz_cmul_sch() {
19359        let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19360        let b = _mm_setr_ph(0.0, -1.0, 8.0, -9.0, 10.0, -11.0, 12.0, -13.0);
19361        let r = _mm_maskz_cmul_sch(0, a, b);
19362        let e = _mm_setr_ph(0.0, 0.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19363        assert_eq_m128h(r, e);
19364    }
19365
19366    #[simd_test(enable = "avx512fp16,avx512vl")]
19367    fn test_mm_cmul_round_sch() {
19368        let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19369        let b = _mm_setr_ph(0.0, -1.0, 8.0, -9.0, 10.0, -11.0, 12.0, -13.0);
19370        let r = _mm_cmul_round_sch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
19371        let e = _mm_setr_ph(-1.0, 0.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19372        assert_eq_m128h(r, e);
19373    }
19374
19375    #[simd_test(enable = "avx512fp16,avx512vl")]
19376    fn test_mm_mask_cmul_round_sch() {
19377        let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19378        let b = _mm_setr_ph(0.0, -1.0, 8.0, -9.0, 10.0, -11.0, 12.0, -13.0);
19379        let src = _mm_setr_ph(14.0, 15.0, 16.0, 17.0, 18.0, 19.0, 20.0, 21.0);
19380        let r = _mm_mask_cmul_round_sch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
19381            src, 0, a, b,
19382        );
19383        let e = _mm_setr_ph(14.0, 15.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19384        assert_eq_m128h(r, e);
19385    }
19386
19387    #[simd_test(enable = "avx512fp16,avx512vl")]
19388    fn test_mm_maskz_cmul_round_sch() {
19389        let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19390        let b = _mm_setr_ph(0.0, -1.0, 8.0, -9.0, 10.0, -11.0, 12.0, -13.0);
19391        let r =
19392            _mm_maskz_cmul_round_sch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
19393        let e = _mm_setr_ph(0.0, 0.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19394        assert_eq_m128h(r, e);
19395    }
19396
19397    #[simd_test(enable = "avx512fp16,avx512vl")]
19398    fn test_mm_fcmul_pch() {
19399        let a = _mm_set1_pch(0.0, 1.0);
19400        let b = _mm_set1_pch(0.0, -1.0);
19401        let r = _mm_fcmul_pch(a, b);
19402        let e = _mm_set1_pch(-1.0, 0.0);
19403        assert_eq_m128h(r, e);
19404    }
19405
19406    #[simd_test(enable = "avx512fp16,avx512vl")]
19407    fn test_mm_mask_fcmul_pch() {
19408        let a = _mm_set1_pch(0.0, 1.0);
19409        let b = _mm_set1_pch(0.0, -1.0);
19410        let src = _mm_setr_ph(2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0);
19411        let r = _mm_mask_fcmul_pch(src, 0b0101, a, b);
19412        let e = _mm_setr_ph(-1.0, 0.0, 4.0, 5.0, -1.0, 0.0, 8.0, 9.0);
19413        assert_eq_m128h(r, e);
19414    }
19415
19416    #[simd_test(enable = "avx512fp16,avx512vl")]
19417    fn test_mm_maskz_fcmul_pch() {
19418        let a = _mm_set1_pch(0.0, 1.0);
19419        let b = _mm_set1_pch(0.0, -1.0);
19420        let r = _mm_maskz_fcmul_pch(0b0101, a, b);
19421        let e = _mm_setr_ph(-1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0);
19422        assert_eq_m128h(r, e);
19423    }
19424
19425    #[simd_test(enable = "avx512fp16,avx512vl")]
19426    fn test_mm256_fcmul_pch() {
19427        let a = _mm256_set1_pch(0.0, 1.0);
19428        let b = _mm256_set1_pch(0.0, -1.0);
19429        let r = _mm256_fcmul_pch(a, b);
19430        let e = _mm256_set1_pch(-1.0, 0.0);
19431        assert_eq_m256h(r, e);
19432    }
19433
19434    #[simd_test(enable = "avx512fp16,avx512vl")]
19435    fn test_mm256_mask_fcmul_pch() {
19436        let a = _mm256_set1_pch(0.0, 1.0);
19437        let b = _mm256_set1_pch(0.0, -1.0);
19438        let src = _mm256_setr_ph(
19439            2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0,
19440        );
19441        let r = _mm256_mask_fcmul_pch(src, 0b01010101, a, b);
19442        let e = _mm256_setr_ph(
19443            -1.0, 0.0, 4.0, 5.0, -1.0, 0.0, 8.0, 9.0, -1.0, 0.0, 12.0, 13.0, -1.0, 0.0, 16.0, 17.0,
19444        );
19445        assert_eq_m256h(r, e);
19446    }
19447
19448    #[simd_test(enable = "avx512fp16,avx512vl")]
19449    fn test_mm256_maskz_fcmul_pch() {
19450        let a = _mm256_set1_pch(0.0, 1.0);
19451        let b = _mm256_set1_pch(0.0, -1.0);
19452        let r = _mm256_maskz_fcmul_pch(0b01010101, a, b);
19453        let e = _mm256_setr_ph(
19454            -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0,
19455        );
19456        assert_eq_m256h(r, e);
19457    }
19458
19459    #[simd_test(enable = "avx512fp16")]
19460    fn test_mm512_fcmul_pch() {
19461        let a = _mm512_set1_pch(0.0, 1.0);
19462        let b = _mm512_set1_pch(0.0, -1.0);
19463        let r = _mm512_fcmul_pch(a, b);
19464        let e = _mm512_set1_pch(-1.0, 0.0);
19465        assert_eq_m512h(r, e);
19466    }
19467
19468    #[simd_test(enable = "avx512fp16")]
19469    fn test_mm512_mask_fcmul_pch() {
19470        let a = _mm512_set1_pch(0.0, 1.0);
19471        let b = _mm512_set1_pch(0.0, -1.0);
19472        let src = _mm512_setr_ph(
19473            2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0,
19474            18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0, 31.0,
19475            32.0, 33.0,
19476        );
19477        let r = _mm512_mask_fcmul_pch(src, 0b0101010101010101, a, b);
19478        let e = _mm512_setr_ph(
19479            -1.0, 0.0, 4.0, 5.0, -1.0, 0.0, 8.0, 9.0, -1.0, 0.0, 12.0, 13.0, -1.0, 0.0, 16.0, 17.0,
19480            -1.0, 0.0, 20.0, 21.0, -1.0, 0.0, 24.0, 25.0, -1.0, 0.0, 28.0, 29.0, -1.0, 0.0, 32.0,
19481            33.0,
19482        );
19483        assert_eq_m512h(r, e);
19484    }
19485
19486    #[simd_test(enable = "avx512fp16")]
19487    fn test_mm512_maskz_fcmul_pch() {
19488        let a = _mm512_set1_pch(0.0, 1.0);
19489        let b = _mm512_set1_pch(0.0, -1.0);
19490        let r = _mm512_maskz_fcmul_pch(0b0101010101010101, a, b);
19491        let e = _mm512_setr_ph(
19492            -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0,
19493            -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0,
19494        );
19495        assert_eq_m512h(r, e);
19496    }
19497
19498    #[simd_test(enable = "avx512fp16")]
19499    fn test_mm512_fcmul_round_pch() {
19500        let a = _mm512_set1_pch(0.0, 1.0);
19501        let b = _mm512_set1_pch(0.0, -1.0);
19502        let r = _mm512_fcmul_round_pch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
19503        let e = _mm512_set1_pch(-1.0, 0.0);
19504        assert_eq_m512h(r, e);
19505    }
19506
19507    #[simd_test(enable = "avx512fp16")]
19508    fn test_mm512_mask_fcmul_round_pch() {
19509        let a = _mm512_set1_pch(0.0, 1.0);
19510        let b = _mm512_set1_pch(0.0, -1.0);
19511        let src = _mm512_setr_ph(
19512            2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0,
19513            18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0, 31.0,
19514            32.0, 33.0,
19515        );
19516        let r = _mm512_mask_fcmul_round_pch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
19517            src,
19518            0b0101010101010101,
19519            a,
19520            b,
19521        );
19522        let e = _mm512_setr_ph(
19523            -1.0, 0.0, 4.0, 5.0, -1.0, 0.0, 8.0, 9.0, -1.0, 0.0, 12.0, 13.0, -1.0, 0.0, 16.0, 17.0,
19524            -1.0, 0.0, 20.0, 21.0, -1.0, 0.0, 24.0, 25.0, -1.0, 0.0, 28.0, 29.0, -1.0, 0.0, 32.0,
19525            33.0,
19526        );
19527        assert_eq_m512h(r, e);
19528    }
19529
19530    #[simd_test(enable = "avx512fp16")]
19531    fn test_mm512_maskz_fcmul_round_pch() {
19532        let a = _mm512_set1_pch(0.0, 1.0);
19533        let b = _mm512_set1_pch(0.0, -1.0);
19534        let r = _mm512_maskz_fcmul_round_pch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
19535            0b0101010101010101,
19536            a,
19537            b,
19538        );
19539        let e = _mm512_setr_ph(
19540            -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0,
19541            -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0,
19542        );
19543        assert_eq_m512h(r, e);
19544    }
19545
19546    #[simd_test(enable = "avx512fp16,avx512vl")]
19547    fn test_mm_fcmul_sch() {
19548        let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19549        let b = _mm_setr_ph(0.0, -1.0, 8.0, -9.0, 10.0, -11.0, 12.0, -13.0);
19550        let r = _mm_fcmul_sch(a, b);
19551        let e = _mm_setr_ph(-1.0, 0.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19552        assert_eq_m128h(r, e);
19553    }
19554
19555    #[simd_test(enable = "avx512fp16,avx512vl")]
19556    fn test_mm_mask_fcmul_sch() {
19557        let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19558        let b = _mm_setr_ph(0.0, -1.0, 8.0, -9.0, 10.0, -11.0, 12.0, -13.0);
19559        let src = _mm_setr_ph(14.0, 15.0, 16.0, 17.0, 18.0, 19.0, 20.0, 21.0);
19560        let r = _mm_mask_fcmul_sch(src, 0, a, b);
19561        let e = _mm_setr_ph(14.0, 15.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19562        assert_eq_m128h(r, e);
19563    }
19564
19565    #[simd_test(enable = "avx512fp16,avx512vl")]
19566    fn test_mm_maskz_fcmul_sch() {
19567        let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19568        let b = _mm_setr_ph(0.0, -1.0, 8.0, -9.0, 10.0, -11.0, 12.0, -13.0);
19569        let r = _mm_maskz_fcmul_sch(0, a, b);
19570        let e = _mm_setr_ph(0.0, 0.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19571        assert_eq_m128h(r, e);
19572    }
19573
19574    #[simd_test(enable = "avx512fp16,avx512vl")]
19575    fn test_mm_fcmul_round_sch() {
19576        let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19577        let b = _mm_setr_ph(0.0, -1.0, 8.0, -9.0, 10.0, -11.0, 12.0, -13.0);
19578        let r = _mm_fcmul_round_sch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
19579        let e = _mm_setr_ph(-1.0, 0.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19580        assert_eq_m128h(r, e);
19581    }
19582
19583    #[simd_test(enable = "avx512fp16,avx512vl")]
19584    fn test_mm_mask_fcmul_round_sch() {
19585        let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19586        let b = _mm_setr_ph(0.0, -1.0, 8.0, -9.0, 10.0, -11.0, 12.0, -13.0);
19587        let src = _mm_setr_ph(14.0, 15.0, 16.0, 17.0, 18.0, 19.0, 20.0, 21.0);
19588        let r = _mm_mask_fcmul_round_sch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
19589            src, 0, a, b,
19590        );
19591        let e = _mm_setr_ph(14.0, 15.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19592        assert_eq_m128h(r, e);
19593    }
19594
19595    #[simd_test(enable = "avx512fp16,avx512vl")]
19596    fn test_mm_maskz_fcmul_round_sch() {
19597        let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19598        let b = _mm_setr_ph(0.0, -1.0, 8.0, -9.0, 10.0, -11.0, 12.0, -13.0);
19599        let r =
19600            _mm_maskz_fcmul_round_sch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
19601        let e = _mm_setr_ph(0.0, 0.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19602        assert_eq_m128h(r, e);
19603    }
19604
19605    #[simd_test(enable = "avx512fp16,avx512vl")]
19606    const fn test_mm_abs_ph() {
19607        let a = _mm_set_ph(-1.0, 0.0, 1.0, -2.0, 3.0, -4.0, 5.0, -6.0);
19608        let r = _mm_abs_ph(a);
19609        let e = _mm_set_ph(1.0, 0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0);
19610        assert_eq_m128h(r, e);
19611    }
19612
19613    #[simd_test(enable = "avx512fp16,avx512vl")]
19614    const fn test_mm256_abs_ph() {
19615        let a = _mm256_set_ph(
19616            -1.0, 0.0, 1.0, -2.0, 3.0, -4.0, 5.0, -6.0, 7.0, -8.0, 9.0, -10.0, 11.0, -12.0, 13.0,
19617            -14.0,
19618        );
19619        let r = _mm256_abs_ph(a);
19620        let e = _mm256_set_ph(
19621            1.0, 0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0,
19622        );
19623        assert_eq_m256h(r, e);
19624    }
19625
19626    #[simd_test(enable = "avx512fp16")]
19627    const fn test_mm512_abs_ph() {
19628        let a = _mm512_set_ph(
19629            -1.0, 0.0, 1.0, -2.0, 3.0, -4.0, 5.0, -6.0, 7.0, -8.0, 9.0, -10.0, 11.0, -12.0, 13.0,
19630            -14.0, 15.0, -16.0, 17.0, -18.0, 19.0, -20.0, 21.0, -22.0, 23.0, -24.0, 25.0, -26.0,
19631            27.0, -28.0, 29.0, -30.0,
19632        );
19633        let r = _mm512_abs_ph(a);
19634        let e = _mm512_set_ph(
19635            1.0, 0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0,
19636            15.0, 16.0, 17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0,
19637            29.0, 30.0,
19638        );
19639        assert_eq_m512h(r, e);
19640    }
19641
19642    #[simd_test(enable = "avx512fp16,avx512vl")]
19643    const fn test_mm_conj_pch() {
19644        let a = _mm_set1_pch(0.0, 1.0);
19645        let r = _mm_conj_pch(a);
19646        let e = _mm_set1_pch(0.0, -1.0);
19647        assert_eq_m128h(r, e);
19648    }
19649
19650    #[simd_test(enable = "avx512fp16,avx512vl")]
19651    const fn test_mm_mask_conj_pch() {
19652        let a = _mm_set1_pch(0.0, 1.0);
19653        let src = _mm_setr_ph(2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0);
19654        let r = _mm_mask_conj_pch(src, 0b0101, a);
19655        let e = _mm_setr_ph(0.0, -1.0, 4.0, 5.0, 0.0, -1.0, 8.0, 9.0);
19656        assert_eq_m128h(r, e);
19657    }
19658
19659    #[simd_test(enable = "avx512fp16,avx512vl")]
19660    const fn test_mm_maskz_conj_pch() {
19661        let a = _mm_set1_pch(0.0, 1.0);
19662        let r = _mm_maskz_conj_pch(0b0101, a);
19663        let e = _mm_setr_ph(0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0);
19664        assert_eq_m128h(r, e);
19665    }
19666
19667    #[simd_test(enable = "avx512fp16,avx512vl")]
19668    const fn test_mm256_conj_pch() {
19669        let a = _mm256_set1_pch(0.0, 1.0);
19670        let r = _mm256_conj_pch(a);
19671        let e = _mm256_set1_pch(0.0, -1.0);
19672        assert_eq_m256h(r, e);
19673    }
19674
19675    #[simd_test(enable = "avx512fp16,avx512vl")]
19676    const fn test_mm256_mask_conj_pch() {
19677        let a = _mm256_set1_pch(0.0, 1.0);
19678        let src = _mm256_setr_ph(
19679            2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0,
19680        );
19681        let r = _mm256_mask_conj_pch(src, 0b01010101, a);
19682        let e = _mm256_setr_ph(
19683            0.0, -1.0, 4.0, 5.0, 0.0, -1.0, 8.0, 9.0, 0.0, -1.0, 12.0, 13.0, 0.0, -1.0, 16.0, 17.0,
19684        );
19685        assert_eq_m256h(r, e);
19686    }
19687
19688    #[simd_test(enable = "avx512fp16,avx512vl")]
19689    const fn test_mm256_maskz_conj_pch() {
19690        let a = _mm256_set1_pch(0.0, 1.0);
19691        let r = _mm256_maskz_conj_pch(0b01010101, a);
19692        let e = _mm256_setr_ph(
19693            0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0,
19694        );
19695        assert_eq_m256h(r, e);
19696    }
19697
19698    #[simd_test(enable = "avx512fp16")]
19699    const fn test_mm512_conj_pch() {
19700        let a = _mm512_set1_pch(0.0, 1.0);
19701        let r = _mm512_conj_pch(a);
19702        let e = _mm512_set1_pch(0.0, -1.0);
19703        assert_eq_m512h(r, e);
19704    }
19705
19706    #[simd_test(enable = "avx512fp16")]
19707    const fn test_mm512_mask_conj_pch() {
19708        let a = _mm512_set1_pch(0.0, 1.0);
19709        let src = _mm512_setr_ph(
19710            2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0,
19711            18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0, 31.0,
19712            32.0, 33.0,
19713        );
19714        let r = _mm512_mask_conj_pch(src, 0b0101010101010101, a);
19715        let e = _mm512_setr_ph(
19716            0.0, -1.0, 4.0, 5.0, 0.0, -1.0, 8.0, 9.0, 0.0, -1.0, 12.0, 13.0, 0.0, -1.0, 16.0, 17.0,
19717            0.0, -1.0, 20.0, 21.0, 0.0, -1.0, 24.0, 25.0, 0.0, -1.0, 28.0, 29.0, 0.0, -1.0, 32.0,
19718            33.0,
19719        );
19720        assert_eq_m512h(r, e);
19721    }
19722
19723    #[simd_test(enable = "avx512fp16")]
19724    const fn test_mm512_maskz_conj_pch() {
19725        let a = _mm512_set1_pch(0.0, 1.0);
19726        let r = _mm512_maskz_conj_pch(0b0101010101010101, a);
19727        let e = _mm512_setr_ph(
19728            0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0,
19729            0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0,
19730        );
19731        assert_eq_m512h(r, e);
19732    }
19733
19734    #[simd_test(enable = "avx512fp16,avx512vl")]
19735    fn test_mm_fmadd_pch() {
19736        let a = _mm_set1_pch(0.0, 1.0);
19737        let b = _mm_set1_pch(0.0, 2.0);
19738        let c = _mm_set1_pch(0.0, 3.0);
19739        let r = _mm_fmadd_pch(a, b, c);
19740        let e = _mm_set1_pch(-2.0, 3.0);
19741        assert_eq_m128h(r, e);
19742    }
19743
19744    #[simd_test(enable = "avx512fp16,avx512vl")]
19745    fn test_mm_mask_fmadd_pch() {
19746        let a = _mm_set1_pch(0.0, 1.0);
19747        let b = _mm_set1_pch(0.0, 2.0);
19748        let c = _mm_set1_pch(0.0, 3.0);
19749        let r = _mm_mask_fmadd_pch(a, 0b0101, b, c);
19750        let e = _mm_setr_ph(-2.0, 3.0, 0.0, 1.0, -2.0, 3.0, 0.0, 1.0);
19751        assert_eq_m128h(r, e);
19752    }
19753
19754    #[simd_test(enable = "avx512fp16,avx512vl")]
19755    fn test_mm_mask3_fmadd_pch() {
19756        let a = _mm_set1_pch(0.0, 1.0);
19757        let b = _mm_set1_pch(0.0, 2.0);
19758        let c = _mm_set1_pch(0.0, 3.0);
19759        let r = _mm_mask3_fmadd_pch(a, b, c, 0b0101);
19760        let e = _mm_setr_ph(-2.0, 3.0, 0.0, 3.0, -2.0, 3.0, 0.0, 3.0);
19761        assert_eq_m128h(r, e);
19762    }
19763
19764    #[simd_test(enable = "avx512fp16,avx512vl")]
19765    fn test_mm_maskz_fmadd_pch() {
19766        let a = _mm_set1_pch(0.0, 1.0);
19767        let b = _mm_set1_pch(0.0, 2.0);
19768        let c = _mm_set1_pch(0.0, 3.0);
19769        let r = _mm_maskz_fmadd_pch(0b0101, a, b, c);
19770        let e = _mm_setr_ph(-2.0, 3.0, 0.0, 0.0, -2.0, 3.0, 0.0, 0.0);
19771        assert_eq_m128h(r, e);
19772    }
19773
19774    #[simd_test(enable = "avx512fp16,avx512vl")]
19775    fn test_mm256_fmadd_pch() {
19776        let a = _mm256_set1_pch(0.0, 1.0);
19777        let b = _mm256_set1_pch(0.0, 2.0);
19778        let c = _mm256_set1_pch(0.0, 3.0);
19779        let r = _mm256_fmadd_pch(a, b, c);
19780        let e = _mm256_set1_pch(-2.0, 3.0);
19781        assert_eq_m256h(r, e);
19782    }
19783
19784    #[simd_test(enable = "avx512fp16,avx512vl")]
19785    fn test_mm256_mask_fmadd_pch() {
19786        let a = _mm256_set1_pch(0.0, 1.0);
19787        let b = _mm256_set1_pch(0.0, 2.0);
19788        let c = _mm256_set1_pch(0.0, 3.0);
19789        let r = _mm256_mask_fmadd_pch(a, 0b01010101, b, c);
19790        let e = _mm256_setr_ph(
19791            -2.0, 3.0, 0.0, 1.0, -2.0, 3.0, 0.0, 1.0, -2.0, 3.0, 0.0, 1.0, -2.0, 3.0, 0.0, 1.0,
19792        );
19793        assert_eq_m256h(r, e);
19794    }
19795
19796    #[simd_test(enable = "avx512fp16,avx512vl")]
19797    fn test_mm256_mask3_fmadd_pch() {
19798        let a = _mm256_set1_pch(0.0, 1.0);
19799        let b = _mm256_set1_pch(0.0, 2.0);
19800        let c = _mm256_set1_pch(0.0, 3.0);
19801        let r = _mm256_mask3_fmadd_pch(a, b, c, 0b01010101);
19802        let e = _mm256_setr_ph(
19803            -2.0, 3.0, 0.0, 3.0, -2.0, 3.0, 0.0, 3.0, -2.0, 3.0, 0.0, 3.0, -2.0, 3.0, 0.0, 3.0,
19804        );
19805        assert_eq_m256h(r, e);
19806    }
19807
19808    #[simd_test(enable = "avx512fp16,avx512vl")]
19809    fn test_mm256_maskz_fmadd_pch() {
19810        let a = _mm256_set1_pch(0.0, 1.0);
19811        let b = _mm256_set1_pch(0.0, 2.0);
19812        let c = _mm256_set1_pch(0.0, 3.0);
19813        let r = _mm256_maskz_fmadd_pch(0b01010101, a, b, c);
19814        let e = _mm256_setr_ph(
19815            -2.0, 3.0, 0.0, 0.0, -2.0, 3.0, 0.0, 0.0, -2.0, 3.0, 0.0, 0.0, -2.0, 3.0, 0.0, 0.0,
19816        );
19817        assert_eq_m256h(r, e);
19818    }
19819
19820    #[simd_test(enable = "avx512fp16")]
19821    fn test_mm512_fmadd_pch() {
19822        let a = _mm512_set1_pch(0.0, 1.0);
19823        let b = _mm512_set1_pch(0.0, 2.0);
19824        let c = _mm512_set1_pch(0.0, 3.0);
19825        let r = _mm512_fmadd_pch(a, b, c);
19826        let e = _mm512_set1_pch(-2.0, 3.0);
19827        assert_eq_m512h(r, e);
19828    }
19829
19830    #[simd_test(enable = "avx512fp16")]
19831    fn test_mm512_mask_fmadd_pch() {
19832        let a = _mm512_set1_pch(0.0, 1.0);
19833        let b = _mm512_set1_pch(0.0, 2.0);
19834        let c = _mm512_set1_pch(0.0, 3.0);
19835        let r = _mm512_mask_fmadd_pch(a, 0b0101010101010101, b, c);
19836        let e = _mm512_setr_ph(
19837            -2.0, 3.0, 0.0, 1.0, -2.0, 3.0, 0.0, 1.0, -2.0, 3.0, 0.0, 1.0, -2.0, 3.0, 0.0, 1.0,
19838            -2.0, 3.0, 0.0, 1.0, -2.0, 3.0, 0.0, 1.0, -2.0, 3.0, 0.0, 1.0, -2.0, 3.0, 0.0, 1.0,
19839        );
19840        assert_eq_m512h(r, e);
19841    }
19842
19843    #[simd_test(enable = "avx512fp16")]
19844    fn test_mm512_mask3_fmadd_pch() {
19845        let a = _mm512_set1_pch(0.0, 1.0);
19846        let b = _mm512_set1_pch(0.0, 2.0);
19847        let c = _mm512_set1_pch(0.0, 3.0);
19848        let r = _mm512_mask3_fmadd_pch(a, b, c, 0b0101010101010101);
19849        let e = _mm512_setr_ph(
19850            -2.0, 3.0, 0.0, 3.0, -2.0, 3.0, 0.0, 3.0, -2.0, 3.0, 0.0, 3.0, -2.0, 3.0, 0.0, 3.0,
19851            -2.0, 3.0, 0.0, 3.0, -2.0, 3.0, 0.0, 3.0, -2.0, 3.0, 0.0, 3.0, -2.0, 3.0, 0.0, 3.0,
19852        );
19853        assert_eq_m512h(r, e);
19854    }
19855
19856    #[simd_test(enable = "avx512fp16")]
19857    fn test_mm512_maskz_fmadd_pch() {
19858        let a = _mm512_set1_pch(0.0, 1.0);
19859        let b = _mm512_set1_pch(0.0, 2.0);
19860        let c = _mm512_set1_pch(0.0, 3.0);
19861        let r = _mm512_maskz_fmadd_pch(0b0101010101010101, a, b, c);
19862        let e = _mm512_setr_ph(
19863            -2.0, 3.0, 0.0, 0.0, -2.0, 3.0, 0.0, 0.0, -2.0, 3.0, 0.0, 0.0, -2.0, 3.0, 0.0, 0.0,
19864            -2.0, 3.0, 0.0, 0.0, -2.0, 3.0, 0.0, 0.0, -2.0, 3.0, 0.0, 0.0, -2.0, 3.0, 0.0, 0.0,
19865        );
19866        assert_eq_m512h(r, e);
19867    }
19868
19869    #[simd_test(enable = "avx512fp16")]
19870    fn test_mm512_fmadd_round_pch() {
19871        let a = _mm512_set1_pch(0.0, 1.0);
19872        let b = _mm512_set1_pch(0.0, 2.0);
19873        let c = _mm512_set1_pch(0.0, 3.0);
19874        let r =
19875            _mm512_fmadd_round_pch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
19876        let e = _mm512_set1_pch(-2.0, 3.0);
19877        assert_eq_m512h(r, e);
19878    }
19879
19880    #[simd_test(enable = "avx512fp16")]
19881    fn test_mm512_mask_fmadd_round_pch() {
19882        let a = _mm512_set1_pch(0.0, 1.0);
19883        let b = _mm512_set1_pch(0.0, 2.0);
19884        let c = _mm512_set1_pch(0.0, 3.0);
19885        let r = _mm512_mask_fmadd_round_pch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
19886            a,
19887            0b0101010101010101,
19888            b,
19889            c,
19890        );
19891        let e = _mm512_setr_ph(
19892            -2.0, 3.0, 0.0, 1.0, -2.0, 3.0, 0.0, 1.0, -2.0, 3.0, 0.0, 1.0, -2.0, 3.0, 0.0, 1.0,
19893            -2.0, 3.0, 0.0, 1.0, -2.0, 3.0, 0.0, 1.0, -2.0, 3.0, 0.0, 1.0, -2.0, 3.0, 0.0, 1.0,
19894        );
19895        assert_eq_m512h(r, e);
19896    }
19897
19898    #[simd_test(enable = "avx512fp16")]
19899    fn test_mm512_mask3_fmadd_round_pch() {
19900        let a = _mm512_set1_pch(0.0, 1.0);
19901        let b = _mm512_set1_pch(0.0, 2.0);
19902        let c = _mm512_set1_pch(0.0, 3.0);
19903        let r = _mm512_mask3_fmadd_round_pch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
19904            a,
19905            b,
19906            c,
19907            0b0101010101010101,
19908        );
19909        let e = _mm512_setr_ph(
19910            -2.0, 3.0, 0.0, 3.0, -2.0, 3.0, 0.0, 3.0, -2.0, 3.0, 0.0, 3.0, -2.0, 3.0, 0.0, 3.0,
19911            -2.0, 3.0, 0.0, 3.0, -2.0, 3.0, 0.0, 3.0, -2.0, 3.0, 0.0, 3.0, -2.0, 3.0, 0.0, 3.0,
19912        );
19913        assert_eq_m512h(r, e);
19914    }
19915
19916    #[simd_test(enable = "avx512fp16")]
19917    fn test_mm512_maskz_fmadd_round_pch() {
19918        let a = _mm512_set1_pch(0.0, 1.0);
19919        let b = _mm512_set1_pch(0.0, 2.0);
19920        let c = _mm512_set1_pch(0.0, 3.0);
19921        let r = _mm512_maskz_fmadd_round_pch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
19922            0b0101010101010101,
19923            a,
19924            b,
19925            c,
19926        );
19927        let e = _mm512_setr_ph(
19928            -2.0, 3.0, 0.0, 0.0, -2.0, 3.0, 0.0, 0.0, -2.0, 3.0, 0.0, 0.0, -2.0, 3.0, 0.0, 0.0,
19929            -2.0, 3.0, 0.0, 0.0, -2.0, 3.0, 0.0, 0.0, -2.0, 3.0, 0.0, 0.0, -2.0, 3.0, 0.0, 0.0,
19930        );
19931        assert_eq_m512h(r, e);
19932    }
19933
19934    #[simd_test(enable = "avx512fp16,avx512vl")]
19935    fn test_mm_fmadd_sch() {
19936        let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19937        let b = _mm_setr_ph(0.0, 2.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
19938        let c = _mm_setr_ph(0.0, 3.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0);
19939        let r = _mm_fmadd_sch(a, b, c);
19940        let e = _mm_setr_ph(-2.0, 3.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19941        assert_eq_m128h(r, e);
19942    }
19943
19944    #[simd_test(enable = "avx512fp16,avx512vl")]
19945    fn test_mm_mask_fmadd_sch() {
19946        let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19947        let b = _mm_setr_ph(0.0, 2.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
19948        let c = _mm_setr_ph(0.0, 3.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0);
19949        let r = _mm_mask_fmadd_sch(a, 0, b, c);
19950        let e = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19951        assert_eq_m128h(r, e);
19952        let r = _mm_mask_fmadd_sch(a, 1, b, c);
19953        let e = _mm_setr_ph(-2.0, 3.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19954        assert_eq_m128h(r, e);
19955    }
19956
19957    #[simd_test(enable = "avx512fp16,avx512vl")]
19958    fn test_mm_mask3_fmadd_sch() {
19959        let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19960        let b = _mm_setr_ph(0.0, 2.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
19961        let c = _mm_setr_ph(0.0, 3.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0);
19962        let r = _mm_mask3_fmadd_sch(a, b, c, 0);
19963        let e = _mm_setr_ph(0.0, 3.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0);
19964        assert_eq_m128h(r, e);
19965        let r = _mm_mask3_fmadd_sch(a, b, c, 1);
19966        let e = _mm_setr_ph(-2.0, 3.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0);
19967        assert_eq_m128h(r, e);
19968    }
19969
19970    #[simd_test(enable = "avx512fp16,avx512vl")]
19971    fn test_mm_maskz_fmadd_sch() {
19972        let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19973        let b = _mm_setr_ph(0.0, 2.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
19974        let c = _mm_setr_ph(0.0, 3.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0);
19975        let r = _mm_maskz_fmadd_sch(0, a, b, c);
19976        let e = _mm_setr_ph(0.0, 0.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19977        assert_eq_m128h(r, e);
19978        let r = _mm_maskz_fmadd_sch(1, a, b, c);
19979        let e = _mm_setr_ph(-2.0, 3.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19980        assert_eq_m128h(r, e);
19981    }
19982
19983    #[simd_test(enable = "avx512fp16,avx512vl")]
19984    fn test_mm_fmadd_round_sch() {
19985        let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19986        let b = _mm_setr_ph(0.0, 2.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
19987        let c = _mm_setr_ph(0.0, 3.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0);
19988        let r = _mm_fmadd_round_sch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
19989        let e = _mm_setr_ph(-2.0, 3.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19990        assert_eq_m128h(r, e);
19991    }
19992
19993    #[simd_test(enable = "avx512fp16,avx512vl")]
19994    fn test_mm_mask_fmadd_round_sch() {
19995        let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
19996        let b = _mm_setr_ph(0.0, 2.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
19997        let c = _mm_setr_ph(0.0, 3.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0);
19998        let r = _mm_mask_fmadd_round_sch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
19999            a, 0, b, c,
20000        );
20001        let e = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
20002        assert_eq_m128h(r, e);
20003        let r = _mm_mask_fmadd_round_sch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
20004            a, 1, b, c,
20005        );
20006        let e = _mm_setr_ph(-2.0, 3.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
20007        assert_eq_m128h(r, e);
20008    }
20009
20010    #[simd_test(enable = "avx512fp16,avx512vl")]
20011    fn test_mm_mask3_fmadd_round_sch() {
20012        let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
20013        let b = _mm_setr_ph(0.0, 2.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
20014        let c = _mm_setr_ph(0.0, 3.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0);
20015        let r = _mm_mask3_fmadd_round_sch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
20016            a, b, c, 0,
20017        );
20018        let e = _mm_setr_ph(0.0, 3.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0);
20019        assert_eq_m128h(r, e);
20020        let r = _mm_mask3_fmadd_round_sch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
20021            a, b, c, 1,
20022        );
20023        let e = _mm_setr_ph(-2.0, 3.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0);
20024        assert_eq_m128h(r, e);
20025    }
20026
20027    #[simd_test(enable = "avx512fp16,avx512vl")]
20028    fn test_mm_maskz_fmadd_round_sch() {
20029        let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
20030        let b = _mm_setr_ph(0.0, 2.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
20031        let c = _mm_setr_ph(0.0, 3.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0);
20032        let r = _mm_maskz_fmadd_round_sch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
20033            0, a, b, c,
20034        );
20035        let e = _mm_setr_ph(0.0, 0.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
20036        assert_eq_m128h(r, e);
20037        let r = _mm_maskz_fmadd_round_sch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
20038            1, a, b, c,
20039        );
20040        let e = _mm_setr_ph(-2.0, 3.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
20041        assert_eq_m128h(r, e);
20042    }
20043
20044    #[simd_test(enable = "avx512fp16,avx512vl")]
20045    fn test_mm_fcmadd_pch() {
20046        let a = _mm_set1_pch(0.0, 1.0);
20047        let b = _mm_set1_pch(0.0, 2.0);
20048        let c = _mm_set1_pch(0.0, 3.0);
20049        let r = _mm_fcmadd_pch(a, b, c);
20050        let e = _mm_set1_pch(2.0, 3.0);
20051        assert_eq_m128h(r, e);
20052    }
20053
20054    #[simd_test(enable = "avx512fp16,avx512vl")]
20055    fn test_mm_mask_fcmadd_pch() {
20056        let a = _mm_set1_pch(0.0, 1.0);
20057        let b = _mm_set1_pch(0.0, 2.0);
20058        let c = _mm_set1_pch(0.0, 3.0);
20059        let r = _mm_mask_fcmadd_pch(a, 0b0101, b, c);
20060        let e = _mm_setr_ph(2.0, 3.0, 0.0, 1.0, 2.0, 3.0, 0.0, 1.0);
20061        assert_eq_m128h(r, e);
20062    }
20063
20064    #[simd_test(enable = "avx512fp16,avx512vl")]
20065    fn test_mm_mask3_fcmadd_pch() {
20066        let a = _mm_set1_pch(0.0, 1.0);
20067        let b = _mm_set1_pch(0.0, 2.0);
20068        let c = _mm_set1_pch(0.0, 3.0);
20069        let r = _mm_mask3_fcmadd_pch(a, b, c, 0b0101);
20070        let e = _mm_setr_ph(2.0, 3.0, 0.0, 3.0, 2.0, 3.0, 0.0, 3.0);
20071        assert_eq_m128h(r, e);
20072    }
20073
20074    #[simd_test(enable = "avx512fp16,avx512vl")]
20075    fn test_mm_maskz_fcmadd_pch() {
20076        let a = _mm_set1_pch(0.0, 1.0);
20077        let b = _mm_set1_pch(0.0, 2.0);
20078        let c = _mm_set1_pch(0.0, 3.0);
20079        let r = _mm_maskz_fcmadd_pch(0b0101, a, b, c);
20080        let e = _mm_setr_ph(2.0, 3.0, 0.0, 0.0, 2.0, 3.0, 0.0, 0.0);
20081        assert_eq_m128h(r, e);
20082    }
20083
20084    #[simd_test(enable = "avx512fp16,avx512vl")]
20085    fn test_mm256_fcmadd_pch() {
20086        let a = _mm256_set1_pch(0.0, 1.0);
20087        let b = _mm256_set1_pch(0.0, 2.0);
20088        let c = _mm256_set1_pch(0.0, 3.0);
20089        let r = _mm256_fcmadd_pch(a, b, c);
20090        let e = _mm256_set1_pch(2.0, 3.0);
20091        assert_eq_m256h(r, e);
20092    }
20093
20094    #[simd_test(enable = "avx512fp16,avx512vl")]
20095    fn test_mm256_mask_fcmadd_pch() {
20096        let a = _mm256_set1_pch(0.0, 1.0);
20097        let b = _mm256_set1_pch(0.0, 2.0);
20098        let c = _mm256_set1_pch(0.0, 3.0);
20099        let r = _mm256_mask_fcmadd_pch(a, 0b01010101, b, c);
20100        let e = _mm256_setr_ph(
20101            2.0, 3.0, 0.0, 1.0, 2.0, 3.0, 0.0, 1.0, 2.0, 3.0, 0.0, 1.0, 2.0, 3.0, 0.0, 1.0,
20102        );
20103        assert_eq_m256h(r, e);
20104    }
20105
20106    #[simd_test(enable = "avx512fp16,avx512vl")]
20107    fn test_mm256_mask3_fcmadd_pch() {
20108        let a = _mm256_set1_pch(0.0, 1.0);
20109        let b = _mm256_set1_pch(0.0, 2.0);
20110        let c = _mm256_set1_pch(0.0, 3.0);
20111        let r = _mm256_mask3_fcmadd_pch(a, b, c, 0b01010101);
20112        let e = _mm256_setr_ph(
20113            2.0, 3.0, 0.0, 3.0, 2.0, 3.0, 0.0, 3.0, 2.0, 3.0, 0.0, 3.0, 2.0, 3.0, 0.0, 3.0,
20114        );
20115        assert_eq_m256h(r, e);
20116    }
20117
20118    #[simd_test(enable = "avx512fp16,avx512vl")]
20119    fn test_mm256_maskz_fcmadd_pch() {
20120        let a = _mm256_set1_pch(0.0, 1.0);
20121        let b = _mm256_set1_pch(0.0, 2.0);
20122        let c = _mm256_set1_pch(0.0, 3.0);
20123        let r = _mm256_maskz_fcmadd_pch(0b01010101, a, b, c);
20124        let e = _mm256_setr_ph(
20125            2.0, 3.0, 0.0, 0.0, 2.0, 3.0, 0.0, 0.0, 2.0, 3.0, 0.0, 0.0, 2.0, 3.0, 0.0, 0.0,
20126        );
20127        assert_eq_m256h(r, e);
20128    }
20129
20130    #[simd_test(enable = "avx512fp16")]
20131    fn test_mm512_fcmadd_pch() {
20132        let a = _mm512_set1_pch(0.0, 1.0);
20133        let b = _mm512_set1_pch(0.0, 2.0);
20134        let c = _mm512_set1_pch(0.0, 3.0);
20135        let r = _mm512_fcmadd_pch(a, b, c);
20136        let e = _mm512_set1_pch(2.0, 3.0);
20137        assert_eq_m512h(r, e);
20138    }
20139
20140    #[simd_test(enable = "avx512fp16")]
20141    fn test_mm512_mask_fcmadd_pch() {
20142        let a = _mm512_set1_pch(0.0, 1.0);
20143        let b = _mm512_set1_pch(0.0, 2.0);
20144        let c = _mm512_set1_pch(0.0, 3.0);
20145        let r = _mm512_mask_fcmadd_pch(a, 0b0101010101010101, b, c);
20146        let e = _mm512_setr_ph(
20147            2.0, 3.0, 0.0, 1.0, 2.0, 3.0, 0.0, 1.0, 2.0, 3.0, 0.0, 1.0, 2.0, 3.0, 0.0, 1.0, 2.0,
20148            3.0, 0.0, 1.0, 2.0, 3.0, 0.0, 1.0, 2.0, 3.0, 0.0, 1.0, 2.0, 3.0, 0.0, 1.0,
20149        );
20150        assert_eq_m512h(r, e);
20151    }
20152
20153    #[simd_test(enable = "avx512fp16")]
20154    fn test_mm512_mask3_fcmadd_pch() {
20155        let a = _mm512_set1_pch(0.0, 1.0);
20156        let b = _mm512_set1_pch(0.0, 2.0);
20157        let c = _mm512_set1_pch(0.0, 3.0);
20158        let r = _mm512_mask3_fcmadd_pch(a, b, c, 0b0101010101010101);
20159        let e = _mm512_setr_ph(
20160            2.0, 3.0, 0.0, 3.0, 2.0, 3.0, 0.0, 3.0, 2.0, 3.0, 0.0, 3.0, 2.0, 3.0, 0.0, 3.0, 2.0,
20161            3.0, 0.0, 3.0, 2.0, 3.0, 0.0, 3.0, 2.0, 3.0, 0.0, 3.0, 2.0, 3.0, 0.0, 3.0,
20162        );
20163        assert_eq_m512h(r, e);
20164    }
20165
20166    #[simd_test(enable = "avx512fp16")]
20167    fn test_mm512_maskz_fcmadd_pch() {
20168        let a = _mm512_set1_pch(0.0, 1.0);
20169        let b = _mm512_set1_pch(0.0, 2.0);
20170        let c = _mm512_set1_pch(0.0, 3.0);
20171        let r = _mm512_maskz_fcmadd_pch(0b0101010101010101, a, b, c);
20172        let e = _mm512_setr_ph(
20173            2.0, 3.0, 0.0, 0.0, 2.0, 3.0, 0.0, 0.0, 2.0, 3.0, 0.0, 0.0, 2.0, 3.0, 0.0, 0.0, 2.0,
20174            3.0, 0.0, 0.0, 2.0, 3.0, 0.0, 0.0, 2.0, 3.0, 0.0, 0.0, 2.0, 3.0, 0.0, 0.0,
20175        );
20176        assert_eq_m512h(r, e);
20177    }
20178
20179    #[simd_test(enable = "avx512fp16")]
20180    fn test_mm512_fcmadd_round_pch() {
20181        let a = _mm512_set1_pch(0.0, 1.0);
20182        let b = _mm512_set1_pch(0.0, 2.0);
20183        let c = _mm512_set1_pch(0.0, 3.0);
20184        let r =
20185            _mm512_fcmadd_round_pch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
20186        let e = _mm512_set1_pch(2.0, 3.0);
20187        assert_eq_m512h(r, e);
20188    }
20189
20190    #[simd_test(enable = "avx512fp16")]
20191    fn test_mm512_mask_fcmadd_round_pch() {
20192        let a = _mm512_set1_pch(0.0, 1.0);
20193        let b = _mm512_set1_pch(0.0, 2.0);
20194        let c = _mm512_set1_pch(0.0, 3.0);
20195        let r = _mm512_mask_fcmadd_round_pch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
20196            a,
20197            0b0101010101010101,
20198            b,
20199            c,
20200        );
20201        let e = _mm512_setr_ph(
20202            2.0, 3.0, 0.0, 1.0, 2.0, 3.0, 0.0, 1.0, 2.0, 3.0, 0.0, 1.0, 2.0, 3.0, 0.0, 1.0, 2.0,
20203            3.0, 0.0, 1.0, 2.0, 3.0, 0.0, 1.0, 2.0, 3.0, 0.0, 1.0, 2.0, 3.0, 0.0, 1.0,
20204        );
20205        assert_eq_m512h(r, e);
20206    }
20207
20208    #[simd_test(enable = "avx512fp16")]
20209    fn test_mm512_mask3_fcmadd_round_pch() {
20210        let a = _mm512_set1_pch(0.0, 1.0);
20211        let b = _mm512_set1_pch(0.0, 2.0);
20212        let c = _mm512_set1_pch(0.0, 3.0);
20213        let r = _mm512_mask3_fcmadd_round_pch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
20214            a,
20215            b,
20216            c,
20217            0b0101010101010101,
20218        );
20219        let e = _mm512_setr_ph(
20220            2.0, 3.0, 0.0, 3.0, 2.0, 3.0, 0.0, 3.0, 2.0, 3.0, 0.0, 3.0, 2.0, 3.0, 0.0, 3.0, 2.0,
20221            3.0, 0.0, 3.0, 2.0, 3.0, 0.0, 3.0, 2.0, 3.0, 0.0, 3.0, 2.0, 3.0, 0.0, 3.0,
20222        );
20223        assert_eq_m512h(r, e);
20224    }
20225
20226    #[simd_test(enable = "avx512fp16")]
20227    fn test_mm512_maskz_fcmadd_round_pch() {
20228        let a = _mm512_set1_pch(0.0, 1.0);
20229        let b = _mm512_set1_pch(0.0, 2.0);
20230        let c = _mm512_set1_pch(0.0, 3.0);
20231        let r = _mm512_maskz_fcmadd_round_pch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
20232            0b0101010101010101,
20233            a,
20234            b,
20235            c,
20236        );
20237        let e = _mm512_setr_ph(
20238            2.0, 3.0, 0.0, 0.0, 2.0, 3.0, 0.0, 0.0, 2.0, 3.0, 0.0, 0.0, 2.0, 3.0, 0.0, 0.0, 2.0,
20239            3.0, 0.0, 0.0, 2.0, 3.0, 0.0, 0.0, 2.0, 3.0, 0.0, 0.0, 2.0, 3.0, 0.0, 0.0,
20240        );
20241        assert_eq_m512h(r, e);
20242    }
20243
20244    #[simd_test(enable = "avx512fp16,avx512vl")]
20245    fn test_mm_fcmadd_sch() {
20246        let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
20247        let b = _mm_setr_ph(0.0, 2.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
20248        let c = _mm_setr_ph(0.0, 3.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0);
20249        let r = _mm_fcmadd_sch(a, b, c);
20250        let e = _mm_setr_ph(2.0, 3.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
20251        assert_eq_m128h(r, e);
20252    }
20253
20254    #[simd_test(enable = "avx512fp16,avx512vl")]
20255    fn test_mm_mask_fcmadd_sch() {
20256        let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
20257        let b = _mm_setr_ph(0.0, 2.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
20258        let c = _mm_setr_ph(0.0, 3.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0);
20259        let r = _mm_mask_fcmadd_sch(a, 0, b, c);
20260        let e = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
20261        assert_eq_m128h(r, e);
20262        let r = _mm_mask_fcmadd_sch(a, 1, b, c);
20263        let e = _mm_setr_ph(2.0, 3.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
20264        assert_eq_m128h(r, e);
20265    }
20266
20267    #[simd_test(enable = "avx512fp16,avx512vl")]
20268    fn test_mm_mask3_fcmadd_sch() {
20269        let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
20270        let b = _mm_setr_ph(0.0, 2.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
20271        let c = _mm_setr_ph(0.0, 3.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0);
20272        let r = _mm_mask3_fcmadd_sch(a, b, c, 0);
20273        let e = _mm_setr_ph(0.0, 3.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0);
20274        assert_eq_m128h(r, e);
20275        let r = _mm_mask3_fcmadd_sch(a, b, c, 1);
20276        let e = _mm_setr_ph(2.0, 3.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0);
20277        assert_eq_m128h(r, e);
20278    }
20279
20280    #[simd_test(enable = "avx512fp16,avx512vl")]
20281    fn test_mm_maskz_fcmadd_sch() {
20282        let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
20283        let b = _mm_setr_ph(0.0, 2.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
20284        let c = _mm_setr_ph(0.0, 3.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0);
20285        let r = _mm_maskz_fcmadd_sch(0, a, b, c);
20286        let e = _mm_setr_ph(0.0, 0.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
20287        assert_eq_m128h(r, e);
20288        let r = _mm_maskz_fcmadd_sch(1, a, b, c);
20289        let e = _mm_setr_ph(2.0, 3.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
20290        assert_eq_m128h(r, e);
20291    }
20292
20293    #[simd_test(enable = "avx512fp16,avx512vl")]
20294    fn test_mm_fcmadd_round_sch() {
20295        let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
20296        let b = _mm_setr_ph(0.0, 2.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
20297        let c = _mm_setr_ph(0.0, 3.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0);
20298        let r = _mm_fcmadd_round_sch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
20299        let e = _mm_setr_ph(2.0, 3.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
20300        assert_eq_m128h(r, e);
20301    }
20302
20303    #[simd_test(enable = "avx512fp16,avx512vl")]
20304    fn test_mm_mask_fcmadd_round_sch() {
20305        let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
20306        let b = _mm_setr_ph(0.0, 2.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
20307        let c = _mm_setr_ph(0.0, 3.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0);
20308        let r = _mm_mask_fcmadd_round_sch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
20309            a, 0, b, c,
20310        );
20311        let e = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
20312        assert_eq_m128h(r, e);
20313        let r = _mm_mask_fcmadd_round_sch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
20314            a, 1, b, c,
20315        );
20316        let e = _mm_setr_ph(2.0, 3.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
20317        assert_eq_m128h(r, e);
20318    }
20319
20320    #[simd_test(enable = "avx512fp16,avx512vl")]
20321    fn test_mm_mask3_fcmadd_round_sch() {
20322        let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
20323        let b = _mm_setr_ph(0.0, 2.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
20324        let c = _mm_setr_ph(0.0, 3.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0);
20325        let r = _mm_mask3_fcmadd_round_sch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
20326            a, b, c, 0,
20327        );
20328        let e = _mm_setr_ph(0.0, 3.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0);
20329        assert_eq_m128h(r, e);
20330        let r = _mm_mask3_fcmadd_round_sch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
20331            a, b, c, 1,
20332        );
20333        let e = _mm_setr_ph(2.0, 3.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0);
20334        assert_eq_m128h(r, e);
20335    }
20336
20337    #[simd_test(enable = "avx512fp16,avx512vl")]
20338    fn test_mm_maskz_fcmadd_round_sch() {
20339        let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
20340        let b = _mm_setr_ph(0.0, 2.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
20341        let c = _mm_setr_ph(0.0, 3.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0);
20342        let r = _mm_maskz_fcmadd_round_sch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
20343            0, a, b, c,
20344        );
20345        let e = _mm_setr_ph(0.0, 0.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
20346        assert_eq_m128h(r, e);
20347        let r = _mm_maskz_fcmadd_round_sch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
20348            1, a, b, c,
20349        );
20350        let e = _mm_setr_ph(2.0, 3.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
20351        assert_eq_m128h(r, e);
20352    }
20353
20354    #[simd_test(enable = "avx512fp16,avx512vl")]
20355    const fn test_mm_fmadd_ph() {
20356        let a = _mm_set1_ph(1.0);
20357        let b = _mm_set1_ph(2.0);
20358        let c = _mm_set1_ph(3.0);
20359        let r = _mm_fmadd_ph(a, b, c);
20360        let e = _mm_set1_ph(5.0);
20361        assert_eq_m128h(r, e);
20362    }
20363
20364    #[simd_test(enable = "avx512fp16,avx512vl")]
20365    const fn test_mm_mask_fmadd_ph() {
20366        let a = _mm_set1_ph(1.0);
20367        let b = _mm_set1_ph(2.0);
20368        let c = _mm_set1_ph(3.0);
20369        let r = _mm_mask_fmadd_ph(a, 0b01010101, b, c);
20370        let e = _mm_set_ph(1.0, 5.0, 1.0, 5.0, 1.0, 5.0, 1.0, 5.0);
20371        assert_eq_m128h(r, e);
20372    }
20373
20374    #[simd_test(enable = "avx512fp16,avx512vl")]
20375    const fn test_mm_mask3_fmadd_ph() {
20376        let a = _mm_set1_ph(1.0);
20377        let b = _mm_set1_ph(2.0);
20378        let c = _mm_set1_ph(3.0);
20379        let r = _mm_mask3_fmadd_ph(a, b, c, 0b01010101);
20380        let e = _mm_set_ph(3.0, 5.0, 3.0, 5.0, 3.0, 5.0, 3.0, 5.0);
20381        assert_eq_m128h(r, e);
20382    }
20383
20384    #[simd_test(enable = "avx512fp16,avx512vl")]
20385    const fn test_mm_maskz_fmadd_ph() {
20386        let a = _mm_set1_ph(1.0);
20387        let b = _mm_set1_ph(2.0);
20388        let c = _mm_set1_ph(3.0);
20389        let r = _mm_maskz_fmadd_ph(0b01010101, a, b, c);
20390        let e = _mm_set_ph(0.0, 5.0, 0.0, 5.0, 0.0, 5.0, 0.0, 5.0);
20391        assert_eq_m128h(r, e);
20392    }
20393
20394    #[simd_test(enable = "avx512fp16,avx512vl")]
20395    const fn test_mm256_fmadd_ph() {
20396        let a = _mm256_set1_ph(1.0);
20397        let b = _mm256_set1_ph(2.0);
20398        let c = _mm256_set1_ph(3.0);
20399        let r = _mm256_fmadd_ph(a, b, c);
20400        let e = _mm256_set1_ph(5.0);
20401        assert_eq_m256h(r, e);
20402    }
20403
20404    #[simd_test(enable = "avx512fp16,avx512vl")]
20405    const fn test_mm256_mask_fmadd_ph() {
20406        let a = _mm256_set1_ph(1.0);
20407        let b = _mm256_set1_ph(2.0);
20408        let c = _mm256_set1_ph(3.0);
20409        let r = _mm256_mask_fmadd_ph(a, 0b0101010101010101, b, c);
20410        let e = _mm256_set_ph(
20411            1.0, 5.0, 1.0, 5.0, 1.0, 5.0, 1.0, 5.0, 1.0, 5.0, 1.0, 5.0, 1.0, 5.0, 1.0, 5.0,
20412        );
20413        assert_eq_m256h(r, e);
20414    }
20415
20416    #[simd_test(enable = "avx512fp16,avx512vl")]
20417    const fn test_mm256_mask3_fmadd_ph() {
20418        let a = _mm256_set1_ph(1.0);
20419        let b = _mm256_set1_ph(2.0);
20420        let c = _mm256_set1_ph(3.0);
20421        let r = _mm256_mask3_fmadd_ph(a, b, c, 0b0101010101010101);
20422        let e = _mm256_set_ph(
20423            3.0, 5.0, 3.0, 5.0, 3.0, 5.0, 3.0, 5.0, 3.0, 5.0, 3.0, 5.0, 3.0, 5.0, 3.0, 5.0,
20424        );
20425        assert_eq_m256h(r, e);
20426    }
20427
20428    #[simd_test(enable = "avx512fp16,avx512vl")]
20429    const fn test_mm256_maskz_fmadd_ph() {
20430        let a = _mm256_set1_ph(1.0);
20431        let b = _mm256_set1_ph(2.0);
20432        let c = _mm256_set1_ph(3.0);
20433        let r = _mm256_maskz_fmadd_ph(0b0101010101010101, a, b, c);
20434        let e = _mm256_set_ph(
20435            0.0, 5.0, 0.0, 5.0, 0.0, 5.0, 0.0, 5.0, 0.0, 5.0, 0.0, 5.0, 0.0, 5.0, 0.0, 5.0,
20436        );
20437        assert_eq_m256h(r, e);
20438    }
20439
20440    #[simd_test(enable = "avx512fp16")]
20441    const fn test_mm512_fmadd_ph() {
20442        let a = _mm512_set1_ph(1.0);
20443        let b = _mm512_set1_ph(2.0);
20444        let c = _mm512_set1_ph(3.0);
20445        let r = _mm512_fmadd_ph(a, b, c);
20446        let e = _mm512_set1_ph(5.0);
20447        assert_eq_m512h(r, e);
20448    }
20449
20450    #[simd_test(enable = "avx512fp16")]
20451    const fn test_mm512_mask_fmadd_ph() {
20452        let a = _mm512_set1_ph(1.0);
20453        let b = _mm512_set1_ph(2.0);
20454        let c = _mm512_set1_ph(3.0);
20455        let r = _mm512_mask_fmadd_ph(a, 0b01010101010101010101010101010101, b, c);
20456        let e = _mm512_set_ph(
20457            1.0, 5.0, 1.0, 5.0, 1.0, 5.0, 1.0, 5.0, 1.0, 5.0, 1.0, 5.0, 1.0, 5.0, 1.0, 5.0, 1.0,
20458            5.0, 1.0, 5.0, 1.0, 5.0, 1.0, 5.0, 1.0, 5.0, 1.0, 5.0, 1.0, 5.0, 1.0, 5.0,
20459        );
20460        assert_eq_m512h(r, e);
20461    }
20462
20463    #[simd_test(enable = "avx512fp16")]
20464    const fn test_mm512_mask3_fmadd_ph() {
20465        let a = _mm512_set1_ph(1.0);
20466        let b = _mm512_set1_ph(2.0);
20467        let c = _mm512_set1_ph(3.0);
20468        let r = _mm512_mask3_fmadd_ph(a, b, c, 0b01010101010101010101010101010101);
20469        let e = _mm512_set_ph(
20470            3.0, 5.0, 3.0, 5.0, 3.0, 5.0, 3.0, 5.0, 3.0, 5.0, 3.0, 5.0, 3.0, 5.0, 3.0, 5.0, 3.0,
20471            5.0, 3.0, 5.0, 3.0, 5.0, 3.0, 5.0, 3.0, 5.0, 3.0, 5.0, 3.0, 5.0, 3.0, 5.0,
20472        );
20473        assert_eq_m512h(r, e);
20474    }
20475
20476    #[simd_test(enable = "avx512fp16")]
20477    const fn test_mm512_maskz_fmadd_ph() {
20478        let a = _mm512_set1_ph(1.0);
20479        let b = _mm512_set1_ph(2.0);
20480        let c = _mm512_set1_ph(3.0);
20481        let r = _mm512_maskz_fmadd_ph(0b01010101010101010101010101010101, a, b, c);
20482        let e = _mm512_set_ph(
20483            0.0, 5.0, 0.0, 5.0, 0.0, 5.0, 0.0, 5.0, 0.0, 5.0, 0.0, 5.0, 0.0, 5.0, 0.0, 5.0, 0.0,
20484            5.0, 0.0, 5.0, 0.0, 5.0, 0.0, 5.0, 0.0, 5.0, 0.0, 5.0, 0.0, 5.0, 0.0, 5.0,
20485        );
20486        assert_eq_m512h(r, e);
20487    }
20488
20489    #[simd_test(enable = "avx512fp16")]
20490    fn test_mm512_fmadd_round_ph() {
20491        let a = _mm512_set1_ph(1.0);
20492        let b = _mm512_set1_ph(2.0);
20493        let c = _mm512_set1_ph(3.0);
20494        let r = _mm512_fmadd_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
20495        let e = _mm512_set1_ph(5.0);
20496        assert_eq_m512h(r, e);
20497    }
20498
20499    #[simd_test(enable = "avx512fp16")]
20500    fn test_mm512_mask_fmadd_round_ph() {
20501        let a = _mm512_set1_ph(1.0);
20502        let b = _mm512_set1_ph(2.0);
20503        let c = _mm512_set1_ph(3.0);
20504        let r = _mm512_mask_fmadd_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
20505            a,
20506            0b01010101010101010101010101010101,
20507            b,
20508            c,
20509        );
20510        let e = _mm512_set_ph(
20511            1.0, 5.0, 1.0, 5.0, 1.0, 5.0, 1.0, 5.0, 1.0, 5.0, 1.0, 5.0, 1.0, 5.0, 1.0, 5.0, 1.0,
20512            5.0, 1.0, 5.0, 1.0, 5.0, 1.0, 5.0, 1.0, 5.0, 1.0, 5.0, 1.0, 5.0, 1.0, 5.0,
20513        );
20514        assert_eq_m512h(r, e);
20515    }
20516
20517    #[simd_test(enable = "avx512fp16")]
20518    fn test_mm512_mask3_fmadd_round_ph() {
20519        let a = _mm512_set1_ph(1.0);
20520        let b = _mm512_set1_ph(2.0);
20521        let c = _mm512_set1_ph(3.0);
20522        let r = _mm512_mask3_fmadd_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
20523            a,
20524            b,
20525            c,
20526            0b01010101010101010101010101010101,
20527        );
20528        let e = _mm512_set_ph(
20529            3.0, 5.0, 3.0, 5.0, 3.0, 5.0, 3.0, 5.0, 3.0, 5.0, 3.0, 5.0, 3.0, 5.0, 3.0, 5.0, 3.0,
20530            5.0, 3.0, 5.0, 3.0, 5.0, 3.0, 5.0, 3.0, 5.0, 3.0, 5.0, 3.0, 5.0, 3.0, 5.0,
20531        );
20532        assert_eq_m512h(r, e);
20533    }
20534
20535    #[simd_test(enable = "avx512fp16")]
20536    fn test_mm512_maskz_fmadd_round_ph() {
20537        let a = _mm512_set1_ph(1.0);
20538        let b = _mm512_set1_ph(2.0);
20539        let c = _mm512_set1_ph(3.0);
20540        let r = _mm512_maskz_fmadd_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
20541            0b01010101010101010101010101010101,
20542            a,
20543            b,
20544            c,
20545        );
20546        let e = _mm512_set_ph(
20547            0.0, 5.0, 0.0, 5.0, 0.0, 5.0, 0.0, 5.0, 0.0, 5.0, 0.0, 5.0, 0.0, 5.0, 0.0, 5.0, 0.0,
20548            5.0, 0.0, 5.0, 0.0, 5.0, 0.0, 5.0, 0.0, 5.0, 0.0, 5.0, 0.0, 5.0, 0.0, 5.0,
20549        );
20550        assert_eq_m512h(r, e);
20551    }
20552
20553    #[simd_test(enable = "avx512fp16,avx512vl")]
20554    const fn test_mm_fmadd_sh() {
20555        let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
20556        let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
20557        let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
20558        let r = _mm_fmadd_sh(a, b, c);
20559        let e = _mm_setr_ph(5.0, 10., 11., 12., 13., 14., 15., 16.);
20560        assert_eq_m128h(r, e);
20561    }
20562
20563    #[simd_test(enable = "avx512fp16,avx512vl")]
20564    const fn test_mm_mask_fmadd_sh() {
20565        let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
20566        let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
20567        let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
20568        let r = _mm_mask_fmadd_sh(a, 0, b, c);
20569        let e = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
20570        assert_eq_m128h(r, e);
20571        let r = _mm_mask_fmadd_sh(a, 1, b, c);
20572        let e = _mm_setr_ph(5.0, 10., 11., 12., 13., 14., 15., 16.);
20573        assert_eq_m128h(r, e);
20574    }
20575
20576    #[simd_test(enable = "avx512fp16,avx512vl")]
20577    const fn test_mm_mask3_fmadd_sh() {
20578        let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
20579        let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
20580        let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
20581        let r = _mm_mask3_fmadd_sh(a, b, c, 0);
20582        let e = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
20583        assert_eq_m128h(r, e);
20584        let r = _mm_mask3_fmadd_sh(a, b, c, 1);
20585        let e = _mm_setr_ph(5.0, 30., 31., 32., 33., 34., 35., 36.);
20586        assert_eq_m128h(r, e);
20587    }
20588
20589    #[simd_test(enable = "avx512fp16,avx512vl")]
20590    const fn test_mm_maskz_fmadd_sh() {
20591        let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
20592        let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
20593        let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
20594        let r = _mm_maskz_fmadd_sh(0, a, b, c);
20595        let e = _mm_setr_ph(0.0, 10., 11., 12., 13., 14., 15., 16.);
20596        assert_eq_m128h(r, e);
20597        let r = _mm_maskz_fmadd_sh(1, a, b, c);
20598        let e = _mm_setr_ph(5.0, 10., 11., 12., 13., 14., 15., 16.);
20599        assert_eq_m128h(r, e);
20600    }
20601
20602    #[simd_test(enable = "avx512fp16,avx512vl")]
20603    fn test_mm_fmadd_round_sh() {
20604        let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
20605        let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
20606        let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
20607        let r = _mm_fmadd_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
20608        let e = _mm_setr_ph(5.0, 10., 11., 12., 13., 14., 15., 16.);
20609        assert_eq_m128h(r, e);
20610    }
20611
20612    #[simd_test(enable = "avx512fp16,avx512vl")]
20613    fn test_mm_mask_fmadd_round_sh() {
20614        let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
20615        let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
20616        let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
20617        let r = _mm_mask_fmadd_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
20618            a, 0, b, c,
20619        );
20620        let e = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
20621        assert_eq_m128h(r, e);
20622        let r = _mm_mask_fmadd_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
20623            a, 1, b, c,
20624        );
20625        let e = _mm_setr_ph(5.0, 10., 11., 12., 13., 14., 15., 16.);
20626        assert_eq_m128h(r, e);
20627    }
20628
20629    #[simd_test(enable = "avx512fp16,avx512vl")]
20630    fn test_mm_mask3_fmadd_round_sh() {
20631        let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
20632        let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
20633        let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
20634        let r = _mm_mask3_fmadd_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
20635            a, b, c, 0,
20636        );
20637        let e = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
20638        assert_eq_m128h(r, e);
20639        let r = _mm_mask3_fmadd_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
20640            a, b, c, 1,
20641        );
20642        let e = _mm_setr_ph(5.0, 30., 31., 32., 33., 34., 35., 36.);
20643        assert_eq_m128h(r, e);
20644    }
20645
20646    #[simd_test(enable = "avx512fp16,avx512vl")]
20647    fn test_mm_maskz_fmadd_round_sh() {
20648        let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
20649        let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
20650        let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
20651        let r = _mm_maskz_fmadd_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
20652            0, a, b, c,
20653        );
20654        let e = _mm_setr_ph(0.0, 10., 11., 12., 13., 14., 15., 16.);
20655        assert_eq_m128h(r, e);
20656        let r = _mm_maskz_fmadd_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
20657            1, a, b, c,
20658        );
20659        let e = _mm_setr_ph(5.0, 10., 11., 12., 13., 14., 15., 16.);
20660        assert_eq_m128h(r, e);
20661    }
20662
20663    #[simd_test(enable = "avx512fp16,avx512vl")]
20664    const fn test_mm_fmsub_ph() {
20665        let a = _mm_set1_ph(1.0);
20666        let b = _mm_set1_ph(2.0);
20667        let c = _mm_set1_ph(3.0);
20668        let r = _mm_fmsub_ph(a, b, c);
20669        let e = _mm_set1_ph(-1.0);
20670        assert_eq_m128h(r, e);
20671    }
20672
20673    #[simd_test(enable = "avx512fp16,avx512vl")]
20674    const fn test_mm_mask_fmsub_ph() {
20675        let a = _mm_set1_ph(1.0);
20676        let b = _mm_set1_ph(2.0);
20677        let c = _mm_set1_ph(3.0);
20678        let r = _mm_mask_fmsub_ph(a, 0b01010101, b, c);
20679        let e = _mm_set_ph(1.0, -1.0, 1.0, -1.0, 1.0, -1.0, 1.0, -1.0);
20680        assert_eq_m128h(r, e);
20681    }
20682
20683    #[simd_test(enable = "avx512fp16,avx512vl")]
20684    const fn test_mm_mask3_fmsub_ph() {
20685        let a = _mm_set1_ph(1.0);
20686        let b = _mm_set1_ph(2.0);
20687        let c = _mm_set1_ph(3.0);
20688        let r = _mm_mask3_fmsub_ph(a, b, c, 0b01010101);
20689        let e = _mm_set_ph(3.0, -1.0, 3.0, -1.0, 3.0, -1.0, 3.0, -1.0);
20690        assert_eq_m128h(r, e);
20691    }
20692
20693    #[simd_test(enable = "avx512fp16,avx512vl")]
20694    const fn test_mm_maskz_fmsub_ph() {
20695        let a = _mm_set1_ph(1.0);
20696        let b = _mm_set1_ph(2.0);
20697        let c = _mm_set1_ph(3.0);
20698        let r = _mm_maskz_fmsub_ph(0b01010101, a, b, c);
20699        let e = _mm_set_ph(0.0, -1.0, 0.0, -1.0, 0.0, -1.0, 0.0, -1.0);
20700        assert_eq_m128h(r, e);
20701    }
20702
20703    #[simd_test(enable = "avx512fp16,avx512vl")]
20704    const fn test_mm256_fmsub_ph() {
20705        let a = _mm256_set1_ph(1.0);
20706        let b = _mm256_set1_ph(2.0);
20707        let c = _mm256_set1_ph(3.0);
20708        let r = _mm256_fmsub_ph(a, b, c);
20709        let e = _mm256_set1_ph(-1.0);
20710        assert_eq_m256h(r, e);
20711    }
20712
20713    #[simd_test(enable = "avx512fp16,avx512vl")]
20714    const fn test_mm256_mask_fmsub_ph() {
20715        let a = _mm256_set1_ph(1.0);
20716        let b = _mm256_set1_ph(2.0);
20717        let c = _mm256_set1_ph(3.0);
20718        let r = _mm256_mask_fmsub_ph(a, 0b0101010101010101, b, c);
20719        let e = _mm256_set_ph(
20720            1.0, -1.0, 1.0, -1.0, 1.0, -1.0, 1.0, -1.0, 1.0, -1.0, 1.0, -1.0, 1.0, -1.0, 1.0, -1.0,
20721        );
20722        assert_eq_m256h(r, e);
20723    }
20724
20725    #[simd_test(enable = "avx512fp16,avx512vl")]
20726    const fn test_mm256_mask3_fmsub_ph() {
20727        let a = _mm256_set1_ph(1.0);
20728        let b = _mm256_set1_ph(2.0);
20729        let c = _mm256_set1_ph(3.0);
20730        let r = _mm256_mask3_fmsub_ph(a, b, c, 0b0101010101010101);
20731        let e = _mm256_set_ph(
20732            3.0, -1.0, 3.0, -1.0, 3.0, -1.0, 3.0, -1.0, 3.0, -1.0, 3.0, -1.0, 3.0, -1.0, 3.0, -1.0,
20733        );
20734        assert_eq_m256h(r, e);
20735    }
20736
20737    #[simd_test(enable = "avx512fp16,avx512vl")]
20738    const fn test_mm256_maskz_fmsub_ph() {
20739        let a = _mm256_set1_ph(1.0);
20740        let b = _mm256_set1_ph(2.0);
20741        let c = _mm256_set1_ph(3.0);
20742        let r = _mm256_maskz_fmsub_ph(0b0101010101010101, a, b, c);
20743        let e = _mm256_set_ph(
20744            0.0, -1.0, 0.0, -1.0, 0.0, -1.0, 0.0, -1.0, 0.0, -1.0, 0.0, -1.0, 0.0, -1.0, 0.0, -1.0,
20745        );
20746        assert_eq_m256h(r, e);
20747    }
20748
20749    #[simd_test(enable = "avx512fp16")]
20750    const fn test_mm512_fmsub_ph() {
20751        let a = _mm512_set1_ph(1.0);
20752        let b = _mm512_set1_ph(2.0);
20753        let c = _mm512_set1_ph(3.0);
20754        let r = _mm512_fmsub_ph(a, b, c);
20755        let e = _mm512_set1_ph(-1.0);
20756        assert_eq_m512h(r, e);
20757    }
20758
20759    #[simd_test(enable = "avx512fp16")]
20760    const fn test_mm512_mask_fmsub_ph() {
20761        let a = _mm512_set1_ph(1.0);
20762        let b = _mm512_set1_ph(2.0);
20763        let c = _mm512_set1_ph(3.0);
20764        let r = _mm512_mask_fmsub_ph(a, 0b01010101010101010101010101010101, b, c);
20765        let e = _mm512_set_ph(
20766            1.0, -1.0, 1.0, -1.0, 1.0, -1.0, 1.0, -1.0, 1.0, -1.0, 1.0, -1.0, 1.0, -1.0, 1.0, -1.0,
20767            1.0, -1.0, 1.0, -1.0, 1.0, -1.0, 1.0, -1.0, 1.0, -1.0, 1.0, -1.0, 1.0, -1.0, 1.0, -1.0,
20768        );
20769        assert_eq_m512h(r, e);
20770    }
20771
20772    #[simd_test(enable = "avx512fp16")]
20773    const fn test_mm512_mask3_fmsub_ph() {
20774        let a = _mm512_set1_ph(1.0);
20775        let b = _mm512_set1_ph(2.0);
20776        let c = _mm512_set1_ph(3.0);
20777        let r = _mm512_mask3_fmsub_ph(a, b, c, 0b01010101010101010101010101010101);
20778        let e = _mm512_set_ph(
20779            3.0, -1.0, 3.0, -1.0, 3.0, -1.0, 3.0, -1.0, 3.0, -1.0, 3.0, -1.0, 3.0, -1.0, 3.0, -1.0,
20780            3.0, -1.0, 3.0, -1.0, 3.0, -1.0, 3.0, -1.0, 3.0, -1.0, 3.0, -1.0, 3.0, -1.0, 3.0, -1.0,
20781        );
20782        assert_eq_m512h(r, e);
20783    }
20784
20785    #[simd_test(enable = "avx512fp16")]
20786    const fn test_mm512_maskz_fmsub_ph() {
20787        let a = _mm512_set1_ph(1.0);
20788        let b = _mm512_set1_ph(2.0);
20789        let c = _mm512_set1_ph(3.0);
20790        let r = _mm512_maskz_fmsub_ph(0b01010101010101010101010101010101, a, b, c);
20791        let e = _mm512_set_ph(
20792            0.0, -1.0, 0.0, -1.0, 0.0, -1.0, 0.0, -1.0, 0.0, -1.0, 0.0, -1.0, 0.0, -1.0, 0.0, -1.0,
20793            0.0, -1.0, 0.0, -1.0, 0.0, -1.0, 0.0, -1.0, 0.0, -1.0, 0.0, -1.0, 0.0, -1.0, 0.0, -1.0,
20794        );
20795        assert_eq_m512h(r, e);
20796    }
20797
20798    #[simd_test(enable = "avx512fp16")]
20799    fn test_mm512_fmsub_round_ph() {
20800        let a = _mm512_set1_ph(1.0);
20801        let b = _mm512_set1_ph(2.0);
20802        let c = _mm512_set1_ph(3.0);
20803        let r = _mm512_fmsub_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
20804        let e = _mm512_set1_ph(-1.0);
20805        assert_eq_m512h(r, e);
20806    }
20807
20808    #[simd_test(enable = "avx512fp16")]
20809    fn test_mm512_mask_fmsub_round_ph() {
20810        let a = _mm512_set1_ph(1.0);
20811        let b = _mm512_set1_ph(2.0);
20812        let c = _mm512_set1_ph(3.0);
20813        let r = _mm512_mask_fmsub_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
20814            a,
20815            0b01010101010101010101010101010101,
20816            b,
20817            c,
20818        );
20819        let e = _mm512_set_ph(
20820            1.0, -1.0, 1.0, -1.0, 1.0, -1.0, 1.0, -1.0, 1.0, -1.0, 1.0, -1.0, 1.0, -1.0, 1.0, -1.0,
20821            1.0, -1.0, 1.0, -1.0, 1.0, -1.0, 1.0, -1.0, 1.0, -1.0, 1.0, -1.0, 1.0, -1.0, 1.0, -1.0,
20822        );
20823        assert_eq_m512h(r, e);
20824    }
20825
20826    #[simd_test(enable = "avx512fp16")]
20827    fn test_mm512_mask3_fmsub_round_ph() {
20828        let a = _mm512_set1_ph(1.0);
20829        let b = _mm512_set1_ph(2.0);
20830        let c = _mm512_set1_ph(3.0);
20831        let r = _mm512_mask3_fmsub_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
20832            a,
20833            b,
20834            c,
20835            0b01010101010101010101010101010101,
20836        );
20837        let e = _mm512_set_ph(
20838            3.0, -1.0, 3.0, -1.0, 3.0, -1.0, 3.0, -1.0, 3.0, -1.0, 3.0, -1.0, 3.0, -1.0, 3.0, -1.0,
20839            3.0, -1.0, 3.0, -1.0, 3.0, -1.0, 3.0, -1.0, 3.0, -1.0, 3.0, -1.0, 3.0, -1.0, 3.0, -1.0,
20840        );
20841        assert_eq_m512h(r, e);
20842    }
20843
20844    #[simd_test(enable = "avx512fp16")]
20845    fn test_mm512_maskz_fmsub_round_ph() {
20846        let a = _mm512_set1_ph(1.0);
20847        let b = _mm512_set1_ph(2.0);
20848        let c = _mm512_set1_ph(3.0);
20849        let r = _mm512_maskz_fmsub_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
20850            0b01010101010101010101010101010101,
20851            a,
20852            b,
20853            c,
20854        );
20855        let e = _mm512_set_ph(
20856            0.0, -1.0, 0.0, -1.0, 0.0, -1.0, 0.0, -1.0, 0.0, -1.0, 0.0, -1.0, 0.0, -1.0, 0.0, -1.0,
20857            0.0, -1.0, 0.0, -1.0, 0.0, -1.0, 0.0, -1.0, 0.0, -1.0, 0.0, -1.0, 0.0, -1.0, 0.0, -1.0,
20858        );
20859        assert_eq_m512h(r, e);
20860    }
20861
20862    #[simd_test(enable = "avx512fp16,avx512vl")]
20863    const fn test_mm_fmsub_sh() {
20864        let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
20865        let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
20866        let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
20867        let r = _mm_fmsub_sh(a, b, c);
20868        let e = _mm_setr_ph(-1.0, 10., 11., 12., 13., 14., 15., 16.);
20869        assert_eq_m128h(r, e);
20870    }
20871
20872    #[simd_test(enable = "avx512fp16,avx512vl")]
20873    const fn test_mm_mask_fmsub_sh() {
20874        let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
20875        let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
20876        let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
20877        let r = _mm_mask_fmsub_sh(a, 0, b, c);
20878        let e = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
20879        assert_eq_m128h(r, e);
20880        let r = _mm_mask_fmsub_sh(a, 1, b, c);
20881        let e = _mm_setr_ph(-1.0, 10., 11., 12., 13., 14., 15., 16.);
20882        assert_eq_m128h(r, e);
20883    }
20884
20885    #[simd_test(enable = "avx512fp16,avx512vl")]
20886    const fn test_mm_mask3_fmsub_sh() {
20887        let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
20888        let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
20889        let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
20890        let r = _mm_mask3_fmsub_sh(a, b, c, 0);
20891        let e = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
20892        assert_eq_m128h(r, e);
20893        let r = _mm_mask3_fmsub_sh(a, b, c, 1);
20894        let e = _mm_setr_ph(-1.0, 30., 31., 32., 33., 34., 35., 36.);
20895        assert_eq_m128h(r, e);
20896    }
20897
20898    #[simd_test(enable = "avx512fp16,avx512vl")]
20899    const fn test_mm_maskz_fmsub_sh() {
20900        let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
20901        let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
20902        let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
20903        let r = _mm_maskz_fmsub_sh(0, a, b, c);
20904        let e = _mm_setr_ph(0.0, 10., 11., 12., 13., 14., 15., 16.);
20905        assert_eq_m128h(r, e);
20906        let r = _mm_maskz_fmsub_sh(1, a, b, c);
20907        let e = _mm_setr_ph(-1.0, 10., 11., 12., 13., 14., 15., 16.);
20908        assert_eq_m128h(r, e);
20909    }
20910
20911    #[simd_test(enable = "avx512fp16,avx512vl")]
20912    fn test_mm_fmsub_round_sh() {
20913        let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
20914        let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
20915        let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
20916        let r = _mm_fmsub_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
20917        let e = _mm_setr_ph(-1.0, 10., 11., 12., 13., 14., 15., 16.);
20918        assert_eq_m128h(r, e);
20919    }
20920
20921    #[simd_test(enable = "avx512fp16,avx512vl")]
20922    fn test_mm_mask_fmsub_round_sh() {
20923        let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
20924        let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
20925        let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
20926        let r = _mm_mask_fmsub_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
20927            a, 0, b, c,
20928        );
20929        let e = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
20930        assert_eq_m128h(r, e);
20931        let r = _mm_mask_fmsub_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
20932            a, 1, b, c,
20933        );
20934        let e = _mm_setr_ph(-1.0, 10., 11., 12., 13., 14., 15., 16.);
20935        assert_eq_m128h(r, e);
20936    }
20937
20938    #[simd_test(enable = "avx512fp16,avx512vl")]
20939    fn test_mm_mask3_fmsub_round_sh() {
20940        let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
20941        let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
20942        let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
20943        let r = _mm_mask3_fmsub_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
20944            a, b, c, 0,
20945        );
20946        let e = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
20947        assert_eq_m128h(r, e);
20948        let r = _mm_mask3_fmsub_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
20949            a, b, c, 1,
20950        );
20951        let e = _mm_setr_ph(-1.0, 30., 31., 32., 33., 34., 35., 36.);
20952        assert_eq_m128h(r, e);
20953    }
20954
20955    #[simd_test(enable = "avx512fp16,avx512vl")]
20956    fn test_mm_maskz_fmsub_round_sh() {
20957        let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
20958        let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
20959        let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
20960        let r = _mm_maskz_fmsub_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
20961            0, a, b, c,
20962        );
20963        let e = _mm_setr_ph(0.0, 10., 11., 12., 13., 14., 15., 16.);
20964        assert_eq_m128h(r, e);
20965        let r = _mm_maskz_fmsub_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
20966            1, a, b, c,
20967        );
20968        let e = _mm_setr_ph(-1.0, 10., 11., 12., 13., 14., 15., 16.);
20969        assert_eq_m128h(r, e);
20970    }
20971
20972    #[simd_test(enable = "avx512fp16,avx512vl")]
20973    const fn test_mm_fnmadd_ph() {
20974        let a = _mm_set1_ph(1.0);
20975        let b = _mm_set1_ph(2.0);
20976        let c = _mm_set1_ph(3.0);
20977        let r = _mm_fnmadd_ph(a, b, c);
20978        let e = _mm_set1_ph(1.0);
20979        assert_eq_m128h(r, e);
20980    }
20981
20982    #[simd_test(enable = "avx512fp16,avx512vl")]
20983    const fn test_mm_mask_fnmadd_ph() {
20984        let a = _mm_set1_ph(1.0);
20985        let b = _mm_set1_ph(2.0);
20986        let c = _mm_set1_ph(3.0);
20987        let r = _mm_mask_fnmadd_ph(a, 0b01010101, b, c);
20988        let e = _mm_set_ph(1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0);
20989        assert_eq_m128h(r, e);
20990    }
20991
20992    #[simd_test(enable = "avx512fp16,avx512vl")]
20993    const fn test_mm_mask3_fnmadd_ph() {
20994        let a = _mm_set1_ph(1.0);
20995        let b = _mm_set1_ph(2.0);
20996        let c = _mm_set1_ph(3.0);
20997        let r = _mm_mask3_fnmadd_ph(a, b, c, 0b01010101);
20998        let e = _mm_set_ph(3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0);
20999        assert_eq_m128h(r, e);
21000    }
21001
21002    #[simd_test(enable = "avx512fp16,avx512vl")]
21003    const fn test_mm_maskz_fnmadd_ph() {
21004        let a = _mm_set1_ph(1.0);
21005        let b = _mm_set1_ph(2.0);
21006        let c = _mm_set1_ph(3.0);
21007        let r = _mm_maskz_fnmadd_ph(0b01010101, a, b, c);
21008        let e = _mm_set_ph(0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0);
21009        assert_eq_m128h(r, e);
21010    }
21011
21012    #[simd_test(enable = "avx512fp16,avx512vl")]
21013    const fn test_mm256_fnmadd_ph() {
21014        let a = _mm256_set1_ph(1.0);
21015        let b = _mm256_set1_ph(2.0);
21016        let c = _mm256_set1_ph(3.0);
21017        let r = _mm256_fnmadd_ph(a, b, c);
21018        let e = _mm256_set1_ph(1.0);
21019        assert_eq_m256h(r, e);
21020    }
21021
21022    #[simd_test(enable = "avx512fp16,avx512vl")]
21023    const fn test_mm256_mask_fnmadd_ph() {
21024        let a = _mm256_set1_ph(1.0);
21025        let b = _mm256_set1_ph(2.0);
21026        let c = _mm256_set1_ph(3.0);
21027        let r = _mm256_mask_fnmadd_ph(a, 0b0101010101010101, b, c);
21028        let e = _mm256_set_ph(
21029            1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0,
21030        );
21031        assert_eq_m256h(r, e);
21032    }
21033
21034    #[simd_test(enable = "avx512fp16,avx512vl")]
21035    const fn test_mm256_mask3_fnmadd_ph() {
21036        let a = _mm256_set1_ph(1.0);
21037        let b = _mm256_set1_ph(2.0);
21038        let c = _mm256_set1_ph(3.0);
21039        let r = _mm256_mask3_fnmadd_ph(a, b, c, 0b0101010101010101);
21040        let e = _mm256_set_ph(
21041            3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0,
21042        );
21043        assert_eq_m256h(r, e);
21044    }
21045
21046    #[simd_test(enable = "avx512fp16,avx512vl")]
21047    const fn test_mm256_maskz_fnmadd_ph() {
21048        let a = _mm256_set1_ph(1.0);
21049        let b = _mm256_set1_ph(2.0);
21050        let c = _mm256_set1_ph(3.0);
21051        let r = _mm256_maskz_fnmadd_ph(0b0101010101010101, a, b, c);
21052        let e = _mm256_set_ph(
21053            0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0,
21054        );
21055        assert_eq_m256h(r, e);
21056    }
21057
21058    #[simd_test(enable = "avx512fp16")]
21059    const fn test_mm512_fnmadd_ph() {
21060        let a = _mm512_set1_ph(1.0);
21061        let b = _mm512_set1_ph(2.0);
21062        let c = _mm512_set1_ph(3.0);
21063        let r = _mm512_fnmadd_ph(a, b, c);
21064        let e = _mm512_set1_ph(1.0);
21065        assert_eq_m512h(r, e);
21066    }
21067
21068    #[simd_test(enable = "avx512fp16")]
21069    const fn test_mm512_mask_fnmadd_ph() {
21070        let a = _mm512_set1_ph(1.0);
21071        let b = _mm512_set1_ph(2.0);
21072        let c = _mm512_set1_ph(3.0);
21073        let r = _mm512_mask_fnmadd_ph(a, 0b01010101010101010101010101010101, b, c);
21074        let e = _mm512_set_ph(
21075            1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0,
21076            1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0,
21077        );
21078        assert_eq_m512h(r, e);
21079    }
21080
21081    #[simd_test(enable = "avx512fp16")]
21082    const fn test_mm512_mask3_fnmadd_ph() {
21083        let a = _mm512_set1_ph(1.0);
21084        let b = _mm512_set1_ph(2.0);
21085        let c = _mm512_set1_ph(3.0);
21086        let r = _mm512_mask3_fnmadd_ph(a, b, c, 0b01010101010101010101010101010101);
21087        let e = _mm512_set_ph(
21088            3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0,
21089            1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0,
21090        );
21091        assert_eq_m512h(r, e);
21092    }
21093
21094    #[simd_test(enable = "avx512fp16")]
21095    const fn test_mm512_maskz_fnmadd_ph() {
21096        let a = _mm512_set1_ph(1.0);
21097        let b = _mm512_set1_ph(2.0);
21098        let c = _mm512_set1_ph(3.0);
21099        let r = _mm512_maskz_fnmadd_ph(0b01010101010101010101010101010101, a, b, c);
21100        let e = _mm512_set_ph(
21101            0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0,
21102            1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0,
21103        );
21104        assert_eq_m512h(r, e);
21105    }
21106
21107    #[simd_test(enable = "avx512fp16")]
21108    fn test_mm512_fnmadd_round_ph() {
21109        let a = _mm512_set1_ph(1.0);
21110        let b = _mm512_set1_ph(2.0);
21111        let c = _mm512_set1_ph(3.0);
21112        let r =
21113            _mm512_fnmadd_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
21114        let e = _mm512_set1_ph(1.0);
21115        assert_eq_m512h(r, e);
21116    }
21117
21118    #[simd_test(enable = "avx512fp16")]
21119    fn test_mm512_mask_fnmadd_round_ph() {
21120        let a = _mm512_set1_ph(1.0);
21121        let b = _mm512_set1_ph(2.0);
21122        let c = _mm512_set1_ph(3.0);
21123        let r = _mm512_mask_fnmadd_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
21124            a,
21125            0b01010101010101010101010101010101,
21126            b,
21127            c,
21128        );
21129        let e = _mm512_set_ph(
21130            1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0,
21131            1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0,
21132        );
21133        assert_eq_m512h(r, e);
21134    }
21135
21136    #[simd_test(enable = "avx512fp16")]
21137    fn test_mm512_mask3_fnmadd_round_ph() {
21138        let a = _mm512_set1_ph(1.0);
21139        let b = _mm512_set1_ph(2.0);
21140        let c = _mm512_set1_ph(3.0);
21141        let r = _mm512_mask3_fnmadd_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
21142            a,
21143            b,
21144            c,
21145            0b01010101010101010101010101010101,
21146        );
21147        let e = _mm512_set_ph(
21148            3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0,
21149            1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0,
21150        );
21151        assert_eq_m512h(r, e);
21152    }
21153
21154    #[simd_test(enable = "avx512fp16")]
21155    fn test_mm512_maskz_fnmadd_round_ph() {
21156        let a = _mm512_set1_ph(1.0);
21157        let b = _mm512_set1_ph(2.0);
21158        let c = _mm512_set1_ph(3.0);
21159        let r = _mm512_maskz_fnmadd_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
21160            0b01010101010101010101010101010101,
21161            a,
21162            b,
21163            c,
21164        );
21165        let e = _mm512_set_ph(
21166            0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0,
21167            1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0,
21168        );
21169        assert_eq_m512h(r, e);
21170    }
21171
21172    #[simd_test(enable = "avx512fp16,avx512vl")]
21173    const fn test_mm_fnmadd_sh() {
21174        let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
21175        let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
21176        let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
21177        let r = _mm_fnmadd_sh(a, b, c);
21178        let e = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
21179        assert_eq_m128h(r, e);
21180    }
21181
21182    #[simd_test(enable = "avx512fp16,avx512vl")]
21183    const fn test_mm_mask_fnmadd_sh() {
21184        let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
21185        let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
21186        let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
21187        let r = _mm_mask_fnmadd_sh(a, 0, b, c);
21188        let e = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
21189        assert_eq_m128h(r, e);
21190        let r = _mm_mask_fnmadd_sh(a, 1, b, c);
21191        let e = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
21192        assert_eq_m128h(r, e);
21193    }
21194
21195    #[simd_test(enable = "avx512fp16,avx512vl")]
21196    const fn test_mm_mask3_fnmadd_sh() {
21197        let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
21198        let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
21199        let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
21200        let r = _mm_mask3_fnmadd_sh(a, b, c, 0);
21201        let e = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
21202        assert_eq_m128h(r, e);
21203        let r = _mm_mask3_fnmadd_sh(a, b, c, 1);
21204        let e = _mm_setr_ph(1.0, 30., 31., 32., 33., 34., 35., 36.);
21205        assert_eq_m128h(r, e);
21206    }
21207
21208    #[simd_test(enable = "avx512fp16,avx512vl")]
21209    const fn test_mm_maskz_fnmadd_sh() {
21210        let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
21211        let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
21212        let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
21213        let r = _mm_maskz_fnmadd_sh(0, a, b, c);
21214        let e = _mm_setr_ph(0.0, 10., 11., 12., 13., 14., 15., 16.);
21215        assert_eq_m128h(r, e);
21216        let r = _mm_maskz_fnmadd_sh(1, a, b, c);
21217        let e = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
21218        assert_eq_m128h(r, e);
21219    }
21220
21221    #[simd_test(enable = "avx512fp16,avx512vl")]
21222    fn test_mm_fnmadd_round_sh() {
21223        let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
21224        let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
21225        let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
21226        let r = _mm_fnmadd_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
21227        let e = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
21228        assert_eq_m128h(r, e);
21229    }
21230
21231    #[simd_test(enable = "avx512fp16,avx512vl")]
21232    fn test_mm_mask_fnmadd_round_sh() {
21233        let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
21234        let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
21235        let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
21236        let r = _mm_mask_fnmadd_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
21237            a, 0, b, c,
21238        );
21239        let e = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
21240        assert_eq_m128h(r, e);
21241        let r = _mm_mask_fnmadd_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
21242            a, 1, b, c,
21243        );
21244        let e = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
21245        assert_eq_m128h(r, e);
21246    }
21247
21248    #[simd_test(enable = "avx512fp16,avx512vl")]
21249    fn test_mm_mask3_fnmadd_round_sh() {
21250        let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
21251        let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
21252        let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
21253        let r = _mm_mask3_fnmadd_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
21254            a, b, c, 0,
21255        );
21256        let e = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
21257        assert_eq_m128h(r, e);
21258        let r = _mm_mask3_fnmadd_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
21259            a, b, c, 1,
21260        );
21261        let e = _mm_setr_ph(1.0, 30., 31., 32., 33., 34., 35., 36.);
21262        assert_eq_m128h(r, e);
21263    }
21264
21265    #[simd_test(enable = "avx512fp16,avx512vl")]
21266    fn test_mm_maskz_fnmadd_round_sh() {
21267        let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
21268        let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
21269        let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
21270        let r = _mm_maskz_fnmadd_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
21271            0, a, b, c,
21272        );
21273        let e = _mm_setr_ph(0.0, 10., 11., 12., 13., 14., 15., 16.);
21274        assert_eq_m128h(r, e);
21275        let r = _mm_maskz_fnmadd_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
21276            1, a, b, c,
21277        );
21278        let e = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
21279        assert_eq_m128h(r, e);
21280    }
21281
21282    #[simd_test(enable = "avx512fp16,avx512vl")]
21283    const fn test_mm_fnmsub_ph() {
21284        let a = _mm_set1_ph(1.0);
21285        let b = _mm_set1_ph(2.0);
21286        let c = _mm_set1_ph(3.0);
21287        let r = _mm_fnmsub_ph(a, b, c);
21288        let e = _mm_set1_ph(-5.0);
21289        assert_eq_m128h(r, e);
21290    }
21291
21292    #[simd_test(enable = "avx512fp16,avx512vl")]
21293    const fn test_mm_mask_fnmsub_ph() {
21294        let a = _mm_set1_ph(1.0);
21295        let b = _mm_set1_ph(2.0);
21296        let c = _mm_set1_ph(3.0);
21297        let r = _mm_mask_fnmsub_ph(a, 0b01010101, b, c);
21298        let e = _mm_set_ph(1.0, -5.0, 1.0, -5.0, 1.0, -5.0, 1.0, -5.0);
21299        assert_eq_m128h(r, e);
21300    }
21301
21302    #[simd_test(enable = "avx512fp16,avx512vl")]
21303    const fn test_mm_mask3_fnmsub_ph() {
21304        let a = _mm_set1_ph(1.0);
21305        let b = _mm_set1_ph(2.0);
21306        let c = _mm_set1_ph(3.0);
21307        let r = _mm_mask3_fnmsub_ph(a, b, c, 0b01010101);
21308        let e = _mm_set_ph(3.0, -5.0, 3.0, -5.0, 3.0, -5.0, 3.0, -5.0);
21309        assert_eq_m128h(r, e);
21310    }
21311
21312    #[simd_test(enable = "avx512fp16,avx512vl")]
21313    const fn test_mm_maskz_fnmsub_ph() {
21314        let a = _mm_set1_ph(1.0);
21315        let b = _mm_set1_ph(2.0);
21316        let c = _mm_set1_ph(3.0);
21317        let r = _mm_maskz_fnmsub_ph(0b01010101, a, b, c);
21318        let e = _mm_set_ph(0.0, -5.0, 0.0, -5.0, 0.0, -5.0, 0.0, -5.0);
21319        assert_eq_m128h(r, e);
21320    }
21321
21322    #[simd_test(enable = "avx512fp16,avx512vl")]
21323    const fn test_mm256_fnmsub_ph() {
21324        let a = _mm256_set1_ph(1.0);
21325        let b = _mm256_set1_ph(2.0);
21326        let c = _mm256_set1_ph(3.0);
21327        let r = _mm256_fnmsub_ph(a, b, c);
21328        let e = _mm256_set1_ph(-5.0);
21329        assert_eq_m256h(r, e);
21330    }
21331
21332    #[simd_test(enable = "avx512fp16,avx512vl")]
21333    const fn test_mm256_mask_fnmsub_ph() {
21334        let a = _mm256_set1_ph(1.0);
21335        let b = _mm256_set1_ph(2.0);
21336        let c = _mm256_set1_ph(3.0);
21337        let r = _mm256_mask_fnmsub_ph(a, 0b0101010101010101, b, c);
21338        let e = _mm256_set_ph(
21339            1.0, -5.0, 1.0, -5.0, 1.0, -5.0, 1.0, -5.0, 1.0, -5.0, 1.0, -5.0, 1.0, -5.0, 1.0, -5.0,
21340        );
21341        assert_eq_m256h(r, e);
21342    }
21343
21344    #[simd_test(enable = "avx512fp16,avx512vl")]
21345    const fn test_mm256_mask3_fnmsub_ph() {
21346        let a = _mm256_set1_ph(1.0);
21347        let b = _mm256_set1_ph(2.0);
21348        let c = _mm256_set1_ph(3.0);
21349        let r = _mm256_mask3_fnmsub_ph(a, b, c, 0b0101010101010101);
21350        let e = _mm256_set_ph(
21351            3.0, -5.0, 3.0, -5.0, 3.0, -5.0, 3.0, -5.0, 3.0, -5.0, 3.0, -5.0, 3.0, -5.0, 3.0, -5.0,
21352        );
21353        assert_eq_m256h(r, e);
21354    }
21355
21356    #[simd_test(enable = "avx512fp16,avx512vl")]
21357    const fn test_mm256_maskz_fnmsub_ph() {
21358        let a = _mm256_set1_ph(1.0);
21359        let b = _mm256_set1_ph(2.0);
21360        let c = _mm256_set1_ph(3.0);
21361        let r = _mm256_maskz_fnmsub_ph(0b0101010101010101, a, b, c);
21362        let e = _mm256_set_ph(
21363            0.0, -5.0, 0.0, -5.0, 0.0, -5.0, 0.0, -5.0, 0.0, -5.0, 0.0, -5.0, 0.0, -5.0, 0.0, -5.0,
21364        );
21365        assert_eq_m256h(r, e);
21366    }
21367
21368    #[simd_test(enable = "avx512fp16")]
21369    const fn test_mm512_fnmsub_ph() {
21370        let a = _mm512_set1_ph(1.0);
21371        let b = _mm512_set1_ph(2.0);
21372        let c = _mm512_set1_ph(3.0);
21373        let r = _mm512_fnmsub_ph(a, b, c);
21374        let e = _mm512_set1_ph(-5.0);
21375        assert_eq_m512h(r, e);
21376    }
21377
21378    #[simd_test(enable = "avx512fp16")]
21379    const fn test_mm512_mask_fnmsub_ph() {
21380        let a = _mm512_set1_ph(1.0);
21381        let b = _mm512_set1_ph(2.0);
21382        let c = _mm512_set1_ph(3.0);
21383        let r = _mm512_mask_fnmsub_ph(a, 0b01010101010101010101010101010101, b, c);
21384        let e = _mm512_set_ph(
21385            1.0, -5.0, 1.0, -5.0, 1.0, -5.0, 1.0, -5.0, 1.0, -5.0, 1.0, -5.0, 1.0, -5.0, 1.0, -5.0,
21386            1.0, -5.0, 1.0, -5.0, 1.0, -5.0, 1.0, -5.0, 1.0, -5.0, 1.0, -5.0, 1.0, -5.0, 1.0, -5.0,
21387        );
21388        assert_eq_m512h(r, e);
21389    }
21390
21391    #[simd_test(enable = "avx512fp16")]
21392    const fn test_mm512_mask3_fnmsub_ph() {
21393        let a = _mm512_set1_ph(1.0);
21394        let b = _mm512_set1_ph(2.0);
21395        let c = _mm512_set1_ph(3.0);
21396        let r = _mm512_mask3_fnmsub_ph(a, b, c, 0b01010101010101010101010101010101);
21397        let e = _mm512_set_ph(
21398            3.0, -5.0, 3.0, -5.0, 3.0, -5.0, 3.0, -5.0, 3.0, -5.0, 3.0, -5.0, 3.0, -5.0, 3.0, -5.0,
21399            3.0, -5.0, 3.0, -5.0, 3.0, -5.0, 3.0, -5.0, 3.0, -5.0, 3.0, -5.0, 3.0, -5.0, 3.0, -5.0,
21400        );
21401        assert_eq_m512h(r, e);
21402    }
21403
21404    #[simd_test(enable = "avx512fp16")]
21405    const fn test_mm512_maskz_fnmsub_ph() {
21406        let a = _mm512_set1_ph(1.0);
21407        let b = _mm512_set1_ph(2.0);
21408        let c = _mm512_set1_ph(3.0);
21409        let r = _mm512_maskz_fnmsub_ph(0b01010101010101010101010101010101, a, b, c);
21410        let e = _mm512_set_ph(
21411            0.0, -5.0, 0.0, -5.0, 0.0, -5.0, 0.0, -5.0, 0.0, -5.0, 0.0, -5.0, 0.0, -5.0, 0.0, -5.0,
21412            0.0, -5.0, 0.0, -5.0, 0.0, -5.0, 0.0, -5.0, 0.0, -5.0, 0.0, -5.0, 0.0, -5.0, 0.0, -5.0,
21413        );
21414        assert_eq_m512h(r, e);
21415    }
21416
21417    #[simd_test(enable = "avx512fp16")]
21418    fn test_mm512_fnmsub_round_ph() {
21419        let a = _mm512_set1_ph(1.0);
21420        let b = _mm512_set1_ph(2.0);
21421        let c = _mm512_set1_ph(3.0);
21422        let r =
21423            _mm512_fnmsub_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
21424        let e = _mm512_set1_ph(-5.0);
21425        assert_eq_m512h(r, e);
21426    }
21427
21428    #[simd_test(enable = "avx512fp16")]
21429    fn test_mm512_mask_fnmsub_round_ph() {
21430        let a = _mm512_set1_ph(1.0);
21431        let b = _mm512_set1_ph(2.0);
21432        let c = _mm512_set1_ph(3.0);
21433        let r = _mm512_mask_fnmsub_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
21434            a,
21435            0b01010101010101010101010101010101,
21436            b,
21437            c,
21438        );
21439        let e = _mm512_set_ph(
21440            1.0, -5.0, 1.0, -5.0, 1.0, -5.0, 1.0, -5.0, 1.0, -5.0, 1.0, -5.0, 1.0, -5.0, 1.0, -5.0,
21441            1.0, -5.0, 1.0, -5.0, 1.0, -5.0, 1.0, -5.0, 1.0, -5.0, 1.0, -5.0, 1.0, -5.0, 1.0, -5.0,
21442        );
21443        assert_eq_m512h(r, e);
21444    }
21445
21446    #[simd_test(enable = "avx512fp16")]
21447    fn test_mm512_mask3_fnmsub_round_ph() {
21448        let a = _mm512_set1_ph(1.0);
21449        let b = _mm512_set1_ph(2.0);
21450        let c = _mm512_set1_ph(3.0);
21451        let r = _mm512_mask3_fnmsub_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
21452            a,
21453            b,
21454            c,
21455            0b01010101010101010101010101010101,
21456        );
21457        let e = _mm512_set_ph(
21458            3.0, -5.0, 3.0, -5.0, 3.0, -5.0, 3.0, -5.0, 3.0, -5.0, 3.0, -5.0, 3.0, -5.0, 3.0, -5.0,
21459            3.0, -5.0, 3.0, -5.0, 3.0, -5.0, 3.0, -5.0, 3.0, -5.0, 3.0, -5.0, 3.0, -5.0, 3.0, -5.0,
21460        );
21461        assert_eq_m512h(r, e);
21462    }
21463
21464    #[simd_test(enable = "avx512fp16")]
21465    fn test_mm512_maskz_fnmsub_round_ph() {
21466        let a = _mm512_set1_ph(1.0);
21467        let b = _mm512_set1_ph(2.0);
21468        let c = _mm512_set1_ph(3.0);
21469        let r = _mm512_maskz_fnmsub_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
21470            0b01010101010101010101010101010101,
21471            a,
21472            b,
21473            c,
21474        );
21475        let e = _mm512_set_ph(
21476            0.0, -5.0, 0.0, -5.0, 0.0, -5.0, 0.0, -5.0, 0.0, -5.0, 0.0, -5.0, 0.0, -5.0, 0.0, -5.0,
21477            0.0, -5.0, 0.0, -5.0, 0.0, -5.0, 0.0, -5.0, 0.0, -5.0, 0.0, -5.0, 0.0, -5.0, 0.0, -5.0,
21478        );
21479        assert_eq_m512h(r, e);
21480    }
21481
21482    #[simd_test(enable = "avx512fp16,avx512vl")]
21483    const fn test_mm_fnmsub_sh() {
21484        let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
21485        let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
21486        let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
21487        let r = _mm_fnmsub_sh(a, b, c);
21488        let e = _mm_setr_ph(-5.0, 10., 11., 12., 13., 14., 15., 16.);
21489        assert_eq_m128h(r, e);
21490    }
21491
21492    #[simd_test(enable = "avx512fp16,avx512vl")]
21493    const fn test_mm_mask_fnmsub_sh() {
21494        let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
21495        let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
21496        let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
21497        let r = _mm_mask_fnmsub_sh(a, 0, b, c);
21498        let e = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
21499        assert_eq_m128h(r, e);
21500        let r = _mm_mask_fnmsub_sh(a, 1, b, c);
21501        let e = _mm_setr_ph(-5.0, 10., 11., 12., 13., 14., 15., 16.);
21502        assert_eq_m128h(r, e);
21503    }
21504
21505    #[simd_test(enable = "avx512fp16,avx512vl")]
21506    const fn test_mm_mask3_fnmsub_sh() {
21507        let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
21508        let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
21509        let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
21510        let r = _mm_mask3_fnmsub_sh(a, b, c, 0);
21511        let e = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
21512        assert_eq_m128h(r, e);
21513        let r = _mm_mask3_fnmsub_sh(a, b, c, 1);
21514        let e = _mm_setr_ph(-5.0, 30., 31., 32., 33., 34., 35., 36.);
21515        assert_eq_m128h(r, e);
21516    }
21517
21518    #[simd_test(enable = "avx512fp16,avx512vl")]
21519    const fn test_mm_maskz_fnmsub_sh() {
21520        let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
21521        let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
21522        let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
21523        let r = _mm_maskz_fnmsub_sh(0, a, b, c);
21524        let e = _mm_setr_ph(0.0, 10., 11., 12., 13., 14., 15., 16.);
21525        assert_eq_m128h(r, e);
21526        let r = _mm_maskz_fnmsub_sh(1, a, b, c);
21527        let e = _mm_setr_ph(-5.0, 10., 11., 12., 13., 14., 15., 16.);
21528        assert_eq_m128h(r, e);
21529    }
21530
21531    #[simd_test(enable = "avx512fp16,avx512vl")]
21532    fn test_mm_fnmsub_round_sh() {
21533        let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
21534        let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
21535        let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
21536        let r = _mm_fnmsub_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
21537        let e = _mm_setr_ph(-5.0, 10., 11., 12., 13., 14., 15., 16.);
21538        assert_eq_m128h(r, e);
21539    }
21540
21541    #[simd_test(enable = "avx512fp16,avx512vl")]
21542    fn test_mm_mask_fnmsub_round_sh() {
21543        let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
21544        let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
21545        let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
21546        let r = _mm_mask_fnmsub_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
21547            a, 0, b, c,
21548        );
21549        let e = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
21550        assert_eq_m128h(r, e);
21551        let r = _mm_mask_fnmsub_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
21552            a, 1, b, c,
21553        );
21554        let e = _mm_setr_ph(-5.0, 10., 11., 12., 13., 14., 15., 16.);
21555        assert_eq_m128h(r, e);
21556    }
21557
21558    #[simd_test(enable = "avx512fp16,avx512vl")]
21559    fn test_mm_mask3_fnmsub_round_sh() {
21560        let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
21561        let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
21562        let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
21563        let r = _mm_mask3_fnmsub_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
21564            a, b, c, 0,
21565        );
21566        let e = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
21567        assert_eq_m128h(r, e);
21568        let r = _mm_mask3_fnmsub_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
21569            a, b, c, 1,
21570        );
21571        let e = _mm_setr_ph(-5.0, 30., 31., 32., 33., 34., 35., 36.);
21572        assert_eq_m128h(r, e);
21573    }
21574
21575    #[simd_test(enable = "avx512fp16,avx512vl")]
21576    fn test_mm_maskz_fnmsub_round_sh() {
21577        let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
21578        let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
21579        let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
21580        let r = _mm_maskz_fnmsub_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
21581            0, a, b, c,
21582        );
21583        let e = _mm_setr_ph(0.0, 10., 11., 12., 13., 14., 15., 16.);
21584        assert_eq_m128h(r, e);
21585        let r = _mm_maskz_fnmsub_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
21586            1, a, b, c,
21587        );
21588        let e = _mm_setr_ph(-5.0, 10., 11., 12., 13., 14., 15., 16.);
21589        assert_eq_m128h(r, e);
21590    }
21591
21592    #[simd_test(enable = "avx512fp16,avx512vl")]
21593    const fn test_mm_fmaddsub_ph() {
21594        let a = _mm_set1_ph(1.0);
21595        let b = _mm_set1_ph(2.0);
21596        let c = _mm_set1_ph(3.0);
21597        let r = _mm_fmaddsub_ph(a, b, c);
21598        let e = _mm_set_ph(5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0);
21599        assert_eq_m128h(r, e);
21600    }
21601
21602    #[simd_test(enable = "avx512fp16,avx512vl")]
21603    const fn test_mm_mask_fmaddsub_ph() {
21604        let a = _mm_set1_ph(1.0);
21605        let b = _mm_set1_ph(2.0);
21606        let c = _mm_set1_ph(3.0);
21607        let r = _mm_mask_fmaddsub_ph(a, 0b00110011, b, c);
21608        let e = _mm_set_ph(1.0, 1.0, 5.0, -1.0, 1.0, 1.0, 5.0, -1.0);
21609        assert_eq_m128h(r, e);
21610    }
21611
21612    #[simd_test(enable = "avx512fp16,avx512vl")]
21613    const fn test_mm_mask3_fmaddsub_ph() {
21614        let a = _mm_set1_ph(1.0);
21615        let b = _mm_set1_ph(2.0);
21616        let c = _mm_set1_ph(3.0);
21617        let r = _mm_mask3_fmaddsub_ph(a, b, c, 0b00110011);
21618        let e = _mm_set_ph(3.0, 3.0, 5.0, -1.0, 3.0, 3.0, 5.0, -1.0);
21619        assert_eq_m128h(r, e);
21620    }
21621
21622    #[simd_test(enable = "avx512fp16,avx512vl")]
21623    const fn test_mm_maskz_fmaddsub_ph() {
21624        let a = _mm_set1_ph(1.0);
21625        let b = _mm_set1_ph(2.0);
21626        let c = _mm_set1_ph(3.0);
21627        let r = _mm_maskz_fmaddsub_ph(0b00110011, a, b, c);
21628        let e = _mm_set_ph(0.0, 0.0, 5.0, -1.0, 0.0, 0.0, 5.0, -1.0);
21629        assert_eq_m128h(r, e);
21630    }
21631
21632    #[simd_test(enable = "avx512fp16,avx512vl")]
21633    const fn test_mm256_fmaddsub_ph() {
21634        let a = _mm256_set1_ph(1.0);
21635        let b = _mm256_set1_ph(2.0);
21636        let c = _mm256_set1_ph(3.0);
21637        let r = _mm256_fmaddsub_ph(a, b, c);
21638        let e = _mm256_set_ph(
21639            5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0,
21640        );
21641        assert_eq_m256h(r, e);
21642    }
21643
21644    #[simd_test(enable = "avx512fp16,avx512vl")]
21645    const fn test_mm256_mask_fmaddsub_ph() {
21646        let a = _mm256_set1_ph(1.0);
21647        let b = _mm256_set1_ph(2.0);
21648        let c = _mm256_set1_ph(3.0);
21649        let r = _mm256_mask_fmaddsub_ph(a, 0b0011001100110011, b, c);
21650        let e = _mm256_set_ph(
21651            1.0, 1.0, 5.0, -1.0, 1.0, 1.0, 5.0, -1.0, 1.0, 1.0, 5.0, -1.0, 1.0, 1.0, 5.0, -1.0,
21652        );
21653        assert_eq_m256h(r, e);
21654    }
21655
21656    #[simd_test(enable = "avx512fp16,avx512vl")]
21657    const fn test_mm256_mask3_fmaddsub_ph() {
21658        let a = _mm256_set1_ph(1.0);
21659        let b = _mm256_set1_ph(2.0);
21660        let c = _mm256_set1_ph(3.0);
21661        let r = _mm256_mask3_fmaddsub_ph(a, b, c, 0b0011001100110011);
21662        let e = _mm256_set_ph(
21663            3.0, 3.0, 5.0, -1.0, 3.0, 3.0, 5.0, -1.0, 3.0, 3.0, 5.0, -1.0, 3.0, 3.0, 5.0, -1.0,
21664        );
21665        assert_eq_m256h(r, e);
21666    }
21667
21668    #[simd_test(enable = "avx512fp16,avx512vl")]
21669    const fn test_mm256_maskz_fmaddsub_ph() {
21670        let a = _mm256_set1_ph(1.0);
21671        let b = _mm256_set1_ph(2.0);
21672        let c = _mm256_set1_ph(3.0);
21673        let r = _mm256_maskz_fmaddsub_ph(0b0011001100110011, a, b, c);
21674        let e = _mm256_set_ph(
21675            0.0, 0.0, 5.0, -1.0, 0.0, 0.0, 5.0, -1.0, 0.0, 0.0, 5.0, -1.0, 0.0, 0.0, 5.0, -1.0,
21676        );
21677        assert_eq_m256h(r, e);
21678    }
21679
21680    #[simd_test(enable = "avx512fp16")]
21681    const fn test_mm512_fmaddsub_ph() {
21682        let a = _mm512_set1_ph(1.0);
21683        let b = _mm512_set1_ph(2.0);
21684        let c = _mm512_set1_ph(3.0);
21685        let r = _mm512_fmaddsub_ph(a, b, c);
21686        let e = _mm512_set_ph(
21687            5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0,
21688            5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0,
21689        );
21690        assert_eq_m512h(r, e);
21691    }
21692
21693    #[simd_test(enable = "avx512fp16")]
21694    const fn test_mm512_mask_fmaddsub_ph() {
21695        let a = _mm512_set1_ph(1.0);
21696        let b = _mm512_set1_ph(2.0);
21697        let c = _mm512_set1_ph(3.0);
21698        let r = _mm512_mask_fmaddsub_ph(a, 0b00110011001100110011001100110011, b, c);
21699        let e = _mm512_set_ph(
21700            1.0, 1.0, 5.0, -1.0, 1.0, 1.0, 5.0, -1.0, 1.0, 1.0, 5.0, -1.0, 1.0, 1.0, 5.0, -1.0,
21701            1.0, 1.0, 5.0, -1.0, 1.0, 1.0, 5.0, -1.0, 1.0, 1.0, 5.0, -1.0, 1.0, 1.0, 5.0, -1.0,
21702        );
21703        assert_eq_m512h(r, e);
21704    }
21705
21706    #[simd_test(enable = "avx512fp16")]
21707    const fn test_mm512_mask3_fmaddsub_ph() {
21708        let a = _mm512_set1_ph(1.0);
21709        let b = _mm512_set1_ph(2.0);
21710        let c = _mm512_set1_ph(3.0);
21711        let r = _mm512_mask3_fmaddsub_ph(a, b, c, 0b00110011001100110011001100110011);
21712        let e = _mm512_set_ph(
21713            3.0, 3.0, 5.0, -1.0, 3.0, 3.0, 5.0, -1.0, 3.0, 3.0, 5.0, -1.0, 3.0, 3.0, 5.0, -1.0,
21714            3.0, 3.0, 5.0, -1.0, 3.0, 3.0, 5.0, -1.0, 3.0, 3.0, 5.0, -1.0, 3.0, 3.0, 5.0, -1.0,
21715        );
21716        assert_eq_m512h(r, e);
21717    }
21718
21719    #[simd_test(enable = "avx512fp16")]
21720    const fn test_mm512_maskz_fmaddsub_ph() {
21721        let a = _mm512_set1_ph(1.0);
21722        let b = _mm512_set1_ph(2.0);
21723        let c = _mm512_set1_ph(3.0);
21724        let r = _mm512_maskz_fmaddsub_ph(0b00110011001100110011001100110011, a, b, c);
21725        let e = _mm512_set_ph(
21726            0.0, 0.0, 5.0, -1.0, 0.0, 0.0, 5.0, -1.0, 0.0, 0.0, 5.0, -1.0, 0.0, 0.0, 5.0, -1.0,
21727            0.0, 0.0, 5.0, -1.0, 0.0, 0.0, 5.0, -1.0, 0.0, 0.0, 5.0, -1.0, 0.0, 0.0, 5.0, -1.0,
21728        );
21729        assert_eq_m512h(r, e);
21730    }
21731
21732    #[simd_test(enable = "avx512fp16")]
21733    fn test_mm512_fmaddsub_round_ph() {
21734        let a = _mm512_set1_ph(1.0);
21735        let b = _mm512_set1_ph(2.0);
21736        let c = _mm512_set1_ph(3.0);
21737        let r =
21738            _mm512_fmaddsub_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
21739        let e = _mm512_set_ph(
21740            5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0,
21741            5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0,
21742        );
21743        assert_eq_m512h(r, e);
21744    }
21745
21746    #[simd_test(enable = "avx512fp16")]
21747    fn test_mm512_mask_fmaddsub_round_ph() {
21748        let a = _mm512_set1_ph(1.0);
21749        let b = _mm512_set1_ph(2.0);
21750        let c = _mm512_set1_ph(3.0);
21751        let r = _mm512_mask_fmaddsub_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
21752            a,
21753            0b00110011001100110011001100110011,
21754            b,
21755            c,
21756        );
21757        let e = _mm512_set_ph(
21758            1.0, 1.0, 5.0, -1.0, 1.0, 1.0, 5.0, -1.0, 1.0, 1.0, 5.0, -1.0, 1.0, 1.0, 5.0, -1.0,
21759            1.0, 1.0, 5.0, -1.0, 1.0, 1.0, 5.0, -1.0, 1.0, 1.0, 5.0, -1.0, 1.0, 1.0, 5.0, -1.0,
21760        );
21761        assert_eq_m512h(r, e);
21762    }
21763
21764    #[simd_test(enable = "avx512fp16")]
21765    fn test_mm512_mask3_fmaddsub_round_ph() {
21766        let a = _mm512_set1_ph(1.0);
21767        let b = _mm512_set1_ph(2.0);
21768        let c = _mm512_set1_ph(3.0);
21769        let r = _mm512_mask3_fmaddsub_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
21770            a,
21771            b,
21772            c,
21773            0b00110011001100110011001100110011,
21774        );
21775        let e = _mm512_set_ph(
21776            3.0, 3.0, 5.0, -1.0, 3.0, 3.0, 5.0, -1.0, 3.0, 3.0, 5.0, -1.0, 3.0, 3.0, 5.0, -1.0,
21777            3.0, 3.0, 5.0, -1.0, 3.0, 3.0, 5.0, -1.0, 3.0, 3.0, 5.0, -1.0, 3.0, 3.0, 5.0, -1.0,
21778        );
21779        assert_eq_m512h(r, e);
21780    }
21781
21782    #[simd_test(enable = "avx512fp16")]
21783    fn test_mm512_maskz_fmaddsub_round_ph() {
21784        let a = _mm512_set1_ph(1.0);
21785        let b = _mm512_set1_ph(2.0);
21786        let c = _mm512_set1_ph(3.0);
21787        let r = _mm512_maskz_fmaddsub_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
21788            0b00110011001100110011001100110011,
21789            a,
21790            b,
21791            c,
21792        );
21793        let e = _mm512_set_ph(
21794            0.0, 0.0, 5.0, -1.0, 0.0, 0.0, 5.0, -1.0, 0.0, 0.0, 5.0, -1.0, 0.0, 0.0, 5.0, -1.0,
21795            0.0, 0.0, 5.0, -1.0, 0.0, 0.0, 5.0, -1.0, 0.0, 0.0, 5.0, -1.0, 0.0, 0.0, 5.0, -1.0,
21796        );
21797        assert_eq_m512h(r, e);
21798    }
21799
21800    #[simd_test(enable = "avx512fp16,avx512vl")]
21801    const fn test_mm_fmsubadd_ph() {
21802        let a = _mm_set1_ph(1.0);
21803        let b = _mm_set1_ph(2.0);
21804        let c = _mm_set1_ph(3.0);
21805        let r = _mm_fmsubadd_ph(a, b, c);
21806        let e = _mm_set_ph(-1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0);
21807        assert_eq_m128h(r, e);
21808    }
21809
21810    #[simd_test(enable = "avx512fp16,avx512vl")]
21811    const fn test_mm_mask_fmsubadd_ph() {
21812        let a = _mm_set1_ph(1.0);
21813        let b = _mm_set1_ph(2.0);
21814        let c = _mm_set1_ph(3.0);
21815        let r = _mm_mask_fmsubadd_ph(a, 0b00110011, b, c);
21816        let e = _mm_set_ph(1.0, 1.0, -1.0, 5.0, 1.0, 1.0, -1.0, 5.0);
21817        assert_eq_m128h(r, e);
21818    }
21819
21820    #[simd_test(enable = "avx512fp16,avx512vl")]
21821    const fn test_mm_mask3_fmsubadd_ph() {
21822        let a = _mm_set1_ph(1.0);
21823        let b = _mm_set1_ph(2.0);
21824        let c = _mm_set1_ph(3.0);
21825        let r = _mm_mask3_fmsubadd_ph(a, b, c, 0b00110011);
21826        let e = _mm_set_ph(3.0, 3.0, -1.0, 5.0, 3.0, 3.0, -1.0, 5.0);
21827        assert_eq_m128h(r, e);
21828    }
21829
21830    #[simd_test(enable = "avx512fp16,avx512vl")]
21831    const fn test_mm_maskz_fmsubadd_ph() {
21832        let a = _mm_set1_ph(1.0);
21833        let b = _mm_set1_ph(2.0);
21834        let c = _mm_set1_ph(3.0);
21835        let r = _mm_maskz_fmsubadd_ph(0b00110011, a, b, c);
21836        let e = _mm_set_ph(0.0, 0.0, -1.0, 5.0, 0.0, 0.0, -1.0, 5.0);
21837        assert_eq_m128h(r, e);
21838    }
21839
21840    #[simd_test(enable = "avx512fp16,avx512vl")]
21841    const fn test_mm256_fmsubadd_ph() {
21842        let a = _mm256_set1_ph(1.0);
21843        let b = _mm256_set1_ph(2.0);
21844        let c = _mm256_set1_ph(3.0);
21845        let r = _mm256_fmsubadd_ph(a, b, c);
21846        let e = _mm256_set_ph(
21847            -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0,
21848        );
21849        assert_eq_m256h(r, e);
21850    }
21851
21852    #[simd_test(enable = "avx512fp16,avx512vl")]
21853    const fn test_mm256_mask_fmsubadd_ph() {
21854        let a = _mm256_set1_ph(1.0);
21855        let b = _mm256_set1_ph(2.0);
21856        let c = _mm256_set1_ph(3.0);
21857        let r = _mm256_mask_fmsubadd_ph(a, 0b0011001100110011, b, c);
21858        let e = _mm256_set_ph(
21859            1.0, 1.0, -1.0, 5.0, 1.0, 1.0, -1.0, 5.0, 1.0, 1.0, -1.0, 5.0, 1.0, 1.0, -1.0, 5.0,
21860        );
21861        assert_eq_m256h(r, e);
21862    }
21863
21864    #[simd_test(enable = "avx512fp16,avx512vl")]
21865    const fn test_mm256_mask3_fmsubadd_ph() {
21866        let a = _mm256_set1_ph(1.0);
21867        let b = _mm256_set1_ph(2.0);
21868        let c = _mm256_set1_ph(3.0);
21869        let r = _mm256_mask3_fmsubadd_ph(a, b, c, 0b0011001100110011);
21870        let e = _mm256_set_ph(
21871            3.0, 3.0, -1.0, 5.0, 3.0, 3.0, -1.0, 5.0, 3.0, 3.0, -1.0, 5.0, 3.0, 3.0, -1.0, 5.0,
21872        );
21873        assert_eq_m256h(r, e);
21874    }
21875
21876    #[simd_test(enable = "avx512fp16,avx512vl")]
21877    const fn test_mm256_maskz_fmsubadd_ph() {
21878        let a = _mm256_set1_ph(1.0);
21879        let b = _mm256_set1_ph(2.0);
21880        let c = _mm256_set1_ph(3.0);
21881        let r = _mm256_maskz_fmsubadd_ph(0b0011001100110011, a, b, c);
21882        let e = _mm256_set_ph(
21883            0.0, 0.0, -1.0, 5.0, 0.0, 0.0, -1.0, 5.0, 0.0, 0.0, -1.0, 5.0, 0.0, 0.0, -1.0, 5.0,
21884        );
21885        assert_eq_m256h(r, e);
21886    }
21887
21888    #[simd_test(enable = "avx512fp16")]
21889    const fn test_mm512_fmsubadd_ph() {
21890        let a = _mm512_set1_ph(1.0);
21891        let b = _mm512_set1_ph(2.0);
21892        let c = _mm512_set1_ph(3.0);
21893        let r = _mm512_fmsubadd_ph(a, b, c);
21894        let e = _mm512_set_ph(
21895            -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0,
21896            -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0,
21897        );
21898        assert_eq_m512h(r, e);
21899    }
21900
21901    #[simd_test(enable = "avx512fp16")]
21902    const fn test_mm512_mask_fmsubadd_ph() {
21903        let a = _mm512_set1_ph(1.0);
21904        let b = _mm512_set1_ph(2.0);
21905        let c = _mm512_set1_ph(3.0);
21906        let r = _mm512_mask_fmsubadd_ph(a, 0b00110011001100110011001100110011, b, c);
21907        let e = _mm512_set_ph(
21908            1.0, 1.0, -1.0, 5.0, 1.0, 1.0, -1.0, 5.0, 1.0, 1.0, -1.0, 5.0, 1.0, 1.0, -1.0, 5.0,
21909            1.0, 1.0, -1.0, 5.0, 1.0, 1.0, -1.0, 5.0, 1.0, 1.0, -1.0, 5.0, 1.0, 1.0, -1.0, 5.0,
21910        );
21911        assert_eq_m512h(r, e);
21912    }
21913
21914    #[simd_test(enable = "avx512fp16")]
21915    const fn test_mm512_mask3_fmsubadd_ph() {
21916        let a = _mm512_set1_ph(1.0);
21917        let b = _mm512_set1_ph(2.0);
21918        let c = _mm512_set1_ph(3.0);
21919        let r = _mm512_mask3_fmsubadd_ph(a, b, c, 0b00110011001100110011001100110011);
21920        let e = _mm512_set_ph(
21921            3.0, 3.0, -1.0, 5.0, 3.0, 3.0, -1.0, 5.0, 3.0, 3.0, -1.0, 5.0, 3.0, 3.0, -1.0, 5.0,
21922            3.0, 3.0, -1.0, 5.0, 3.0, 3.0, -1.0, 5.0, 3.0, 3.0, -1.0, 5.0, 3.0, 3.0, -1.0, 5.0,
21923        );
21924        assert_eq_m512h(r, e);
21925    }
21926
21927    #[simd_test(enable = "avx512fp16")]
21928    const fn test_mm512_maskz_fmsubadd_ph() {
21929        let a = _mm512_set1_ph(1.0);
21930        let b = _mm512_set1_ph(2.0);
21931        let c = _mm512_set1_ph(3.0);
21932        let r = _mm512_maskz_fmsubadd_ph(0b00110011001100110011001100110011, a, b, c);
21933        let e = _mm512_set_ph(
21934            0.0, 0.0, -1.0, 5.0, 0.0, 0.0, -1.0, 5.0, 0.0, 0.0, -1.0, 5.0, 0.0, 0.0, -1.0, 5.0,
21935            0.0, 0.0, -1.0, 5.0, 0.0, 0.0, -1.0, 5.0, 0.0, 0.0, -1.0, 5.0, 0.0, 0.0, -1.0, 5.0,
21936        );
21937        assert_eq_m512h(r, e);
21938    }
21939
21940    #[simd_test(enable = "avx512fp16")]
21941    fn test_mm512_fmsubadd_round_ph() {
21942        let a = _mm512_set1_ph(1.0);
21943        let b = _mm512_set1_ph(2.0);
21944        let c = _mm512_set1_ph(3.0);
21945        let r =
21946            _mm512_fmsubadd_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
21947        let e = _mm512_set_ph(
21948            -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0,
21949            -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0, -1.0, 5.0,
21950        );
21951        assert_eq_m512h(r, e);
21952    }
21953
21954    #[simd_test(enable = "avx512fp16")]
21955    fn test_mm512_mask_fmsubadd_round_ph() {
21956        let a = _mm512_set1_ph(1.0);
21957        let b = _mm512_set1_ph(2.0);
21958        let c = _mm512_set1_ph(3.0);
21959        let r = _mm512_mask_fmsubadd_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
21960            a,
21961            0b00110011001100110011001100110011,
21962            b,
21963            c,
21964        );
21965        let e = _mm512_set_ph(
21966            1.0, 1.0, -1.0, 5.0, 1.0, 1.0, -1.0, 5.0, 1.0, 1.0, -1.0, 5.0, 1.0, 1.0, -1.0, 5.0,
21967            1.0, 1.0, -1.0, 5.0, 1.0, 1.0, -1.0, 5.0, 1.0, 1.0, -1.0, 5.0, 1.0, 1.0, -1.0, 5.0,
21968        );
21969        assert_eq_m512h(r, e);
21970    }
21971
21972    #[simd_test(enable = "avx512fp16")]
21973    fn test_mm512_mask3_fmsubadd_round_ph() {
21974        let a = _mm512_set1_ph(1.0);
21975        let b = _mm512_set1_ph(2.0);
21976        let c = _mm512_set1_ph(3.0);
21977        let r = _mm512_mask3_fmsubadd_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
21978            a,
21979            b,
21980            c,
21981            0b00110011001100110011001100110011,
21982        );
21983        let e = _mm512_set_ph(
21984            3.0, 3.0, -1.0, 5.0, 3.0, 3.0, -1.0, 5.0, 3.0, 3.0, -1.0, 5.0, 3.0, 3.0, -1.0, 5.0,
21985            3.0, 3.0, -1.0, 5.0, 3.0, 3.0, -1.0, 5.0, 3.0, 3.0, -1.0, 5.0, 3.0, 3.0, -1.0, 5.0,
21986        );
21987        assert_eq_m512h(r, e);
21988    }
21989
21990    #[simd_test(enable = "avx512fp16")]
21991    fn test_mm512_maskz_fmsubadd_round_ph() {
21992        let a = _mm512_set1_ph(1.0);
21993        let b = _mm512_set1_ph(2.0);
21994        let c = _mm512_set1_ph(3.0);
21995        let r = _mm512_maskz_fmsubadd_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
21996            0b00110011001100110011001100110011,
21997            a,
21998            b,
21999            c,
22000        );
22001        let e = _mm512_set_ph(
22002            0.0, 0.0, -1.0, 5.0, 0.0, 0.0, -1.0, 5.0, 0.0, 0.0, -1.0, 5.0, 0.0, 0.0, -1.0, 5.0,
22003            0.0, 0.0, -1.0, 5.0, 0.0, 0.0, -1.0, 5.0, 0.0, 0.0, -1.0, 5.0, 0.0, 0.0, -1.0, 5.0,
22004        );
22005        assert_eq_m512h(r, e);
22006    }
22007
22008    #[simd_test(enable = "avx512fp16,avx512vl")]
22009    fn test_mm_rcp_ph() {
22010        let a = _mm_set1_ph(2.0);
22011        let r = _mm_rcp_ph(a);
22012        let e = _mm_set1_ph(0.5);
22013        assert_eq_m128h(r, e);
22014    }
22015
22016    #[simd_test(enable = "avx512fp16,avx512vl")]
22017    fn test_mm_mask_rcp_ph() {
22018        let a = _mm_set1_ph(2.0);
22019        let src = _mm_set1_ph(1.0);
22020        let r = _mm_mask_rcp_ph(src, 0b01010101, a);
22021        let e = _mm_set_ph(1.0, 0.5, 1.0, 0.5, 1.0, 0.5, 1.0, 0.5);
22022        assert_eq_m128h(r, e);
22023    }
22024
22025    #[simd_test(enable = "avx512fp16,avx512vl")]
22026    fn test_mm_maskz_rcp_ph() {
22027        let a = _mm_set1_ph(2.0);
22028        let r = _mm_maskz_rcp_ph(0b01010101, a);
22029        let e = _mm_set_ph(0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5);
22030        assert_eq_m128h(r, e);
22031    }
22032
22033    #[simd_test(enable = "avx512fp16,avx512vl")]
22034    fn test_mm256_rcp_ph() {
22035        let a = _mm256_set1_ph(2.0);
22036        let r = _mm256_rcp_ph(a);
22037        let e = _mm256_set1_ph(0.5);
22038        assert_eq_m256h(r, e);
22039    }
22040
22041    #[simd_test(enable = "avx512fp16,avx512vl")]
22042    fn test_mm256_mask_rcp_ph() {
22043        let a = _mm256_set1_ph(2.0);
22044        let src = _mm256_set1_ph(1.0);
22045        let r = _mm256_mask_rcp_ph(src, 0b0101010101010101, a);
22046        let e = _mm256_set_ph(
22047            1.0, 0.5, 1.0, 0.5, 1.0, 0.5, 1.0, 0.5, 1.0, 0.5, 1.0, 0.5, 1.0, 0.5, 1.0, 0.5,
22048        );
22049        assert_eq_m256h(r, e);
22050    }
22051
22052    #[simd_test(enable = "avx512fp16,avx512vl")]
22053    fn test_mm256_maskz_rcp_ph() {
22054        let a = _mm256_set1_ph(2.0);
22055        let r = _mm256_maskz_rcp_ph(0b0101010101010101, a);
22056        let e = _mm256_set_ph(
22057            0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5,
22058        );
22059        assert_eq_m256h(r, e);
22060    }
22061
22062    #[simd_test(enable = "avx512fp16")]
22063    fn test_mm512_rcp_ph() {
22064        let a = _mm512_set1_ph(2.0);
22065        let r = _mm512_rcp_ph(a);
22066        let e = _mm512_set1_ph(0.5);
22067        assert_eq_m512h(r, e);
22068    }
22069
22070    #[simd_test(enable = "avx512fp16")]
22071    fn test_mm512_mask_rcp_ph() {
22072        let a = _mm512_set1_ph(2.0);
22073        let src = _mm512_set1_ph(1.0);
22074        let r = _mm512_mask_rcp_ph(src, 0b01010101010101010101010101010101, a);
22075        let e = _mm512_set_ph(
22076            1.0, 0.5, 1.0, 0.5, 1.0, 0.5, 1.0, 0.5, 1.0, 0.5, 1.0, 0.5, 1.0, 0.5, 1.0, 0.5, 1.0,
22077            0.5, 1.0, 0.5, 1.0, 0.5, 1.0, 0.5, 1.0, 0.5, 1.0, 0.5, 1.0, 0.5, 1.0, 0.5,
22078        );
22079        assert_eq_m512h(r, e);
22080    }
22081
22082    #[simd_test(enable = "avx512fp16")]
22083    fn test_mm512_maskz_rcp_ph() {
22084        let a = _mm512_set1_ph(2.0);
22085        let r = _mm512_maskz_rcp_ph(0b01010101010101010101010101010101, a);
22086        let e = _mm512_set_ph(
22087            0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0,
22088            0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5,
22089        );
22090        assert_eq_m512h(r, e);
22091    }
22092
22093    #[simd_test(enable = "avx512fp16,avx512vl")]
22094    fn test_mm_rcp_sh() {
22095        let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22096        let b = _mm_setr_ph(2.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0);
22097        let r = _mm_rcp_sh(a, b);
22098        let e = _mm_setr_ph(0.5, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22099        assert_eq_m128h(r, e);
22100    }
22101
22102    #[simd_test(enable = "avx512fp16,avx512vl")]
22103    fn test_mm_mask_rcp_sh() {
22104        let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22105        let b = _mm_setr_ph(2.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0);
22106        let src = _mm_setr_ph(3.0, 30.0, 31.0, 32.0, 33.0, 34.0, 35.0, 36.0);
22107        let r = _mm_mask_rcp_sh(src, 0, a, b);
22108        let e = _mm_setr_ph(3.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22109        assert_eq_m128h(r, e);
22110        let r = _mm_mask_rcp_sh(src, 1, a, b);
22111        let e = _mm_setr_ph(0.5, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22112        assert_eq_m128h(r, e);
22113    }
22114
22115    #[simd_test(enable = "avx512fp16,avx512vl")]
22116    fn test_mm_maskz_rcp_sh() {
22117        let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22118        let b = _mm_setr_ph(2.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0);
22119        let r = _mm_maskz_rcp_sh(0, a, b);
22120        let e = _mm_setr_ph(0.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22121        assert_eq_m128h(r, e);
22122        let r = _mm_maskz_rcp_sh(1, a, b);
22123        let e = _mm_setr_ph(0.5, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22124        assert_eq_m128h(r, e);
22125    }
22126
22127    #[simd_test(enable = "avx512fp16,avx512vl")]
22128    fn test_mm_rsqrt_ph() {
22129        let a = _mm_set1_ph(4.0);
22130        let r = _mm_rsqrt_ph(a);
22131        let e = _mm_set1_ph(0.5);
22132        assert_eq_m128h(r, e);
22133    }
22134
22135    #[simd_test(enable = "avx512fp16,avx512vl")]
22136    fn test_mm_mask_rsqrt_ph() {
22137        let a = _mm_set1_ph(4.0);
22138        let src = _mm_set1_ph(1.0);
22139        let r = _mm_mask_rsqrt_ph(src, 0b01010101, a);
22140        let e = _mm_set_ph(1.0, 0.5, 1.0, 0.5, 1.0, 0.5, 1.0, 0.5);
22141        assert_eq_m128h(r, e);
22142    }
22143
22144    #[simd_test(enable = "avx512fp16,avx512vl")]
22145    fn test_mm_maskz_rsqrt_ph() {
22146        let a = _mm_set1_ph(4.0);
22147        let r = _mm_maskz_rsqrt_ph(0b01010101, a);
22148        let e = _mm_set_ph(0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5);
22149        assert_eq_m128h(r, e);
22150    }
22151
22152    #[simd_test(enable = "avx512fp16,avx512vl")]
22153    fn test_mm256_rsqrt_ph() {
22154        let a = _mm256_set1_ph(4.0);
22155        let r = _mm256_rsqrt_ph(a);
22156        let e = _mm256_set1_ph(0.5);
22157        assert_eq_m256h(r, e);
22158    }
22159
22160    #[simd_test(enable = "avx512fp16,avx512vl")]
22161    fn test_mm256_mask_rsqrt_ph() {
22162        let a = _mm256_set1_ph(4.0);
22163        let src = _mm256_set1_ph(1.0);
22164        let r = _mm256_mask_rsqrt_ph(src, 0b0101010101010101, a);
22165        let e = _mm256_set_ph(
22166            1.0, 0.5, 1.0, 0.5, 1.0, 0.5, 1.0, 0.5, 1.0, 0.5, 1.0, 0.5, 1.0, 0.5, 1.0, 0.5,
22167        );
22168        assert_eq_m256h(r, e);
22169    }
22170
22171    #[simd_test(enable = "avx512fp16,avx512vl")]
22172    fn test_mm256_maskz_rsqrt_ph() {
22173        let a = _mm256_set1_ph(4.0);
22174        let r = _mm256_maskz_rsqrt_ph(0b0101010101010101, a);
22175        let e = _mm256_set_ph(
22176            0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5,
22177        );
22178        assert_eq_m256h(r, e);
22179    }
22180
22181    #[simd_test(enable = "avx512fp16")]
22182    fn test_mm512_rsqrt_ph() {
22183        let a = _mm512_set1_ph(4.0);
22184        let r = _mm512_rsqrt_ph(a);
22185        let e = _mm512_set1_ph(0.5);
22186        assert_eq_m512h(r, e);
22187    }
22188
22189    #[simd_test(enable = "avx512fp16")]
22190    fn test_mm512_mask_rsqrt_ph() {
22191        let a = _mm512_set1_ph(4.0);
22192        let src = _mm512_set1_ph(1.0);
22193        let r = _mm512_mask_rsqrt_ph(src, 0b01010101010101010101010101010101, a);
22194        let e = _mm512_set_ph(
22195            1.0, 0.5, 1.0, 0.5, 1.0, 0.5, 1.0, 0.5, 1.0, 0.5, 1.0, 0.5, 1.0, 0.5, 1.0, 0.5, 1.0,
22196            0.5, 1.0, 0.5, 1.0, 0.5, 1.0, 0.5, 1.0, 0.5, 1.0, 0.5, 1.0, 0.5, 1.0, 0.5,
22197        );
22198        assert_eq_m512h(r, e);
22199    }
22200
22201    #[simd_test(enable = "avx512fp16")]
22202    fn test_mm512_maskz_rsqrt_ph() {
22203        let a = _mm512_set1_ph(4.0);
22204        let r = _mm512_maskz_rsqrt_ph(0b01010101010101010101010101010101, a);
22205        let e = _mm512_set_ph(
22206            0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0,
22207            0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5,
22208        );
22209        assert_eq_m512h(r, e);
22210    }
22211
22212    #[simd_test(enable = "avx512fp16,avx512vl")]
22213    fn test_mm_rsqrt_sh() {
22214        let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22215        let b = _mm_setr_ph(4.0, 40.0, 41.0, 42.0, 43.0, 44.0, 45.0, 46.0);
22216        let r = _mm_rsqrt_sh(a, b);
22217        let e = _mm_setr_ph(0.5, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22218        assert_eq_m128h(r, e);
22219    }
22220
22221    #[simd_test(enable = "avx512fp16,avx512vl")]
22222    fn test_mm_mask_rsqrt_sh() {
22223        let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22224        let b = _mm_setr_ph(4.0, 40.0, 41.0, 42.0, 43.0, 44.0, 45.0, 46.0);
22225        let src = _mm_setr_ph(3.0, 30.0, 31.0, 32.0, 33.0, 34.0, 35.0, 36.0);
22226        let r = _mm_mask_rsqrt_sh(src, 0, a, b);
22227        let e = _mm_setr_ph(3.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22228        assert_eq_m128h(r, e);
22229        let r = _mm_mask_rsqrt_sh(src, 1, a, b);
22230        let e = _mm_setr_ph(0.5, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22231        assert_eq_m128h(r, e);
22232    }
22233
22234    #[simd_test(enable = "avx512fp16,avx512vl")]
22235    fn test_mm_maskz_rsqrt_sh() {
22236        let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22237        let b = _mm_setr_ph(4.0, 40.0, 41.0, 42.0, 43.0, 44.0, 45.0, 46.0);
22238        let r = _mm_maskz_rsqrt_sh(0, a, b);
22239        let e = _mm_setr_ph(0.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22240        assert_eq_m128h(r, e);
22241        let r = _mm_maskz_rsqrt_sh(1, a, b);
22242        let e = _mm_setr_ph(0.5, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22243        assert_eq_m128h(r, e);
22244    }
22245
22246    #[simd_test(enable = "avx512fp16,avx512vl")]
22247    fn test_mm_sqrt_ph() {
22248        let a = _mm_set1_ph(4.0);
22249        let r = _mm_sqrt_ph(a);
22250        let e = _mm_set1_ph(2.0);
22251        assert_eq_m128h(r, e);
22252    }
22253
22254    #[simd_test(enable = "avx512fp16,avx512vl")]
22255    fn test_mm_mask_sqrt_ph() {
22256        let a = _mm_set1_ph(4.0);
22257        let src = _mm_set1_ph(1.0);
22258        let r = _mm_mask_sqrt_ph(src, 0b01010101, a);
22259        let e = _mm_set_ph(1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0);
22260        assert_eq_m128h(r, e);
22261    }
22262
22263    #[simd_test(enable = "avx512fp16,avx512vl")]
22264    fn test_mm_maskz_sqrt_ph() {
22265        let a = _mm_set1_ph(4.0);
22266        let r = _mm_maskz_sqrt_ph(0b01010101, a);
22267        let e = _mm_set_ph(0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0);
22268        assert_eq_m128h(r, e);
22269    }
22270
22271    #[simd_test(enable = "avx512fp16,avx512vl")]
22272    fn test_mm256_sqrt_ph() {
22273        let a = _mm256_set1_ph(4.0);
22274        let r = _mm256_sqrt_ph(a);
22275        let e = _mm256_set1_ph(2.0);
22276        assert_eq_m256h(r, e);
22277    }
22278
22279    #[simd_test(enable = "avx512fp16,avx512vl")]
22280    fn test_mm256_mask_sqrt_ph() {
22281        let a = _mm256_set1_ph(4.0);
22282        let src = _mm256_set1_ph(1.0);
22283        let r = _mm256_mask_sqrt_ph(src, 0b0101010101010101, a);
22284        let e = _mm256_set_ph(
22285            1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0,
22286        );
22287        assert_eq_m256h(r, e);
22288    }
22289
22290    #[simd_test(enable = "avx512fp16,avx512vl")]
22291    fn test_mm256_maskz_sqrt_ph() {
22292        let a = _mm256_set1_ph(4.0);
22293        let r = _mm256_maskz_sqrt_ph(0b0101010101010101, a);
22294        let e = _mm256_set_ph(
22295            0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0,
22296        );
22297        assert_eq_m256h(r, e);
22298    }
22299
22300    #[simd_test(enable = "avx512fp16")]
22301    fn test_mm512_sqrt_ph() {
22302        let a = _mm512_set1_ph(4.0);
22303        let r = _mm512_sqrt_ph(a);
22304        let e = _mm512_set1_ph(2.0);
22305        assert_eq_m512h(r, e);
22306    }
22307
22308    #[simd_test(enable = "avx512fp16")]
22309    fn test_mm512_mask_sqrt_ph() {
22310        let a = _mm512_set1_ph(4.0);
22311        let src = _mm512_set1_ph(1.0);
22312        let r = _mm512_mask_sqrt_ph(src, 0b01010101010101010101010101010101, a);
22313        let e = _mm512_set_ph(
22314            1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0,
22315            2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0,
22316        );
22317        assert_eq_m512h(r, e);
22318    }
22319
22320    #[simd_test(enable = "avx512fp16")]
22321    fn test_mm512_maskz_sqrt_ph() {
22322        let a = _mm512_set1_ph(4.0);
22323        let r = _mm512_maskz_sqrt_ph(0b01010101010101010101010101010101, a);
22324        let e = _mm512_set_ph(
22325            0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0,
22326            2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0,
22327        );
22328        assert_eq_m512h(r, e);
22329    }
22330
22331    #[simd_test(enable = "avx512fp16")]
22332    fn test_mm512_sqrt_round_ph() {
22333        let a = _mm512_set1_ph(4.0);
22334        let r = _mm512_sqrt_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
22335        let e = _mm512_set1_ph(2.0);
22336        assert_eq_m512h(r, e);
22337    }
22338
22339    #[simd_test(enable = "avx512fp16")]
22340    fn test_mm512_mask_sqrt_round_ph() {
22341        let a = _mm512_set1_ph(4.0);
22342        let src = _mm512_set1_ph(1.0);
22343        let r = _mm512_mask_sqrt_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
22344            src,
22345            0b01010101010101010101010101010101,
22346            a,
22347        );
22348        let e = _mm512_set_ph(
22349            1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0,
22350            2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0,
22351        );
22352        assert_eq_m512h(r, e);
22353    }
22354
22355    #[simd_test(enable = "avx512fp16")]
22356    fn test_mm512_maskz_sqrt_round_ph() {
22357        let a = _mm512_set1_ph(4.0);
22358        let r = _mm512_maskz_sqrt_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
22359            0b01010101010101010101010101010101,
22360            a,
22361        );
22362        let e = _mm512_set_ph(
22363            0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0,
22364            2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0,
22365        );
22366        assert_eq_m512h(r, e);
22367    }
22368
22369    #[simd_test(enable = "avx512fp16,avx512vl")]
22370    fn test_mm_sqrt_sh() {
22371        let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22372        let b = _mm_setr_ph(4.0, 40.0, 41.0, 42.0, 43.0, 44.0, 45.0, 46.0);
22373        let r = _mm_sqrt_sh(a, b);
22374        let e = _mm_setr_ph(2.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22375        assert_eq_m128h(r, e);
22376    }
22377
22378    #[simd_test(enable = "avx512fp16,avx512vl")]
22379    fn test_mm_mask_sqrt_sh() {
22380        let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22381        let b = _mm_setr_ph(4.0, 40.0, 41.0, 42.0, 43.0, 44.0, 45.0, 46.0);
22382        let src = _mm_setr_ph(3.0, 30.0, 31.0, 32.0, 33.0, 34.0, 35.0, 36.0);
22383        let r = _mm_mask_sqrt_sh(src, 0, a, b);
22384        let e = _mm_setr_ph(3.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22385        assert_eq_m128h(r, e);
22386        let r = _mm_mask_sqrt_sh(src, 1, a, b);
22387        let e = _mm_setr_ph(2.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22388        assert_eq_m128h(r, e);
22389    }
22390
22391    #[simd_test(enable = "avx512fp16,avx512vl")]
22392    fn test_mm_maskz_sqrt_sh() {
22393        let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22394        let b = _mm_setr_ph(4.0, 40.0, 41.0, 42.0, 43.0, 44.0, 45.0, 46.0);
22395        let r = _mm_maskz_sqrt_sh(0, a, b);
22396        let e = _mm_setr_ph(0.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22397        assert_eq_m128h(r, e);
22398        let r = _mm_maskz_sqrt_sh(1, a, b);
22399        let e = _mm_setr_ph(2.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22400        assert_eq_m128h(r, e);
22401    }
22402
22403    #[simd_test(enable = "avx512fp16,avx512vl")]
22404    fn test_mm_sqrt_round_sh() {
22405        let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22406        let b = _mm_setr_ph(4.0, 40.0, 41.0, 42.0, 43.0, 44.0, 45.0, 46.0);
22407        let r = _mm_sqrt_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
22408        let e = _mm_setr_ph(2.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22409        assert_eq_m128h(r, e);
22410    }
22411
22412    #[simd_test(enable = "avx512fp16,avx512vl")]
22413    fn test_mm_mask_sqrt_round_sh() {
22414        let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22415        let b = _mm_setr_ph(4.0, 40.0, 41.0, 42.0, 43.0, 44.0, 45.0, 46.0);
22416        let src = _mm_setr_ph(3.0, 30.0, 31.0, 32.0, 33.0, 34.0, 35.0, 36.0);
22417        let r = _mm_mask_sqrt_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
22418            src, 0, a, b,
22419        );
22420        let e = _mm_setr_ph(3.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22421        assert_eq_m128h(r, e);
22422        let r = _mm_mask_sqrt_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
22423            src, 1, a, b,
22424        );
22425        let e = _mm_setr_ph(2.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22426        assert_eq_m128h(r, e);
22427    }
22428
22429    #[simd_test(enable = "avx512fp16,avx512vl")]
22430    fn test_mm_maskz_sqrt_round_sh() {
22431        let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22432        let b = _mm_setr_ph(4.0, 40.0, 41.0, 42.0, 43.0, 44.0, 45.0, 46.0);
22433        let r =
22434            _mm_maskz_sqrt_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
22435        let e = _mm_setr_ph(0.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22436        assert_eq_m128h(r, e);
22437        let r =
22438            _mm_maskz_sqrt_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(1, a, b);
22439        let e = _mm_setr_ph(2.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22440        assert_eq_m128h(r, e);
22441    }
22442
22443    #[simd_test(enable = "avx512fp16,avx512vl")]
22444    fn test_mm_max_ph() {
22445        let a = _mm_set1_ph(2.0);
22446        let b = _mm_set1_ph(1.0);
22447        let r = _mm_max_ph(a, b);
22448        let e = _mm_set1_ph(2.0);
22449        assert_eq_m128h(r, e);
22450    }
22451
22452    #[simd_test(enable = "avx512fp16,avx512vl")]
22453    fn test_mm_mask_max_ph() {
22454        let a = _mm_set1_ph(2.0);
22455        let b = _mm_set1_ph(1.0);
22456        let src = _mm_set1_ph(3.0);
22457        let r = _mm_mask_max_ph(src, 0b01010101, a, b);
22458        let e = _mm_set_ph(3.0, 2.0, 3.0, 2.0, 3.0, 2.0, 3.0, 2.0);
22459        assert_eq_m128h(r, e);
22460    }
22461
22462    #[simd_test(enable = "avx512fp16,avx512vl")]
22463    fn test_mm_maskz_max_ph() {
22464        let a = _mm_set1_ph(2.0);
22465        let b = _mm_set1_ph(1.0);
22466        let r = _mm_maskz_max_ph(0b01010101, a, b);
22467        let e = _mm_set_ph(0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0);
22468        assert_eq_m128h(r, e);
22469    }
22470
22471    #[simd_test(enable = "avx512fp16,avx512vl")]
22472    fn test_mm256_max_ph() {
22473        let a = _mm256_set1_ph(2.0);
22474        let b = _mm256_set1_ph(1.0);
22475        let r = _mm256_max_ph(a, b);
22476        let e = _mm256_set1_ph(2.0);
22477        assert_eq_m256h(r, e);
22478    }
22479
22480    #[simd_test(enable = "avx512fp16,avx512vl")]
22481    fn test_mm256_mask_max_ph() {
22482        let a = _mm256_set1_ph(2.0);
22483        let b = _mm256_set1_ph(1.0);
22484        let src = _mm256_set1_ph(3.0);
22485        let r = _mm256_mask_max_ph(src, 0b0101010101010101, a, b);
22486        let e = _mm256_set_ph(
22487            3.0, 2.0, 3.0, 2.0, 3.0, 2.0, 3.0, 2.0, 3.0, 2.0, 3.0, 2.0, 3.0, 2.0, 3.0, 2.0,
22488        );
22489        assert_eq_m256h(r, e);
22490    }
22491
22492    #[simd_test(enable = "avx512fp16,avx512vl")]
22493    fn test_mm256_maskz_max_ph() {
22494        let a = _mm256_set1_ph(2.0);
22495        let b = _mm256_set1_ph(1.0);
22496        let r = _mm256_maskz_max_ph(0b0101010101010101, a, b);
22497        let e = _mm256_set_ph(
22498            0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0,
22499        );
22500        assert_eq_m256h(r, e);
22501    }
22502
22503    #[simd_test(enable = "avx512fp16")]
22504    fn test_mm512_max_ph() {
22505        let a = _mm512_set1_ph(2.0);
22506        let b = _mm512_set1_ph(1.0);
22507        let r = _mm512_max_ph(a, b);
22508        let e = _mm512_set1_ph(2.0);
22509        assert_eq_m512h(r, e);
22510    }
22511
22512    #[simd_test(enable = "avx512fp16")]
22513    fn test_mm512_mask_max_ph() {
22514        let a = _mm512_set1_ph(2.0);
22515        let b = _mm512_set1_ph(1.0);
22516        let src = _mm512_set1_ph(3.0);
22517        let r = _mm512_mask_max_ph(src, 0b01010101010101010101010101010101, a, b);
22518        let e = _mm512_set_ph(
22519            3.0, 2.0, 3.0, 2.0, 3.0, 2.0, 3.0, 2.0, 3.0, 2.0, 3.0, 2.0, 3.0, 2.0, 3.0, 2.0, 3.0,
22520            2.0, 3.0, 2.0, 3.0, 2.0, 3.0, 2.0, 3.0, 2.0, 3.0, 2.0, 3.0, 2.0, 3.0, 2.0,
22521        );
22522        assert_eq_m512h(r, e);
22523    }
22524
22525    #[simd_test(enable = "avx512fp16")]
22526    fn test_mm512_maskz_max_ph() {
22527        let a = _mm512_set1_ph(2.0);
22528        let b = _mm512_set1_ph(1.0);
22529        let r = _mm512_maskz_max_ph(0b01010101010101010101010101010101, a, b);
22530        let e = _mm512_set_ph(
22531            0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0,
22532            2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0,
22533        );
22534        assert_eq_m512h(r, e);
22535    }
22536
22537    #[simd_test(enable = "avx512fp16")]
22538    fn test_mm512_max_round_ph() {
22539        let a = _mm512_set1_ph(2.0);
22540        let b = _mm512_set1_ph(1.0);
22541        let r = _mm512_max_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
22542        let e = _mm512_set1_ph(2.0);
22543        assert_eq_m512h(r, e);
22544    }
22545
22546    #[simd_test(enable = "avx512fp16")]
22547    fn test_mm512_mask_max_round_ph() {
22548        let a = _mm512_set1_ph(2.0);
22549        let b = _mm512_set1_ph(1.0);
22550        let src = _mm512_set1_ph(3.0);
22551        let r = _mm512_mask_max_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
22552            src,
22553            0b01010101010101010101010101010101,
22554            a,
22555            b,
22556        );
22557        let e = _mm512_set_ph(
22558            3.0, 2.0, 3.0, 2.0, 3.0, 2.0, 3.0, 2.0, 3.0, 2.0, 3.0, 2.0, 3.0, 2.0, 3.0, 2.0, 3.0,
22559            2.0, 3.0, 2.0, 3.0, 2.0, 3.0, 2.0, 3.0, 2.0, 3.0, 2.0, 3.0, 2.0, 3.0, 2.0,
22560        );
22561        assert_eq_m512h(r, e);
22562    }
22563
22564    #[simd_test(enable = "avx512fp16")]
22565    fn test_mm512_maskz_max_round_ph() {
22566        let a = _mm512_set1_ph(2.0);
22567        let b = _mm512_set1_ph(1.0);
22568        let r = _mm512_maskz_max_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
22569            0b01010101010101010101010101010101,
22570            a,
22571            b,
22572        );
22573        let e = _mm512_set_ph(
22574            0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0,
22575            2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0,
22576        );
22577        assert_eq_m512h(r, e);
22578    }
22579
22580    #[simd_test(enable = "avx512fp16,avx512vl")]
22581    fn test_mm_max_sh() {
22582        let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22583        let b = _mm_setr_ph(2.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0);
22584        let r = _mm_max_sh(a, b);
22585        let e = _mm_setr_ph(2.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22586        assert_eq_m128h(r, e);
22587    }
22588
22589    #[simd_test(enable = "avx512fp16,avx512vl")]
22590    fn test_mm_mask_max_sh() {
22591        let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22592        let b = _mm_setr_ph(2.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0);
22593        let src = _mm_setr_ph(3.0, 30.0, 31.0, 32.0, 33.0, 34.0, 35.0, 36.0);
22594        let r = _mm_mask_max_sh(src, 0, a, b);
22595        let e = _mm_setr_ph(3.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22596        assert_eq_m128h(r, e);
22597        let r = _mm_mask_max_sh(src, 1, a, b);
22598        let e = _mm_setr_ph(2.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22599        assert_eq_m128h(r, e);
22600    }
22601
22602    #[simd_test(enable = "avx512fp16,avx512vl")]
22603    fn test_mm_maskz_max_sh() {
22604        let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22605        let b = _mm_setr_ph(2.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0);
22606        let r = _mm_maskz_max_sh(0, a, b);
22607        let e = _mm_setr_ph(0.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22608        assert_eq_m128h(r, e);
22609        let r = _mm_maskz_max_sh(1, a, b);
22610        let e = _mm_setr_ph(2.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22611        assert_eq_m128h(r, e);
22612    }
22613
22614    #[simd_test(enable = "avx512fp16,avx512vl")]
22615    fn test_mm_max_round_sh() {
22616        let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22617        let b = _mm_setr_ph(2.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0);
22618        let r = _mm_max_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
22619        let e = _mm_setr_ph(2.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22620        assert_eq_m128h(r, e);
22621    }
22622
22623    #[simd_test(enable = "avx512fp16,avx512vl")]
22624    fn test_mm_mask_max_round_sh() {
22625        let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22626        let b = _mm_setr_ph(2.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0);
22627        let src = _mm_setr_ph(3.0, 30.0, 31.0, 32.0, 33.0, 34.0, 35.0, 36.0);
22628        let r = _mm_mask_max_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
22629            src, 0, a, b,
22630        );
22631        let e = _mm_setr_ph(3.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22632        assert_eq_m128h(r, e);
22633        let r = _mm_mask_max_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
22634            src, 1, a, b,
22635        );
22636        let e = _mm_setr_ph(2.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22637        assert_eq_m128h(r, e);
22638    }
22639
22640    #[simd_test(enable = "avx512fp16,avx512vl")]
22641    fn test_mm_maskz_max_round_sh() {
22642        let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22643        let b = _mm_setr_ph(2.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0);
22644        let r =
22645            _mm_maskz_max_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
22646        let e = _mm_setr_ph(0.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22647        assert_eq_m128h(r, e);
22648        let r =
22649            _mm_maskz_max_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(1, a, b);
22650        let e = _mm_setr_ph(2.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22651        assert_eq_m128h(r, e);
22652    }
22653
22654    #[simd_test(enable = "avx512fp16,avx512vl")]
22655    fn test_mm_min_ph() {
22656        let a = _mm_set1_ph(2.0);
22657        let b = _mm_set1_ph(1.0);
22658        let r = _mm_min_ph(a, b);
22659        let e = _mm_set1_ph(1.0);
22660        assert_eq_m128h(r, e);
22661    }
22662
22663    #[simd_test(enable = "avx512fp16,avx512vl")]
22664    fn test_mm_mask_min_ph() {
22665        let a = _mm_set1_ph(2.0);
22666        let b = _mm_set1_ph(1.0);
22667        let src = _mm_set1_ph(3.0);
22668        let r = _mm_mask_min_ph(src, 0b01010101, a, b);
22669        let e = _mm_set_ph(3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0);
22670        assert_eq_m128h(r, e);
22671    }
22672
22673    #[simd_test(enable = "avx512fp16,avx512vl")]
22674    fn test_mm_maskz_min_ph() {
22675        let a = _mm_set1_ph(2.0);
22676        let b = _mm_set1_ph(1.0);
22677        let r = _mm_maskz_min_ph(0b01010101, a, b);
22678        let e = _mm_set_ph(0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0);
22679        assert_eq_m128h(r, e);
22680    }
22681
22682    #[simd_test(enable = "avx512fp16,avx512vl")]
22683    fn test_mm256_min_ph() {
22684        let a = _mm256_set1_ph(2.0);
22685        let b = _mm256_set1_ph(1.0);
22686        let r = _mm256_min_ph(a, b);
22687        let e = _mm256_set1_ph(1.0);
22688        assert_eq_m256h(r, e);
22689    }
22690
22691    #[simd_test(enable = "avx512fp16,avx512vl")]
22692    fn test_mm256_mask_min_ph() {
22693        let a = _mm256_set1_ph(2.0);
22694        let b = _mm256_set1_ph(1.0);
22695        let src = _mm256_set1_ph(3.0);
22696        let r = _mm256_mask_min_ph(src, 0b0101010101010101, a, b);
22697        let e = _mm256_set_ph(
22698            3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0,
22699        );
22700        assert_eq_m256h(r, e);
22701    }
22702
22703    #[simd_test(enable = "avx512fp16,avx512vl")]
22704    fn test_mm256_maskz_min_ph() {
22705        let a = _mm256_set1_ph(2.0);
22706        let b = _mm256_set1_ph(1.0);
22707        let r = _mm256_maskz_min_ph(0b0101010101010101, a, b);
22708        let e = _mm256_set_ph(
22709            0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0,
22710        );
22711        assert_eq_m256h(r, e);
22712    }
22713
22714    #[simd_test(enable = "avx512fp16")]
22715    fn test_mm512_min_ph() {
22716        let a = _mm512_set1_ph(2.0);
22717        let b = _mm512_set1_ph(1.0);
22718        let r = _mm512_min_ph(a, b);
22719        let e = _mm512_set1_ph(1.0);
22720        assert_eq_m512h(r, e);
22721    }
22722
22723    #[simd_test(enable = "avx512fp16")]
22724    fn test_mm512_mask_min_ph() {
22725        let a = _mm512_set1_ph(2.0);
22726        let b = _mm512_set1_ph(1.0);
22727        let src = _mm512_set1_ph(3.0);
22728        let r = _mm512_mask_min_ph(src, 0b01010101010101010101010101010101, a, b);
22729        let e = _mm512_set_ph(
22730            3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0,
22731            1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0,
22732        );
22733        assert_eq_m512h(r, e);
22734    }
22735
22736    #[simd_test(enable = "avx512fp16")]
22737    fn test_mm512_maskz_min_ph() {
22738        let a = _mm512_set1_ph(2.0);
22739        let b = _mm512_set1_ph(1.0);
22740        let r = _mm512_maskz_min_ph(0b01010101010101010101010101010101, a, b);
22741        let e = _mm512_set_ph(
22742            0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0,
22743            1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0,
22744        );
22745        assert_eq_m512h(r, e);
22746    }
22747
22748    #[simd_test(enable = "avx512fp16")]
22749    fn test_mm512_min_round_ph() {
22750        let a = _mm512_set1_ph(2.0);
22751        let b = _mm512_set1_ph(1.0);
22752        let r = _mm512_min_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
22753        let e = _mm512_set1_ph(1.0);
22754        assert_eq_m512h(r, e);
22755    }
22756
22757    #[simd_test(enable = "avx512fp16")]
22758    fn test_mm512_mask_min_round_ph() {
22759        let a = _mm512_set1_ph(2.0);
22760        let b = _mm512_set1_ph(1.0);
22761        let src = _mm512_set1_ph(3.0);
22762        let r = _mm512_mask_min_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
22763            src,
22764            0b01010101010101010101010101010101,
22765            a,
22766            b,
22767        );
22768        let e = _mm512_set_ph(
22769            3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0,
22770            1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0, 3.0, 1.0,
22771        );
22772        assert_eq_m512h(r, e);
22773    }
22774
22775    #[simd_test(enable = "avx512fp16")]
22776    fn test_mm512_maskz_min_round_ph() {
22777        let a = _mm512_set1_ph(2.0);
22778        let b = _mm512_set1_ph(1.0);
22779        let r = _mm512_maskz_min_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
22780            0b01010101010101010101010101010101,
22781            a,
22782            b,
22783        );
22784        let e = _mm512_set_ph(
22785            0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0,
22786            1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0,
22787        );
22788        assert_eq_m512h(r, e);
22789    }
22790
22791    #[simd_test(enable = "avx512fp16,avx512vl")]
22792    fn test_mm_min_sh() {
22793        let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22794        let b = _mm_setr_ph(2.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0);
22795        let r = _mm_min_sh(a, b);
22796        let e = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22797        assert_eq_m128h(r, e);
22798    }
22799
22800    #[simd_test(enable = "avx512fp16,avx512vl")]
22801    fn test_mm_mask_min_sh() {
22802        let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22803        let b = _mm_setr_ph(2.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0);
22804        let src = _mm_setr_ph(3.0, 30.0, 31.0, 32.0, 33.0, 34.0, 35.0, 36.0);
22805        let r = _mm_mask_min_sh(src, 0, a, b);
22806        let e = _mm_setr_ph(3.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22807        assert_eq_m128h(r, e);
22808        let r = _mm_mask_min_sh(src, 1, a, b);
22809        let e = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22810        assert_eq_m128h(r, e);
22811    }
22812
22813    #[simd_test(enable = "avx512fp16,avx512vl")]
22814    fn test_mm_maskz_min_sh() {
22815        let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22816        let b = _mm_setr_ph(2.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0);
22817        let r = _mm_maskz_min_sh(0, a, b);
22818        let e = _mm_setr_ph(0.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22819        assert_eq_m128h(r, e);
22820        let r = _mm_maskz_min_sh(1, a, b);
22821        let e = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22822        assert_eq_m128h(r, e);
22823    }
22824
22825    #[simd_test(enable = "avx512fp16,avx512vl")]
22826    fn test_mm_min_round_sh() {
22827        let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22828        let b = _mm_setr_ph(2.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0);
22829        let r = _mm_min_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
22830        let e = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22831        assert_eq_m128h(r, e);
22832    }
22833
22834    #[simd_test(enable = "avx512fp16,avx512vl")]
22835    fn test_mm_mask_min_round_sh() {
22836        let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22837        let b = _mm_setr_ph(2.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0);
22838        let src = _mm_setr_ph(3.0, 30.0, 31.0, 32.0, 33.0, 34.0, 35.0, 36.0);
22839        let r = _mm_mask_min_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
22840            src, 0, a, b,
22841        );
22842        let e = _mm_setr_ph(3.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22843        assert_eq_m128h(r, e);
22844        let r = _mm_mask_min_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
22845            src, 1, a, b,
22846        );
22847        let e = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22848        assert_eq_m128h(r, e);
22849    }
22850
22851    #[simd_test(enable = "avx512fp16,avx512vl")]
22852    fn test_mm_maskz_min_round_sh() {
22853        let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22854        let b = _mm_setr_ph(2.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0);
22855        let r =
22856            _mm_maskz_min_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
22857        let e = _mm_setr_ph(0.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22858        assert_eq_m128h(r, e);
22859        let r =
22860            _mm_maskz_min_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(1, a, b);
22861        let e = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
22862        assert_eq_m128h(r, e);
22863    }
22864
22865    #[simd_test(enable = "avx512fp16,avx512vl")]
22866    fn test_mm_getexp_ph() {
22867        let a = _mm_set1_ph(3.0);
22868        let r = _mm_getexp_ph(a);
22869        let e = _mm_set1_ph(1.0);
22870        assert_eq_m128h(r, e);
22871    }
22872
22873    #[simd_test(enable = "avx512fp16,avx512vl")]
22874    fn test_mm_mask_getexp_ph() {
22875        let a = _mm_set1_ph(3.0);
22876        let src = _mm_set1_ph(4.0);
22877        let r = _mm_mask_getexp_ph(src, 0b01010101, a);
22878        let e = _mm_set_ph(4.0, 1.0, 4.0, 1.0, 4.0, 1.0, 4.0, 1.0);
22879        assert_eq_m128h(r, e);
22880    }
22881
22882    #[simd_test(enable = "avx512fp16,avx512vl")]
22883    fn test_mm_maskz_getexp_ph() {
22884        let a = _mm_set1_ph(3.0);
22885        let r = _mm_maskz_getexp_ph(0b01010101, a);
22886        let e = _mm_set_ph(0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0);
22887        assert_eq_m128h(r, e);
22888    }
22889
22890    #[simd_test(enable = "avx512fp16,avx512vl")]
22891    fn test_mm256_getexp_ph() {
22892        let a = _mm256_set1_ph(3.0);
22893        let r = _mm256_getexp_ph(a);
22894        let e = _mm256_set1_ph(1.0);
22895        assert_eq_m256h(r, e);
22896    }
22897
22898    #[simd_test(enable = "avx512fp16,avx512vl")]
22899    fn test_mm256_mask_getexp_ph() {
22900        let a = _mm256_set1_ph(3.0);
22901        let src = _mm256_set1_ph(4.0);
22902        let r = _mm256_mask_getexp_ph(src, 0b0101010101010101, a);
22903        let e = _mm256_set_ph(
22904            4.0, 1.0, 4.0, 1.0, 4.0, 1.0, 4.0, 1.0, 4.0, 1.0, 4.0, 1.0, 4.0, 1.0, 4.0, 1.0,
22905        );
22906        assert_eq_m256h(r, e);
22907    }
22908
22909    #[simd_test(enable = "avx512fp16,avx512vl")]
22910    fn test_mm256_maskz_getexp_ph() {
22911        let a = _mm256_set1_ph(3.0);
22912        let r = _mm256_maskz_getexp_ph(0b0101010101010101, a);
22913        let e = _mm256_set_ph(
22914            0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0,
22915        );
22916        assert_eq_m256h(r, e);
22917    }
22918
22919    #[simd_test(enable = "avx512fp16")]
22920    fn test_mm512_getexp_ph() {
22921        let a = _mm512_set1_ph(3.0);
22922        let r = _mm512_getexp_ph(a);
22923        let e = _mm512_set1_ph(1.0);
22924        assert_eq_m512h(r, e);
22925    }
22926
22927    #[simd_test(enable = "avx512fp16")]
22928    fn test_mm512_mask_getexp_ph() {
22929        let a = _mm512_set1_ph(3.0);
22930        let src = _mm512_set1_ph(4.0);
22931        let r = _mm512_mask_getexp_ph(src, 0b01010101010101010101010101010101, a);
22932        let e = _mm512_set_ph(
22933            4.0, 1.0, 4.0, 1.0, 4.0, 1.0, 4.0, 1.0, 4.0, 1.0, 4.0, 1.0, 4.0, 1.0, 4.0, 1.0, 4.0,
22934            1.0, 4.0, 1.0, 4.0, 1.0, 4.0, 1.0, 4.0, 1.0, 4.0, 1.0, 4.0, 1.0, 4.0, 1.0,
22935        );
22936        assert_eq_m512h(r, e);
22937    }
22938
22939    #[simd_test(enable = "avx512fp16")]
22940    fn test_mm512_maskz_getexp_ph() {
22941        let a = _mm512_set1_ph(3.0);
22942        let r = _mm512_maskz_getexp_ph(0b01010101010101010101010101010101, a);
22943        let e = _mm512_set_ph(
22944            0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0,
22945            1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0,
22946        );
22947        assert_eq_m512h(r, e);
22948    }
22949
22950    #[simd_test(enable = "avx512fp16")]
22951    fn test_mm512_getexp_round_ph() {
22952        let a = _mm512_set1_ph(3.0);
22953        let r = _mm512_getexp_round_ph::<_MM_FROUND_NO_EXC>(a);
22954        let e = _mm512_set1_ph(1.0);
22955        assert_eq_m512h(r, e);
22956    }
22957
22958    #[simd_test(enable = "avx512fp16")]
22959    fn test_mm512_mask_getexp_round_ph() {
22960        let a = _mm512_set1_ph(3.0);
22961        let src = _mm512_set1_ph(4.0);
22962        let r = _mm512_mask_getexp_round_ph::<_MM_FROUND_NO_EXC>(
22963            src,
22964            0b01010101010101010101010101010101,
22965            a,
22966        );
22967        let e = _mm512_set_ph(
22968            4.0, 1.0, 4.0, 1.0, 4.0, 1.0, 4.0, 1.0, 4.0, 1.0, 4.0, 1.0, 4.0, 1.0, 4.0, 1.0, 4.0,
22969            1.0, 4.0, 1.0, 4.0, 1.0, 4.0, 1.0, 4.0, 1.0, 4.0, 1.0, 4.0, 1.0, 4.0, 1.0,
22970        );
22971        assert_eq_m512h(r, e);
22972    }
22973
22974    #[simd_test(enable = "avx512fp16")]
22975    fn test_mm512_maskz_getexp_round_ph() {
22976        let a = _mm512_set1_ph(3.0);
22977        let r = _mm512_maskz_getexp_round_ph::<_MM_FROUND_NO_EXC>(
22978            0b01010101010101010101010101010101,
22979            a,
22980        );
22981        let e = _mm512_set_ph(
22982            0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0,
22983            1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0,
22984        );
22985        assert_eq_m512h(r, e);
22986    }
22987
22988    #[simd_test(enable = "avx512fp16,avx512vl")]
22989    fn test_mm_getexp_sh() {
22990        let a = _mm_setr_ph(4.0, 10., 11., 12., 13., 14., 15., 16.);
22991        let b = _mm_setr_ph(3.0, 20., 21., 22., 23., 24., 25., 26.);
22992        let r = _mm_getexp_sh(a, b);
22993        let e = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
22994        assert_eq_m128h(r, e);
22995    }
22996
22997    #[simd_test(enable = "avx512fp16,avx512vl")]
22998    fn test_mm_mask_getexp_sh() {
22999        let a = _mm_setr_ph(4.0, 10., 11., 12., 13., 14., 15., 16.);
23000        let b = _mm_setr_ph(3.0, 20., 21., 22., 23., 24., 25., 26.);
23001        let src = _mm_setr_ph(4.0, 30., 31., 32., 33., 34., 35., 36.);
23002        let r = _mm_mask_getexp_sh(src, 0, a, b);
23003        let e = _mm_setr_ph(4.0, 10., 11., 12., 13., 14., 15., 16.);
23004        assert_eq_m128h(r, e);
23005        let r = _mm_mask_getexp_sh(src, 1, a, b);
23006        let e = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
23007        assert_eq_m128h(r, e);
23008    }
23009
23010    #[simd_test(enable = "avx512fp16,avx512vl")]
23011    fn test_mm_maskz_getexp_sh() {
23012        let a = _mm_setr_ph(4.0, 10., 11., 12., 13., 14., 15., 16.);
23013        let b = _mm_setr_ph(3.0, 20., 21., 22., 23., 24., 25., 26.);
23014        let r = _mm_maskz_getexp_sh(0, a, b);
23015        let e = _mm_setr_ph(0.0, 10., 11., 12., 13., 14., 15., 16.);
23016        assert_eq_m128h(r, e);
23017        let r = _mm_maskz_getexp_sh(1, a, b);
23018        let e = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
23019        assert_eq_m128h(r, e);
23020    }
23021
23022    #[simd_test(enable = "avx512fp16,avx512vl")]
23023    fn test_mm_getexp_round_sh() {
23024        let a = _mm_setr_ph(4.0, 10., 11., 12., 13., 14., 15., 16.);
23025        let b = _mm_setr_ph(3.0, 20., 21., 22., 23., 24., 25., 26.);
23026        let r = _mm_getexp_round_sh::<_MM_FROUND_NO_EXC>(a, b);
23027        let e = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
23028        assert_eq_m128h(r, e);
23029    }
23030
23031    #[simd_test(enable = "avx512fp16,avx512vl")]
23032    fn test_mm_mask_getexp_round_sh() {
23033        let a = _mm_setr_ph(4.0, 10., 11., 12., 13., 14., 15., 16.);
23034        let b = _mm_setr_ph(3.0, 20., 21., 22., 23., 24., 25., 26.);
23035        let src = _mm_setr_ph(4.0, 30., 31., 32., 33., 34., 35., 36.);
23036        let r = _mm_mask_getexp_round_sh::<_MM_FROUND_NO_EXC>(src, 0, a, b);
23037        let e = _mm_setr_ph(4.0, 10., 11., 12., 13., 14., 15., 16.);
23038        assert_eq_m128h(r, e);
23039        let r = _mm_mask_getexp_round_sh::<_MM_FROUND_NO_EXC>(src, 1, a, b);
23040        let e = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
23041        assert_eq_m128h(r, e);
23042    }
23043
23044    #[simd_test(enable = "avx512fp16,avx512vl")]
23045    fn test_mm_maskz_getexp_round_sh() {
23046        let a = _mm_setr_ph(4.0, 10., 11., 12., 13., 14., 15., 16.);
23047        let b = _mm_setr_ph(3.0, 20., 21., 22., 23., 24., 25., 26.);
23048        let r = _mm_maskz_getexp_round_sh::<_MM_FROUND_NO_EXC>(0, a, b);
23049        let e = _mm_setr_ph(0.0, 10., 11., 12., 13., 14., 15., 16.);
23050        assert_eq_m128h(r, e);
23051        let r = _mm_maskz_getexp_round_sh::<_MM_FROUND_NO_EXC>(1, a, b);
23052        let e = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
23053        assert_eq_m128h(r, e);
23054    }
23055
23056    #[simd_test(enable = "avx512fp16,avx512vl")]
23057    fn test_mm_getmant_ph() {
23058        let a = _mm_set1_ph(10.0);
23059        let r = _mm_getmant_ph::<_MM_MANT_NORM_P75_1P5, _MM_MANT_SIGN_NAN>(a);
23060        let e = _mm_set1_ph(1.25);
23061        assert_eq_m128h(r, e);
23062    }
23063
23064    #[simd_test(enable = "avx512fp16,avx512vl")]
23065    fn test_mm_mask_getmant_ph() {
23066        let a = _mm_set1_ph(10.0);
23067        let src = _mm_set1_ph(20.0);
23068        let r = _mm_mask_getmant_ph::<_MM_MANT_NORM_P75_1P5, _MM_MANT_SIGN_NAN>(src, 0b01010101, a);
23069        let e = _mm_set_ph(20.0, 1.25, 20.0, 1.25, 20.0, 1.25, 20.0, 1.25);
23070        assert_eq_m128h(r, e);
23071    }
23072
23073    #[simd_test(enable = "avx512fp16,avx512vl")]
23074    fn test_mm_maskz_getmant_ph() {
23075        let a = _mm_set1_ph(10.0);
23076        let r = _mm_maskz_getmant_ph::<_MM_MANT_NORM_P75_1P5, _MM_MANT_SIGN_NAN>(0b01010101, a);
23077        let e = _mm_set_ph(0.0, 1.25, 0.0, 1.25, 0.0, 1.25, 0.0, 1.25);
23078        assert_eq_m128h(r, e);
23079    }
23080
23081    #[simd_test(enable = "avx512fp16,avx512vl")]
23082    fn test_mm256_getmant_ph() {
23083        let a = _mm256_set1_ph(10.0);
23084        let r = _mm256_getmant_ph::<_MM_MANT_NORM_P75_1P5, _MM_MANT_SIGN_NAN>(a);
23085        let e = _mm256_set1_ph(1.25);
23086        assert_eq_m256h(r, e);
23087    }
23088
23089    #[simd_test(enable = "avx512fp16,avx512vl")]
23090    fn test_mm256_mask_getmant_ph() {
23091        let a = _mm256_set1_ph(10.0);
23092        let src = _mm256_set1_ph(20.0);
23093        let r = _mm256_mask_getmant_ph::<_MM_MANT_NORM_P75_1P5, _MM_MANT_SIGN_NAN>(
23094            src,
23095            0b0101010101010101,
23096            a,
23097        );
23098        let e = _mm256_set_ph(
23099            20.0, 1.25, 20.0, 1.25, 20.0, 1.25, 20.0, 1.25, 20.0, 1.25, 20.0, 1.25, 20.0, 1.25,
23100            20.0, 1.25,
23101        );
23102        assert_eq_m256h(r, e);
23103    }
23104
23105    #[simd_test(enable = "avx512fp16,avx512vl")]
23106    fn test_mm256_maskz_getmant_ph() {
23107        let a = _mm256_set1_ph(10.0);
23108        let r = _mm256_maskz_getmant_ph::<_MM_MANT_NORM_P75_1P5, _MM_MANT_SIGN_NAN>(
23109            0b0101010101010101,
23110            a,
23111        );
23112        let e = _mm256_set_ph(
23113            0.0, 1.25, 0.0, 1.25, 0.0, 1.25, 0.0, 1.25, 0.0, 1.25, 0.0, 1.25, 0.0, 1.25, 0.0, 1.25,
23114        );
23115        assert_eq_m256h(r, e);
23116    }
23117
23118    #[simd_test(enable = "avx512fp16")]
23119    fn test_mm512_getmant_ph() {
23120        let a = _mm512_set1_ph(10.0);
23121        let r = _mm512_getmant_ph::<_MM_MANT_NORM_P75_1P5, _MM_MANT_SIGN_NAN>(a);
23122        let e = _mm512_set1_ph(1.25);
23123        assert_eq_m512h(r, e);
23124    }
23125
23126    #[simd_test(enable = "avx512fp16")]
23127    fn test_mm512_mask_getmant_ph() {
23128        let a = _mm512_set1_ph(10.0);
23129        let src = _mm512_set1_ph(20.0);
23130        let r = _mm512_mask_getmant_ph::<_MM_MANT_NORM_P75_1P5, _MM_MANT_SIGN_NAN>(
23131            src,
23132            0b01010101010101010101010101010101,
23133            a,
23134        );
23135        let e = _mm512_set_ph(
23136            20.0, 1.25, 20.0, 1.25, 20.0, 1.25, 20.0, 1.25, 20.0, 1.25, 20.0, 1.25, 20.0, 1.25,
23137            20.0, 1.25, 20.0, 1.25, 20.0, 1.25, 20.0, 1.25, 20.0, 1.25, 20.0, 1.25, 20.0, 1.25,
23138            20.0, 1.25, 20.0, 1.25,
23139        );
23140        assert_eq_m512h(r, e);
23141    }
23142
23143    #[simd_test(enable = "avx512fp16")]
23144    fn test_mm512_maskz_getmant_ph() {
23145        let a = _mm512_set1_ph(10.0);
23146        let r = _mm512_maskz_getmant_ph::<_MM_MANT_NORM_P75_1P5, _MM_MANT_SIGN_NAN>(
23147            0b01010101010101010101010101010101,
23148            a,
23149        );
23150        let e = _mm512_set_ph(
23151            0.0, 1.25, 0.0, 1.25, 0.0, 1.25, 0.0, 1.25, 0.0, 1.25, 0.0, 1.25, 0.0, 1.25, 0.0, 1.25,
23152            0.0, 1.25, 0.0, 1.25, 0.0, 1.25, 0.0, 1.25, 0.0, 1.25, 0.0, 1.25, 0.0, 1.25, 0.0, 1.25,
23153        );
23154        assert_eq_m512h(r, e);
23155    }
23156
23157    #[simd_test(enable = "avx512fp16")]
23158    fn test_mm512_getmant_round_ph() {
23159        let a = _mm512_set1_ph(10.0);
23160        let r =
23161            _mm512_getmant_round_ph::<_MM_MANT_NORM_P75_1P5, _MM_MANT_SIGN_NAN, _MM_FROUND_NO_EXC>(
23162                a,
23163            );
23164        let e = _mm512_set1_ph(1.25);
23165        assert_eq_m512h(r, e);
23166    }
23167
23168    #[simd_test(enable = "avx512fp16")]
23169    fn test_mm512_mask_getmant_round_ph() {
23170        let a = _mm512_set1_ph(10.0);
23171        let src = _mm512_set1_ph(20.0);
23172        let r = _mm512_mask_getmant_round_ph::<
23173            _MM_MANT_NORM_P75_1P5,
23174            _MM_MANT_SIGN_NAN,
23175            _MM_FROUND_NO_EXC,
23176        >(src, 0b01010101010101010101010101010101, a);
23177        let e = _mm512_set_ph(
23178            20.0, 1.25, 20.0, 1.25, 20.0, 1.25, 20.0, 1.25, 20.0, 1.25, 20.0, 1.25, 20.0, 1.25,
23179            20.0, 1.25, 20.0, 1.25, 20.0, 1.25, 20.0, 1.25, 20.0, 1.25, 20.0, 1.25, 20.0, 1.25,
23180            20.0, 1.25, 20.0, 1.25,
23181        );
23182        assert_eq_m512h(r, e);
23183    }
23184
23185    #[simd_test(enable = "avx512fp16")]
23186    fn test_mm512_maskz_getmant_round_ph() {
23187        let a = _mm512_set1_ph(10.0);
23188        let r = _mm512_maskz_getmant_round_ph::<
23189            _MM_MANT_NORM_P75_1P5,
23190            _MM_MANT_SIGN_NAN,
23191            _MM_FROUND_NO_EXC,
23192        >(0b01010101010101010101010101010101, a);
23193        let e = _mm512_set_ph(
23194            0.0, 1.25, 0.0, 1.25, 0.0, 1.25, 0.0, 1.25, 0.0, 1.25, 0.0, 1.25, 0.0, 1.25, 0.0, 1.25,
23195            0.0, 1.25, 0.0, 1.25, 0.0, 1.25, 0.0, 1.25, 0.0, 1.25, 0.0, 1.25, 0.0, 1.25, 0.0, 1.25,
23196        );
23197        assert_eq_m512h(r, e);
23198    }
23199
23200    #[simd_test(enable = "avx512fp16,avx512vl")]
23201    fn test_mm_getmant_sh() {
23202        let a = _mm_setr_ph(15.0, 10., 11., 12., 13., 14., 15., 16.);
23203        let b = _mm_setr_ph(10.0, 20., 21., 22., 23., 24., 25., 26.);
23204        let r = _mm_getmant_sh::<_MM_MANT_NORM_P75_1P5, _MM_MANT_SIGN_NAN>(a, b);
23205        let e = _mm_setr_ph(1.25, 10., 11., 12., 13., 14., 15., 16.);
23206        assert_eq_m128h(r, e);
23207    }
23208
23209    #[simd_test(enable = "avx512fp16,avx512vl")]
23210    fn test_mm_mask_getmant_sh() {
23211        let a = _mm_setr_ph(15.0, 10., 11., 12., 13., 14., 15., 16.);
23212        let b = _mm_setr_ph(10.0, 20., 21., 22., 23., 24., 25., 26.);
23213        let src = _mm_setr_ph(20.0, 30., 31., 32., 33., 34., 35., 36.);
23214        let r = _mm_mask_getmant_sh::<_MM_MANT_NORM_P75_1P5, _MM_MANT_SIGN_NAN>(src, 0, a, b);
23215        let e = _mm_setr_ph(20.0, 10., 11., 12., 13., 14., 15., 16.);
23216        assert_eq_m128h(r, e);
23217        let r = _mm_mask_getmant_sh::<_MM_MANT_NORM_P75_1P5, _MM_MANT_SIGN_NAN>(src, 1, a, b);
23218        let e = _mm_setr_ph(1.25, 10., 11., 12., 13., 14., 15., 16.);
23219        assert_eq_m128h(r, e);
23220    }
23221
23222    #[simd_test(enable = "avx512fp16,avx512vl")]
23223    fn test_mm_maskz_getmant_sh() {
23224        let a = _mm_setr_ph(15.0, 10., 11., 12., 13., 14., 15., 16.);
23225        let b = _mm_setr_ph(10.0, 20., 21., 22., 23., 24., 25., 26.);
23226        let r = _mm_maskz_getmant_sh::<_MM_MANT_NORM_P75_1P5, _MM_MANT_SIGN_NAN>(0, a, b);
23227        let e = _mm_setr_ph(0.0, 10., 11., 12., 13., 14., 15., 16.);
23228        assert_eq_m128h(r, e);
23229        let r = _mm_maskz_getmant_sh::<_MM_MANT_NORM_P75_1P5, _MM_MANT_SIGN_NAN>(1, a, b);
23230        let e = _mm_setr_ph(1.25, 10., 11., 12., 13., 14., 15., 16.);
23231        assert_eq_m128h(r, e);
23232    }
23233
23234    #[simd_test(enable = "avx512fp16,avx512vl")]
23235    fn test_mm_getmant_round_sh() {
23236        let a = _mm_setr_ph(15.0, 10., 11., 12., 13., 14., 15., 16.);
23237        let b = _mm_setr_ph(10.0, 20., 21., 22., 23., 24., 25., 26.);
23238        let r = _mm_getmant_round_sh::<_MM_MANT_NORM_P75_1P5, _MM_MANT_SIGN_NAN, _MM_FROUND_NO_EXC>(
23239            a, b,
23240        );
23241        let e = _mm_setr_ph(1.25, 10., 11., 12., 13., 14., 15., 16.);
23242        assert_eq_m128h(r, e);
23243    }
23244
23245    #[simd_test(enable = "avx512fp16,avx512vl")]
23246    fn test_mm_mask_getmant_round_sh() {
23247        let a = _mm_setr_ph(15.0, 10., 11., 12., 13., 14., 15., 16.);
23248        let b = _mm_setr_ph(10.0, 20., 21., 22., 23., 24., 25., 26.);
23249        let src = _mm_setr_ph(20.0, 30., 31., 32., 33., 34., 35., 36.);
23250        let r = _mm_mask_getmant_round_sh::<
23251            _MM_MANT_NORM_P75_1P5,
23252            _MM_MANT_SIGN_NAN,
23253            _MM_FROUND_NO_EXC,
23254        >(src, 0, a, b);
23255        let e = _mm_setr_ph(20.0, 10., 11., 12., 13., 14., 15., 16.);
23256        assert_eq_m128h(r, e);
23257        let r = _mm_mask_getmant_round_sh::<
23258            _MM_MANT_NORM_P75_1P5,
23259            _MM_MANT_SIGN_NAN,
23260            _MM_FROUND_NO_EXC,
23261        >(src, 1, a, b);
23262        let e = _mm_setr_ph(1.25, 10., 11., 12., 13., 14., 15., 16.);
23263        assert_eq_m128h(r, e);
23264    }
23265
23266    #[simd_test(enable = "avx512fp16,avx512vl")]
23267    fn test_mm_maskz_getmant_round_sh() {
23268        let a = _mm_setr_ph(15.0, 10., 11., 12., 13., 14., 15., 16.);
23269        let b = _mm_setr_ph(10.0, 20., 21., 22., 23., 24., 25., 26.);
23270        let r = _mm_maskz_getmant_round_sh::<
23271            _MM_MANT_NORM_P75_1P5,
23272            _MM_MANT_SIGN_NAN,
23273            _MM_FROUND_NO_EXC,
23274        >(0, a, b);
23275        let e = _mm_setr_ph(0.0, 10., 11., 12., 13., 14., 15., 16.);
23276        assert_eq_m128h(r, e);
23277        let r = _mm_maskz_getmant_round_sh::<
23278            _MM_MANT_NORM_P75_1P5,
23279            _MM_MANT_SIGN_NAN,
23280            _MM_FROUND_NO_EXC,
23281        >(1, a, b);
23282        let e = _mm_setr_ph(1.25, 10., 11., 12., 13., 14., 15., 16.);
23283        assert_eq_m128h(r, e);
23284    }
23285
23286    #[simd_test(enable = "avx512fp16,avx512vl")]
23287    fn test_mm_roundscale_ph() {
23288        let a = _mm_set1_ph(1.1);
23289        let r = _mm_roundscale_ph::<0>(a);
23290        let e = _mm_set1_ph(1.0);
23291        assert_eq_m128h(r, e);
23292    }
23293
23294    #[simd_test(enable = "avx512fp16,avx512vl")]
23295    fn test_mm_mask_roundscale_ph() {
23296        let a = _mm_set1_ph(1.1);
23297        let src = _mm_set1_ph(2.0);
23298        let r = _mm_mask_roundscale_ph::<0>(src, 0b01010101, a);
23299        let e = _mm_set_ph(2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0);
23300        assert_eq_m128h(r, e);
23301    }
23302
23303    #[simd_test(enable = "avx512fp16,avx512vl")]
23304    fn test_mm_maskz_roundscale_ph() {
23305        let a = _mm_set1_ph(1.1);
23306        let r = _mm_maskz_roundscale_ph::<0>(0b01010101, a);
23307        let e = _mm_set_ph(0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0);
23308        assert_eq_m128h(r, e);
23309    }
23310
23311    #[simd_test(enable = "avx512fp16,avx512vl")]
23312    fn test_mm256_roundscale_ph() {
23313        let a = _mm256_set1_ph(1.1);
23314        let r = _mm256_roundscale_ph::<0>(a);
23315        let e = _mm256_set1_ph(1.0);
23316        assert_eq_m256h(r, e);
23317    }
23318
23319    #[simd_test(enable = "avx512fp16,avx512vl")]
23320    fn test_mm256_mask_roundscale_ph() {
23321        let a = _mm256_set1_ph(1.1);
23322        let src = _mm256_set1_ph(2.0);
23323        let r = _mm256_mask_roundscale_ph::<0>(src, 0b0101010101010101, a);
23324        let e = _mm256_set_ph(
23325            2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0,
23326        );
23327        assert_eq_m256h(r, e);
23328    }
23329
23330    #[simd_test(enable = "avx512fp16,avx512vl")]
23331    fn test_mm256_maskz_roundscale_ph() {
23332        let a = _mm256_set1_ph(1.1);
23333        let r = _mm256_maskz_roundscale_ph::<0>(0b0101010101010101, a);
23334        let e = _mm256_set_ph(
23335            0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0,
23336        );
23337        assert_eq_m256h(r, e);
23338    }
23339
23340    #[simd_test(enable = "avx512fp16")]
23341    fn test_mm512_roundscale_ph() {
23342        let a = _mm512_set1_ph(1.1);
23343        let r = _mm512_roundscale_ph::<0>(a);
23344        let e = _mm512_set1_ph(1.0);
23345        assert_eq_m512h(r, e);
23346    }
23347
23348    #[simd_test(enable = "avx512fp16")]
23349    fn test_mm512_mask_roundscale_ph() {
23350        let a = _mm512_set1_ph(1.1);
23351        let src = _mm512_set1_ph(2.0);
23352        let r = _mm512_mask_roundscale_ph::<0>(src, 0b01010101010101010101010101010101, a);
23353        let e = _mm512_set_ph(
23354            2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0,
23355            1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0,
23356        );
23357        assert_eq_m512h(r, e);
23358    }
23359
23360    #[simd_test(enable = "avx512fp16")]
23361    fn test_mm512_maskz_roundscale_ph() {
23362        let a = _mm512_set1_ph(1.1);
23363        let r = _mm512_maskz_roundscale_ph::<0>(0b01010101010101010101010101010101, a);
23364        let e = _mm512_set_ph(
23365            0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0,
23366            1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0,
23367        );
23368        assert_eq_m512h(r, e);
23369    }
23370
23371    #[simd_test(enable = "avx512fp16")]
23372    fn test_mm512_roundscale_round_ph() {
23373        let a = _mm512_set1_ph(1.1);
23374        let r = _mm512_roundscale_round_ph::<0, _MM_FROUND_NO_EXC>(a);
23375        let e = _mm512_set1_ph(1.0);
23376        assert_eq_m512h(r, e);
23377    }
23378
23379    #[simd_test(enable = "avx512fp16")]
23380    fn test_mm512_mask_roundscale_round_ph() {
23381        let a = _mm512_set1_ph(1.1);
23382        let src = _mm512_set1_ph(2.0);
23383        let r = _mm512_mask_roundscale_round_ph::<0, _MM_FROUND_NO_EXC>(
23384            src,
23385            0b01010101010101010101010101010101,
23386            a,
23387        );
23388        let e = _mm512_set_ph(
23389            2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0,
23390            1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0, 2.0, 1.0,
23391        );
23392        assert_eq_m512h(r, e);
23393    }
23394
23395    #[simd_test(enable = "avx512fp16")]
23396    fn test_mm512_maskz_roundscale_round_ph() {
23397        let a = _mm512_set1_ph(1.1);
23398        let r = _mm512_maskz_roundscale_round_ph::<0, _MM_FROUND_NO_EXC>(
23399            0b01010101010101010101010101010101,
23400            a,
23401        );
23402        let e = _mm512_set_ph(
23403            0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0,
23404            1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0,
23405        );
23406        assert_eq_m512h(r, e);
23407    }
23408
23409    #[simd_test(enable = "avx512fp16,avx512vl")]
23410    fn test_mm_roundscale_sh() {
23411        let a = _mm_setr_ph(2.0, 10., 11., 12., 13., 14., 15., 16.);
23412        let b = _mm_setr_ph(1.1, 20., 21., 22., 23., 24., 25., 26.);
23413        let r = _mm_roundscale_sh::<0>(a, b);
23414        let e = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
23415        assert_eq_m128h(r, e);
23416    }
23417
23418    #[simd_test(enable = "avx512fp16,avx512vl")]
23419    fn test_mm_mask_roundscale_sh() {
23420        let a = _mm_setr_ph(2.0, 10., 11., 12., 13., 14., 15., 16.);
23421        let b = _mm_setr_ph(1.1, 20., 21., 22., 23., 24., 25., 26.);
23422        let src = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
23423        let r = _mm_mask_roundscale_sh::<0>(src, 0, a, b);
23424        let e = _mm_setr_ph(3.0, 10., 11., 12., 13., 14., 15., 16.);
23425        assert_eq_m128h(r, e);
23426        let r = _mm_mask_roundscale_sh::<0>(src, 1, a, b);
23427        let e = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
23428        assert_eq_m128h(r, e);
23429    }
23430
23431    #[simd_test(enable = "avx512fp16,avx512vl")]
23432    fn test_mm_maskz_roundscale_sh() {
23433        let a = _mm_setr_ph(2.0, 10., 11., 12., 13., 14., 15., 16.);
23434        let b = _mm_setr_ph(1.1, 20., 21., 22., 23., 24., 25., 26.);
23435        let r = _mm_maskz_roundscale_sh::<0>(0, a, b);
23436        let e = _mm_setr_ph(0.0, 10., 11., 12., 13., 14., 15., 16.);
23437        assert_eq_m128h(r, e);
23438        let r = _mm_maskz_roundscale_sh::<0>(1, a, b);
23439        let e = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
23440        assert_eq_m128h(r, e);
23441    }
23442
23443    #[simd_test(enable = "avx512fp16,avx512vl")]
23444    fn test_mm_roundscale_round_sh() {
23445        let a = _mm_setr_ph(2.0, 10., 11., 12., 13., 14., 15., 16.);
23446        let b = _mm_setr_ph(1.1, 20., 21., 22., 23., 24., 25., 26.);
23447        let r = _mm_roundscale_round_sh::<0, _MM_FROUND_NO_EXC>(a, b);
23448        let e = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
23449        assert_eq_m128h(r, e);
23450    }
23451
23452    #[simd_test(enable = "avx512fp16,avx512vl")]
23453    fn test_mm_mask_roundscale_round_sh() {
23454        let a = _mm_setr_ph(2.0, 10., 11., 12., 13., 14., 15., 16.);
23455        let b = _mm_setr_ph(1.1, 20., 21., 22., 23., 24., 25., 26.);
23456        let src = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
23457        let r = _mm_mask_roundscale_round_sh::<0, _MM_FROUND_NO_EXC>(src, 0, a, b);
23458        let e = _mm_setr_ph(3.0, 10., 11., 12., 13., 14., 15., 16.);
23459        assert_eq_m128h(r, e);
23460        let r = _mm_mask_roundscale_round_sh::<0, _MM_FROUND_NO_EXC>(src, 1, a, b);
23461        let e = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
23462        assert_eq_m128h(r, e);
23463    }
23464
23465    #[simd_test(enable = "avx512fp16,avx512vl")]
23466    fn test_mm_maskz_roundscale_round_sh() {
23467        let a = _mm_setr_ph(2.0, 10., 11., 12., 13., 14., 15., 16.);
23468        let b = _mm_setr_ph(1.1, 20., 21., 22., 23., 24., 25., 26.);
23469        let r = _mm_maskz_roundscale_round_sh::<0, _MM_FROUND_NO_EXC>(0, a, b);
23470        let e = _mm_setr_ph(0.0, 10., 11., 12., 13., 14., 15., 16.);
23471        assert_eq_m128h(r, e);
23472        let r = _mm_maskz_roundscale_round_sh::<0, _MM_FROUND_NO_EXC>(1, a, b);
23473        let e = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
23474        assert_eq_m128h(r, e);
23475    }
23476
23477    #[simd_test(enable = "avx512fp16,avx512vl")]
23478    fn test_mm_scalef_ph() {
23479        let a = _mm_set1_ph(1.);
23480        let b = _mm_set1_ph(3.);
23481        let r = _mm_scalef_ph(a, b);
23482        let e = _mm_set1_ph(8.0);
23483        assert_eq_m128h(r, e);
23484    }
23485
23486    #[simd_test(enable = "avx512fp16,avx512vl")]
23487    fn test_mm_mask_scalef_ph() {
23488        let a = _mm_set1_ph(1.);
23489        let b = _mm_set1_ph(3.);
23490        let src = _mm_set1_ph(2.);
23491        let r = _mm_mask_scalef_ph(src, 0b01010101, a, b);
23492        let e = _mm_set_ph(2.0, 8.0, 2.0, 8.0, 2.0, 8.0, 2.0, 8.0);
23493        assert_eq_m128h(r, e);
23494    }
23495
23496    #[simd_test(enable = "avx512fp16,avx512vl")]
23497    fn test_mm_maskz_scalef_ph() {
23498        let a = _mm_set1_ph(1.);
23499        let b = _mm_set1_ph(3.);
23500        let r = _mm_maskz_scalef_ph(0b01010101, a, b);
23501        let e = _mm_set_ph(0.0, 8.0, 0.0, 8.0, 0.0, 8.0, 0.0, 8.0);
23502        assert_eq_m128h(r, e);
23503    }
23504
23505    #[simd_test(enable = "avx512fp16,avx512vl")]
23506    fn test_mm256_scalef_ph() {
23507        let a = _mm256_set1_ph(1.);
23508        let b = _mm256_set1_ph(3.);
23509        let r = _mm256_scalef_ph(a, b);
23510        let e = _mm256_set1_ph(8.0);
23511        assert_eq_m256h(r, e);
23512    }
23513
23514    #[simd_test(enable = "avx512fp16,avx512vl")]
23515    fn test_mm256_mask_scalef_ph() {
23516        let a = _mm256_set1_ph(1.);
23517        let b = _mm256_set1_ph(3.);
23518        let src = _mm256_set1_ph(2.);
23519        let r = _mm256_mask_scalef_ph(src, 0b0101010101010101, a, b);
23520        let e = _mm256_set_ph(
23521            2.0, 8.0, 2.0, 8.0, 2.0, 8.0, 2.0, 8.0, 2.0, 8.0, 2.0, 8.0, 2.0, 8.0, 2.0, 8.0,
23522        );
23523        assert_eq_m256h(r, e);
23524    }
23525
23526    #[simd_test(enable = "avx512fp16,avx512vl")]
23527    fn test_mm256_maskz_scalef_ph() {
23528        let a = _mm256_set1_ph(1.);
23529        let b = _mm256_set1_ph(3.);
23530        let r = _mm256_maskz_scalef_ph(0b0101010101010101, a, b);
23531        let e = _mm256_set_ph(
23532            0.0, 8.0, 0.0, 8.0, 0.0, 8.0, 0.0, 8.0, 0.0, 8.0, 0.0, 8.0, 0.0, 8.0, 0.0, 8.0,
23533        );
23534        assert_eq_m256h(r, e);
23535    }
23536
23537    #[simd_test(enable = "avx512fp16")]
23538    fn test_mm512_scalef_ph() {
23539        let a = _mm512_set1_ph(1.);
23540        let b = _mm512_set1_ph(3.);
23541        let r = _mm512_scalef_ph(a, b);
23542        let e = _mm512_set1_ph(8.0);
23543        assert_eq_m512h(r, e);
23544    }
23545
23546    #[simd_test(enable = "avx512fp16")]
23547    fn test_mm512_mask_scalef_ph() {
23548        let a = _mm512_set1_ph(1.);
23549        let b = _mm512_set1_ph(3.);
23550        let src = _mm512_set1_ph(2.);
23551        let r = _mm512_mask_scalef_ph(src, 0b01010101010101010101010101010101, a, b);
23552        let e = _mm512_set_ph(
23553            2.0, 8.0, 2.0, 8.0, 2.0, 8.0, 2.0, 8.0, 2.0, 8.0, 2.0, 8.0, 2.0, 8.0, 2.0, 8.0, 2.0,
23554            8.0, 2.0, 8.0, 2.0, 8.0, 2.0, 8.0, 2.0, 8.0, 2.0, 8.0, 2.0, 8.0, 2.0, 8.0,
23555        );
23556        assert_eq_m512h(r, e);
23557    }
23558
23559    #[simd_test(enable = "avx512fp16")]
23560    fn test_mm512_maskz_scalef_ph() {
23561        let a = _mm512_set1_ph(1.);
23562        let b = _mm512_set1_ph(3.);
23563        let r = _mm512_maskz_scalef_ph(0b01010101010101010101010101010101, a, b);
23564        let e = _mm512_set_ph(
23565            0.0, 8.0, 0.0, 8.0, 0.0, 8.0, 0.0, 8.0, 0.0, 8.0, 0.0, 8.0, 0.0, 8.0, 0.0, 8.0, 0.0,
23566            8.0, 0.0, 8.0, 0.0, 8.0, 0.0, 8.0, 0.0, 8.0, 0.0, 8.0, 0.0, 8.0, 0.0, 8.0,
23567        );
23568        assert_eq_m512h(r, e);
23569    }
23570
23571    #[simd_test(enable = "avx512fp16")]
23572    fn test_mm512_scalef_round_ph() {
23573        let a = _mm512_set1_ph(1.);
23574        let b = _mm512_set1_ph(3.);
23575        let r = _mm512_scalef_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
23576        let e = _mm512_set1_ph(8.0);
23577        assert_eq_m512h(r, e);
23578    }
23579
23580    #[simd_test(enable = "avx512fp16")]
23581    fn test_mm512_mask_scalef_round_ph() {
23582        let a = _mm512_set1_ph(1.);
23583        let b = _mm512_set1_ph(3.);
23584        let src = _mm512_set1_ph(2.);
23585        let r = _mm512_mask_scalef_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
23586            src,
23587            0b01010101010101010101010101010101,
23588            a,
23589            b,
23590        );
23591        let e = _mm512_set_ph(
23592            2.0, 8.0, 2.0, 8.0, 2.0, 8.0, 2.0, 8.0, 2.0, 8.0, 2.0, 8.0, 2.0, 8.0, 2.0, 8.0, 2.0,
23593            8.0, 2.0, 8.0, 2.0, 8.0, 2.0, 8.0, 2.0, 8.0, 2.0, 8.0, 2.0, 8.0, 2.0, 8.0,
23594        );
23595        assert_eq_m512h(r, e);
23596    }
23597
23598    #[simd_test(enable = "avx512fp16")]
23599    fn test_mm512_maskz_scalef_round_ph() {
23600        let a = _mm512_set1_ph(1.);
23601        let b = _mm512_set1_ph(3.);
23602        let r = _mm512_maskz_scalef_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
23603            0b01010101010101010101010101010101,
23604            a,
23605            b,
23606        );
23607        let e = _mm512_set_ph(
23608            0.0, 8.0, 0.0, 8.0, 0.0, 8.0, 0.0, 8.0, 0.0, 8.0, 0.0, 8.0, 0.0, 8.0, 0.0, 8.0, 0.0,
23609            8.0, 0.0, 8.0, 0.0, 8.0, 0.0, 8.0, 0.0, 8.0, 0.0, 8.0, 0.0, 8.0, 0.0, 8.0,
23610        );
23611        assert_eq_m512h(r, e);
23612    }
23613
23614    #[simd_test(enable = "avx512fp16,avx512vl")]
23615    fn test_mm_scalef_sh() {
23616        let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
23617        let b = _mm_setr_ph(3.0, 20., 21., 22., 23., 24., 25., 26.);
23618        let r = _mm_scalef_sh(a, b);
23619        let e = _mm_setr_ph(8.0, 10., 11., 12., 13., 14., 15., 16.);
23620        assert_eq_m128h(r, e);
23621    }
23622
23623    #[simd_test(enable = "avx512fp16,avx512vl")]
23624    fn test_mm_mask_scalef_sh() {
23625        let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
23626        let b = _mm_setr_ph(3.0, 20., 21., 22., 23., 24., 25., 26.);
23627        let src = _mm_setr_ph(2.0, 30., 31., 32., 33., 34., 35., 36.);
23628        let r = _mm_mask_scalef_sh(src, 0, a, b);
23629        let e = _mm_setr_ph(2.0, 10., 11., 12., 13., 14., 15., 16.);
23630        assert_eq_m128h(r, e);
23631        let r = _mm_mask_scalef_sh(src, 1, a, b);
23632        let e = _mm_setr_ph(8.0, 10., 11., 12., 13., 14., 15., 16.);
23633        assert_eq_m128h(r, e);
23634    }
23635
23636    #[simd_test(enable = "avx512fp16,avx512vl")]
23637    fn test_mm_maskz_scalef_sh() {
23638        let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
23639        let b = _mm_setr_ph(3.0, 20., 21., 22., 23., 24., 25., 26.);
23640        let r = _mm_maskz_scalef_sh(0, a, b);
23641        let e = _mm_setr_ph(0.0, 10., 11., 12., 13., 14., 15., 16.);
23642        assert_eq_m128h(r, e);
23643        let r = _mm_maskz_scalef_sh(1, a, b);
23644        let e = _mm_setr_ph(8.0, 10., 11., 12., 13., 14., 15., 16.);
23645        assert_eq_m128h(r, e);
23646    }
23647
23648    #[simd_test(enable = "avx512fp16,avx512vl")]
23649    fn test_mm_scalef_round_sh() {
23650        let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
23651        let b = _mm_setr_ph(3.0, 20., 21., 22., 23., 24., 25., 26.);
23652        let r = _mm_scalef_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
23653        let e = _mm_setr_ph(8.0, 10., 11., 12., 13., 14., 15., 16.);
23654        assert_eq_m128h(r, e);
23655    }
23656
23657    #[simd_test(enable = "avx512fp16,avx512vl")]
23658    fn test_mm_mask_scalef_round_sh() {
23659        let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
23660        let b = _mm_setr_ph(3.0, 20., 21., 22., 23., 24., 25., 26.);
23661        let src = _mm_setr_ph(2.0, 30., 31., 32., 33., 34., 35., 36.);
23662        let r = _mm_mask_scalef_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
23663            src, 0, a, b,
23664        );
23665        let e = _mm_setr_ph(2.0, 10., 11., 12., 13., 14., 15., 16.);
23666        assert_eq_m128h(r, e);
23667        let r = _mm_mask_scalef_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
23668            src, 1, a, b,
23669        );
23670        let e = _mm_setr_ph(8.0, 10., 11., 12., 13., 14., 15., 16.);
23671        assert_eq_m128h(r, e);
23672    }
23673
23674    #[simd_test(enable = "avx512fp16,avx512vl")]
23675    fn test_mm_maskz_scalef_round_sh() {
23676        let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
23677        let b = _mm_setr_ph(3.0, 20., 21., 22., 23., 24., 25., 26.);
23678        let r =
23679            _mm_maskz_scalef_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
23680        let e = _mm_setr_ph(0.0, 10., 11., 12., 13., 14., 15., 16.);
23681        assert_eq_m128h(r, e);
23682        let r =
23683            _mm_maskz_scalef_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(1, a, b);
23684        let e = _mm_setr_ph(8.0, 10., 11., 12., 13., 14., 15., 16.);
23685        assert_eq_m128h(r, e);
23686    }
23687
23688    #[simd_test(enable = "avx512fp16,avx512vl")]
23689    fn test_mm_reduce_ph() {
23690        let a = _mm_set1_ph(1.25);
23691        let r = _mm_reduce_ph::<{ 16 | _MM_FROUND_TO_ZERO }>(a);
23692        let e = _mm_set1_ph(0.25);
23693        assert_eq_m128h(r, e);
23694    }
23695
23696    #[simd_test(enable = "avx512fp16,avx512vl")]
23697    fn test_mm_mask_reduce_ph() {
23698        let a = _mm_set1_ph(1.25);
23699        let src = _mm_set1_ph(2.0);
23700        let r = _mm_mask_reduce_ph::<{ 16 | _MM_FROUND_TO_ZERO }>(src, 0b01010101, a);
23701        let e = _mm_set_ph(2.0, 0.25, 2.0, 0.25, 2.0, 0.25, 2.0, 0.25);
23702        assert_eq_m128h(r, e);
23703    }
23704
23705    #[simd_test(enable = "avx512fp16,avx512vl")]
23706    fn test_mm_maskz_reduce_ph() {
23707        let a = _mm_set1_ph(1.25);
23708        let r = _mm_maskz_reduce_ph::<{ 16 | _MM_FROUND_TO_ZERO }>(0b01010101, a);
23709        let e = _mm_set_ph(0.0, 0.25, 0.0, 0.25, 0.0, 0.25, 0.0, 0.25);
23710        assert_eq_m128h(r, e);
23711    }
23712
23713    #[simd_test(enable = "avx512fp16,avx512vl")]
23714    fn test_mm256_reduce_ph() {
23715        let a = _mm256_set1_ph(1.25);
23716        let r = _mm256_reduce_ph::<{ 16 | _MM_FROUND_TO_ZERO }>(a);
23717        let e = _mm256_set1_ph(0.25);
23718        assert_eq_m256h(r, e);
23719    }
23720
23721    #[simd_test(enable = "avx512fp16,avx512vl")]
23722    fn test_mm256_mask_reduce_ph() {
23723        let a = _mm256_set1_ph(1.25);
23724        let src = _mm256_set1_ph(2.0);
23725        let r = _mm256_mask_reduce_ph::<{ 16 | _MM_FROUND_TO_ZERO }>(src, 0b0101010101010101, a);
23726        let e = _mm256_set_ph(
23727            2.0, 0.25, 2.0, 0.25, 2.0, 0.25, 2.0, 0.25, 2.0, 0.25, 2.0, 0.25, 2.0, 0.25, 2.0, 0.25,
23728        );
23729        assert_eq_m256h(r, e);
23730    }
23731
23732    #[simd_test(enable = "avx512fp16,avx512vl")]
23733    fn test_mm256_maskz_reduce_ph() {
23734        let a = _mm256_set1_ph(1.25);
23735        let r = _mm256_maskz_reduce_ph::<{ 16 | _MM_FROUND_TO_ZERO }>(0b0101010101010101, a);
23736        let e = _mm256_set_ph(
23737            0.0, 0.25, 0.0, 0.25, 0.0, 0.25, 0.0, 0.25, 0.0, 0.25, 0.0, 0.25, 0.0, 0.25, 0.0, 0.25,
23738        );
23739        assert_eq_m256h(r, e);
23740    }
23741
23742    #[simd_test(enable = "avx512fp16")]
23743    fn test_mm512_reduce_ph() {
23744        let a = _mm512_set1_ph(1.25);
23745        let r = _mm512_reduce_ph::<{ 16 | _MM_FROUND_TO_ZERO }>(a);
23746        let e = _mm512_set1_ph(0.25);
23747        assert_eq_m512h(r, e);
23748    }
23749
23750    #[simd_test(enable = "avx512fp16")]
23751    fn test_mm512_mask_reduce_ph() {
23752        let a = _mm512_set1_ph(1.25);
23753        let src = _mm512_set1_ph(2.0);
23754        let r = _mm512_mask_reduce_ph::<{ 16 | _MM_FROUND_TO_ZERO }>(
23755            src,
23756            0b01010101010101010101010101010101,
23757            a,
23758        );
23759        let e = _mm512_set_ph(
23760            2.0, 0.25, 2.0, 0.25, 2.0, 0.25, 2.0, 0.25, 2.0, 0.25, 2.0, 0.25, 2.0, 0.25, 2.0, 0.25,
23761            2.0, 0.25, 2.0, 0.25, 2.0, 0.25, 2.0, 0.25, 2.0, 0.25, 2.0, 0.25, 2.0, 0.25, 2.0, 0.25,
23762        );
23763        assert_eq_m512h(r, e);
23764    }
23765
23766    #[simd_test(enable = "avx512fp16")]
23767    fn test_mm512_maskz_reduce_ph() {
23768        let a = _mm512_set1_ph(1.25);
23769        let r = _mm512_maskz_reduce_ph::<{ 16 | _MM_FROUND_TO_ZERO }>(
23770            0b01010101010101010101010101010101,
23771            a,
23772        );
23773        let e = _mm512_set_ph(
23774            0.0, 0.25, 0.0, 0.25, 0.0, 0.25, 0.0, 0.25, 0.0, 0.25, 0.0, 0.25, 0.0, 0.25, 0.0, 0.25,
23775            0.0, 0.25, 0.0, 0.25, 0.0, 0.25, 0.0, 0.25, 0.0, 0.25, 0.0, 0.25, 0.0, 0.25, 0.0, 0.25,
23776        );
23777        assert_eq_m512h(r, e);
23778    }
23779
23780    #[simd_test(enable = "avx512fp16")]
23781    fn test_mm512_reduce_round_ph() {
23782        let a = _mm512_set1_ph(1.25);
23783        let r = _mm512_reduce_round_ph::<{ 16 | _MM_FROUND_TO_ZERO }, _MM_FROUND_NO_EXC>(a);
23784        let e = _mm512_set1_ph(0.25);
23785        assert_eq_m512h(r, e);
23786    }
23787
23788    #[simd_test(enable = "avx512fp16")]
23789    fn test_mm512_mask_reduce_round_ph() {
23790        let a = _mm512_set1_ph(1.25);
23791        let src = _mm512_set1_ph(2.0);
23792        let r = _mm512_mask_reduce_round_ph::<{ 16 | _MM_FROUND_TO_ZERO }, _MM_FROUND_NO_EXC>(
23793            src,
23794            0b01010101010101010101010101010101,
23795            a,
23796        );
23797        let e = _mm512_set_ph(
23798            2.0, 0.25, 2.0, 0.25, 2.0, 0.25, 2.0, 0.25, 2.0, 0.25, 2.0, 0.25, 2.0, 0.25, 2.0, 0.25,
23799            2.0, 0.25, 2.0, 0.25, 2.0, 0.25, 2.0, 0.25, 2.0, 0.25, 2.0, 0.25, 2.0, 0.25, 2.0, 0.25,
23800        );
23801        assert_eq_m512h(r, e);
23802    }
23803
23804    #[simd_test(enable = "avx512fp16")]
23805    fn test_mm512_maskz_reduce_round_ph() {
23806        let a = _mm512_set1_ph(1.25);
23807        let r = _mm512_maskz_reduce_round_ph::<{ 16 | _MM_FROUND_TO_ZERO }, _MM_FROUND_NO_EXC>(
23808            0b01010101010101010101010101010101,
23809            a,
23810        );
23811        let e = _mm512_set_ph(
23812            0.0, 0.25, 0.0, 0.25, 0.0, 0.25, 0.0, 0.25, 0.0, 0.25, 0.0, 0.25, 0.0, 0.25, 0.0, 0.25,
23813            0.0, 0.25, 0.0, 0.25, 0.0, 0.25, 0.0, 0.25, 0.0, 0.25, 0.0, 0.25, 0.0, 0.25, 0.0, 0.25,
23814        );
23815        assert_eq_m512h(r, e);
23816    }
23817
23818    #[simd_test(enable = "avx512fp16,avx512vl")]
23819    fn test_mm_reduce_sh() {
23820        let a = _mm_setr_ph(3.0, 10., 11., 12., 13., 14., 15., 16.);
23821        let b = _mm_setr_ph(1.25, 20., 21., 22., 23., 24., 25., 26.);
23822        let r = _mm_reduce_sh::<{ 16 | _MM_FROUND_TO_ZERO }>(a, b);
23823        let e = _mm_setr_ph(0.25, 10., 11., 12., 13., 14., 15., 16.);
23824        assert_eq_m128h(r, e);
23825    }
23826
23827    #[simd_test(enable = "avx512fp16,avx512vl")]
23828    fn test_mm_mask_reduce_sh() {
23829        let a = _mm_setr_ph(3.0, 10., 11., 12., 13., 14., 15., 16.);
23830        let b = _mm_setr_ph(1.25, 20., 21., 22., 23., 24., 25., 26.);
23831        let src = _mm_setr_ph(2.0, 30., 31., 32., 33., 34., 35., 36.);
23832        let r = _mm_mask_reduce_sh::<{ 16 | _MM_FROUND_TO_ZERO }>(src, 0, a, b);
23833        let e = _mm_setr_ph(2.0, 10., 11., 12., 13., 14., 15., 16.);
23834        assert_eq_m128h(r, e);
23835        let r = _mm_mask_reduce_sh::<{ 16 | _MM_FROUND_TO_ZERO }>(src, 1, a, b);
23836        let e = _mm_setr_ph(0.25, 10., 11., 12., 13., 14., 15., 16.);
23837        assert_eq_m128h(r, e);
23838    }
23839
23840    #[simd_test(enable = "avx512fp16,avx512vl")]
23841    fn test_mm_maskz_reduce_sh() {
23842        let a = _mm_setr_ph(3.0, 10., 11., 12., 13., 14., 15., 16.);
23843        let b = _mm_setr_ph(1.25, 20., 21., 22., 23., 24., 25., 26.);
23844        let r = _mm_maskz_reduce_sh::<{ 16 | _MM_FROUND_TO_ZERO }>(0, a, b);
23845        let e = _mm_setr_ph(0.0, 10., 11., 12., 13., 14., 15., 16.);
23846        assert_eq_m128h(r, e);
23847        let r = _mm_maskz_reduce_sh::<{ 16 | _MM_FROUND_TO_ZERO }>(1, a, b);
23848        let e = _mm_setr_ph(0.25, 10., 11., 12., 13., 14., 15., 16.);
23849        assert_eq_m128h(r, e);
23850    }
23851
23852    #[simd_test(enable = "avx512fp16,avx512vl")]
23853    fn test_mm_reduce_round_sh() {
23854        let a = _mm_setr_ph(3.0, 10., 11., 12., 13., 14., 15., 16.);
23855        let b = _mm_setr_ph(1.25, 20., 21., 22., 23., 24., 25., 26.);
23856        let r = _mm_reduce_round_sh::<{ 16 | _MM_FROUND_TO_ZERO }, _MM_FROUND_NO_EXC>(a, b);
23857        let e = _mm_setr_ph(0.25, 10., 11., 12., 13., 14., 15., 16.);
23858        assert_eq_m128h(r, e);
23859    }
23860
23861    #[simd_test(enable = "avx512fp16,avx512vl")]
23862    fn test_mm_mask_reduce_round_sh() {
23863        let a = _mm_setr_ph(3.0, 10., 11., 12., 13., 14., 15., 16.);
23864        let b = _mm_setr_ph(1.25, 20., 21., 22., 23., 24., 25., 26.);
23865        let src = _mm_setr_ph(2.0, 30., 31., 32., 33., 34., 35., 36.);
23866        let r = _mm_mask_reduce_round_sh::<{ 16 | _MM_FROUND_TO_ZERO }, _MM_FROUND_NO_EXC>(
23867            src, 0, a, b,
23868        );
23869        let e = _mm_setr_ph(2.0, 10., 11., 12., 13., 14., 15., 16.);
23870        assert_eq_m128h(r, e);
23871        let r = _mm_mask_reduce_round_sh::<{ 16 | _MM_FROUND_TO_ZERO }, _MM_FROUND_NO_EXC>(
23872            src, 1, a, b,
23873        );
23874        let e = _mm_setr_ph(0.25, 10., 11., 12., 13., 14., 15., 16.);
23875        assert_eq_m128h(r, e);
23876    }
23877
23878    #[simd_test(enable = "avx512fp16,avx512vl")]
23879    fn test_mm_maskz_reduce_round_sh() {
23880        let a = _mm_setr_ph(3.0, 10., 11., 12., 13., 14., 15., 16.);
23881        let b = _mm_setr_ph(1.25, 20., 21., 22., 23., 24., 25., 26.);
23882        let r =
23883            _mm_maskz_reduce_round_sh::<{ 16 | _MM_FROUND_TO_ZERO }, _MM_FROUND_NO_EXC>(0, a, b);
23884        let e = _mm_setr_ph(0.0, 10., 11., 12., 13., 14., 15., 16.);
23885        assert_eq_m128h(r, e);
23886        let r =
23887            _mm_maskz_reduce_round_sh::<{ 16 | _MM_FROUND_TO_ZERO }, _MM_FROUND_NO_EXC>(1, a, b);
23888        let e = _mm_setr_ph(0.25, 10., 11., 12., 13., 14., 15., 16.);
23889        assert_eq_m128h(r, e);
23890    }
23891
23892    #[simd_test(enable = "avx512fp16,avx512vl")]
23893    const fn test_mm_reduce_add_ph() {
23894        let a = _mm_set1_ph(2.0);
23895        let r = _mm_reduce_add_ph(a);
23896        assert_eq!(r, 16.0);
23897    }
23898
23899    #[simd_test(enable = "avx512fp16,avx512vl")]
23900    const fn test_mm256_reduce_add_ph() {
23901        let a = _mm256_set1_ph(2.0);
23902        let r = _mm256_reduce_add_ph(a);
23903        assert_eq!(r, 32.0);
23904    }
23905
23906    #[simd_test(enable = "avx512fp16")]
23907    const fn test_mm512_reduce_add_ph() {
23908        let a = _mm512_set1_ph(2.0);
23909        let r = _mm512_reduce_add_ph(a);
23910        assert_eq!(r, 64.0);
23911    }
23912
23913    #[simd_test(enable = "avx512fp16,avx512vl")]
23914    const fn test_mm_reduce_mul_ph() {
23915        let a = _mm_set1_ph(2.0);
23916        let r = _mm_reduce_mul_ph(a);
23917        assert_eq!(r, 256.0);
23918    }
23919
23920    #[simd_test(enable = "avx512fp16,avx512vl")]
23921    const fn test_mm256_reduce_mul_ph() {
23922        let a = _mm256_set1_ph(1.2);
23923        let r = _mm256_reduce_mul_ph(a);
23924        assert_eq!(r, 18.5);
23925    }
23926
23927    #[simd_test(enable = "avx512fp16")]
23928    const fn test_mm512_reduce_mul_ph() {
23929        let a = _mm512_set1_ph(1.2);
23930        let r = _mm512_reduce_mul_ph(a);
23931        assert_eq!(r, 342.3);
23932    }
23933
23934    #[simd_test(enable = "avx512fp16,avx512vl")]
23935    fn test_mm_reduce_max_ph() {
23936        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
23937        let r = _mm_reduce_max_ph(a);
23938        assert_eq!(r, 8.0);
23939    }
23940
23941    #[simd_test(enable = "avx512fp16,avx512vl")]
23942    fn test_mm256_reduce_max_ph() {
23943        let a = _mm256_set_ph(
23944            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
23945        );
23946        let r = _mm256_reduce_max_ph(a);
23947        assert_eq!(r, 16.0);
23948    }
23949
23950    #[simd_test(enable = "avx512fp16")]
23951    fn test_mm512_reduce_max_ph() {
23952        let a = _mm512_set_ph(
23953            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
23954            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
23955            31.0, 32.0,
23956        );
23957        let r = _mm512_reduce_max_ph(a);
23958        assert_eq!(r, 32.0);
23959    }
23960
23961    #[simd_test(enable = "avx512fp16,avx512vl")]
23962    fn test_mm_reduce_min_ph() {
23963        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
23964        let r = _mm_reduce_min_ph(a);
23965        assert_eq!(r, 1.0);
23966    }
23967
23968    #[simd_test(enable = "avx512fp16,avx512vl")]
23969    fn test_mm256_reduce_min_ph() {
23970        let a = _mm256_set_ph(
23971            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
23972        );
23973        let r = _mm256_reduce_min_ph(a);
23974        assert_eq!(r, 1.0);
23975    }
23976
23977    #[simd_test(enable = "avx512fp16")]
23978    fn test_mm512_reduce_min_ph() {
23979        let a = _mm512_set_ph(
23980            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
23981            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
23982            31.0, 32.0,
23983        );
23984        let r = _mm512_reduce_min_ph(a);
23985        assert_eq!(r, 1.0);
23986    }
23987
23988    #[simd_test(enable = "avx512fp16,avx512vl")]
23989    fn test_mm_fpclass_ph_mask() {
23990        let a = _mm_set_ph(
23991            1.,
23992            f16::INFINITY,
23993            f16::NEG_INFINITY,
23994            0.0,
23995            -0.0,
23996            -2.0,
23997            f16::NAN,
23998            5.9e-8, // Denormal
23999        );
24000        let r = _mm_fpclass_ph_mask::<0x18>(a); // infinities
24001        assert_eq!(r, 0b01100000);
24002    }
24003
24004    #[simd_test(enable = "avx512fp16,avx512vl")]
24005    fn test_mm_mask_fpclass_ph_mask() {
24006        let a = _mm_set_ph(
24007            1.,
24008            f16::INFINITY,
24009            f16::NEG_INFINITY,
24010            0.0,
24011            -0.0,
24012            -2.0,
24013            f16::NAN,
24014            5.9e-8, // Denormal
24015        );
24016        let r = _mm_mask_fpclass_ph_mask::<0x18>(0b01010101, a);
24017        assert_eq!(r, 0b01000000);
24018    }
24019
24020    #[simd_test(enable = "avx512fp16,avx512vl")]
24021    fn test_mm256_fpclass_ph_mask() {
24022        let a = _mm256_set_ph(
24023            1.,
24024            f16::INFINITY,
24025            f16::NEG_INFINITY,
24026            0.0,
24027            -0.0,
24028            -2.0,
24029            f16::NAN,
24030            5.9e-8, // Denormal
24031            1.,
24032            f16::INFINITY,
24033            f16::NEG_INFINITY,
24034            0.0,
24035            -0.0,
24036            -2.0,
24037            f16::NAN,
24038            5.9e-8, // Denormal
24039        );
24040        let r = _mm256_fpclass_ph_mask::<0x18>(a); // infinities
24041        assert_eq!(r, 0b0110000001100000);
24042    }
24043
24044    #[simd_test(enable = "avx512fp16,avx512vl")]
24045    fn test_mm256_mask_fpclass_ph_mask() {
24046        let a = _mm256_set_ph(
24047            1.,
24048            f16::INFINITY,
24049            f16::NEG_INFINITY,
24050            0.0,
24051            -0.0,
24052            -2.0,
24053            f16::NAN,
24054            5.9e-8, // Denormal
24055            1.,
24056            f16::INFINITY,
24057            f16::NEG_INFINITY,
24058            0.0,
24059            -0.0,
24060            -2.0,
24061            f16::NAN,
24062            5.9e-8, // Denormal
24063        );
24064        let r = _mm256_mask_fpclass_ph_mask::<0x18>(0b0101010101010101, a);
24065        assert_eq!(r, 0b0100000001000000);
24066    }
24067
24068    #[simd_test(enable = "avx512fp16")]
24069    fn test_mm512_fpclass_ph_mask() {
24070        let a = _mm512_set_ph(
24071            1.,
24072            f16::INFINITY,
24073            f16::NEG_INFINITY,
24074            0.0,
24075            -0.0,
24076            -2.0,
24077            f16::NAN,
24078            5.9e-8, // Denormal
24079            1.,
24080            f16::INFINITY,
24081            f16::NEG_INFINITY,
24082            0.0,
24083            -0.0,
24084            -2.0,
24085            f16::NAN,
24086            5.9e-8, // Denormal
24087            1.,
24088            f16::INFINITY,
24089            f16::NEG_INFINITY,
24090            0.0,
24091            -0.0,
24092            -2.0,
24093            f16::NAN,
24094            5.9e-8, // Denormal
24095            1.,
24096            f16::INFINITY,
24097            f16::NEG_INFINITY,
24098            0.0,
24099            -0.0,
24100            -2.0,
24101            f16::NAN,
24102            5.9e-8, // Denormal
24103        );
24104        let r = _mm512_fpclass_ph_mask::<0x18>(a); // infinities
24105        assert_eq!(r, 0b01100000011000000110000001100000);
24106    }
24107
24108    #[simd_test(enable = "avx512fp16")]
24109    fn test_mm512_mask_fpclass_ph_mask() {
24110        let a = _mm512_set_ph(
24111            1.,
24112            f16::INFINITY,
24113            f16::NEG_INFINITY,
24114            0.0,
24115            -0.0,
24116            -2.0,
24117            f16::NAN,
24118            5.9e-8, // Denormal
24119            1.,
24120            f16::INFINITY,
24121            f16::NEG_INFINITY,
24122            0.0,
24123            -0.0,
24124            -2.0,
24125            f16::NAN,
24126            5.9e-8, // Denormal
24127            1.,
24128            f16::INFINITY,
24129            f16::NEG_INFINITY,
24130            0.0,
24131            -0.0,
24132            -2.0,
24133            f16::NAN,
24134            5.9e-8, // Denormal
24135            1.,
24136            f16::INFINITY,
24137            f16::NEG_INFINITY,
24138            0.0,
24139            -0.0,
24140            -2.0,
24141            f16::NAN,
24142            5.9e-8, // Denormal
24143        );
24144        let r = _mm512_mask_fpclass_ph_mask::<0x18>(0b01010101010101010101010101010101, a);
24145        assert_eq!(r, 0b01000000010000000100000001000000);
24146    }
24147
24148    #[simd_test(enable = "avx512fp16")]
24149    fn test_mm_fpclass_sh_mask() {
24150        let a = _mm_set_sh(f16::INFINITY);
24151        let r = _mm_fpclass_sh_mask::<0x18>(a);
24152        assert_eq!(r, 1);
24153    }
24154
24155    #[simd_test(enable = "avx512fp16")]
24156    fn test_mm_mask_fpclass_sh_mask() {
24157        let a = _mm_set_sh(f16::INFINITY);
24158        let r = _mm_mask_fpclass_sh_mask::<0x18>(0, a);
24159        assert_eq!(r, 0);
24160        let r = _mm_mask_fpclass_sh_mask::<0x18>(1, a);
24161        assert_eq!(r, 1);
24162    }
24163
24164    #[simd_test(enable = "avx512fp16,avx512vl")]
24165    const fn test_mm_mask_blend_ph() {
24166        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
24167        let b = _mm_set_ph(-1.0, -2.0, -3.0, -4.0, -5.0, -6.0, -7.0, -8.0);
24168        let r = _mm_mask_blend_ph(0b01010101, a, b);
24169        let e = _mm_set_ph(1.0, -2.0, 3.0, -4.0, 5.0, -6.0, 7.0, -8.0);
24170        assert_eq_m128h(r, e);
24171    }
24172
24173    #[simd_test(enable = "avx512fp16,avx512vl")]
24174    const fn test_mm256_mask_blend_ph() {
24175        let a = _mm256_set_ph(
24176            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
24177        );
24178        let b = _mm256_set_ph(
24179            -1.0, -2.0, -3.0, -4.0, -5.0, -6.0, -7.0, -8.0, -9.0, -10.0, -11.0, -12.0, -13.0,
24180            -14.0, -15.0, -16.0,
24181        );
24182        let r = _mm256_mask_blend_ph(0b0101010101010101, a, b);
24183        let e = _mm256_set_ph(
24184            1.0, -2.0, 3.0, -4.0, 5.0, -6.0, 7.0, -8.0, 9.0, -10.0, 11.0, -12.0, 13.0, -14.0, 15.0,
24185            -16.0,
24186        );
24187        assert_eq_m256h(r, e);
24188    }
24189
24190    #[simd_test(enable = "avx512fp16")]
24191    const fn test_mm512_mask_blend_ph() {
24192        let a = _mm512_set_ph(
24193            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
24194            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
24195            31.0, 32.0,
24196        );
24197        let b = _mm512_set_ph(
24198            -1.0, -2.0, -3.0, -4.0, -5.0, -6.0, -7.0, -8.0, -9.0, -10.0, -11.0, -12.0, -13.0,
24199            -14.0, -15.0, -16.0, -17.0, -18.0, -19.0, -20.0, -21.0, -22.0, -23.0, -24.0, -25.0,
24200            -26.0, -27.0, -28.0, -29.0, -30.0, -31.0, -32.0,
24201        );
24202        let r = _mm512_mask_blend_ph(0b01010101010101010101010101010101, a, b);
24203        let e = _mm512_set_ph(
24204            1.0, -2.0, 3.0, -4.0, 5.0, -6.0, 7.0, -8.0, 9.0, -10.0, 11.0, -12.0, 13.0, -14.0, 15.0,
24205            -16.0, 17.0, -18.0, 19.0, -20.0, 21.0, -22.0, 23.0, -24.0, 25.0, -26.0, 27.0, -28.0,
24206            29.0, -30.0, 31.0, -32.0,
24207        );
24208        assert_eq_m512h(r, e);
24209    }
24210
24211    #[simd_test(enable = "avx512fp16,avx512vl")]
24212    fn test_mm_permutex2var_ph() {
24213        let a = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
24214        let b = _mm_setr_ph(9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
24215        let idx = _mm_setr_epi16(0, 2, 4, 6, 8, 10, 12, 14);
24216        let r = _mm_permutex2var_ph(a, idx, b);
24217        let e = _mm_setr_ph(1.0, 3.0, 5.0, 7.0, 9.0, 11.0, 13.0, 15.0);
24218        assert_eq_m128h(r, e);
24219    }
24220
24221    #[simd_test(enable = "avx512fp16,avx512vl")]
24222    fn test_mm256_permutex2var_ph() {
24223        let a = _mm256_setr_ph(
24224            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
24225        );
24226        let b = _mm256_setr_ph(
24227            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
24228            31.0, 32.0,
24229        );
24230        let idx = _mm256_setr_epi16(0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30);
24231        let r = _mm256_permutex2var_ph(a, idx, b);
24232        let e = _mm256_setr_ph(
24233            1.0, 3.0, 5.0, 7.0, 9.0, 11.0, 13.0, 15.0, 17.0, 19.0, 21.0, 23.0, 25.0, 27.0, 29.0,
24234            31.0,
24235        );
24236        assert_eq_m256h(r, e);
24237    }
24238
24239    #[simd_test(enable = "avx512fp16")]
24240    fn test_mm512_permutex2var_ph() {
24241        let a = _mm512_setr_ph(
24242            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
24243            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
24244            31.0, 32.0,
24245        );
24246        let b = _mm512_setr_ph(
24247            33.0, 34.0, 35.0, 36.0, 37.0, 38.0, 39.0, 40.0, 41.0, 42.0, 43.0, 44.0, 45.0, 46.0,
24248            47.0, 48.0, 49.0, 50.0, 51.0, 52.0, 53.0, 54.0, 55.0, 56.0, 57.0, 58.0, 59.0, 60.0,
24249            61.0, 62.0, 63.0, 64.0,
24250        );
24251        let idx = _mm512_set_epi16(
24252            62, 60, 58, 56, 54, 52, 50, 48, 46, 44, 42, 40, 38, 36, 34, 32, 30, 28, 26, 24, 22, 20,
24253            18, 16, 14, 12, 10, 8, 6, 4, 2, 0,
24254        );
24255        let r = _mm512_permutex2var_ph(a, idx, b);
24256        let e = _mm512_setr_ph(
24257            1.0, 3.0, 5.0, 7.0, 9.0, 11.0, 13.0, 15.0, 17.0, 19.0, 21.0, 23.0, 25.0, 27.0, 29.0,
24258            31.0, 33.0, 35.0, 37.0, 39.0, 41.0, 43.0, 45.0, 47.0, 49.0, 51.0, 53.0, 55.0, 57.0,
24259            59.0, 61.0, 63.0,
24260        );
24261        assert_eq_m512h(r, e);
24262    }
24263
24264    #[simd_test(enable = "avx512fp16,avx512vl")]
24265    fn test_mm_permutexvar_ph() {
24266        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
24267        let idx = _mm_set_epi16(0, 2, 4, 6, 1, 3, 5, 7);
24268        let r = _mm_permutexvar_ph(idx, a);
24269        let e = _mm_setr_ph(1.0, 3.0, 5.0, 7.0, 2.0, 4.0, 6.0, 8.0);
24270        assert_eq_m128h(r, e);
24271    }
24272
24273    #[simd_test(enable = "avx512fp16,avx512vl")]
24274    fn test_mm256_permutexvar_ph() {
24275        let a = _mm256_set_ph(
24276            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
24277        );
24278        let idx = _mm256_set_epi16(0, 2, 4, 6, 8, 10, 12, 14, 1, 3, 5, 7, 9, 11, 13, 15);
24279        let r = _mm256_permutexvar_ph(idx, a);
24280        let e = _mm256_setr_ph(
24281            1.0, 3.0, 5.0, 7.0, 9.0, 11.0, 13.0, 15.0, 2.0, 4.0, 6.0, 8.0, 10.0, 12.0, 14.0, 16.0,
24282        );
24283        assert_eq_m256h(r, e);
24284    }
24285
24286    #[simd_test(enable = "avx512fp16")]
24287    fn test_mm512_permutexvar_ph() {
24288        let a = _mm512_set_ph(
24289            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
24290            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
24291            31.0, 32.0,
24292        );
24293        let idx = _mm512_set_epi16(
24294            0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 1, 3, 5, 7, 9, 11, 13, 15,
24295            17, 19, 21, 23, 25, 27, 29, 31,
24296        );
24297        let r = _mm512_permutexvar_ph(idx, a);
24298        let e = _mm512_setr_ph(
24299            1.0, 3.0, 5.0, 7.0, 9.0, 11.0, 13.0, 15.0, 17.0, 19.0, 21.0, 23.0, 25.0, 27.0, 29.0,
24300            31.0, 2.0, 4.0, 6.0, 8.0, 10.0, 12.0, 14.0, 16.0, 18.0, 20.0, 22.0, 24.0, 26.0, 28.0,
24301            30.0, 32.0,
24302        );
24303        assert_eq_m512h(r, e);
24304    }
24305
24306    #[simd_test(enable = "avx512fp16,avx512vl")]
24307    fn test_mm_cvtepi16_ph() {
24308        let a = _mm_set_epi16(1, 2, 3, 4, 5, 6, 7, 8);
24309        let r = _mm_cvtepi16_ph(a);
24310        let e = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
24311        assert_eq_m128h(r, e);
24312    }
24313
24314    #[simd_test(enable = "avx512fp16,avx512vl")]
24315    fn test_mm_mask_cvtepi16_ph() {
24316        let a = _mm_set_epi16(1, 2, 3, 4, 5, 6, 7, 8);
24317        let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
24318        let r = _mm_mask_cvtepi16_ph(src, 0b01010101, a);
24319        let e = _mm_set_ph(10., 2., 12., 4., 14., 6., 16., 8.);
24320        assert_eq_m128h(r, e);
24321    }
24322
24323    #[simd_test(enable = "avx512fp16,avx512vl")]
24324    fn test_mm_maskz_cvtepi16_ph() {
24325        let a = _mm_set_epi16(1, 2, 3, 4, 5, 6, 7, 8);
24326        let r = _mm_maskz_cvtepi16_ph(0b01010101, a);
24327        let e = _mm_set_ph(0., 2., 0., 4., 0., 6., 0., 8.);
24328        assert_eq_m128h(r, e);
24329    }
24330
24331    #[simd_test(enable = "avx512fp16,avx512vl")]
24332    fn test_mm256_cvtepi16_ph() {
24333        let a = _mm256_set_epi16(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
24334        let r = _mm256_cvtepi16_ph(a);
24335        let e = _mm256_set_ph(
24336            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
24337        );
24338        assert_eq_m256h(r, e);
24339    }
24340
24341    #[simd_test(enable = "avx512fp16,avx512vl")]
24342    fn test_mm256_mask_cvtepi16_ph() {
24343        let a = _mm256_set_epi16(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
24344        let src = _mm256_set_ph(
24345            10., 11., 12., 13., 14., 15., 16., 17., 18., 19., 20., 21., 22., 23., 24., 25.,
24346        );
24347        let r = _mm256_mask_cvtepi16_ph(src, 0b0101010101010101, a);
24348        let e = _mm256_set_ph(
24349            10., 2., 12., 4., 14., 6., 16., 8., 18., 10., 20., 12., 22., 14., 24., 16.,
24350        );
24351        assert_eq_m256h(r, e);
24352    }
24353
24354    #[simd_test(enable = "avx512fp16,avx512vl")]
24355    fn test_mm256_maskz_cvtepi16_ph() {
24356        let a = _mm256_set_epi16(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
24357        let r = _mm256_maskz_cvtepi16_ph(0b0101010101010101, a);
24358        let e = _mm256_set_ph(
24359            0., 2., 0., 4., 0., 6., 0., 8., 0., 10., 0., 12., 0., 14., 0., 16.,
24360        );
24361        assert_eq_m256h(r, e);
24362    }
24363
24364    #[simd_test(enable = "avx512fp16")]
24365    fn test_mm512_cvtepi16_ph() {
24366        let a = _mm512_set_epi16(
24367            1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
24368            25, 26, 27, 28, 29, 30, 31, 32,
24369        );
24370        let r = _mm512_cvtepi16_ph(a);
24371        let e = _mm512_set_ph(
24372            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
24373            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
24374            31.0, 32.0,
24375        );
24376        assert_eq_m512h(r, e);
24377    }
24378
24379    #[simd_test(enable = "avx512fp16")]
24380    fn test_mm512_mask_cvtepi16_ph() {
24381        let a = _mm512_set_epi16(
24382            1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
24383            25, 26, 27, 28, 29, 30, 31, 32,
24384        );
24385        let src = _mm512_set_ph(
24386            10., 11., 12., 13., 14., 15., 16., 17., 18., 19., 20., 21., 22., 23., 24., 25., 26.,
24387            27., 28., 29., 30., 31., 32., 33., 34., 35., 36., 37., 38., 39., 40., 41.,
24388        );
24389        let r = _mm512_mask_cvtepi16_ph(src, 0b01010101010101010101010101010101, a);
24390        let e = _mm512_set_ph(
24391            10., 2., 12., 4., 14., 6., 16., 8., 18., 10., 20., 12., 22., 14., 24., 16., 26., 18.,
24392            28., 20., 30., 22., 32., 24., 34., 26., 36., 28., 38., 30., 40., 32.,
24393        );
24394        assert_eq_m512h(r, e);
24395    }
24396
24397    #[simd_test(enable = "avx512fp16")]
24398    fn test_mm512_maskz_cvtepi16_ph() {
24399        let a = _mm512_set_epi16(
24400            1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
24401            25, 26, 27, 28, 29, 30, 31, 32,
24402        );
24403        let r = _mm512_maskz_cvtepi16_ph(0b01010101010101010101010101010101, a);
24404        let e = _mm512_set_ph(
24405            0., 2., 0., 4., 0., 6., 0., 8., 0., 10., 0., 12., 0., 14., 0., 16., 0., 18., 0., 20.,
24406            0., 22., 0., 24., 0., 26., 0., 28., 0., 30., 0., 32.,
24407        );
24408        assert_eq_m512h(r, e);
24409    }
24410
24411    #[simd_test(enable = "avx512fp16")]
24412    fn test_mm512_cvt_roundepi16_ph() {
24413        let a = _mm512_set_epi16(
24414            1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
24415            25, 26, 27, 28, 29, 30, 31, 32,
24416        );
24417        let r = _mm512_cvt_roundepi16_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
24418        let e = _mm512_set_ph(
24419            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
24420            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
24421            31.0, 32.0,
24422        );
24423        assert_eq_m512h(r, e);
24424    }
24425
24426    #[simd_test(enable = "avx512fp16")]
24427    fn test_mm512_mask_cvt_roundepi16_ph() {
24428        let a = _mm512_set_epi16(
24429            1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
24430            25, 26, 27, 28, 29, 30, 31, 32,
24431        );
24432        let src = _mm512_set_ph(
24433            10., 11., 12., 13., 14., 15., 16., 17., 18., 19., 20., 21., 22., 23., 24., 25., 26.,
24434            27., 28., 29., 30., 31., 32., 33., 34., 35., 36., 37., 38., 39., 40., 41.,
24435        );
24436        let r = _mm512_mask_cvt_roundepi16_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
24437            src,
24438            0b01010101010101010101010101010101,
24439            a,
24440        );
24441        let e = _mm512_set_ph(
24442            10., 2., 12., 4., 14., 6., 16., 8., 18., 10., 20., 12., 22., 14., 24., 16., 26., 18.,
24443            28., 20., 30., 22., 32., 24., 34., 26., 36., 28., 38., 30., 40., 32.,
24444        );
24445        assert_eq_m512h(r, e);
24446    }
24447
24448    #[simd_test(enable = "avx512fp16")]
24449    fn test_mm512_maskz_cvt_roundepi16_ph() {
24450        let a = _mm512_set_epi16(
24451            1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
24452            25, 26, 27, 28, 29, 30, 31, 32,
24453        );
24454        let r = _mm512_maskz_cvt_roundepi16_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
24455            0b01010101010101010101010101010101,
24456            a,
24457        );
24458        let e = _mm512_set_ph(
24459            0., 2., 0., 4., 0., 6., 0., 8., 0., 10., 0., 12., 0., 14., 0., 16., 0., 18., 0., 20.,
24460            0., 22., 0., 24., 0., 26., 0., 28., 0., 30., 0., 32.,
24461        );
24462        assert_eq_m512h(r, e);
24463    }
24464
24465    #[simd_test(enable = "avx512fp16,avx512vl")]
24466    fn test_mm_cvtepu16_ph() {
24467        let a = _mm_set_epi16(1, 2, 3, 4, 5, 6, 7, 8);
24468        let r = _mm_cvtepu16_ph(a);
24469        let e = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
24470        assert_eq_m128h(r, e);
24471    }
24472
24473    #[simd_test(enable = "avx512fp16,avx512vl")]
24474    fn test_mm_mask_cvtepu16_ph() {
24475        let a = _mm_set_epi16(1, 2, 3, 4, 5, 6, 7, 8);
24476        let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
24477        let r = _mm_mask_cvtepu16_ph(src, 0b01010101, a);
24478        let e = _mm_set_ph(10., 2., 12., 4., 14., 6., 16., 8.);
24479        assert_eq_m128h(r, e);
24480    }
24481
24482    #[simd_test(enable = "avx512fp16,avx512vl")]
24483    fn test_mm_maskz_cvtepu16_ph() {
24484        let a = _mm_set_epi16(1, 2, 3, 4, 5, 6, 7, 8);
24485        let r = _mm_maskz_cvtepu16_ph(0b01010101, a);
24486        let e = _mm_set_ph(0., 2., 0., 4., 0., 6., 0., 8.);
24487        assert_eq_m128h(r, e);
24488    }
24489
24490    #[simd_test(enable = "avx512fp16,avx512vl")]
24491    fn test_mm256_cvtepu16_ph() {
24492        let a = _mm256_set_epi16(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
24493        let r = _mm256_cvtepu16_ph(a);
24494        let e = _mm256_set_ph(
24495            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
24496        );
24497        assert_eq_m256h(r, e);
24498    }
24499
24500    #[simd_test(enable = "avx512fp16,avx512vl")]
24501    fn test_mm256_mask_cvtepu16_ph() {
24502        let a = _mm256_set_epi16(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
24503        let src = _mm256_set_ph(
24504            10., 11., 12., 13., 14., 15., 16., 17., 18., 19., 20., 21., 22., 23., 24., 25.,
24505        );
24506        let r = _mm256_mask_cvtepu16_ph(src, 0b0101010101010101, a);
24507        let e = _mm256_set_ph(
24508            10., 2., 12., 4., 14., 6., 16., 8., 18., 10., 20., 12., 22., 14., 24., 16.,
24509        );
24510        assert_eq_m256h(r, e);
24511    }
24512
24513    #[simd_test(enable = "avx512fp16,avx512vl")]
24514    fn test_mm256_maskz_cvtepu16_ph() {
24515        let a = _mm256_set_epi16(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
24516        let r = _mm256_maskz_cvtepu16_ph(0b0101010101010101, a);
24517        let e = _mm256_set_ph(
24518            0., 2., 0., 4., 0., 6., 0., 8., 0., 10., 0., 12., 0., 14., 0., 16.,
24519        );
24520        assert_eq_m256h(r, e);
24521    }
24522
24523    #[simd_test(enable = "avx512fp16")]
24524    fn test_mm512_cvtepu16_ph() {
24525        let a = _mm512_set_epi16(
24526            1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
24527            25, 26, 27, 28, 29, 30, 31, 32,
24528        );
24529        let r = _mm512_cvtepu16_ph(a);
24530        let e = _mm512_set_ph(
24531            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
24532            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
24533            31.0, 32.0,
24534        );
24535        assert_eq_m512h(r, e);
24536    }
24537
24538    #[simd_test(enable = "avx512fp16")]
24539    fn test_mm512_mask_cvtepu16_ph() {
24540        let a = _mm512_set_epi16(
24541            1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
24542            25, 26, 27, 28, 29, 30, 31, 32,
24543        );
24544        let src = _mm512_set_ph(
24545            10., 11., 12., 13., 14., 15., 16., 17., 18., 19., 20., 21., 22., 23., 24., 25., 26.,
24546            27., 28., 29., 30., 31., 32., 33., 34., 35., 36., 37., 38., 39., 40., 41.,
24547        );
24548        let r = _mm512_mask_cvtepu16_ph(src, 0b01010101010101010101010101010101, a);
24549        let e = _mm512_set_ph(
24550            10., 2., 12., 4., 14., 6., 16., 8., 18., 10., 20., 12., 22., 14., 24., 16., 26., 18.,
24551            28., 20., 30., 22., 32., 24., 34., 26., 36., 28., 38., 30., 40., 32.,
24552        );
24553        assert_eq_m512h(r, e);
24554    }
24555
24556    #[simd_test(enable = "avx512fp16")]
24557    fn test_mm512_maskz_cvtepu16_ph() {
24558        let a = _mm512_set_epi16(
24559            1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
24560            25, 26, 27, 28, 29, 30, 31, 32,
24561        );
24562        let r = _mm512_maskz_cvtepu16_ph(0b01010101010101010101010101010101, a);
24563        let e = _mm512_set_ph(
24564            0., 2., 0., 4., 0., 6., 0., 8., 0., 10., 0., 12., 0., 14., 0., 16., 0., 18., 0., 20.,
24565            0., 22., 0., 24., 0., 26., 0., 28., 0., 30., 0., 32.,
24566        );
24567        assert_eq_m512h(r, e);
24568    }
24569
24570    #[simd_test(enable = "avx512fp16")]
24571    fn test_mm512_cvt_roundepu16_ph() {
24572        let a = _mm512_set_epi16(
24573            1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
24574            25, 26, 27, 28, 29, 30, 31, 32,
24575        );
24576        let r = _mm512_cvt_roundepu16_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
24577        let e = _mm512_set_ph(
24578            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
24579            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
24580            31.0, 32.0,
24581        );
24582        assert_eq_m512h(r, e);
24583    }
24584
24585    #[simd_test(enable = "avx512fp16")]
24586    fn test_mm512_mask_cvt_roundepu16_ph() {
24587        let a = _mm512_set_epi16(
24588            1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
24589            25, 26, 27, 28, 29, 30, 31, 32,
24590        );
24591        let src = _mm512_set_ph(
24592            10., 11., 12., 13., 14., 15., 16., 17., 18., 19., 20., 21., 22., 23., 24., 25., 26.,
24593            27., 28., 29., 30., 31., 32., 33., 34., 35., 36., 37., 38., 39., 40., 41.,
24594        );
24595        let r = _mm512_mask_cvt_roundepu16_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
24596            src,
24597            0b01010101010101010101010101010101,
24598            a,
24599        );
24600        let e = _mm512_set_ph(
24601            10., 2., 12., 4., 14., 6., 16., 8., 18., 10., 20., 12., 22., 14., 24., 16., 26., 18.,
24602            28., 20., 30., 22., 32., 24., 34., 26., 36., 28., 38., 30., 40., 32.,
24603        );
24604        assert_eq_m512h(r, e);
24605    }
24606
24607    #[simd_test(enable = "avx512fp16")]
24608    fn test_mm512_maskz_cvt_roundepu16_ph() {
24609        let a = _mm512_set_epi16(
24610            1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
24611            25, 26, 27, 28, 29, 30, 31, 32,
24612        );
24613        let r = _mm512_maskz_cvt_roundepu16_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
24614            0b01010101010101010101010101010101,
24615            a,
24616        );
24617        let e = _mm512_set_ph(
24618            0., 2., 0., 4., 0., 6., 0., 8., 0., 10., 0., 12., 0., 14., 0., 16., 0., 18., 0., 20.,
24619            0., 22., 0., 24., 0., 26., 0., 28., 0., 30., 0., 32.,
24620        );
24621        assert_eq_m512h(r, e);
24622    }
24623
24624    #[simd_test(enable = "avx512fp16,avx512vl")]
24625    fn test_mm_cvtepi32_ph() {
24626        let a = _mm_set_epi32(1, 2, 3, 4);
24627        let r = _mm_cvtepi32_ph(a);
24628        let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
24629        assert_eq_m128h(r, e);
24630    }
24631
24632    #[simd_test(enable = "avx512fp16,avx512vl")]
24633    fn test_mm_mask_cvtepi32_ph() {
24634        let a = _mm_set_epi32(1, 2, 3, 4);
24635        let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
24636        let r = _mm_mask_cvtepi32_ph(src, 0b0101, a);
24637        let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 14., 2., 16., 4.);
24638        assert_eq_m128h(r, e);
24639    }
24640
24641    #[simd_test(enable = "avx512fp16,avx512vl")]
24642    fn test_mm_maskz_cvtepi32_ph() {
24643        let a = _mm_set_epi32(1, 2, 3, 4);
24644        let r = _mm_maskz_cvtepi32_ph(0b0101, a);
24645        let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 2., 0.0, 4.);
24646        assert_eq_m128h(r, e);
24647    }
24648
24649    #[simd_test(enable = "avx512fp16,avx512vl")]
24650    fn test_mm256_cvtepi32_ph() {
24651        let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
24652        let r = _mm256_cvtepi32_ph(a);
24653        let e = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
24654        assert_eq_m128h(r, e);
24655    }
24656
24657    #[simd_test(enable = "avx512fp16,avx512vl")]
24658    fn test_mm256_mask_cvtepi32_ph() {
24659        let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
24660        let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
24661        let r = _mm256_mask_cvtepi32_ph(src, 0b01010101, a);
24662        let e = _mm_set_ph(10., 2., 12., 4., 14., 6., 16., 8.);
24663        assert_eq_m128h(r, e);
24664    }
24665
24666    #[simd_test(enable = "avx512fp16,avx512vl")]
24667    fn test_mm256_maskz_cvtepi32_ph() {
24668        let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
24669        let r = _mm256_maskz_cvtepi32_ph(0b01010101, a);
24670        let e = _mm_set_ph(0.0, 2.0, 0.0, 4.0, 0.0, 6.0, 0.0, 8.0);
24671        assert_eq_m128h(r, e);
24672    }
24673
24674    #[simd_test(enable = "avx512fp16")]
24675    fn test_mm512_cvtepi32_ph() {
24676        let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
24677        let r = _mm512_cvtepi32_ph(a);
24678        let e = _mm256_set_ph(
24679            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
24680        );
24681        assert_eq_m256h(r, e);
24682    }
24683
24684    #[simd_test(enable = "avx512fp16,avx512vl")]
24685    fn test_mm512_mask_cvtepi32_ph() {
24686        let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
24687        let src = _mm256_set_ph(
24688            10., 11., 12., 13., 14., 15., 16., 17., 18., 19., 20., 21., 22., 23., 24., 25.,
24689        );
24690        let r = _mm512_mask_cvtepi32_ph(src, 0b0101010101010101, a);
24691        let e = _mm256_set_ph(
24692            10., 2., 12., 4., 14., 6., 16., 8., 18., 10., 20., 12., 22., 14., 24., 16.,
24693        );
24694        assert_eq_m256h(r, e);
24695    }
24696
24697    #[simd_test(enable = "avx512fp16,avx512vl")]
24698    fn test_mm512_maskz_cvtepi32_ph() {
24699        let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
24700        let r = _mm512_maskz_cvtepi32_ph(0b0101010101010101, a);
24701        let e = _mm256_set_ph(
24702            0.0, 2.0, 0.0, 4.0, 0.0, 6.0, 0.0, 8.0, 0.0, 10.0, 0.0, 12.0, 0.0, 14.0, 0.0, 16.0,
24703        );
24704        assert_eq_m256h(r, e);
24705    }
24706
24707    #[simd_test(enable = "avx512fp16,avx512vl")]
24708    fn test_mm512_cvt_roundepi32_ph() {
24709        let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
24710        let r = _mm512_cvt_roundepi32_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
24711        let e = _mm256_set_ph(
24712            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
24713        );
24714        assert_eq_m256h(r, e);
24715    }
24716
24717    #[simd_test(enable = "avx512fp16,avx512vl")]
24718    fn test_mm512_mask_cvt_roundepi32_ph() {
24719        let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
24720        let src = _mm256_set_ph(
24721            10., 11., 12., 13., 14., 15., 16., 17., 18., 19., 20., 21., 22., 23., 24., 25.,
24722        );
24723        let r = _mm512_mask_cvt_roundepi32_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
24724            src,
24725            0b0101010101010101,
24726            a,
24727        );
24728        let e = _mm256_set_ph(
24729            10., 2., 12., 4., 14., 6., 16., 8., 18., 10., 20., 12., 22., 14., 24., 16.,
24730        );
24731        assert_eq_m256h(r, e);
24732    }
24733
24734    #[simd_test(enable = "avx512fp16,avx512vl")]
24735    fn test_mm512_maskz_cvt_roundepi32_ph() {
24736        let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
24737        let r = _mm512_maskz_cvt_roundepi32_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
24738            0b0101010101010101,
24739            a,
24740        );
24741        let e = _mm256_set_ph(
24742            0.0, 2.0, 0.0, 4.0, 0.0, 6.0, 0.0, 8.0, 0.0, 10.0, 0.0, 12.0, 0.0, 14.0, 0.0, 16.0,
24743        );
24744        assert_eq_m256h(r, e);
24745    }
24746
24747    #[simd_test(enable = "avx512fp16,avx512vl")]
24748    fn test_mm_cvti32_sh() {
24749        let a = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
24750        let r = _mm_cvti32_sh(a, 10);
24751        let e = _mm_setr_ph(10.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
24752        assert_eq_m128h(r, e);
24753    }
24754
24755    #[simd_test(enable = "avx512fp16,avx512vl")]
24756    fn test_mm_cvt_roundi32_sh() {
24757        let a = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
24758        let r = _mm_cvt_roundi32_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, 10);
24759        let e = _mm_setr_ph(10.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
24760        assert_eq_m128h(r, e);
24761    }
24762
24763    #[simd_test(enable = "avx512fp16,avx512vl")]
24764    fn test_mm_cvtepu32_ph() {
24765        let a = _mm_set_epi32(1, 2, 3, 4);
24766        let r = _mm_cvtepu32_ph(a);
24767        let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
24768        assert_eq_m128h(r, e);
24769    }
24770
24771    #[simd_test(enable = "avx512fp16,avx512vl")]
24772    fn test_mm_mask_cvtepu32_ph() {
24773        let a = _mm_set_epi32(1, 2, 3, 4);
24774        let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
24775        let r = _mm_mask_cvtepu32_ph(src, 0b0101, a);
24776        let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 14., 2., 16., 4.);
24777        assert_eq_m128h(r, e);
24778    }
24779
24780    #[simd_test(enable = "avx512fp16,avx512vl")]
24781    fn test_mm_maskz_cvtepu32_ph() {
24782        let a = _mm_set_epi32(1, 2, 3, 4);
24783        let r = _mm_maskz_cvtepu32_ph(0b0101, a);
24784        let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 2., 0.0, 4.);
24785        assert_eq_m128h(r, e);
24786    }
24787
24788    #[simd_test(enable = "avx512fp16,avx512vl")]
24789    fn test_mm256_cvtepu32_ph() {
24790        let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
24791        let r = _mm256_cvtepu32_ph(a);
24792        let e = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
24793        assert_eq_m128h(r, e);
24794    }
24795
24796    #[simd_test(enable = "avx512fp16,avx512vl")]
24797    fn test_mm256_mask_cvtepu32_ph() {
24798        let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
24799        let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
24800        let r = _mm256_mask_cvtepu32_ph(src, 0b01010101, a);
24801        let e = _mm_set_ph(10., 2., 12., 4., 14., 6., 16., 8.);
24802        assert_eq_m128h(r, e);
24803    }
24804
24805    #[simd_test(enable = "avx512fp16,avx512vl")]
24806    fn test_mm256_maskz_cvtepu32_ph() {
24807        let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
24808        let r = _mm256_maskz_cvtepu32_ph(0b01010101, a);
24809        let e = _mm_set_ph(0.0, 2.0, 0.0, 4.0, 0.0, 6.0, 0.0, 8.0);
24810        assert_eq_m128h(r, e);
24811    }
24812
24813    #[simd_test(enable = "avx512fp16,avx512vl")]
24814    fn test_mm512_cvtepu32_ph() {
24815        let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
24816        let r = _mm512_cvtepu32_ph(a);
24817        let e = _mm256_set_ph(
24818            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
24819        );
24820        assert_eq_m256h(r, e);
24821    }
24822
24823    #[simd_test(enable = "avx512fp16,avx512vl")]
24824    fn test_mm512_mask_cvtepu32_ph() {
24825        let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
24826        let src = _mm256_set_ph(
24827            10., 11., 12., 13., 14., 15., 16., 17., 18., 19., 20., 21., 22., 23., 24., 25.,
24828        );
24829        let r = _mm512_mask_cvtepu32_ph(src, 0b0101010101010101, a);
24830        let e = _mm256_set_ph(
24831            10., 2.0, 12., 4.0, 14., 6.0, 16., 8.0, 18., 10.0, 20., 12.0, 22., 14.0, 24., 16.0,
24832        );
24833        assert_eq_m256h(r, e);
24834    }
24835
24836    #[simd_test(enable = "avx512fp16,avx512vl")]
24837    fn test_mm512_maskz_cvtepu32_ph() {
24838        let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
24839        let r = _mm512_maskz_cvtepu32_ph(0b0101010101010101, a);
24840        let e = _mm256_set_ph(
24841            0.0, 2.0, 0.0, 4.0, 0.0, 6.0, 0.0, 8.0, 0.0, 10.0, 0.0, 12.0, 0.0, 14.0, 0.0, 16.0,
24842        );
24843        assert_eq_m256h(r, e);
24844    }
24845
24846    #[simd_test(enable = "avx512fp16,avx512vl")]
24847    fn test_mm512_cvt_roundepu32_ph() {
24848        let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
24849        let r = _mm512_cvt_roundepu32_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
24850        let e = _mm256_set_ph(
24851            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
24852        );
24853        assert_eq_m256h(r, e);
24854    }
24855
24856    #[simd_test(enable = "avx512fp16,avx512vl")]
24857    fn test_mm512_mask_cvt_roundepu32_ph() {
24858        let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
24859        let src = _mm256_set_ph(
24860            10., 11., 12., 13., 14., 15., 16., 17., 18., 19., 20., 21., 22., 23., 24., 25.,
24861        );
24862        let r = _mm512_mask_cvt_roundepu32_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
24863            src,
24864            0b0101010101010101,
24865            a,
24866        );
24867        let e = _mm256_set_ph(
24868            10.0, 2.0, 12.0, 4.0, 14.0, 6.0, 16.0, 8.0, 18.0, 10.0, 20.0, 12.0, 22.0, 14.0, 24.0,
24869            16.0,
24870        );
24871        assert_eq_m256h(r, e);
24872    }
24873
24874    #[simd_test(enable = "avx512fp16,avx512vl")]
24875    fn test_mm512_maskz_cvt_roundepu32_ph() {
24876        let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
24877        let r = _mm512_maskz_cvt_roundepu32_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
24878            0b0101010101010101,
24879            a,
24880        );
24881        let e = _mm256_set_ph(
24882            0.0, 2.0, 0.0, 4.0, 0.0, 6.0, 0.0, 8.0, 0.0, 10.0, 0.0, 12.0, 0.0, 14.0, 0.0, 16.0,
24883        );
24884        assert_eq_m256h(r, e);
24885    }
24886
24887    #[simd_test(enable = "avx512fp16,avx512vl")]
24888    fn test_mm_cvtu32_sh() {
24889        let a = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
24890        let r = _mm_cvtu32_sh(a, 10);
24891        let e = _mm_setr_ph(10.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
24892        assert_eq_m128h(r, e);
24893    }
24894
24895    #[simd_test(enable = "avx512fp16,avx512vl")]
24896    fn test_mm_cvt_roundu32_sh() {
24897        let a = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
24898        let r = _mm_cvt_roundu32_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, 10);
24899        let e = _mm_setr_ph(10.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
24900        assert_eq_m128h(r, e);
24901    }
24902
24903    #[simd_test(enable = "avx512fp16,avx512vl")]
24904    fn test_mm_cvtepi64_ph() {
24905        let a = _mm_set_epi64x(1, 2);
24906        let r = _mm_cvtepi64_ph(a);
24907        let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0, 2.0);
24908        assert_eq_m128h(r, e);
24909    }
24910
24911    #[simd_test(enable = "avx512fp16,avx512vl")]
24912    fn test_mm_mask_cvtepi64_ph() {
24913        let a = _mm_set_epi64x(1, 2);
24914        let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
24915        let r = _mm_mask_cvtepi64_ph(src, 0b01, a);
24916        let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 16., 2.);
24917        assert_eq_m128h(r, e);
24918    }
24919
24920    #[simd_test(enable = "avx512fp16,avx512vl")]
24921    fn test_mm_maskz_cvtepi64_ph() {
24922        let a = _mm_set_epi64x(1, 2);
24923        let r = _mm_maskz_cvtepi64_ph(0b01, a);
24924        let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 2.);
24925        assert_eq_m128h(r, e);
24926    }
24927
24928    #[simd_test(enable = "avx512fp16,avx512vl")]
24929    fn test_mm256_cvtepi64_ph() {
24930        let a = _mm256_set_epi64x(1, 2, 3, 4);
24931        let r = _mm256_cvtepi64_ph(a);
24932        let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
24933        assert_eq_m128h(r, e);
24934    }
24935
24936    #[simd_test(enable = "avx512fp16,avx512vl")]
24937    fn test_mm256_mask_cvtepi64_ph() {
24938        let a = _mm256_set_epi64x(1, 2, 3, 4);
24939        let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
24940        let r = _mm256_mask_cvtepi64_ph(src, 0b0101, a);
24941        let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 14., 2.0, 16.0, 4.0);
24942        assert_eq_m128h(r, e);
24943    }
24944
24945    #[simd_test(enable = "avx512fp16,avx512vl")]
24946    fn test_mm256_maskz_cvtepi64_ph() {
24947        let a = _mm256_set_epi64x(1, 2, 3, 4);
24948        let r = _mm256_maskz_cvtepi64_ph(0b0101, a);
24949        let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 2.0, 0.0, 4.0);
24950        assert_eq_m128h(r, e);
24951    }
24952
24953    #[simd_test(enable = "avx512fp16,avx512vl")]
24954    fn test_mm512_cvtepi64_ph() {
24955        let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
24956        let r = _mm512_cvtepi64_ph(a);
24957        let e = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
24958        assert_eq_m128h(r, e);
24959    }
24960
24961    #[simd_test(enable = "avx512fp16,avx512vl")]
24962    fn test_mm512_mask_cvtepi64_ph() {
24963        let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
24964        let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
24965        let r = _mm512_mask_cvtepi64_ph(src, 0b01010101, a);
24966        let e = _mm_set_ph(10., 2., 12., 4., 14., 6., 16., 8.);
24967        assert_eq_m128h(r, e);
24968    }
24969
24970    #[simd_test(enable = "avx512fp16,avx512vl")]
24971    fn test_mm512_maskz_cvtepi64_ph() {
24972        let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
24973        let r = _mm512_maskz_cvtepi64_ph(0b01010101, a);
24974        let e = _mm_set_ph(0.0, 2., 0.0, 4., 0.0, 6., 0.0, 8.);
24975        assert_eq_m128h(r, e);
24976    }
24977
24978    #[simd_test(enable = "avx512fp16,avx512vl")]
24979    fn test_mm512_cvt_roundepi64_ph() {
24980        let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
24981        let r = _mm512_cvt_roundepi64_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
24982        let e = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
24983        assert_eq_m128h(r, e);
24984    }
24985
24986    #[simd_test(enable = "avx512fp16")]
24987    fn test_mm512_mask_cvt_roundepi64_ph() {
24988        let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
24989        let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
24990        let r = _mm512_mask_cvt_roundepi64_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
24991            src, 0b01010101, a,
24992        );
24993        let e = _mm_set_ph(10., 2., 12., 4., 14., 6., 16., 8.);
24994        assert_eq_m128h(r, e);
24995    }
24996
24997    #[simd_test(enable = "avx512fp16,avx512vl")]
24998    fn test_mm512_maskz_cvt_roundepi64_ph() {
24999        let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
25000        let r = _mm512_maskz_cvt_roundepi64_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
25001            0b01010101, a,
25002        );
25003        let e = _mm_set_ph(0.0, 2., 0.0, 4., 0.0, 6., 0.0, 8.);
25004        assert_eq_m128h(r, e);
25005    }
25006
25007    #[simd_test(enable = "avx512fp16,avx512vl")]
25008    fn test_mm_cvtepu64_ph() {
25009        let a = _mm_set_epi64x(1, 2);
25010        let r = _mm_cvtepu64_ph(a);
25011        let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0, 2.0);
25012        assert_eq_m128h(r, e);
25013    }
25014
25015    #[simd_test(enable = "avx512fp16,avx512vl")]
25016    fn test_mm_mask_cvtepu64_ph() {
25017        let a = _mm_set_epi64x(1, 2);
25018        let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
25019        let r = _mm_mask_cvtepu64_ph(src, 0b01, a);
25020        let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 16., 2.);
25021        assert_eq_m128h(r, e);
25022    }
25023
25024    #[simd_test(enable = "avx512fp16,avx512vl")]
25025    fn test_mm_maskz_cvtepu64_ph() {
25026        let a = _mm_set_epi64x(1, 2);
25027        let r = _mm_maskz_cvtepu64_ph(0b01, a);
25028        let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 2.0);
25029        assert_eq_m128h(r, e);
25030    }
25031
25032    #[simd_test(enable = "avx512fp16,avx512vl")]
25033    fn test_mm256_cvtepu64_ph() {
25034        let a = _mm256_set_epi64x(1, 2, 3, 4);
25035        let r = _mm256_cvtepu64_ph(a);
25036        let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
25037        assert_eq_m128h(r, e);
25038    }
25039
25040    #[simd_test(enable = "avx512fp16,avx512vl")]
25041    fn test_mm256_mask_cvtepu64_ph() {
25042        let a = _mm256_set_epi64x(1, 2, 3, 4);
25043        let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
25044        let r = _mm256_mask_cvtepu64_ph(src, 0b0101, a);
25045        let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 14., 2.0, 16.0, 4.0);
25046        assert_eq_m128h(r, e);
25047    }
25048
25049    #[simd_test(enable = "avx512fp16,avx512vl")]
25050    fn test_mm256_maskz_cvtepu64_ph() {
25051        let a = _mm256_set_epi64x(1, 2, 3, 4);
25052        let r = _mm256_maskz_cvtepu64_ph(0b0101, a);
25053        let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 2.0, 0.0, 4.0);
25054        assert_eq_m128h(r, e);
25055    }
25056
25057    #[simd_test(enable = "avx512fp16,avx512vl")]
25058    fn test_mm512_cvtepu64_ph() {
25059        let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
25060        let r = _mm512_cvtepu64_ph(a);
25061        let e = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
25062        assert_eq_m128h(r, e);
25063    }
25064
25065    #[simd_test(enable = "avx512fp16,avx512vl")]
25066    fn test_mm512_mask_cvtepu64_ph() {
25067        let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
25068        let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
25069        let r = _mm512_mask_cvtepu64_ph(src, 0b01010101, a);
25070        let e = _mm_set_ph(10., 2., 12., 4., 14., 6., 16., 8.);
25071        assert_eq_m128h(r, e);
25072    }
25073
25074    #[simd_test(enable = "avx512fp16,avx512vl")]
25075    fn test_mm512_maskz_cvtepu64_ph() {
25076        let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
25077        let r = _mm512_maskz_cvtepu64_ph(0b01010101, a);
25078        let e = _mm_set_ph(0.0, 2., 0.0, 4., 0.0, 6., 0.0, 8.);
25079        assert_eq_m128h(r, e);
25080    }
25081
25082    #[simd_test(enable = "avx512fp16,avx512vl")]
25083    fn test_mm512_cvt_roundepu64_ph() {
25084        let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
25085        let r = _mm512_cvt_roundepu64_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
25086        let e = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
25087        assert_eq_m128h(r, e);
25088    }
25089
25090    #[simd_test(enable = "avx512fp16,avx512vl")]
25091    fn test_mm512_mask_cvt_roundepu64_ph() {
25092        let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
25093        let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
25094        let r = _mm512_mask_cvt_roundepu64_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
25095            src, 0b01010101, a,
25096        );
25097        let e = _mm_set_ph(10., 2., 12., 4., 14., 6., 16., 8.);
25098        assert_eq_m128h(r, e);
25099    }
25100
25101    #[simd_test(enable = "avx512fp16,avx512vl")]
25102    fn test_mm512_maskz_cvt_roundepu64_ph() {
25103        let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
25104        let r = _mm512_maskz_cvt_roundepu64_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
25105            0b01010101, a,
25106        );
25107        let e = _mm_set_ph(0.0, 2., 0.0, 4., 0.0, 6., 0.0, 8.);
25108        assert_eq_m128h(r, e);
25109    }
25110
25111    #[simd_test(enable = "avx512fp16,avx512vl")]
25112    fn test_mm_cvtxps_ph() {
25113        let a = _mm_set_ps(1.0, 2.0, 3.0, 4.0);
25114        let r = _mm_cvtxps_ph(a);
25115        let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
25116        assert_eq_m128h(r, e);
25117    }
25118
25119    #[simd_test(enable = "avx512fp16,avx512vl")]
25120    fn test_mm_mask_cvtxps_ph() {
25121        let a = _mm_set_ps(1.0, 2.0, 3.0, 4.0);
25122        let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
25123        let r = _mm_mask_cvtxps_ph(src, 0b0101, a);
25124        let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 14., 2.0, 16., 4.0);
25125        assert_eq_m128h(r, e);
25126    }
25127
25128    #[simd_test(enable = "avx512fp16,avx512vl")]
25129    fn test_mm_maskz_cvtxps_ph() {
25130        let a = _mm_set_ps(1.0, 2.0, 3.0, 4.0);
25131        let r = _mm_maskz_cvtxps_ph(0b0101, a);
25132        let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 2.0, 0.0, 4.0);
25133        assert_eq_m128h(r, e);
25134    }
25135
25136    #[simd_test(enable = "avx512fp16,avx512vl")]
25137    fn test_mm256_cvtxps_ph() {
25138        let a = _mm256_set_ps(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
25139        let r = _mm256_cvtxps_ph(a);
25140        let e = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
25141        assert_eq_m128h(r, e);
25142    }
25143
25144    #[simd_test(enable = "avx512fp16,avx512vl")]
25145    fn test_mm256_mask_cvtxps_ph() {
25146        let a = _mm256_set_ps(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
25147        let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
25148        let r = _mm256_mask_cvtxps_ph(src, 0b01010101, a);
25149        let e = _mm_set_ph(10., 2., 12., 4., 14., 6., 16., 8.);
25150        assert_eq_m128h(r, e);
25151    }
25152
25153    #[simd_test(enable = "avx512fp16,avx512vl")]
25154    fn test_mm256_maskz_cvtxps_ph() {
25155        let a = _mm256_set_ps(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
25156        let r = _mm256_maskz_cvtxps_ph(0b01010101, a);
25157        let e = _mm_set_ph(0.0, 2.0, 0.0, 4.0, 0.0, 6.0, 0.0, 8.0);
25158        assert_eq_m128h(r, e);
25159    }
25160
25161    #[simd_test(enable = "avx512fp16,avx512vl")]
25162    fn test_mm512_cvtxps_ph() {
25163        let a = _mm512_set_ps(
25164            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
25165        );
25166        let r = _mm512_cvtxps_ph(a);
25167        let e = _mm256_set_ph(
25168            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
25169        );
25170        assert_eq_m256h(r, e);
25171    }
25172
25173    #[simd_test(enable = "avx512fp16,avx512vl")]
25174    fn test_mm512_mask_cvtxps_ph() {
25175        let a = _mm512_set_ps(
25176            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
25177        );
25178        let src = _mm256_set_ph(
25179            10., 11., 12., 13., 14., 15., 16., 17., 18., 19., 20., 21., 22., 23., 24., 25.,
25180        );
25181        let r = _mm512_mask_cvtxps_ph(src, 0b0101010101010101, a);
25182        let e = _mm256_set_ph(
25183            10., 2.0, 12., 4.0, 14., 6.0, 16., 8.0, 18., 10.0, 20., 12.0, 22., 14.0, 24., 16.0,
25184        );
25185        assert_eq_m256h(r, e);
25186    }
25187
25188    #[simd_test(enable = "avx512fp16,avx512vl")]
25189    fn test_mm512_maskz_cvtxps_ph() {
25190        let a = _mm512_set_ps(
25191            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
25192        );
25193        let r = _mm512_maskz_cvtxps_ph(0b0101010101010101, a);
25194        let e = _mm256_set_ph(
25195            0.0, 2.0, 0.0, 4.0, 0.0, 6.0, 0.0, 8.0, 0.0, 10.0, 0.0, 12.0, 0.0, 14.0, 0.0, 16.0,
25196        );
25197        assert_eq_m256h(r, e);
25198    }
25199
25200    #[simd_test(enable = "avx512fp16,avx512vl")]
25201    fn test_mm512_cvtx_roundps_ph() {
25202        let a = _mm512_set_ps(
25203            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
25204        );
25205        let r = _mm512_cvtx_roundps_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
25206        let e = _mm256_set_ph(
25207            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
25208        );
25209        assert_eq_m256h(r, e);
25210    }
25211
25212    #[simd_test(enable = "avx512fp16,avx512vl")]
25213    fn test_mm512_mask_cvtx_roundps_ph() {
25214        let a = _mm512_set_ps(
25215            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
25216        );
25217        let src = _mm256_set_ph(
25218            10., 11., 12., 13., 14., 15., 16., 17., 18., 19., 20., 21., 22., 23., 24., 25.,
25219        );
25220        let r = _mm512_mask_cvtx_roundps_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
25221            src,
25222            0b0101010101010101,
25223            a,
25224        );
25225        let e = _mm256_set_ph(
25226            10.0, 2.0, 12.0, 4.0, 14.0, 6.0, 16.0, 8.0, 18.0, 10.0, 20.0, 12.0, 22.0, 14.0, 24.0,
25227            16.0,
25228        );
25229        assert_eq_m256h(r, e);
25230    }
25231
25232    #[simd_test(enable = "avx512fp16,avx512vl")]
25233    fn test_mm512_maskz_cvtx_roundps_ph() {
25234        let a = _mm512_set_ps(
25235            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
25236        );
25237        let r = _mm512_maskz_cvtx_roundps_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
25238            0b0101010101010101,
25239            a,
25240        );
25241        let e = _mm256_set_ph(
25242            0.0, 2.0, 0.0, 4.0, 0.0, 6.0, 0.0, 8.0, 0.0, 10.0, 0.0, 12.0, 0.0, 14.0, 0.0, 16.0,
25243        );
25244        assert_eq_m256h(r, e);
25245    }
25246
25247    #[simd_test(enable = "avx512fp16,avx512vl")]
25248    fn test_mm_cvtss_sh() {
25249        let a = _mm_setr_ph(10., 11., 12., 13., 14., 15., 16., 17.);
25250        let b = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
25251        let r = _mm_cvtss_sh(a, b);
25252        let e = _mm_setr_ph(1.0, 11., 12., 13., 14., 15., 16., 17.);
25253        assert_eq_m128h(r, e);
25254    }
25255
25256    #[simd_test(enable = "avx512fp16,avx512vl")]
25257    fn test_mm_mask_cvtss_sh() {
25258        let a = _mm_setr_ph(10., 11., 12., 13., 14., 15., 16., 17.);
25259        let b = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
25260        let src = _mm_setr_ph(20., 21., 22., 23., 24., 25., 26., 27.);
25261        let r = _mm_mask_cvtss_sh(src, 0, a, b);
25262        let e = _mm_setr_ph(20., 11., 12., 13., 14., 15., 16., 17.);
25263        assert_eq_m128h(r, e);
25264        let r = _mm_mask_cvtss_sh(src, 1, a, b);
25265        let e = _mm_setr_ph(1.0, 11., 12., 13., 14., 15., 16., 17.);
25266        assert_eq_m128h(r, e);
25267    }
25268
25269    #[simd_test(enable = "avx512fp16,avx512vl")]
25270    fn test_mm_maskz_cvtss_sh() {
25271        let a = _mm_setr_ph(10., 11., 12., 13., 14., 15., 16., 17.);
25272        let b = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
25273        let r = _mm_maskz_cvtss_sh(0, a, b);
25274        let e = _mm_setr_ph(0.0, 11., 12., 13., 14., 15., 16., 17.);
25275        assert_eq_m128h(r, e);
25276        let r = _mm_maskz_cvtss_sh(1, a, b);
25277        let e = _mm_setr_ph(1.0, 11., 12., 13., 14., 15., 16., 17.);
25278        assert_eq_m128h(r, e);
25279    }
25280
25281    #[simd_test(enable = "avx512fp16,avx512vl")]
25282    fn test_mm_cvt_roundss_sh() {
25283        let a = _mm_setr_ph(10., 11., 12., 13., 14., 15., 16., 17.);
25284        let b = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
25285        let r = _mm_cvt_roundss_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
25286        let e = _mm_setr_ph(1.0, 11., 12., 13., 14., 15., 16., 17.);
25287        assert_eq_m128h(r, e);
25288    }
25289
25290    #[simd_test(enable = "avx512fp16,avx512vl")]
25291    fn test_mm_mask_cvt_roundss_sh() {
25292        let a = _mm_setr_ph(10., 11., 12., 13., 14., 15., 16., 17.);
25293        let b = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
25294        let src = _mm_setr_ph(20., 21., 22., 23., 24., 25., 26., 27.);
25295        let r = _mm_mask_cvt_roundss_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
25296            src, 0, a, b,
25297        );
25298        let e = _mm_setr_ph(20., 11., 12., 13., 14., 15., 16., 17.);
25299        assert_eq_m128h(r, e);
25300        let r = _mm_mask_cvt_roundss_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
25301            src, 1, a, b,
25302        );
25303        let e = _mm_setr_ph(1.0, 11., 12., 13., 14., 15., 16., 17.);
25304        assert_eq_m128h(r, e);
25305    }
25306
25307    #[simd_test(enable = "avx512fp16,avx512vl")]
25308    fn test_mm_maskz_cvt_roundss_sh() {
25309        let a = _mm_setr_ph(10., 11., 12., 13., 14., 15., 16., 17.);
25310        let b = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
25311        let r =
25312            _mm_maskz_cvt_roundss_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
25313        let e = _mm_setr_ph(0.0, 11., 12., 13., 14., 15., 16., 17.);
25314        assert_eq_m128h(r, e);
25315        let r =
25316            _mm_maskz_cvt_roundss_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(1, a, b);
25317        let e = _mm_setr_ph(1.0, 11., 12., 13., 14., 15., 16., 17.);
25318        assert_eq_m128h(r, e);
25319    }
25320
25321    #[simd_test(enable = "avx512fp16,avx512vl")]
25322    fn test_mm_cvtpd_ph() {
25323        let a = _mm_set_pd(1.0, 2.0);
25324        let r = _mm_cvtpd_ph(a);
25325        let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0, 2.0);
25326        assert_eq_m128h(r, e);
25327    }
25328
25329    #[simd_test(enable = "avx512fp16,avx512vl")]
25330    fn test_mm_mask_cvtpd_ph() {
25331        let a = _mm_set_pd(1.0, 2.0);
25332        let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
25333        let r = _mm_mask_cvtpd_ph(src, 0b01, a);
25334        let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 16., 2.);
25335        assert_eq_m128h(r, e);
25336    }
25337
25338    #[simd_test(enable = "avx512fp16,avx512vl")]
25339    fn test_mm_maskz_cvtpd_ph() {
25340        let a = _mm_set_pd(1.0, 2.0);
25341        let r = _mm_maskz_cvtpd_ph(0b01, a);
25342        let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 2.0);
25343        assert_eq_m128h(r, e);
25344    }
25345
25346    #[simd_test(enable = "avx512fp16,avx512vl")]
25347    fn test_mm256_cvtpd_ph() {
25348        let a = _mm256_set_pd(1.0, 2.0, 3.0, 4.0);
25349        let r = _mm256_cvtpd_ph(a);
25350        let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
25351        assert_eq_m128h(r, e);
25352    }
25353
25354    #[simd_test(enable = "avx512fp16,avx512vl")]
25355    fn test_mm256_mask_cvtpd_ph() {
25356        let a = _mm256_set_pd(1.0, 2.0, 3.0, 4.0);
25357        let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
25358        let r = _mm256_mask_cvtpd_ph(src, 0b0101, a);
25359        let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 14., 2.0, 16.0, 4.0);
25360        assert_eq_m128h(r, e);
25361    }
25362
25363    #[simd_test(enable = "avx512fp16,avx512vl")]
25364    fn test_mm256_maskz_cvtpd_ph() {
25365        let a = _mm256_set_pd(1.0, 2.0, 3.0, 4.0);
25366        let r = _mm256_maskz_cvtpd_ph(0b0101, a);
25367        let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 2.0, 0.0, 4.0);
25368        assert_eq_m128h(r, e);
25369    }
25370
25371    #[simd_test(enable = "avx512fp16,avx512vl")]
25372    fn test_mm512_cvtpd_ph() {
25373        let a = _mm512_set_pd(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
25374        let r = _mm512_cvtpd_ph(a);
25375        let e = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
25376        assert_eq_m128h(r, e);
25377    }
25378
25379    #[simd_test(enable = "avx512fp16,avx512vl")]
25380    fn test_mm512_mask_cvtpd_ph() {
25381        let a = _mm512_set_pd(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
25382        let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
25383        let r = _mm512_mask_cvtpd_ph(src, 0b01010101, a);
25384        let e = _mm_set_ph(10., 2., 12., 4., 14., 6., 16., 8.);
25385        assert_eq_m128h(r, e);
25386    }
25387
25388    #[simd_test(enable = "avx512fp16,avx512vl")]
25389    fn test_mm512_maskz_cvtpd_ph() {
25390        let a = _mm512_set_pd(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
25391        let r = _mm512_maskz_cvtpd_ph(0b01010101, a);
25392        let e = _mm_set_ph(0.0, 2., 0.0, 4., 0.0, 6., 0.0, 8.);
25393        assert_eq_m128h(r, e);
25394    }
25395
25396    #[simd_test(enable = "avx512fp16,avx512vl")]
25397    fn test_mm512_cvt_roundpd_ph() {
25398        let a = _mm512_set_pd(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
25399        let r = _mm512_cvt_roundpd_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
25400        let e = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
25401        assert_eq_m128h(r, e);
25402    }
25403
25404    #[simd_test(enable = "avx512fp16,avx512vl")]
25405    fn test_mm512_mask_cvt_roundpd_ph() {
25406        let a = _mm512_set_pd(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
25407        let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
25408        let r = _mm512_mask_cvt_roundpd_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
25409            src, 0b01010101, a,
25410        );
25411        let e = _mm_set_ph(10., 2., 12., 4., 14., 6., 16., 8.);
25412        assert_eq_m128h(r, e);
25413    }
25414
25415    #[simd_test(enable = "avx512fp16,avx512vl")]
25416    fn test_mm512_maskz_cvt_roundpd_ph() {
25417        let a = _mm512_set_pd(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
25418        let r = _mm512_maskz_cvt_roundpd_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
25419            0b01010101, a,
25420        );
25421        let e = _mm_set_ph(0.0, 2., 0.0, 4., 0.0, 6., 0.0, 8.);
25422        assert_eq_m128h(r, e);
25423    }
25424
25425    #[simd_test(enable = "avx512fp16,avx512vl")]
25426    fn test_mm_cvtsd_sh() {
25427        let a = _mm_setr_ph(10., 11., 12., 13., 14., 15., 16., 17.);
25428        let b = _mm_setr_pd(1.0, 2.0);
25429        let r = _mm_cvtsd_sh(a, b);
25430        let e = _mm_setr_ph(1.0, 11., 12., 13., 14., 15., 16., 17.);
25431        assert_eq_m128h(r, e);
25432    }
25433
25434    #[simd_test(enable = "avx512fp16,avx512vl")]
25435    fn test_mm_mask_cvtsd_sh() {
25436        let a = _mm_setr_ph(10., 11., 12., 13., 14., 15., 16., 17.);
25437        let b = _mm_setr_pd(1.0, 2.0);
25438        let src = _mm_setr_ph(20., 21., 22., 23., 24., 25., 26., 27.);
25439        let r = _mm_mask_cvtsd_sh(src, 0, a, b);
25440        let e = _mm_setr_ph(20., 11., 12., 13., 14., 15., 16., 17.);
25441        assert_eq_m128h(r, e);
25442        let r = _mm_mask_cvtsd_sh(src, 1, a, b);
25443        let e = _mm_setr_ph(1.0, 11., 12., 13., 14., 15., 16., 17.);
25444        assert_eq_m128h(r, e);
25445    }
25446
25447    #[simd_test(enable = "avx512fp16,avx512vl")]
25448    fn test_mm_maskz_cvtsd_sh() {
25449        let a = _mm_setr_ph(10., 11., 12., 13., 14., 15., 16., 17.);
25450        let b = _mm_setr_pd(1.0, 2.0);
25451        let r = _mm_maskz_cvtsd_sh(0, a, b);
25452        let e = _mm_setr_ph(0.0, 11., 12., 13., 14., 15., 16., 17.);
25453        assert_eq_m128h(r, e);
25454        let r = _mm_maskz_cvtsd_sh(1, a, b);
25455        let e = _mm_setr_ph(1.0, 11., 12., 13., 14., 15., 16., 17.);
25456        assert_eq_m128h(r, e);
25457    }
25458
25459    #[simd_test(enable = "avx512fp16,avx512vl")]
25460    fn test_mm_cvt_roundsd_sh() {
25461        let a = _mm_setr_ph(10., 11., 12., 13., 14., 15., 16., 17.);
25462        let b = _mm_setr_pd(1.0, 2.0);
25463        let r = _mm_cvt_roundsd_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
25464        let e = _mm_setr_ph(1.0, 11., 12., 13., 14., 15., 16., 17.);
25465        assert_eq_m128h(r, e);
25466    }
25467
25468    #[simd_test(enable = "avx512fp16,avx512vl")]
25469    fn test_mm_mask_cvt_roundsd_sh() {
25470        let a = _mm_setr_ph(10., 11., 12., 13., 14., 15., 16., 17.);
25471        let b = _mm_setr_pd(1.0, 2.0);
25472        let src = _mm_setr_ph(20., 21., 22., 23., 24., 25., 26., 27.);
25473        let r = _mm_mask_cvt_roundsd_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
25474            src, 0, a, b,
25475        );
25476        let e = _mm_setr_ph(20., 11., 12., 13., 14., 15., 16., 17.);
25477        assert_eq_m128h(r, e);
25478        let r = _mm_mask_cvt_roundsd_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
25479            src, 1, a, b,
25480        );
25481        let e = _mm_setr_ph(1.0, 11., 12., 13., 14., 15., 16., 17.);
25482        assert_eq_m128h(r, e);
25483    }
25484
25485    #[simd_test(enable = "avx512fp16,avx512vl")]
25486    fn test_mm_maskz_cvt_roundsd_sh() {
25487        let a = _mm_setr_ph(10., 11., 12., 13., 14., 15., 16., 17.);
25488        let b = _mm_setr_pd(1.0, 2.0);
25489        let r =
25490            _mm_maskz_cvt_roundsd_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
25491        let e = _mm_setr_ph(0.0, 11., 12., 13., 14., 15., 16., 17.);
25492        assert_eq_m128h(r, e);
25493        let r =
25494            _mm_maskz_cvt_roundsd_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(1, a, b);
25495        let e = _mm_setr_ph(1.0, 11., 12., 13., 14., 15., 16., 17.);
25496        assert_eq_m128h(r, e);
25497    }
25498
25499    #[simd_test(enable = "avx512fp16,avx512vl")]
25500    fn test_mm_cvtph_epi16() {
25501        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
25502        let r = _mm_cvttph_epi16(a);
25503        let e = _mm_set_epi16(1, 2, 3, 4, 5, 6, 7, 8);
25504        assert_eq_m128i(r, e);
25505    }
25506
25507    #[simd_test(enable = "avx512fp16,avx512vl")]
25508    fn test_mm_mask_cvtph_epi16() {
25509        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
25510        let src = _mm_set_epi16(10, 11, 12, 13, 14, 15, 16, 17);
25511        let r = _mm_mask_cvttph_epi16(src, 0b01010101, a);
25512        let e = _mm_set_epi16(10, 2, 12, 4, 14, 6, 16, 8);
25513        assert_eq_m128i(r, e);
25514    }
25515
25516    #[simd_test(enable = "avx512fp16,avx512vl")]
25517    fn test_mm_maskz_cvtph_epi16() {
25518        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
25519        let r = _mm_maskz_cvttph_epi16(0b01010101, a);
25520        let e = _mm_set_epi16(0, 2, 0, 4, 0, 6, 0, 8);
25521        assert_eq_m128i(r, e);
25522    }
25523
25524    #[simd_test(enable = "avx512fp16,avx512vl")]
25525    fn test_mm256_cvtph_epi16() {
25526        let a = _mm256_set_ph(
25527            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
25528        );
25529        let r = _mm256_cvttph_epi16(a);
25530        let e = _mm256_set_epi16(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
25531        assert_eq_m256i(r, e);
25532    }
25533
25534    #[simd_test(enable = "avx512fp16,avx512vl")]
25535    fn test_mm256_mask_cvtph_epi16() {
25536        let a = _mm256_set_ph(
25537            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
25538        );
25539        let src = _mm256_set_epi16(
25540            10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25,
25541        );
25542        let r = _mm256_mask_cvttph_epi16(src, 0b0101010101010101, a);
25543        let e = _mm256_set_epi16(10, 2, 12, 4, 14, 6, 16, 8, 18, 10, 20, 12, 22, 14, 24, 16);
25544        assert_eq_m256i(r, e);
25545    }
25546
25547    #[simd_test(enable = "avx512fp16,avx512vl")]
25548    fn test_mm256_maskz_cvtph_epi16() {
25549        let a = _mm256_set_ph(
25550            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
25551        );
25552        let r = _mm256_maskz_cvttph_epi16(0b0101010101010101, a);
25553        let e = _mm256_set_epi16(0, 2, 0, 4, 0, 6, 0, 8, 0, 10, 0, 12, 0, 14, 0, 16);
25554        assert_eq_m256i(r, e);
25555    }
25556
25557    #[simd_test(enable = "avx512fp16")]
25558    fn test_mm512_cvtph_epi16() {
25559        let a = _mm512_set_ph(
25560            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
25561            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
25562            31.0, 32.0,
25563        );
25564        let r = _mm512_cvttph_epi16(a);
25565        let e = _mm512_set_epi16(
25566            1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
25567            25, 26, 27, 28, 29, 30, 31, 32,
25568        );
25569        assert_eq_m512i(r, e);
25570    }
25571
25572    #[simd_test(enable = "avx512fp16")]
25573    fn test_mm512_mask_cvtph_epi16() {
25574        let a = _mm512_set_ph(
25575            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
25576            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
25577            31.0, 32.0,
25578        );
25579        let src = _mm512_set_epi16(
25580            10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
25581            32, 33, 34, 35, 36, 37, 38, 39, 40, 41,
25582        );
25583        let r = _mm512_mask_cvttph_epi16(src, 0b01010101010101010101010101010101, a);
25584        let e = _mm512_set_epi16(
25585            10, 2, 12, 4, 14, 6, 16, 8, 18, 10, 20, 12, 22, 14, 24, 16, 26, 18, 28, 20, 30, 22, 32,
25586            24, 34, 26, 36, 28, 38, 30, 40, 32,
25587        );
25588        assert_eq_m512i(r, e);
25589    }
25590
25591    #[simd_test(enable = "avx512fp16")]
25592    fn test_mm512_maskz_cvtph_epi16() {
25593        let a = _mm512_set_ph(
25594            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
25595            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
25596            31.0, 32.0,
25597        );
25598        let r = _mm512_maskz_cvttph_epi16(0b01010101010101010101010101010101, a);
25599        let e = _mm512_set_epi16(
25600            0, 2, 0, 4, 0, 6, 0, 8, 0, 10, 0, 12, 0, 14, 0, 16, 0, 18, 0, 20, 0, 22, 0, 24, 0, 26,
25601            0, 28, 0, 30, 0, 32,
25602        );
25603        assert_eq_m512i(r, e);
25604    }
25605
25606    #[simd_test(enable = "avx512fp16")]
25607    fn test_mm512_cvt_roundph_epi16() {
25608        let a = _mm512_set_ph(
25609            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
25610            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
25611            31.0, 32.0,
25612        );
25613        let r = _mm512_cvtt_roundph_epi16::<_MM_FROUND_NO_EXC>(a);
25614        let e = _mm512_set_epi16(
25615            1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
25616            25, 26, 27, 28, 29, 30, 31, 32,
25617        );
25618        assert_eq_m512i(r, e);
25619    }
25620
25621    #[simd_test(enable = "avx512fp16")]
25622    fn test_mm512_mask_cvt_roundph_epi16() {
25623        let a = _mm512_set_ph(
25624            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
25625            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
25626            31.0, 32.0,
25627        );
25628        let src = _mm512_set_epi16(
25629            10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
25630            32, 33, 34, 35, 36, 37, 38, 39, 40, 41,
25631        );
25632        let r = _mm512_mask_cvtt_roundph_epi16::<_MM_FROUND_NO_EXC>(
25633            src,
25634            0b01010101010101010101010101010101,
25635            a,
25636        );
25637        let e = _mm512_set_epi16(
25638            10, 2, 12, 4, 14, 6, 16, 8, 18, 10, 20, 12, 22, 14, 24, 16, 26, 18, 28, 20, 30, 22, 32,
25639            24, 34, 26, 36, 28, 38, 30, 40, 32,
25640        );
25641        assert_eq_m512i(r, e);
25642    }
25643
25644    #[simd_test(enable = "avx512fp16")]
25645    fn test_mm512_maskz_cvt_roundph_epi16() {
25646        let a = _mm512_set_ph(
25647            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
25648            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
25649            31.0, 32.0,
25650        );
25651        let r = _mm512_maskz_cvtt_roundph_epi16::<_MM_FROUND_NO_EXC>(
25652            0b01010101010101010101010101010101,
25653            a,
25654        );
25655        let e = _mm512_set_epi16(
25656            0, 2, 0, 4, 0, 6, 0, 8, 0, 10, 0, 12, 0, 14, 0, 16, 0, 18, 0, 20, 0, 22, 0, 24, 0, 26,
25657            0, 28, 0, 30, 0, 32,
25658        );
25659        assert_eq_m512i(r, e);
25660    }
25661
25662    #[simd_test(enable = "avx512fp16,avx512vl")]
25663    fn test_mm_cvtph_epu16() {
25664        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
25665        let r = _mm_cvttph_epu16(a);
25666        let e = _mm_set_epi16(1, 2, 3, 4, 5, 6, 7, 8);
25667        assert_eq_m128i(r, e);
25668    }
25669
25670    #[simd_test(enable = "avx512fp16,avx512vl")]
25671    fn test_mm_mask_cvtph_epu16() {
25672        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
25673        let src = _mm_set_epi16(10, 11, 12, 13, 14, 15, 16, 17);
25674        let r = _mm_mask_cvttph_epu16(src, 0b01010101, a);
25675        let e = _mm_set_epi16(10, 2, 12, 4, 14, 6, 16, 8);
25676        assert_eq_m128i(r, e);
25677    }
25678
25679    #[simd_test(enable = "avx512fp16,avx512vl")]
25680    fn test_mm_maskz_cvtph_epu16() {
25681        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
25682        let r = _mm_maskz_cvttph_epu16(0b01010101, a);
25683        let e = _mm_set_epi16(0, 2, 0, 4, 0, 6, 0, 8);
25684        assert_eq_m128i(r, e);
25685    }
25686
25687    #[simd_test(enable = "avx512fp16,avx512vl")]
25688    fn test_mm256_cvtph_epu16() {
25689        let a = _mm256_set_ph(
25690            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
25691        );
25692        let r = _mm256_cvttph_epu16(a);
25693        let e = _mm256_set_epi16(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
25694        assert_eq_m256i(r, e);
25695    }
25696
25697    #[simd_test(enable = "avx512fp16,avx512vl")]
25698    fn test_mm256_mask_cvtph_epu16() {
25699        let a = _mm256_set_ph(
25700            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
25701        );
25702        let src = _mm256_set_epi16(
25703            10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25,
25704        );
25705        let r = _mm256_mask_cvttph_epu16(src, 0b0101010101010101, a);
25706        let e = _mm256_set_epi16(10, 2, 12, 4, 14, 6, 16, 8, 18, 10, 20, 12, 22, 14, 24, 16);
25707        assert_eq_m256i(r, e);
25708    }
25709
25710    #[simd_test(enable = "avx512fp16,avx512vl")]
25711    fn test_mm256_maskz_cvtph_epu16() {
25712        let a = _mm256_set_ph(
25713            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
25714        );
25715        let r = _mm256_maskz_cvttph_epu16(0b0101010101010101, a);
25716        let e = _mm256_set_epi16(0, 2, 0, 4, 0, 6, 0, 8, 0, 10, 0, 12, 0, 14, 0, 16);
25717        assert_eq_m256i(r, e);
25718    }
25719
25720    #[simd_test(enable = "avx512fp16")]
25721    fn test_mm512_cvtph_epu16() {
25722        let a = _mm512_set_ph(
25723            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
25724            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
25725            31.0, 32.0,
25726        );
25727        let r = _mm512_cvttph_epu16(a);
25728        let e = _mm512_set_epi16(
25729            1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
25730            25, 26, 27, 28, 29, 30, 31, 32,
25731        );
25732        assert_eq_m512i(r, e);
25733    }
25734
25735    #[simd_test(enable = "avx512fp16")]
25736    fn test_mm512_mask_cvtph_epu16() {
25737        let a = _mm512_set_ph(
25738            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
25739            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
25740            31.0, 32.0,
25741        );
25742        let src = _mm512_set_epi16(
25743            10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
25744            32, 33, 34, 35, 36, 37, 38, 39, 40, 41,
25745        );
25746        let r = _mm512_mask_cvttph_epu16(src, 0b01010101010101010101010101010101, a);
25747        let e = _mm512_set_epi16(
25748            10, 2, 12, 4, 14, 6, 16, 8, 18, 10, 20, 12, 22, 14, 24, 16, 26, 18, 28, 20, 30, 22, 32,
25749            24, 34, 26, 36, 28, 38, 30, 40, 32,
25750        );
25751        assert_eq_m512i(r, e);
25752    }
25753
25754    #[simd_test(enable = "avx512fp16")]
25755    fn test_mm512_maskz_cvtph_epu16() {
25756        let a = _mm512_set_ph(
25757            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
25758            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
25759            31.0, 32.0,
25760        );
25761        let r = _mm512_maskz_cvttph_epu16(0b01010101010101010101010101010101, a);
25762        let e = _mm512_set_epi16(
25763            0, 2, 0, 4, 0, 6, 0, 8, 0, 10, 0, 12, 0, 14, 0, 16, 0, 18, 0, 20, 0, 22, 0, 24, 0, 26,
25764            0, 28, 0, 30, 0, 32,
25765        );
25766        assert_eq_m512i(r, e);
25767    }
25768
25769    #[simd_test(enable = "avx512fp16")]
25770    fn test_mm512_cvt_roundph_epu16() {
25771        let a = _mm512_set_ph(
25772            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
25773            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
25774            31.0, 32.0,
25775        );
25776        let r = _mm512_cvt_roundph_epu16::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
25777        let e = _mm512_set_epi16(
25778            1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
25779            25, 26, 27, 28, 29, 30, 31, 32,
25780        );
25781        assert_eq_m512i(r, e);
25782    }
25783
25784    #[simd_test(enable = "avx512fp16")]
25785    fn test_mm512_mask_cvt_roundph_epu16() {
25786        let a = _mm512_set_ph(
25787            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
25788            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
25789            31.0, 32.0,
25790        );
25791        let src = _mm512_set_epi16(
25792            10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
25793            32, 33, 34, 35, 36, 37, 38, 39, 40, 41,
25794        );
25795        let r = _mm512_mask_cvt_roundph_epu16::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
25796            src,
25797            0b01010101010101010101010101010101,
25798            a,
25799        );
25800        let e = _mm512_set_epi16(
25801            10, 2, 12, 4, 14, 6, 16, 8, 18, 10, 20, 12, 22, 14, 24, 16, 26, 18, 28, 20, 30, 22, 32,
25802            24, 34, 26, 36, 28, 38, 30, 40, 32,
25803        );
25804        assert_eq_m512i(r, e);
25805    }
25806
25807    #[simd_test(enable = "avx512fp16")]
25808    fn test_mm512_maskz_cvt_roundph_epu16() {
25809        let a = _mm512_set_ph(
25810            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
25811            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
25812            31.0, 32.0,
25813        );
25814        let r = _mm512_maskz_cvt_roundph_epu16::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
25815            0b01010101010101010101010101010101,
25816            a,
25817        );
25818        let e = _mm512_set_epi16(
25819            0, 2, 0, 4, 0, 6, 0, 8, 0, 10, 0, 12, 0, 14, 0, 16, 0, 18, 0, 20, 0, 22, 0, 24, 0, 26,
25820            0, 28, 0, 30, 0, 32,
25821        );
25822        assert_eq_m512i(r, e);
25823    }
25824
25825    #[simd_test(enable = "avx512fp16,avx512vl")]
25826    fn test_mm_cvttph_epi16() {
25827        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
25828        let r = _mm_cvttph_epi16(a);
25829        let e = _mm_set_epi16(1, 2, 3, 4, 5, 6, 7, 8);
25830        assert_eq_m128i(r, e);
25831    }
25832
25833    #[simd_test(enable = "avx512fp16,avx512vl")]
25834    fn test_mm_mask_cvttph_epi16() {
25835        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
25836        let src = _mm_set_epi16(10, 11, 12, 13, 14, 15, 16, 17);
25837        let r = _mm_mask_cvttph_epi16(src, 0b01010101, a);
25838        let e = _mm_set_epi16(10, 2, 12, 4, 14, 6, 16, 8);
25839        assert_eq_m128i(r, e);
25840    }
25841
25842    #[simd_test(enable = "avx512fp16,avx512vl")]
25843    fn test_mm_maskz_cvttph_epi16() {
25844        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
25845        let r = _mm_maskz_cvttph_epi16(0b01010101, a);
25846        let e = _mm_set_epi16(0, 2, 0, 4, 0, 6, 0, 8);
25847        assert_eq_m128i(r, e);
25848    }
25849
25850    #[simd_test(enable = "avx512fp16,avx512vl")]
25851    fn test_mm256_cvttph_epi16() {
25852        let a = _mm256_set_ph(
25853            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
25854        );
25855        let r = _mm256_cvttph_epi16(a);
25856        let e = _mm256_set_epi16(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
25857        assert_eq_m256i(r, e);
25858    }
25859
25860    #[simd_test(enable = "avx512fp16,avx512vl")]
25861    fn test_mm256_mask_cvttph_epi16() {
25862        let a = _mm256_set_ph(
25863            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
25864        );
25865        let src = _mm256_set_epi16(
25866            10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25,
25867        );
25868        let r = _mm256_mask_cvttph_epi16(src, 0b0101010101010101, a);
25869        let e = _mm256_set_epi16(10, 2, 12, 4, 14, 6, 16, 8, 18, 10, 20, 12, 22, 14, 24, 16);
25870        assert_eq_m256i(r, e);
25871    }
25872
25873    #[simd_test(enable = "avx512fp16,avx512vl")]
25874    fn test_mm256_maskz_cvttph_epi16() {
25875        let a = _mm256_set_ph(
25876            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
25877        );
25878        let r = _mm256_maskz_cvttph_epi16(0b0101010101010101, a);
25879        let e = _mm256_set_epi16(0, 2, 0, 4, 0, 6, 0, 8, 0, 10, 0, 12, 0, 14, 0, 16);
25880        assert_eq_m256i(r, e);
25881    }
25882
25883    #[simd_test(enable = "avx512fp16")]
25884    fn test_mm512_cvttph_epi16() {
25885        let a = _mm512_set_ph(
25886            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
25887            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
25888            31.0, 32.0,
25889        );
25890        let r = _mm512_cvttph_epi16(a);
25891        let e = _mm512_set_epi16(
25892            1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
25893            25, 26, 27, 28, 29, 30, 31, 32,
25894        );
25895        assert_eq_m512i(r, e);
25896    }
25897
25898    #[simd_test(enable = "avx512fp16")]
25899    fn test_mm512_mask_cvttph_epi16() {
25900        let a = _mm512_set_ph(
25901            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
25902            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
25903            31.0, 32.0,
25904        );
25905        let src = _mm512_set_epi16(
25906            10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
25907            32, 33, 34, 35, 36, 37, 38, 39, 40, 41,
25908        );
25909        let r = _mm512_mask_cvttph_epi16(src, 0b01010101010101010101010101010101, a);
25910        let e = _mm512_set_epi16(
25911            10, 2, 12, 4, 14, 6, 16, 8, 18, 10, 20, 12, 22, 14, 24, 16, 26, 18, 28, 20, 30, 22, 32,
25912            24, 34, 26, 36, 28, 38, 30, 40, 32,
25913        );
25914        assert_eq_m512i(r, e);
25915    }
25916
25917    #[simd_test(enable = "avx512fp16")]
25918    fn test_mm512_maskz_cvttph_epi16() {
25919        let a = _mm512_set_ph(
25920            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
25921            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
25922            31.0, 32.0,
25923        );
25924        let r = _mm512_maskz_cvttph_epi16(0b01010101010101010101010101010101, a);
25925        let e = _mm512_set_epi16(
25926            0, 2, 0, 4, 0, 6, 0, 8, 0, 10, 0, 12, 0, 14, 0, 16, 0, 18, 0, 20, 0, 22, 0, 24, 0, 26,
25927            0, 28, 0, 30, 0, 32,
25928        );
25929        assert_eq_m512i(r, e);
25930    }
25931
25932    #[simd_test(enable = "avx512fp16")]
25933    fn test_mm512_cvtt_roundph_epi16() {
25934        let a = _mm512_set_ph(
25935            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
25936            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
25937            31.0, 32.0,
25938        );
25939        let r = _mm512_cvtt_roundph_epi16::<_MM_FROUND_NO_EXC>(a);
25940        let e = _mm512_set_epi16(
25941            1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
25942            25, 26, 27, 28, 29, 30, 31, 32,
25943        );
25944        assert_eq_m512i(r, e);
25945    }
25946
25947    #[simd_test(enable = "avx512fp16")]
25948    fn test_mm512_mask_cvtt_roundph_epi16() {
25949        let a = _mm512_set_ph(
25950            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
25951            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
25952            31.0, 32.0,
25953        );
25954        let src = _mm512_set_epi16(
25955            10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
25956            32, 33, 34, 35, 36, 37, 38, 39, 40, 41,
25957        );
25958        let r = _mm512_mask_cvtt_roundph_epi16::<_MM_FROUND_NO_EXC>(
25959            src,
25960            0b01010101010101010101010101010101,
25961            a,
25962        );
25963        let e = _mm512_set_epi16(
25964            10, 2, 12, 4, 14, 6, 16, 8, 18, 10, 20, 12, 22, 14, 24, 16, 26, 18, 28, 20, 30, 22, 32,
25965            24, 34, 26, 36, 28, 38, 30, 40, 32,
25966        );
25967        assert_eq_m512i(r, e);
25968    }
25969
25970    #[simd_test(enable = "avx512fp16")]
25971    fn test_mm512_maskz_cvtt_roundph_epi16() {
25972        let a = _mm512_set_ph(
25973            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
25974            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
25975            31.0, 32.0,
25976        );
25977        let r = _mm512_maskz_cvtt_roundph_epi16::<_MM_FROUND_NO_EXC>(
25978            0b01010101010101010101010101010101,
25979            a,
25980        );
25981        let e = _mm512_set_epi16(
25982            0, 2, 0, 4, 0, 6, 0, 8, 0, 10, 0, 12, 0, 14, 0, 16, 0, 18, 0, 20, 0, 22, 0, 24, 0, 26,
25983            0, 28, 0, 30, 0, 32,
25984        );
25985        assert_eq_m512i(r, e);
25986    }
25987
25988    #[simd_test(enable = "avx512fp16,avx512vl")]
25989    fn test_mm_cvttph_epu16() {
25990        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
25991        let r = _mm_cvttph_epu16(a);
25992        let e = _mm_set_epi16(1, 2, 3, 4, 5, 6, 7, 8);
25993        assert_eq_m128i(r, e);
25994    }
25995
25996    #[simd_test(enable = "avx512fp16,avx512vl")]
25997    fn test_mm_mask_cvttph_epu16() {
25998        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
25999        let src = _mm_set_epi16(10, 11, 12, 13, 14, 15, 16, 17);
26000        let r = _mm_mask_cvttph_epu16(src, 0b01010101, a);
26001        let e = _mm_set_epi16(10, 2, 12, 4, 14, 6, 16, 8);
26002        assert_eq_m128i(r, e);
26003    }
26004
26005    #[simd_test(enable = "avx512fp16,avx512vl")]
26006    fn test_mm_maskz_cvttph_epu16() {
26007        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
26008        let r = _mm_maskz_cvttph_epu16(0b01010101, a);
26009        let e = _mm_set_epi16(0, 2, 0, 4, 0, 6, 0, 8);
26010        assert_eq_m128i(r, e);
26011    }
26012
26013    #[simd_test(enable = "avx512fp16,avx512vl")]
26014    fn test_mm256_cvttph_epu16() {
26015        let a = _mm256_set_ph(
26016            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
26017        );
26018        let r = _mm256_cvttph_epu16(a);
26019        let e = _mm256_set_epi16(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
26020        assert_eq_m256i(r, e);
26021    }
26022
26023    #[simd_test(enable = "avx512fp16,avx512vl")]
26024    fn test_mm256_mask_cvttph_epu16() {
26025        let a = _mm256_set_ph(
26026            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
26027        );
26028        let src = _mm256_set_epi16(
26029            10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25,
26030        );
26031        let r = _mm256_mask_cvttph_epu16(src, 0b0101010101010101, a);
26032        let e = _mm256_set_epi16(10, 2, 12, 4, 14, 6, 16, 8, 18, 10, 20, 12, 22, 14, 24, 16);
26033        assert_eq_m256i(r, e);
26034    }
26035
26036    #[simd_test(enable = "avx512fp16,avx512vl")]
26037    fn test_mm256_maskz_cvttph_epu16() {
26038        let a = _mm256_set_ph(
26039            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
26040        );
26041        let r = _mm256_maskz_cvttph_epu16(0b0101010101010101, a);
26042        let e = _mm256_set_epi16(0, 2, 0, 4, 0, 6, 0, 8, 0, 10, 0, 12, 0, 14, 0, 16);
26043        assert_eq_m256i(r, e);
26044    }
26045
26046    #[simd_test(enable = "avx512fp16")]
26047    fn test_mm512_cvttph_epu16() {
26048        let a = _mm512_set_ph(
26049            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
26050            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
26051            31.0, 32.0,
26052        );
26053        let r = _mm512_cvttph_epu16(a);
26054        let e = _mm512_set_epi16(
26055            1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
26056            25, 26, 27, 28, 29, 30, 31, 32,
26057        );
26058        assert_eq_m512i(r, e);
26059    }
26060
26061    #[simd_test(enable = "avx512fp16")]
26062    fn test_mm512_mask_cvttph_epu16() {
26063        let a = _mm512_set_ph(
26064            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
26065            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
26066            31.0, 32.0,
26067        );
26068        let src = _mm512_set_epi16(
26069            10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
26070            32, 33, 34, 35, 36, 37, 38, 39, 40, 41,
26071        );
26072        let r = _mm512_mask_cvttph_epu16(src, 0b01010101010101010101010101010101, a);
26073        let e = _mm512_set_epi16(
26074            10, 2, 12, 4, 14, 6, 16, 8, 18, 10, 20, 12, 22, 14, 24, 16, 26, 18, 28, 20, 30, 22, 32,
26075            24, 34, 26, 36, 28, 38, 30, 40, 32,
26076        );
26077        assert_eq_m512i(r, e);
26078    }
26079
26080    #[simd_test(enable = "avx512fp16")]
26081    fn test_mm512_maskz_cvttph_epu16() {
26082        let a = _mm512_set_ph(
26083            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
26084            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
26085            31.0, 32.0,
26086        );
26087        let r = _mm512_maskz_cvttph_epu16(0b01010101010101010101010101010101, a);
26088        let e = _mm512_set_epi16(
26089            0, 2, 0, 4, 0, 6, 0, 8, 0, 10, 0, 12, 0, 14, 0, 16, 0, 18, 0, 20, 0, 22, 0, 24, 0, 26,
26090            0, 28, 0, 30, 0, 32,
26091        );
26092        assert_eq_m512i(r, e);
26093    }
26094
26095    #[simd_test(enable = "avx512fp16")]
26096    fn test_mm512_cvtt_roundph_epu16() {
26097        let a = _mm512_set_ph(
26098            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
26099            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
26100            31.0, 32.0,
26101        );
26102        let r = _mm512_cvtt_roundph_epu16::<_MM_FROUND_NO_EXC>(a);
26103        let e = _mm512_set_epi16(
26104            1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
26105            25, 26, 27, 28, 29, 30, 31, 32,
26106        );
26107        assert_eq_m512i(r, e);
26108    }
26109
26110    #[simd_test(enable = "avx512fp16")]
26111    fn test_mm512_mask_cvtt_roundph_epu16() {
26112        let a = _mm512_set_ph(
26113            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
26114            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
26115            31.0, 32.0,
26116        );
26117        let src = _mm512_set_epi16(
26118            10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
26119            32, 33, 34, 35, 36, 37, 38, 39, 40, 41,
26120        );
26121        let r = _mm512_mask_cvtt_roundph_epu16::<_MM_FROUND_NO_EXC>(
26122            src,
26123            0b01010101010101010101010101010101,
26124            a,
26125        );
26126        let e = _mm512_set_epi16(
26127            10, 2, 12, 4, 14, 6, 16, 8, 18, 10, 20, 12, 22, 14, 24, 16, 26, 18, 28, 20, 30, 22, 32,
26128            24, 34, 26, 36, 28, 38, 30, 40, 32,
26129        );
26130        assert_eq_m512i(r, e);
26131    }
26132
26133    #[simd_test(enable = "avx512fp16")]
26134    fn test_mm512_maskz_cvtt_roundph_epu16() {
26135        let a = _mm512_set_ph(
26136            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
26137            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
26138            31.0, 32.0,
26139        );
26140        let r = _mm512_maskz_cvtt_roundph_epu16::<_MM_FROUND_NO_EXC>(
26141            0b01010101010101010101010101010101,
26142            a,
26143        );
26144        let e = _mm512_set_epi16(
26145            0, 2, 0, 4, 0, 6, 0, 8, 0, 10, 0, 12, 0, 14, 0, 16, 0, 18, 0, 20, 0, 22, 0, 24, 0, 26,
26146            0, 28, 0, 30, 0, 32,
26147        );
26148        assert_eq_m512i(r, e);
26149    }
26150
26151    #[simd_test(enable = "avx512fp16,avx512vl")]
26152    fn test_mm_cvtph_epi32() {
26153        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
26154        let r = _mm_cvtph_epi32(a);
26155        let e = _mm_set_epi32(1, 2, 3, 4);
26156        assert_eq_m128i(r, e);
26157    }
26158
26159    #[simd_test(enable = "avx512fp16,avx512vl")]
26160    fn test_mm_mask_cvtph_epi32() {
26161        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
26162        let src = _mm_set_epi32(10, 11, 12, 13);
26163        let r = _mm_mask_cvtph_epi32(src, 0b0101, a);
26164        let e = _mm_set_epi32(10, 2, 12, 4);
26165        assert_eq_m128i(r, e);
26166    }
26167
26168    #[simd_test(enable = "avx512fp16,avx512vl")]
26169    fn test_mm_maskz_cvtph_epi32() {
26170        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
26171        let r = _mm_maskz_cvtph_epi32(0b0101, a);
26172        let e = _mm_set_epi32(0, 2, 0, 4);
26173        assert_eq_m128i(r, e);
26174    }
26175
26176    #[simd_test(enable = "avx512fp16,avx512vl")]
26177    fn test_mm256_cvtph_epi32() {
26178        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
26179        let r = _mm256_cvtph_epi32(a);
26180        let e = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
26181        assert_eq_m256i(r, e);
26182    }
26183
26184    #[simd_test(enable = "avx512fp16,avx512vl")]
26185    fn test_mm256_mask_cvtph_epi32() {
26186        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
26187        let src = _mm256_set_epi32(10, 11, 12, 13, 14, 15, 16, 17);
26188        let r = _mm256_mask_cvtph_epi32(src, 0b01010101, a);
26189        let e = _mm256_set_epi32(10, 2, 12, 4, 14, 6, 16, 8);
26190        assert_eq_m256i(r, e);
26191    }
26192
26193    #[simd_test(enable = "avx512fp16,avx512vl")]
26194    fn test_mm256_maskz_cvtph_epi32() {
26195        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
26196        let r = _mm256_maskz_cvtph_epi32(0b01010101, a);
26197        let e = _mm256_set_epi32(0, 2, 0, 4, 0, 6, 0, 8);
26198        assert_eq_m256i(r, e);
26199    }
26200
26201    #[simd_test(enable = "avx512fp16")]
26202    fn test_mm512_cvtph_epi32() {
26203        let a = _mm256_set_ph(
26204            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
26205        );
26206        let r = _mm512_cvtph_epi32(a);
26207        let e = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
26208        assert_eq_m512i(r, e);
26209    }
26210
26211    #[simd_test(enable = "avx512fp16")]
26212    fn test_mm512_mask_cvtph_epi32() {
26213        let a = _mm256_set_ph(
26214            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
26215        );
26216        let src = _mm512_set_epi32(
26217            10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25,
26218        );
26219        let r = _mm512_mask_cvtph_epi32(src, 0b0101010101010101, a);
26220        let e = _mm512_set_epi32(10, 2, 12, 4, 14, 6, 16, 8, 18, 10, 20, 12, 22, 14, 24, 16);
26221        assert_eq_m512i(r, e);
26222    }
26223
26224    #[simd_test(enable = "avx512fp16")]
26225    fn test_mm512_maskz_cvtph_epi32() {
26226        let a = _mm256_set_ph(
26227            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
26228        );
26229        let r = _mm512_maskz_cvtph_epi32(0b0101010101010101, a);
26230        let e = _mm512_set_epi32(0, 2, 0, 4, 0, 6, 0, 8, 0, 10, 0, 12, 0, 14, 0, 16);
26231        assert_eq_m512i(r, e);
26232    }
26233
26234    #[simd_test(enable = "avx512fp16")]
26235    fn test_mm512_cvt_roundph_epi32() {
26236        let a = _mm256_set_ph(
26237            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
26238        );
26239        let r = _mm512_cvt_roundph_epi32::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
26240        let e = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
26241        assert_eq_m512i(r, e);
26242    }
26243
26244    #[simd_test(enable = "avx512fp16")]
26245    fn test_mm512_mask_cvt_roundph_epi32() {
26246        let a = _mm256_set_ph(
26247            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
26248        );
26249        let src = _mm512_set_epi32(
26250            10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25,
26251        );
26252        let r = _mm512_mask_cvt_roundph_epi32::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
26253            src,
26254            0b0101010101010101,
26255            a,
26256        );
26257        let e = _mm512_set_epi32(10, 2, 12, 4, 14, 6, 16, 8, 18, 10, 20, 12, 22, 14, 24, 16);
26258        assert_eq_m512i(r, e);
26259    }
26260
26261    #[simd_test(enable = "avx512fp16")]
26262    fn test_mm512_maskz_cvt_roundph_epi32() {
26263        let a = _mm256_set_ph(
26264            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
26265        );
26266        let r = _mm512_maskz_cvt_roundph_epi32::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
26267            0b0101010101010101,
26268            a,
26269        );
26270        let e = _mm512_set_epi32(0, 2, 0, 4, 0, 6, 0, 8, 0, 10, 0, 12, 0, 14, 0, 16);
26271        assert_eq_m512i(r, e);
26272    }
26273
26274    #[simd_test(enable = "avx512fp16")]
26275    fn test_mm_cvtsh_i32() {
26276        let a = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
26277        let r = _mm_cvtsh_i32(a);
26278        assert_eq!(r, 1);
26279    }
26280
26281    #[simd_test(enable = "avx512fp16")]
26282    fn test_mm_cvt_roundsh_i32() {
26283        let a = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
26284        let r = _mm_cvt_roundsh_i32::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
26285        assert_eq!(r, 1);
26286    }
26287
26288    #[simd_test(enable = "avx512fp16,avx512vl")]
26289    fn test_mm_cvtph_epu32() {
26290        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
26291        let r = _mm_cvtph_epu32(a);
26292        let e = _mm_set_epi32(1, 2, 3, 4);
26293        assert_eq_m128i(r, e);
26294    }
26295
26296    #[simd_test(enable = "avx512fp16,avx512vl")]
26297    fn test_mm_mask_cvtph_epu32() {
26298        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
26299        let src = _mm_set_epi32(10, 11, 12, 13);
26300        let r = _mm_mask_cvtph_epu32(src, 0b0101, a);
26301        let e = _mm_set_epi32(10, 2, 12, 4);
26302        assert_eq_m128i(r, e);
26303    }
26304
26305    #[simd_test(enable = "avx512fp16,avx512vl")]
26306    fn test_mm_maskz_cvtph_epu32() {
26307        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
26308        let r = _mm_maskz_cvtph_epu32(0b0101, a);
26309        let e = _mm_set_epi32(0, 2, 0, 4);
26310        assert_eq_m128i(r, e);
26311    }
26312
26313    #[simd_test(enable = "avx512fp16,avx512vl")]
26314    fn test_mm256_cvtph_epu32() {
26315        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
26316        let r = _mm256_cvtph_epu32(a);
26317        let e = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
26318        assert_eq_m256i(r, e);
26319    }
26320
26321    #[simd_test(enable = "avx512fp16,avx512vl")]
26322    fn test_mm256_mask_cvtph_epu32() {
26323        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
26324        let src = _mm256_set_epi32(10, 11, 12, 13, 14, 15, 16, 17);
26325        let r = _mm256_mask_cvtph_epu32(src, 0b01010101, a);
26326        let e = _mm256_set_epi32(10, 2, 12, 4, 14, 6, 16, 8);
26327        assert_eq_m256i(r, e);
26328    }
26329
26330    #[simd_test(enable = "avx512fp16,avx512vl")]
26331    fn test_mm256_maskz_cvtph_epu32() {
26332        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
26333        let r = _mm256_maskz_cvtph_epu32(0b01010101, a);
26334        let e = _mm256_set_epi32(0, 2, 0, 4, 0, 6, 0, 8);
26335        assert_eq_m256i(r, e);
26336    }
26337
26338    #[simd_test(enable = "avx512fp16")]
26339    fn test_mm512_cvtph_epu32() {
26340        let a = _mm256_set_ph(
26341            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
26342        );
26343        let r = _mm512_cvtph_epu32(a);
26344        let e = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
26345        assert_eq_m512i(r, e);
26346    }
26347
26348    #[simd_test(enable = "avx512fp16")]
26349    fn test_mm512_mask_cvtph_epu32() {
26350        let a = _mm256_set_ph(
26351            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
26352        );
26353        let src = _mm512_set_epi32(
26354            10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25,
26355        );
26356        let r = _mm512_mask_cvtph_epu32(src, 0b0101010101010101, a);
26357        let e = _mm512_set_epi32(10, 2, 12, 4, 14, 6, 16, 8, 18, 10, 20, 12, 22, 14, 24, 16);
26358        assert_eq_m512i(r, e);
26359    }
26360
26361    #[simd_test(enable = "avx512fp16")]
26362    fn test_mm512_maskz_cvtph_epu32() {
26363        let a = _mm256_set_ph(
26364            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
26365        );
26366        let r = _mm512_maskz_cvtph_epu32(0b0101010101010101, a);
26367        let e = _mm512_set_epi32(0, 2, 0, 4, 0, 6, 0, 8, 0, 10, 0, 12, 0, 14, 0, 16);
26368        assert_eq_m512i(r, e);
26369    }
26370
26371    #[simd_test(enable = "avx512fp16")]
26372    fn test_mm512_cvt_roundph_epu32() {
26373        let a = _mm256_set_ph(
26374            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
26375        );
26376        let r = _mm512_cvt_roundph_epu32::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
26377        let e = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
26378        assert_eq_m512i(r, e);
26379    }
26380
26381    #[simd_test(enable = "avx512fp16")]
26382    fn test_mm512_mask_cvt_roundph_epu32() {
26383        let a = _mm256_set_ph(
26384            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
26385        );
26386        let src = _mm512_set_epi32(
26387            10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25,
26388        );
26389        let r = _mm512_mask_cvt_roundph_epu32::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
26390            src,
26391            0b0101010101010101,
26392            a,
26393        );
26394        let e = _mm512_set_epi32(10, 2, 12, 4, 14, 6, 16, 8, 18, 10, 20, 12, 22, 14, 24, 16);
26395        assert_eq_m512i(r, e);
26396    }
26397
26398    #[simd_test(enable = "avx512fp16")]
26399    fn test_mm512_maskz_cvt_roundph_epu32() {
26400        let a = _mm256_set_ph(
26401            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
26402        );
26403        let r = _mm512_maskz_cvt_roundph_epu32::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
26404            0b0101010101010101,
26405            a,
26406        );
26407        let e = _mm512_set_epi32(0, 2, 0, 4, 0, 6, 0, 8, 0, 10, 0, 12, 0, 14, 0, 16);
26408        assert_eq_m512i(r, e);
26409    }
26410
26411    #[simd_test(enable = "avx512fp16")]
26412    fn test_mm_cvtsh_u32() {
26413        let a = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
26414        let r = _mm_cvtsh_u32(a);
26415        assert_eq!(r, 1);
26416    }
26417
26418    #[simd_test(enable = "avx512fp16")]
26419    fn test_mm_cvt_roundsh_u32() {
26420        let a = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
26421        let r = _mm_cvt_roundsh_u32::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
26422        assert_eq!(r, 1);
26423    }
26424
26425    #[simd_test(enable = "avx512fp16,avx512vl")]
26426    fn test_mm_cvttph_epi32() {
26427        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
26428        let r = _mm_cvttph_epi32(a);
26429        let e = _mm_set_epi32(1, 2, 3, 4);
26430        assert_eq_m128i(r, e);
26431    }
26432
26433    #[simd_test(enable = "avx512fp16,avx512vl")]
26434    fn test_mm_mask_cvttph_epi32() {
26435        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
26436        let src = _mm_set_epi32(10, 11, 12, 13);
26437        let r = _mm_mask_cvttph_epi32(src, 0b0101, a);
26438        let e = _mm_set_epi32(10, 2, 12, 4);
26439        assert_eq_m128i(r, e);
26440    }
26441
26442    #[simd_test(enable = "avx512fp16,avx512vl")]
26443    fn test_mm_maskz_cvttph_epi32() {
26444        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
26445        let r = _mm_maskz_cvttph_epi32(0b0101, a);
26446        let e = _mm_set_epi32(0, 2, 0, 4);
26447        assert_eq_m128i(r, e);
26448    }
26449
26450    #[simd_test(enable = "avx512fp16,avx512vl")]
26451    fn test_mm256_cvttph_epi32() {
26452        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
26453        let r = _mm256_cvttph_epi32(a);
26454        let e = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
26455        assert_eq_m256i(r, e);
26456    }
26457
26458    #[simd_test(enable = "avx512fp16,avx512vl")]
26459    fn test_mm256_mask_cvttph_epi32() {
26460        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
26461        let src = _mm256_set_epi32(10, 11, 12, 13, 14, 15, 16, 17);
26462        let r = _mm256_mask_cvttph_epi32(src, 0b01010101, a);
26463        let e = _mm256_set_epi32(10, 2, 12, 4, 14, 6, 16, 8);
26464        assert_eq_m256i(r, e);
26465    }
26466
26467    #[simd_test(enable = "avx512fp16,avx512vl")]
26468    fn test_mm256_maskz_cvttph_epi32() {
26469        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
26470        let r = _mm256_maskz_cvttph_epi32(0b01010101, a);
26471        let e = _mm256_set_epi32(0, 2, 0, 4, 0, 6, 0, 8);
26472        assert_eq_m256i(r, e);
26473    }
26474
26475    #[simd_test(enable = "avx512fp16")]
26476    fn test_mm512_cvttph_epi32() {
26477        let a = _mm256_set_ph(
26478            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
26479        );
26480        let r = _mm512_cvttph_epi32(a);
26481        let e = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
26482        assert_eq_m512i(r, e);
26483    }
26484
26485    #[simd_test(enable = "avx512fp16")]
26486    fn test_mm512_mask_cvttph_epi32() {
26487        let a = _mm256_set_ph(
26488            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
26489        );
26490        let src = _mm512_set_epi32(
26491            10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25,
26492        );
26493        let r = _mm512_mask_cvttph_epi32(src, 0b0101010101010101, a);
26494        let e = _mm512_set_epi32(10, 2, 12, 4, 14, 6, 16, 8, 18, 10, 20, 12, 22, 14, 24, 16);
26495        assert_eq_m512i(r, e);
26496    }
26497
26498    #[simd_test(enable = "avx512fp16")]
26499    fn test_mm512_maskz_cvttph_epi32() {
26500        let a = _mm256_set_ph(
26501            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
26502        );
26503        let r = _mm512_maskz_cvttph_epi32(0b0101010101010101, a);
26504        let e = _mm512_set_epi32(0, 2, 0, 4, 0, 6, 0, 8, 0, 10, 0, 12, 0, 14, 0, 16);
26505        assert_eq_m512i(r, e);
26506    }
26507
26508    #[simd_test(enable = "avx512fp16")]
26509    fn test_mm512_cvtt_roundph_epi32() {
26510        let a = _mm256_set_ph(
26511            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
26512        );
26513        let r = _mm512_cvtt_roundph_epi32::<_MM_FROUND_NO_EXC>(a);
26514        let e = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
26515        assert_eq_m512i(r, e);
26516    }
26517
26518    #[simd_test(enable = "avx512fp16")]
26519    fn test_mm512_mask_cvtt_roundph_epi32() {
26520        let a = _mm256_set_ph(
26521            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
26522        );
26523        let src = _mm512_set_epi32(
26524            10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25,
26525        );
26526        let r = _mm512_mask_cvtt_roundph_epi32::<_MM_FROUND_NO_EXC>(src, 0b0101010101010101, a);
26527        let e = _mm512_set_epi32(10, 2, 12, 4, 14, 6, 16, 8, 18, 10, 20, 12, 22, 14, 24, 16);
26528        assert_eq_m512i(r, e);
26529    }
26530
26531    #[simd_test(enable = "avx512fp16")]
26532    fn test_mm512_maskz_cvtt_roundph_epi32() {
26533        let a = _mm256_set_ph(
26534            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
26535        );
26536        let r = _mm512_maskz_cvtt_roundph_epi32::<_MM_FROUND_NO_EXC>(0b0101010101010101, a);
26537        let e = _mm512_set_epi32(0, 2, 0, 4, 0, 6, 0, 8, 0, 10, 0, 12, 0, 14, 0, 16);
26538        assert_eq_m512i(r, e);
26539    }
26540
26541    #[simd_test(enable = "avx512fp16")]
26542    fn test_mm_cvttsh_i32() {
26543        let a = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
26544        let r = _mm_cvttsh_i32(a);
26545        assert_eq!(r, 1);
26546    }
26547
26548    #[simd_test(enable = "avx512fp16")]
26549    fn test_mm_cvtt_roundsh_i32() {
26550        let a = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
26551        let r = _mm_cvtt_roundsh_i32::<_MM_FROUND_NO_EXC>(a);
26552        assert_eq!(r, 1);
26553    }
26554
26555    #[simd_test(enable = "avx512fp16,avx512vl")]
26556    fn test_mm_cvttph_epu32() {
26557        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
26558        let r = _mm_cvttph_epu32(a);
26559        let e = _mm_set_epi32(1, 2, 3, 4);
26560        assert_eq_m128i(r, e);
26561    }
26562
26563    #[simd_test(enable = "avx512fp16,avx512vl")]
26564    fn test_mm_mask_cvttph_epu32() {
26565        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
26566        let src = _mm_set_epi32(10, 11, 12, 13);
26567        let r = _mm_mask_cvttph_epu32(src, 0b0101, a);
26568        let e = _mm_set_epi32(10, 2, 12, 4);
26569        assert_eq_m128i(r, e);
26570    }
26571
26572    #[simd_test(enable = "avx512fp16,avx512vl")]
26573    fn test_mm_maskz_cvttph_epu32() {
26574        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
26575        let r = _mm_maskz_cvttph_epu32(0b0101, a);
26576        let e = _mm_set_epi32(0, 2, 0, 4);
26577        assert_eq_m128i(r, e);
26578    }
26579
26580    #[simd_test(enable = "avx512fp16,avx512vl")]
26581    fn test_mm256_cvttph_epu32() {
26582        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
26583        let r = _mm256_cvttph_epu32(a);
26584        let e = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
26585        assert_eq_m256i(r, e);
26586    }
26587
26588    #[simd_test(enable = "avx512fp16,avx512vl")]
26589    fn test_mm256_mask_cvttph_epu32() {
26590        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
26591        let src = _mm256_set_epi32(10, 11, 12, 13, 14, 15, 16, 17);
26592        let r = _mm256_mask_cvttph_epu32(src, 0b01010101, a);
26593        let e = _mm256_set_epi32(10, 2, 12, 4, 14, 6, 16, 8);
26594        assert_eq_m256i(r, e);
26595    }
26596
26597    #[simd_test(enable = "avx512fp16,avx512vl")]
26598    fn test_mm256_maskz_cvttph_epu32() {
26599        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
26600        let r = _mm256_maskz_cvttph_epu32(0b01010101, a);
26601        let e = _mm256_set_epi32(0, 2, 0, 4, 0, 6, 0, 8);
26602        assert_eq_m256i(r, e);
26603    }
26604
26605    #[simd_test(enable = "avx512fp16")]
26606    fn test_mm512_cvttph_epu32() {
26607        let a = _mm256_set_ph(
26608            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
26609        );
26610        let r = _mm512_cvttph_epu32(a);
26611        let e = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
26612        assert_eq_m512i(r, e);
26613    }
26614
26615    #[simd_test(enable = "avx512fp16")]
26616    fn test_mm512_mask_cvttph_epu32() {
26617        let a = _mm256_set_ph(
26618            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
26619        );
26620        let src = _mm512_set_epi32(
26621            10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25,
26622        );
26623        let r = _mm512_mask_cvttph_epu32(src, 0b0101010101010101, a);
26624        let e = _mm512_set_epi32(10, 2, 12, 4, 14, 6, 16, 8, 18, 10, 20, 12, 22, 14, 24, 16);
26625        assert_eq_m512i(r, e);
26626    }
26627
26628    #[simd_test(enable = "avx512fp16")]
26629    fn test_mm512_maskz_cvttph_epu32() {
26630        let a = _mm256_set_ph(
26631            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
26632        );
26633        let r = _mm512_maskz_cvttph_epu32(0b0101010101010101, a);
26634        let e = _mm512_set_epi32(0, 2, 0, 4, 0, 6, 0, 8, 0, 10, 0, 12, 0, 14, 0, 16);
26635        assert_eq_m512i(r, e);
26636    }
26637
26638    #[simd_test(enable = "avx512fp16")]
26639    fn test_mm512_cvtt_roundph_epu32() {
26640        let a = _mm256_set_ph(
26641            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
26642        );
26643        let r = _mm512_cvtt_roundph_epu32::<_MM_FROUND_NO_EXC>(a);
26644        let e = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
26645        assert_eq_m512i(r, e);
26646    }
26647
26648    #[simd_test(enable = "avx512fp16")]
26649    fn test_mm512_mask_cvtt_roundph_epu32() {
26650        let a = _mm256_set_ph(
26651            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
26652        );
26653        let src = _mm512_set_epi32(
26654            10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25,
26655        );
26656        let r = _mm512_mask_cvtt_roundph_epu32::<_MM_FROUND_NO_EXC>(src, 0b0101010101010101, a);
26657        let e = _mm512_set_epi32(10, 2, 12, 4, 14, 6, 16, 8, 18, 10, 20, 12, 22, 14, 24, 16);
26658        assert_eq_m512i(r, e);
26659    }
26660
26661    #[simd_test(enable = "avx512fp16")]
26662    fn test_mm512_maskz_cvtt_roundph_epu32() {
26663        let a = _mm256_set_ph(
26664            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
26665        );
26666        let r = _mm512_maskz_cvtt_roundph_epu32::<_MM_FROUND_NO_EXC>(0b0101010101010101, a);
26667        let e = _mm512_set_epi32(0, 2, 0, 4, 0, 6, 0, 8, 0, 10, 0, 12, 0, 14, 0, 16);
26668        assert_eq_m512i(r, e);
26669    }
26670
26671    #[simd_test(enable = "avx512fp16")]
26672    fn test_mm_cvttsh_u32() {
26673        let a = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
26674        let r = _mm_cvttsh_u32(a);
26675        assert_eq!(r, 1);
26676    }
26677
26678    #[simd_test(enable = "avx512fp16")]
26679    fn test_mm_cvtt_roundsh_u32() {
26680        let a = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
26681        let r = _mm_cvtt_roundsh_u32::<_MM_FROUND_NO_EXC>(a);
26682        assert_eq!(r, 1);
26683    }
26684
26685    #[simd_test(enable = "avx512fp16,avx512vl")]
26686    fn test_mm_cvtph_epi64() {
26687        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0, 2.0);
26688        let r = _mm_cvtph_epi64(a);
26689        let e = _mm_set_epi64x(1, 2);
26690        assert_eq_m128i(r, e);
26691    }
26692
26693    #[simd_test(enable = "avx512fp16,avx512vl")]
26694    fn test_mm_mask_cvtph_epi64() {
26695        let src = _mm_set_epi64x(3, 4);
26696        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0, 2.0);
26697        let r = _mm_mask_cvtph_epi64(src, 0b01, a);
26698        let e = _mm_set_epi64x(3, 2);
26699        assert_eq_m128i(r, e);
26700    }
26701
26702    #[simd_test(enable = "avx512fp16,avx512vl")]
26703    fn test_mm_maskz_cvtph_epi64() {
26704        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0, 2.0);
26705        let r = _mm_maskz_cvtph_epi64(0b01, a);
26706        let e = _mm_set_epi64x(0, 2);
26707        assert_eq_m128i(r, e);
26708    }
26709
26710    #[simd_test(enable = "avx512fp16,avx512vl")]
26711    fn test_mm256_cvtph_epi64() {
26712        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
26713        let r = _mm256_cvtph_epi64(a);
26714        let e = _mm256_set_epi64x(1, 2, 3, 4);
26715        assert_eq_m256i(r, e);
26716    }
26717
26718    #[simd_test(enable = "avx512fp16,avx512vl")]
26719    fn test_mm256_mask_cvtph_epi64() {
26720        let src = _mm256_set_epi64x(5, 6, 7, 8);
26721        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
26722        let r = _mm256_mask_cvtph_epi64(src, 0b0101, a);
26723        let e = _mm256_set_epi64x(5, 2, 7, 4);
26724        assert_eq_m256i(r, e);
26725    }
26726
26727    #[simd_test(enable = "avx512fp16,avx512vl")]
26728    fn test_mm256_maskz_cvtph_epi64() {
26729        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
26730        let r = _mm256_maskz_cvtph_epi64(0b0101, a);
26731        let e = _mm256_set_epi64x(0, 2, 0, 4);
26732        assert_eq_m256i(r, e);
26733    }
26734
26735    #[simd_test(enable = "avx512fp16")]
26736    fn test_mm512_cvtph_epi64() {
26737        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
26738        let r = _mm512_cvtph_epi64(a);
26739        let e = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
26740        assert_eq_m512i(r, e);
26741    }
26742
26743    #[simd_test(enable = "avx512fp16")]
26744    fn test_mm512_mask_cvtph_epi64() {
26745        let src = _mm512_set_epi64(9, 10, 11, 12, 13, 14, 15, 16);
26746        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
26747        let r = _mm512_mask_cvtph_epi64(src, 0b01010101, a);
26748        let e = _mm512_set_epi64(9, 2, 11, 4, 13, 6, 15, 8);
26749        assert_eq_m512i(r, e);
26750    }
26751
26752    #[simd_test(enable = "avx512fp16")]
26753    fn test_mm512_maskz_cvtph_epi64() {
26754        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
26755        let r = _mm512_maskz_cvtph_epi64(0b01010101, a);
26756        let e = _mm512_set_epi64(0, 2, 0, 4, 0, 6, 0, 8);
26757        assert_eq_m512i(r, e);
26758    }
26759
26760    #[simd_test(enable = "avx512fp16")]
26761    fn test_mm512_cvt_roundph_epi64() {
26762        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
26763        let r = _mm512_cvt_roundph_epi64::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
26764        let e = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
26765        assert_eq_m512i(r, e);
26766    }
26767
26768    #[simd_test(enable = "avx512fp16")]
26769    fn test_mm512_mask_cvt_roundph_epi64() {
26770        let src = _mm512_set_epi64(9, 10, 11, 12, 13, 14, 15, 16);
26771        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
26772        let r = _mm512_mask_cvt_roundph_epi64::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
26773            src, 0b01010101, a,
26774        );
26775        let e = _mm512_set_epi64(9, 2, 11, 4, 13, 6, 15, 8);
26776        assert_eq_m512i(r, e);
26777    }
26778
26779    #[simd_test(enable = "avx512fp16")]
26780    fn test_mm512_maskz_cvt_roundph_epi64() {
26781        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
26782        let r = _mm512_maskz_cvt_roundph_epi64::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
26783            0b01010101, a,
26784        );
26785        let e = _mm512_set_epi64(0, 2, 0, 4, 0, 6, 0, 8);
26786        assert_eq_m512i(r, e);
26787    }
26788
26789    #[simd_test(enable = "avx512fp16,avx512vl")]
26790    fn test_mm_cvtph_epu64() {
26791        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0, 2.0);
26792        let r = _mm_cvtph_epu64(a);
26793        let e = _mm_set_epi64x(1, 2);
26794        assert_eq_m128i(r, e);
26795    }
26796
26797    #[simd_test(enable = "avx512fp16,avx512vl")]
26798    fn test_mm_mask_cvtph_epu64() {
26799        let src = _mm_set_epi64x(3, 4);
26800        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0, 2.0);
26801        let r = _mm_mask_cvtph_epu64(src, 0b01, a);
26802        let e = _mm_set_epi64x(3, 2);
26803        assert_eq_m128i(r, e);
26804    }
26805
26806    #[simd_test(enable = "avx512fp16,avx512vl")]
26807    fn test_mm_maskz_cvtph_epu64() {
26808        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0, 2.0);
26809        let r = _mm_maskz_cvtph_epu64(0b01, a);
26810        let e = _mm_set_epi64x(0, 2);
26811        assert_eq_m128i(r, e);
26812    }
26813
26814    #[simd_test(enable = "avx512fp16,avx512vl")]
26815    fn test_mm256_cvtph_epu64() {
26816        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
26817        let r = _mm256_cvtph_epu64(a);
26818        let e = _mm256_set_epi64x(1, 2, 3, 4);
26819        assert_eq_m256i(r, e);
26820    }
26821
26822    #[simd_test(enable = "avx512fp16,avx512vl")]
26823    fn test_mm256_mask_cvtph_epu64() {
26824        let src = _mm256_set_epi64x(5, 6, 7, 8);
26825        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
26826        let r = _mm256_mask_cvtph_epu64(src, 0b0101, a);
26827        let e = _mm256_set_epi64x(5, 2, 7, 4);
26828        assert_eq_m256i(r, e);
26829    }
26830
26831    #[simd_test(enable = "avx512fp16,avx512vl")]
26832    fn test_mm256_maskz_cvtph_epu64() {
26833        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
26834        let r = _mm256_maskz_cvtph_epu64(0b0101, a);
26835        let e = _mm256_set_epi64x(0, 2, 0, 4);
26836        assert_eq_m256i(r, e);
26837    }
26838
26839    #[simd_test(enable = "avx512fp16")]
26840    fn test_mm512_cvtph_epu64() {
26841        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
26842        let r = _mm512_cvtph_epu64(a);
26843        let e = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
26844        assert_eq_m512i(r, e);
26845    }
26846
26847    #[simd_test(enable = "avx512fp16")]
26848    fn test_mm512_mask_cvtph_epu64() {
26849        let src = _mm512_set_epi64(9, 10, 11, 12, 13, 14, 15, 16);
26850        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
26851        let r = _mm512_mask_cvtph_epu64(src, 0b01010101, a);
26852        let e = _mm512_set_epi64(9, 2, 11, 4, 13, 6, 15, 8);
26853        assert_eq_m512i(r, e);
26854    }
26855
26856    #[simd_test(enable = "avx512fp16")]
26857    fn test_mm512_maskz_cvtph_epu64() {
26858        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
26859        let r = _mm512_maskz_cvtph_epu64(0b01010101, a);
26860        let e = _mm512_set_epi64(0, 2, 0, 4, 0, 6, 0, 8);
26861        assert_eq_m512i(r, e);
26862    }
26863
26864    #[simd_test(enable = "avx512fp16")]
26865    fn test_mm512_cvt_roundph_epu64() {
26866        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
26867        let r = _mm512_cvt_roundph_epu64::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
26868        let e = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
26869        assert_eq_m512i(r, e);
26870    }
26871
26872    #[simd_test(enable = "avx512fp16")]
26873    fn test_mm512_mask_cvt_roundph_epu64() {
26874        let src = _mm512_set_epi64(9, 10, 11, 12, 13, 14, 15, 16);
26875        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
26876        let r = _mm512_mask_cvt_roundph_epu64::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
26877            src, 0b01010101, a,
26878        );
26879        let e = _mm512_set_epi64(9, 2, 11, 4, 13, 6, 15, 8);
26880        assert_eq_m512i(r, e);
26881    }
26882
26883    #[simd_test(enable = "avx512fp16")]
26884    fn test_mm512_maskz_cvt_roundph_epu64() {
26885        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
26886        let r = _mm512_maskz_cvt_roundph_epu64::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
26887            0b01010101, a,
26888        );
26889        let e = _mm512_set_epi64(0, 2, 0, 4, 0, 6, 0, 8);
26890        assert_eq_m512i(r, e);
26891    }
26892
26893    #[simd_test(enable = "avx512fp16,avx512vl")]
26894    fn test_mm_cvttph_epi64() {
26895        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0, 2.0);
26896        let r = _mm_cvttph_epi64(a);
26897        let e = _mm_set_epi64x(1, 2);
26898        assert_eq_m128i(r, e);
26899    }
26900
26901    #[simd_test(enable = "avx512fp16,avx512vl")]
26902    fn test_mm_mask_cvttph_epi64() {
26903        let src = _mm_set_epi64x(3, 4);
26904        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0, 2.0);
26905        let r = _mm_mask_cvttph_epi64(src, 0b01, a);
26906        let e = _mm_set_epi64x(3, 2);
26907        assert_eq_m128i(r, e);
26908    }
26909
26910    #[simd_test(enable = "avx512fp16,avx512vl")]
26911    fn test_mm_maskz_cvttph_epi64() {
26912        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0, 2.0);
26913        let r = _mm_maskz_cvttph_epi64(0b01, a);
26914        let e = _mm_set_epi64x(0, 2);
26915        assert_eq_m128i(r, e);
26916    }
26917
26918    #[simd_test(enable = "avx512fp16,avx512vl")]
26919    fn test_mm256_cvttph_epi64() {
26920        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
26921        let r = _mm256_cvttph_epi64(a);
26922        let e = _mm256_set_epi64x(1, 2, 3, 4);
26923        assert_eq_m256i(r, e);
26924    }
26925
26926    #[simd_test(enable = "avx512fp16,avx512vl")]
26927    fn test_mm256_mask_cvttph_epi64() {
26928        let src = _mm256_set_epi64x(5, 6, 7, 8);
26929        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
26930        let r = _mm256_mask_cvttph_epi64(src, 0b0101, a);
26931        let e = _mm256_set_epi64x(5, 2, 7, 4);
26932        assert_eq_m256i(r, e);
26933    }
26934
26935    #[simd_test(enable = "avx512fp16,avx512vl")]
26936    fn test_mm256_maskz_cvttph_epi64() {
26937        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
26938        let r = _mm256_maskz_cvttph_epi64(0b0101, a);
26939        let e = _mm256_set_epi64x(0, 2, 0, 4);
26940        assert_eq_m256i(r, e);
26941    }
26942
26943    #[simd_test(enable = "avx512fp16")]
26944    fn test_mm512_cvttph_epi64() {
26945        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
26946        let r = _mm512_cvttph_epi64(a);
26947        let e = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
26948        assert_eq_m512i(r, e);
26949    }
26950
26951    #[simd_test(enable = "avx512fp16")]
26952    fn test_mm512_mask_cvttph_epi64() {
26953        let src = _mm512_set_epi64(9, 10, 11, 12, 13, 14, 15, 16);
26954        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
26955        let r = _mm512_mask_cvttph_epi64(src, 0b01010101, a);
26956        let e = _mm512_set_epi64(9, 2, 11, 4, 13, 6, 15, 8);
26957        assert_eq_m512i(r, e);
26958    }
26959
26960    #[simd_test(enable = "avx512fp16")]
26961    fn test_mm512_maskz_cvttph_epi64() {
26962        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
26963        let r = _mm512_maskz_cvttph_epi64(0b01010101, a);
26964        let e = _mm512_set_epi64(0, 2, 0, 4, 0, 6, 0, 8);
26965        assert_eq_m512i(r, e);
26966    }
26967
26968    #[simd_test(enable = "avx512fp16")]
26969    fn test_mm512_cvtt_roundph_epi64() {
26970        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
26971        let r = _mm512_cvtt_roundph_epi64::<_MM_FROUND_NO_EXC>(a);
26972        let e = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
26973        assert_eq_m512i(r, e);
26974    }
26975
26976    #[simd_test(enable = "avx512fp16")]
26977    fn test_mm512_mask_cvtt_roundph_epi64() {
26978        let src = _mm512_set_epi64(9, 10, 11, 12, 13, 14, 15, 16);
26979        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
26980        let r = _mm512_mask_cvtt_roundph_epi64::<_MM_FROUND_NO_EXC>(src, 0b01010101, a);
26981        let e = _mm512_set_epi64(9, 2, 11, 4, 13, 6, 15, 8);
26982        assert_eq_m512i(r, e);
26983    }
26984
26985    #[simd_test(enable = "avx512fp16")]
26986    fn test_mm512_maskz_cvtt_roundph_epi64() {
26987        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
26988        let r = _mm512_maskz_cvtt_roundph_epi64::<_MM_FROUND_NO_EXC>(0b01010101, a);
26989        let e = _mm512_set_epi64(0, 2, 0, 4, 0, 6, 0, 8);
26990        assert_eq_m512i(r, e);
26991    }
26992
26993    #[simd_test(enable = "avx512fp16,avx512vl")]
26994    fn test_mm_cvttph_epu64() {
26995        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0, 2.0);
26996        let r = _mm_cvttph_epu64(a);
26997        let e = _mm_set_epi64x(1, 2);
26998        assert_eq_m128i(r, e);
26999    }
27000
27001    #[simd_test(enable = "avx512fp16,avx512vl")]
27002    fn test_mm_mask_cvttph_epu64() {
27003        let src = _mm_set_epi64x(3, 4);
27004        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0, 2.0);
27005        let r = _mm_mask_cvttph_epu64(src, 0b01, a);
27006        let e = _mm_set_epi64x(3, 2);
27007        assert_eq_m128i(r, e);
27008    }
27009
27010    #[simd_test(enable = "avx512fp16,avx512vl")]
27011    fn test_mm_maskz_cvttph_epu64() {
27012        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0, 2.0);
27013        let r = _mm_maskz_cvttph_epu64(0b01, a);
27014        let e = _mm_set_epi64x(0, 2);
27015        assert_eq_m128i(r, e);
27016    }
27017
27018    #[simd_test(enable = "avx512fp16,avx512vl")]
27019    fn test_mm256_cvttph_epu64() {
27020        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
27021        let r = _mm256_cvttph_epu64(a);
27022        let e = _mm256_set_epi64x(1, 2, 3, 4);
27023        assert_eq_m256i(r, e);
27024    }
27025
27026    #[simd_test(enable = "avx512fp16,avx512vl")]
27027    fn test_mm256_mask_cvttph_epu64() {
27028        let src = _mm256_set_epi64x(5, 6, 7, 8);
27029        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
27030        let r = _mm256_mask_cvttph_epu64(src, 0b0101, a);
27031        let e = _mm256_set_epi64x(5, 2, 7, 4);
27032        assert_eq_m256i(r, e);
27033    }
27034
27035    #[simd_test(enable = "avx512fp16,avx512vl")]
27036    fn test_mm256_maskz_cvttph_epu64() {
27037        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
27038        let r = _mm256_maskz_cvttph_epu64(0b0101, a);
27039        let e = _mm256_set_epi64x(0, 2, 0, 4);
27040        assert_eq_m256i(r, e);
27041    }
27042
27043    #[simd_test(enable = "avx512fp16")]
27044    fn test_mm512_cvttph_epu64() {
27045        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
27046        let r = _mm512_cvttph_epu64(a);
27047        let e = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
27048        assert_eq_m512i(r, e);
27049    }
27050
27051    #[simd_test(enable = "avx512fp16")]
27052    fn test_mm512_mask_cvttph_epu64() {
27053        let src = _mm512_set_epi64(9, 10, 11, 12, 13, 14, 15, 16);
27054        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
27055        let r = _mm512_mask_cvttph_epu64(src, 0b01010101, a);
27056        let e = _mm512_set_epi64(9, 2, 11, 4, 13, 6, 15, 8);
27057        assert_eq_m512i(r, e);
27058    }
27059
27060    #[simd_test(enable = "avx512fp16")]
27061    fn test_mm512_maskz_cvttph_epu64() {
27062        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
27063        let r = _mm512_maskz_cvttph_epu64(0b01010101, a);
27064        let e = _mm512_set_epi64(0, 2, 0, 4, 0, 6, 0, 8);
27065        assert_eq_m512i(r, e);
27066    }
27067
27068    #[simd_test(enable = "avx512fp16")]
27069    fn test_mm512_cvtt_roundph_epu64() {
27070        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
27071        let r = _mm512_cvtt_roundph_epu64::<_MM_FROUND_NO_EXC>(a);
27072        let e = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
27073        assert_eq_m512i(r, e);
27074    }
27075
27076    #[simd_test(enable = "avx512fp16")]
27077    fn test_mm512_mask_cvtt_roundph_epu64() {
27078        let src = _mm512_set_epi64(9, 10, 11, 12, 13, 14, 15, 16);
27079        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
27080        let r = _mm512_mask_cvtt_roundph_epu64::<_MM_FROUND_NO_EXC>(src, 0b01010101, a);
27081        let e = _mm512_set_epi64(9, 2, 11, 4, 13, 6, 15, 8);
27082        assert_eq_m512i(r, e);
27083    }
27084
27085    #[simd_test(enable = "avx512fp16")]
27086    fn test_mm512_maskz_cvtt_roundph_epu64() {
27087        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
27088        let r = _mm512_maskz_cvtt_roundph_epu64::<_MM_FROUND_NO_EXC>(0b01010101, a);
27089        let e = _mm512_set_epi64(0, 2, 0, 4, 0, 6, 0, 8);
27090        assert_eq_m512i(r, e);
27091    }
27092
27093    #[simd_test(enable = "avx512fp16,avx512vl")]
27094    fn test_mm_cvtxph_ps() {
27095        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
27096        let r = _mm_cvtxph_ps(a);
27097        let e = _mm_set_ps(1.0, 2.0, 3.0, 4.0);
27098        assert_eq_m128(r, e);
27099    }
27100
27101    #[simd_test(enable = "avx512fp16,avx512vl")]
27102    fn test_mm_mask_cvtxph_ps() {
27103        let src = _mm_set_ps(10.0, 11.0, 12.0, 13.0);
27104        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
27105        let r = _mm_mask_cvtxph_ps(src, 0b0101, a);
27106        let e = _mm_set_ps(10.0, 2.0, 12.0, 4.0);
27107        assert_eq_m128(r, e);
27108    }
27109
27110    #[simd_test(enable = "avx512fp16,avx512vl")]
27111    fn test_mm_maskz_cvtxph_ps() {
27112        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
27113        let r = _mm_maskz_cvtxph_ps(0b0101, a);
27114        let e = _mm_set_ps(0.0, 2.0, 0.0, 4.0);
27115        assert_eq_m128(r, e);
27116    }
27117
27118    #[simd_test(enable = "avx512fp16,avx512vl")]
27119    fn test_mm256_cvtxph_ps() {
27120        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
27121        let r = _mm256_cvtxph_ps(a);
27122        let e = _mm256_set_ps(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
27123        assert_eq_m256(r, e);
27124    }
27125
27126    #[simd_test(enable = "avx512fp16,avx512vl")]
27127    fn test_mm256_mask_cvtxph_ps() {
27128        let src = _mm256_set_ps(10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0);
27129        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
27130        let r = _mm256_mask_cvtxph_ps(src, 0b01010101, a);
27131        let e = _mm256_set_ps(10.0, 2.0, 12.0, 4.0, 14.0, 6.0, 16.0, 8.0);
27132        assert_eq_m256(r, e);
27133    }
27134
27135    #[simd_test(enable = "avx512fp16,avx512vl")]
27136    fn test_mm256_maskz_cvtxph_ps() {
27137        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
27138        let r = _mm256_maskz_cvtxph_ps(0b01010101, a);
27139        let e = _mm256_set_ps(0.0, 2.0, 0.0, 4.0, 0.0, 6.0, 0.0, 8.0);
27140        assert_eq_m256(r, e);
27141    }
27142
27143    #[simd_test(enable = "avx512fp16")]
27144    fn test_mm512_cvtxph_ps() {
27145        let a = _mm256_set_ph(
27146            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
27147        );
27148        let r = _mm512_cvtxph_ps(a);
27149        let e = _mm512_set_ps(
27150            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
27151        );
27152        assert_eq_m512(r, e);
27153    }
27154
27155    #[simd_test(enable = "avx512fp16")]
27156    fn test_mm512_mask_cvtxph_ps() {
27157        let src = _mm512_set_ps(
27158            10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0,
27159            24.0, 25.0,
27160        );
27161        let a = _mm256_set_ph(
27162            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
27163        );
27164        let r = _mm512_mask_cvtxph_ps(src, 0b0101010101010101, a);
27165        let e = _mm512_set_ps(
27166            10.0, 2.0, 12.0, 4.0, 14.0, 6.0, 16.0, 8.0, 18.0, 10.0, 20.0, 12.0, 22.0, 14.0, 24.0,
27167            16.0,
27168        );
27169        assert_eq_m512(r, e);
27170    }
27171
27172    #[simd_test(enable = "avx512fp16")]
27173    fn test_mm512_maskz_cvtxph_ps() {
27174        let a = _mm256_set_ph(
27175            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
27176        );
27177        let r = _mm512_maskz_cvtxph_ps(0b0101010101010101, a);
27178        let e = _mm512_set_ps(
27179            0.0, 2.0, 0.0, 4.0, 0.0, 6.0, 0.0, 8.0, 0.0, 10.0, 0.0, 12.0, 0.0, 14.0, 0.0, 16.0,
27180        );
27181        assert_eq_m512(r, e);
27182    }
27183
27184    #[simd_test(enable = "avx512fp16")]
27185    fn test_mm512_cvtx_roundph_ps() {
27186        let a = _mm256_set_ph(
27187            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
27188        );
27189        let r = _mm512_cvtx_roundph_ps::<_MM_FROUND_NO_EXC>(a);
27190        let e = _mm512_set_ps(
27191            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
27192        );
27193        assert_eq_m512(r, e);
27194    }
27195
27196    #[simd_test(enable = "avx512fp16")]
27197    fn test_mm512_mask_cvtx_roundph_ps() {
27198        let src = _mm512_set_ps(
27199            10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0,
27200            24.0, 25.0,
27201        );
27202        let a = _mm256_set_ph(
27203            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
27204        );
27205        let r = _mm512_mask_cvtx_roundph_ps::<_MM_FROUND_NO_EXC>(src, 0b0101010101010101, a);
27206        let e = _mm512_set_ps(
27207            10.0, 2.0, 12.0, 4.0, 14.0, 6.0, 16.0, 8.0, 18.0, 10.0, 20.0, 12.0, 22.0, 14.0, 24.0,
27208            16.0,
27209        );
27210        assert_eq_m512(r, e);
27211    }
27212
27213    #[simd_test(enable = "avx512fp16")]
27214    fn test_mm512_maskz_cvtx_roundph_ps() {
27215        let a = _mm256_set_ph(
27216            1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
27217        );
27218        let r = _mm512_maskz_cvtx_roundph_ps::<_MM_FROUND_NO_EXC>(0b0101010101010101, a);
27219        let e = _mm512_set_ps(
27220            0.0, 2.0, 0.0, 4.0, 0.0, 6.0, 0.0, 8.0, 0.0, 10.0, 0.0, 12.0, 0.0, 14.0, 0.0, 16.0,
27221        );
27222        assert_eq_m512(r, e);
27223    }
27224
27225    #[simd_test(enable = "avx512fp16")]
27226    fn test_mm_cvtsh_ss() {
27227        let a = _mm_setr_ps(2.0, 20.0, 21.0, 22.0);
27228        let b = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
27229        let r = _mm_cvtsh_ss(a, b);
27230        let e = _mm_setr_ps(1.0, 20.0, 21.0, 22.0);
27231        assert_eq_m128(r, e);
27232    }
27233
27234    #[simd_test(enable = "avx512fp16")]
27235    fn test_mm_mask_cvtsh_ss() {
27236        let src = _mm_setr_ps(3.0, 11.0, 12.0, 13.0);
27237        let a = _mm_setr_ps(2.0, 20.0, 21.0, 22.0);
27238        let b = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
27239        let r = _mm_mask_cvtsh_ss(src, 0, a, b);
27240        let e = _mm_setr_ps(3.0, 20.0, 21.0, 22.0);
27241        assert_eq_m128(r, e);
27242        let r = _mm_mask_cvtsh_ss(src, 1, a, b);
27243        let e = _mm_setr_ps(1.0, 20.0, 21.0, 22.0);
27244        assert_eq_m128(r, e);
27245    }
27246
27247    #[simd_test(enable = "avx512fp16")]
27248    fn test_mm_maskz_cvtsh_ss() {
27249        let a = _mm_setr_ps(2.0, 20.0, 21.0, 22.0);
27250        let b = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
27251        let r = _mm_maskz_cvtsh_ss(0, a, b);
27252        let e = _mm_setr_ps(0.0, 20.0, 21.0, 22.0);
27253        assert_eq_m128(r, e);
27254        let r = _mm_maskz_cvtsh_ss(1, a, b);
27255        let e = _mm_setr_ps(1.0, 20.0, 21.0, 22.0);
27256        assert_eq_m128(r, e);
27257    }
27258
27259    #[simd_test(enable = "avx512fp16")]
27260    fn test_mm_cvt_roundsh_ss() {
27261        let a = _mm_setr_ps(2.0, 20.0, 21.0, 22.0);
27262        let b = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
27263        let r = _mm_cvt_roundsh_ss::<_MM_FROUND_NO_EXC>(a, b);
27264        let e = _mm_setr_ps(1.0, 20.0, 21.0, 22.0);
27265        assert_eq_m128(r, e);
27266    }
27267
27268    #[simd_test(enable = "avx512fp16")]
27269    fn test_mm_mask_cvt_roundsh_ss() {
27270        let src = _mm_setr_ps(3.0, 11.0, 12.0, 13.0);
27271        let a = _mm_setr_ps(2.0, 20.0, 21.0, 22.0);
27272        let b = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
27273        let r = _mm_mask_cvt_roundsh_ss::<_MM_FROUND_NO_EXC>(src, 0, a, b);
27274        let e = _mm_setr_ps(3.0, 20.0, 21.0, 22.0);
27275        assert_eq_m128(r, e);
27276        let r = _mm_mask_cvt_roundsh_ss::<_MM_FROUND_NO_EXC>(src, 1, a, b);
27277        let e = _mm_setr_ps(1.0, 20.0, 21.0, 22.0);
27278        assert_eq_m128(r, e);
27279    }
27280
27281    #[simd_test(enable = "avx512fp16")]
27282    fn test_mm_maskz_cvt_roundsh_ss() {
27283        let a = _mm_setr_ps(2.0, 20.0, 21.0, 22.0);
27284        let b = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
27285        let r = _mm_maskz_cvt_roundsh_ss::<_MM_FROUND_NO_EXC>(0, a, b);
27286        let e = _mm_setr_ps(0.0, 20.0, 21.0, 22.0);
27287        assert_eq_m128(r, e);
27288        let r = _mm_maskz_cvt_roundsh_ss::<_MM_FROUND_NO_EXC>(1, a, b);
27289        let e = _mm_setr_ps(1.0, 20.0, 21.0, 22.0);
27290        assert_eq_m128(r, e);
27291    }
27292
27293    #[simd_test(enable = "avx512fp16,avx512vl")]
27294    fn test_mm_cvtph_pd() {
27295        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0, 2.0);
27296        let r = _mm_cvtph_pd(a);
27297        let e = _mm_set_pd(1.0, 2.0);
27298        assert_eq_m128d(r, e);
27299    }
27300
27301    #[simd_test(enable = "avx512fp16,avx512vl")]
27302    fn test_mm_mask_cvtph_pd() {
27303        let src = _mm_set_pd(10.0, 11.0);
27304        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0, 2.0);
27305        let r = _mm_mask_cvtph_pd(src, 0b01, a);
27306        let e = _mm_set_pd(10.0, 2.0);
27307        assert_eq_m128d(r, e);
27308    }
27309
27310    #[simd_test(enable = "avx512fp16,avx512vl")]
27311    fn test_mm_maskz_cvtph_pd() {
27312        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0, 2.0);
27313        let r = _mm_maskz_cvtph_pd(0b01, a);
27314        let e = _mm_set_pd(0.0, 2.0);
27315        assert_eq_m128d(r, e);
27316    }
27317
27318    #[simd_test(enable = "avx512fp16,avx512vl")]
27319    fn test_mm256_cvtph_pd() {
27320        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
27321        let r = _mm256_cvtph_pd(a);
27322        let e = _mm256_set_pd(1.0, 2.0, 3.0, 4.0);
27323        assert_eq_m256d(r, e);
27324    }
27325
27326    #[simd_test(enable = "avx512fp16,avx512vl")]
27327    fn test_mm256_mask_cvtph_pd() {
27328        let src = _mm256_set_pd(10.0, 11.0, 12.0, 13.0);
27329        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
27330        let r = _mm256_mask_cvtph_pd(src, 0b0101, a);
27331        let e = _mm256_set_pd(10.0, 2.0, 12.0, 4.0);
27332        assert_eq_m256d(r, e);
27333    }
27334
27335    #[simd_test(enable = "avx512fp16,avx512vl")]
27336    fn test_mm256_maskz_cvtph_pd() {
27337        let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
27338        let r = _mm256_maskz_cvtph_pd(0b0101, a);
27339        let e = _mm256_set_pd(0.0, 2.0, 0.0, 4.0);
27340        assert_eq_m256d(r, e);
27341    }
27342
27343    #[simd_test(enable = "avx512fp16")]
27344    fn test_mm512_cvtph_pd() {
27345        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
27346        let r = _mm512_cvtph_pd(a);
27347        let e = _mm512_set_pd(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
27348        assert_eq_m512d(r, e);
27349    }
27350
27351    #[simd_test(enable = "avx512fp16")]
27352    fn test_mm512_mask_cvtph_pd() {
27353        let src = _mm512_set_pd(10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0);
27354        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
27355        let r = _mm512_mask_cvtph_pd(src, 0b01010101, a);
27356        let e = _mm512_set_pd(10.0, 2.0, 12.0, 4.0, 14.0, 6.0, 16.0, 8.0);
27357        assert_eq_m512d(r, e);
27358    }
27359
27360    #[simd_test(enable = "avx512fp16")]
27361    fn test_mm512_maskz_cvtph_pd() {
27362        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
27363        let r = _mm512_maskz_cvtph_pd(0b01010101, a);
27364        let e = _mm512_set_pd(0.0, 2.0, 0.0, 4.0, 0.0, 6.0, 0.0, 8.0);
27365        assert_eq_m512d(r, e);
27366    }
27367
27368    #[simd_test(enable = "avx512fp16")]
27369    fn test_mm512_cvt_roundph_pd() {
27370        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
27371        let r = _mm512_cvt_roundph_pd::<_MM_FROUND_NO_EXC>(a);
27372        let e = _mm512_set_pd(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
27373        assert_eq_m512d(r, e);
27374    }
27375
27376    #[simd_test(enable = "avx512fp16")]
27377    fn test_mm512_mask_cvt_roundph_pd() {
27378        let src = _mm512_set_pd(10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0);
27379        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
27380        let r = _mm512_mask_cvt_roundph_pd::<_MM_FROUND_NO_EXC>(src, 0b01010101, a);
27381        let e = _mm512_set_pd(10.0, 2.0, 12.0, 4.0, 14.0, 6.0, 16.0, 8.0);
27382        assert_eq_m512d(r, e);
27383    }
27384
27385    #[simd_test(enable = "avx512fp16")]
27386    fn test_mm512_maskz_cvt_roundph_pd() {
27387        let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
27388        let r = _mm512_maskz_cvt_roundph_pd::<_MM_FROUND_NO_EXC>(0b01010101, a);
27389        let e = _mm512_set_pd(0.0, 2.0, 0.0, 4.0, 0.0, 6.0, 0.0, 8.0);
27390        assert_eq_m512d(r, e);
27391    }
27392
27393    #[simd_test(enable = "avx512fp16")]
27394    fn test_mm_cvtsh_sd() {
27395        let a = _mm_setr_pd(2.0, 20.0);
27396        let b = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
27397        let r = _mm_cvtsh_sd(a, b);
27398        let e = _mm_setr_pd(1.0, 20.0);
27399        assert_eq_m128d(r, e);
27400    }
27401
27402    #[simd_test(enable = "avx512fp16")]
27403    fn test_mm_mask_cvtsh_sd() {
27404        let src = _mm_setr_pd(3.0, 11.0);
27405        let a = _mm_setr_pd(2.0, 20.0);
27406        let b = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
27407        let r = _mm_mask_cvtsh_sd(src, 0, a, b);
27408        let e = _mm_setr_pd(3.0, 20.0);
27409        assert_eq_m128d(r, e);
27410        let r = _mm_mask_cvtsh_sd(src, 1, a, b);
27411        let e = _mm_setr_pd(1.0, 20.0);
27412        assert_eq_m128d(r, e);
27413    }
27414
27415    #[simd_test(enable = "avx512fp16")]
27416    fn test_mm_maskz_cvtsh_sd() {
27417        let a = _mm_setr_pd(2.0, 20.0);
27418        let b = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
27419        let r = _mm_maskz_cvtsh_sd(0, a, b);
27420        let e = _mm_setr_pd(0.0, 20.0);
27421        assert_eq_m128d(r, e);
27422        let r = _mm_maskz_cvtsh_sd(1, a, b);
27423        let e = _mm_setr_pd(1.0, 20.0);
27424        assert_eq_m128d(r, e);
27425    }
27426
27427    #[simd_test(enable = "avx512fp16")]
27428    fn test_mm_cvt_roundsh_sd() {
27429        let a = _mm_setr_pd(2.0, 20.0);
27430        let b = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
27431        let r = _mm_cvt_roundsh_sd::<_MM_FROUND_NO_EXC>(a, b);
27432        let e = _mm_setr_pd(1.0, 20.0);
27433        assert_eq_m128d(r, e);
27434    }
27435
27436    #[simd_test(enable = "avx512fp16")]
27437    fn test_mm_mask_cvt_roundsh_sd() {
27438        let src = _mm_setr_pd(3.0, 11.0);
27439        let a = _mm_setr_pd(2.0, 20.0);
27440        let b = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
27441        let r = _mm_mask_cvt_roundsh_sd::<_MM_FROUND_NO_EXC>(src, 0, a, b);
27442        let e = _mm_setr_pd(3.0, 20.0);
27443        assert_eq_m128d(r, e);
27444        let r = _mm_mask_cvt_roundsh_sd::<_MM_FROUND_NO_EXC>(src, 1, a, b);
27445        let e = _mm_setr_pd(1.0, 20.0);
27446        assert_eq_m128d(r, e);
27447    }
27448
27449    #[simd_test(enable = "avx512fp16")]
27450    fn test_mm_maskz_cvt_roundsh_sd() {
27451        let a = _mm_setr_pd(2.0, 20.0);
27452        let b = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
27453        let r = _mm_maskz_cvt_roundsh_sd::<_MM_FROUND_NO_EXC>(0, a, b);
27454        let e = _mm_setr_pd(0.0, 20.0);
27455        assert_eq_m128d(r, e);
27456        let r = _mm_maskz_cvt_roundsh_sd::<_MM_FROUND_NO_EXC>(1, a, b);
27457        let e = _mm_setr_pd(1.0, 20.0);
27458        assert_eq_m128d(r, e);
27459    }
27460
27461    #[simd_test(enable = "avx512fp16")]
27462    const fn test_mm_cvtsh_h() {
27463        let a = _mm_setr_ph(1.0, 2.0, 3.0, 42.0, 5.0, 6.0, 7.0, 8.0);
27464        let r = _mm_cvtsh_h(a);
27465        assert_eq!(r, 1.0);
27466    }
27467
27468    #[simd_test(enable = "avx512fp16")]
27469    const fn test_mm256_cvtsh_h() {
27470        let a = _mm256_setr_ph(
27471            1.0, 2.0, 3.0, 42.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
27472        );
27473        let r = _mm256_cvtsh_h(a);
27474        assert_eq!(r, 1.0);
27475    }
27476
27477    #[simd_test(enable = "avx512fp16")]
27478    const fn test_mm512_cvtsh_h() {
27479        let a = _mm512_setr_ph(
27480            1.0, 2.0, 3.0, 42.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
27481            17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
27482            31.0, 32.0,
27483        );
27484        let r = _mm512_cvtsh_h(a);
27485        assert_eq!(r, 1.0);
27486    }
27487
27488    #[simd_test(enable = "avx512fp16")]
27489    const fn test_mm_cvtsi128_si16() {
27490        let a = _mm_setr_epi16(1, 2, 3, 4, 5, 6, 7, 8);
27491        let r = _mm_cvtsi128_si16(a);
27492        assert_eq!(r, 1);
27493    }
27494
27495    #[simd_test(enable = "avx512fp16")]
27496    const fn test_mm_cvtsi16_si128() {
27497        let a = 1;
27498        let r = _mm_cvtsi16_si128(a);
27499        let e = _mm_setr_epi16(1, 0, 0, 0, 0, 0, 0, 0);
27500        assert_eq_m128i(r, e);
27501    }
27502}
core/stdarch/crates/core_arch/src/x86/avx512fp16.rs

core/stdarch/crates/core_arch/src/x86/
avx512fp16.rs
