core/stdarch/crates/core_arch/src/hexagon/
scalar.rs

1//! Hexagon scalar intrinsics
2//!
3//! This module provides intrinsics for scalar (non-HVX) Hexagon DSP operations,
4//! including arithmetic, multiply, shift, saturate, compare, and floating-point
5//! operations.
6//!
7//! [Hexagon V68 Programmer's Reference Manual](https://docs.qualcomm.com/doc/80-N2040-45)
8//!
9//! ## Naming Convention
10//!
11//! Function names preserve the original Q6 naming case because the convention
12//! uses case to distinguish register types:
13//! - `P` (uppercase) = 64-bit register pair (`Word64`)
14//! - `p` (lowercase) = predicate register (`Byte`)
15//!
16//! For example, `Q6_P_and_PP` operates on 64-bit pairs while `Q6_p_and_pp`
17//! operates on predicate registers.
18//!
19//! ## Architecture Versions
20//!
21//! Most scalar intrinsics are available on all Hexagon architectures.
22//! Some intrinsics require specific architecture versions (v60, v62, v65,
23//! v66, v67, v68, or v67+audio) and carry
24//! `#[target_feature(enable = "v68")]` (or the appropriate version).
25//! Enable these with `-C target-feature=+v68` or by setting the target CPU
26//! via `-C target-cpu=hexagonv68`.
27//!
28//! Each version includes all features from previous versions.
29
30#![allow(non_snake_case)]
31
32#[cfg(test)]
33use stdarch_test::assert_instr;
34
35// LLVM intrinsic declarations for Hexagon scalar operations
36#[allow(improper_ctypes)]
37unsafe extern "unadjusted" {
38    #[link_name = "llvm.hexagon.A2.abs"]
39    fn hexagon_A2_abs(_: i32) -> i32;
40    #[link_name = "llvm.hexagon.A2.absp"]
41    fn hexagon_A2_absp(_: i64) -> i64;
42    #[link_name = "llvm.hexagon.A2.abssat"]
43    fn hexagon_A2_abssat(_: i32) -> i32;
44    #[link_name = "llvm.hexagon.A2.add"]
45    fn hexagon_A2_add(_: i32, _: i32) -> i32;
46    #[link_name = "llvm.hexagon.A2.addh.h16.hh"]
47    fn hexagon_A2_addh_h16_hh(_: i32, _: i32) -> i32;
48    #[link_name = "llvm.hexagon.A2.addh.h16.hl"]
49    fn hexagon_A2_addh_h16_hl(_: i32, _: i32) -> i32;
50    #[link_name = "llvm.hexagon.A2.addh.h16.lh"]
51    fn hexagon_A2_addh_h16_lh(_: i32, _: i32) -> i32;
52    #[link_name = "llvm.hexagon.A2.addh.h16.ll"]
53    fn hexagon_A2_addh_h16_ll(_: i32, _: i32) -> i32;
54    #[link_name = "llvm.hexagon.A2.addh.h16.sat.hh"]
55    fn hexagon_A2_addh_h16_sat_hh(_: i32, _: i32) -> i32;
56    #[link_name = "llvm.hexagon.A2.addh.h16.sat.hl"]
57    fn hexagon_A2_addh_h16_sat_hl(_: i32, _: i32) -> i32;
58    #[link_name = "llvm.hexagon.A2.addh.h16.sat.lh"]
59    fn hexagon_A2_addh_h16_sat_lh(_: i32, _: i32) -> i32;
60    #[link_name = "llvm.hexagon.A2.addh.h16.sat.ll"]
61    fn hexagon_A2_addh_h16_sat_ll(_: i32, _: i32) -> i32;
62    #[link_name = "llvm.hexagon.A2.addh.l16.hl"]
63    fn hexagon_A2_addh_l16_hl(_: i32, _: i32) -> i32;
64    #[link_name = "llvm.hexagon.A2.addh.l16.ll"]
65    fn hexagon_A2_addh_l16_ll(_: i32, _: i32) -> i32;
66    #[link_name = "llvm.hexagon.A2.addh.l16.sat.hl"]
67    fn hexagon_A2_addh_l16_sat_hl(_: i32, _: i32) -> i32;
68    #[link_name = "llvm.hexagon.A2.addh.l16.sat.ll"]
69    fn hexagon_A2_addh_l16_sat_ll(_: i32, _: i32) -> i32;
70    #[link_name = "llvm.hexagon.A2.addi"]
71    fn hexagon_A2_addi(_: i32, _: i32) -> i32;
72    #[link_name = "llvm.hexagon.A2.addp"]
73    fn hexagon_A2_addp(_: i64, _: i64) -> i64;
74    #[link_name = "llvm.hexagon.A2.addpsat"]
75    fn hexagon_A2_addpsat(_: i64, _: i64) -> i64;
76    #[link_name = "llvm.hexagon.A2.addsat"]
77    fn hexagon_A2_addsat(_: i32, _: i32) -> i32;
78    #[link_name = "llvm.hexagon.A2.addsp"]
79    fn hexagon_A2_addsp(_: i32, _: i64) -> i64;
80    #[link_name = "llvm.hexagon.A2.and"]
81    fn hexagon_A2_and(_: i32, _: i32) -> i32;
82    #[link_name = "llvm.hexagon.A2.andir"]
83    fn hexagon_A2_andir(_: i32, _: i32) -> i32;
84    #[link_name = "llvm.hexagon.A2.andp"]
85    fn hexagon_A2_andp(_: i64, _: i64) -> i64;
86    #[link_name = "llvm.hexagon.A2.aslh"]
87    fn hexagon_A2_aslh(_: i32) -> i32;
88    #[link_name = "llvm.hexagon.A2.asrh"]
89    fn hexagon_A2_asrh(_: i32) -> i32;
90    #[link_name = "llvm.hexagon.A2.combine.hh"]
91    fn hexagon_A2_combine_hh(_: i32, _: i32) -> i32;
92    #[link_name = "llvm.hexagon.A2.combine.hl"]
93    fn hexagon_A2_combine_hl(_: i32, _: i32) -> i32;
94    #[link_name = "llvm.hexagon.A2.combine.lh"]
95    fn hexagon_A2_combine_lh(_: i32, _: i32) -> i32;
96    #[link_name = "llvm.hexagon.A2.combine.ll"]
97    fn hexagon_A2_combine_ll(_: i32, _: i32) -> i32;
98    #[link_name = "llvm.hexagon.A2.combineii"]
99    fn hexagon_A2_combineii(_: i32, _: i32) -> i64;
100    #[link_name = "llvm.hexagon.A2.combinew"]
101    fn hexagon_A2_combinew(_: i32, _: i32) -> i64;
102    #[link_name = "llvm.hexagon.A2.max"]
103    fn hexagon_A2_max(_: i32, _: i32) -> i32;
104    #[link_name = "llvm.hexagon.A2.maxp"]
105    fn hexagon_A2_maxp(_: i64, _: i64) -> i64;
106    #[link_name = "llvm.hexagon.A2.maxu"]
107    fn hexagon_A2_maxu(_: i32, _: i32) -> i32;
108    #[link_name = "llvm.hexagon.A2.maxup"]
109    fn hexagon_A2_maxup(_: i64, _: i64) -> i64;
110    #[link_name = "llvm.hexagon.A2.min"]
111    fn hexagon_A2_min(_: i32, _: i32) -> i32;
112    #[link_name = "llvm.hexagon.A2.minp"]
113    fn hexagon_A2_minp(_: i64, _: i64) -> i64;
114    #[link_name = "llvm.hexagon.A2.minu"]
115    fn hexagon_A2_minu(_: i32, _: i32) -> i32;
116    #[link_name = "llvm.hexagon.A2.minup"]
117    fn hexagon_A2_minup(_: i64, _: i64) -> i64;
118    #[link_name = "llvm.hexagon.A2.neg"]
119    fn hexagon_A2_neg(_: i32) -> i32;
120    #[link_name = "llvm.hexagon.A2.negp"]
121    fn hexagon_A2_negp(_: i64) -> i64;
122    #[link_name = "llvm.hexagon.A2.negsat"]
123    fn hexagon_A2_negsat(_: i32) -> i32;
124    #[link_name = "llvm.hexagon.A2.not"]
125    fn hexagon_A2_not(_: i32) -> i32;
126    #[link_name = "llvm.hexagon.A2.notp"]
127    fn hexagon_A2_notp(_: i64) -> i64;
128    #[link_name = "llvm.hexagon.A2.or"]
129    fn hexagon_A2_or(_: i32, _: i32) -> i32;
130    #[link_name = "llvm.hexagon.A2.orir"]
131    fn hexagon_A2_orir(_: i32, _: i32) -> i32;
132    #[link_name = "llvm.hexagon.A2.orp"]
133    fn hexagon_A2_orp(_: i64, _: i64) -> i64;
134    #[link_name = "llvm.hexagon.A2.roundsat"]
135    fn hexagon_A2_roundsat(_: i64) -> i32;
136    #[link_name = "llvm.hexagon.A2.sat"]
137    fn hexagon_A2_sat(_: i64) -> i32;
138    #[link_name = "llvm.hexagon.A2.satb"]
139    fn hexagon_A2_satb(_: i32) -> i32;
140    #[link_name = "llvm.hexagon.A2.sath"]
141    fn hexagon_A2_sath(_: i32) -> i32;
142    #[link_name = "llvm.hexagon.A2.satub"]
143    fn hexagon_A2_satub(_: i32) -> i32;
144    #[link_name = "llvm.hexagon.A2.satuh"]
145    fn hexagon_A2_satuh(_: i32) -> i32;
146    #[link_name = "llvm.hexagon.A2.sub"]
147    fn hexagon_A2_sub(_: i32, _: i32) -> i32;
148    #[link_name = "llvm.hexagon.A2.subh.h16.hh"]
149    fn hexagon_A2_subh_h16_hh(_: i32, _: i32) -> i32;
150    #[link_name = "llvm.hexagon.A2.subh.h16.hl"]
151    fn hexagon_A2_subh_h16_hl(_: i32, _: i32) -> i32;
152    #[link_name = "llvm.hexagon.A2.subh.h16.lh"]
153    fn hexagon_A2_subh_h16_lh(_: i32, _: i32) -> i32;
154    #[link_name = "llvm.hexagon.A2.subh.h16.ll"]
155    fn hexagon_A2_subh_h16_ll(_: i32, _: i32) -> i32;
156    #[link_name = "llvm.hexagon.A2.subh.h16.sat.hh"]
157    fn hexagon_A2_subh_h16_sat_hh(_: i32, _: i32) -> i32;
158    #[link_name = "llvm.hexagon.A2.subh.h16.sat.hl"]
159    fn hexagon_A2_subh_h16_sat_hl(_: i32, _: i32) -> i32;
160    #[link_name = "llvm.hexagon.A2.subh.h16.sat.lh"]
161    fn hexagon_A2_subh_h16_sat_lh(_: i32, _: i32) -> i32;
162    #[link_name = "llvm.hexagon.A2.subh.h16.sat.ll"]
163    fn hexagon_A2_subh_h16_sat_ll(_: i32, _: i32) -> i32;
164    #[link_name = "llvm.hexagon.A2.subh.l16.hl"]
165    fn hexagon_A2_subh_l16_hl(_: i32, _: i32) -> i32;
166    #[link_name = "llvm.hexagon.A2.subh.l16.ll"]
167    fn hexagon_A2_subh_l16_ll(_: i32, _: i32) -> i32;
168    #[link_name = "llvm.hexagon.A2.subh.l16.sat.hl"]
169    fn hexagon_A2_subh_l16_sat_hl(_: i32, _: i32) -> i32;
170    #[link_name = "llvm.hexagon.A2.subh.l16.sat.ll"]
171    fn hexagon_A2_subh_l16_sat_ll(_: i32, _: i32) -> i32;
172    #[link_name = "llvm.hexagon.A2.subp"]
173    fn hexagon_A2_subp(_: i64, _: i64) -> i64;
174    #[link_name = "llvm.hexagon.A2.subri"]
175    fn hexagon_A2_subri(_: i32, _: i32) -> i32;
176    #[link_name = "llvm.hexagon.A2.subsat"]
177    fn hexagon_A2_subsat(_: i32, _: i32) -> i32;
178    #[link_name = "llvm.hexagon.A2.svaddh"]
179    fn hexagon_A2_svaddh(_: i32, _: i32) -> i32;
180    #[link_name = "llvm.hexagon.A2.svaddhs"]
181    fn hexagon_A2_svaddhs(_: i32, _: i32) -> i32;
182    #[link_name = "llvm.hexagon.A2.svadduhs"]
183    fn hexagon_A2_svadduhs(_: i32, _: i32) -> i32;
184    #[link_name = "llvm.hexagon.A2.svavgh"]
185    fn hexagon_A2_svavgh(_: i32, _: i32) -> i32;
186    #[link_name = "llvm.hexagon.A2.svavghs"]
187    fn hexagon_A2_svavghs(_: i32, _: i32) -> i32;
188    #[link_name = "llvm.hexagon.A2.svnavgh"]
189    fn hexagon_A2_svnavgh(_: i32, _: i32) -> i32;
190    #[link_name = "llvm.hexagon.A2.svsubh"]
191    fn hexagon_A2_svsubh(_: i32, _: i32) -> i32;
192    #[link_name = "llvm.hexagon.A2.svsubhs"]
193    fn hexagon_A2_svsubhs(_: i32, _: i32) -> i32;
194    #[link_name = "llvm.hexagon.A2.svsubuhs"]
195    fn hexagon_A2_svsubuhs(_: i32, _: i32) -> i32;
196    #[link_name = "llvm.hexagon.A2.swiz"]
197    fn hexagon_A2_swiz(_: i32) -> i32;
198    #[link_name = "llvm.hexagon.A2.sxtb"]
199    fn hexagon_A2_sxtb(_: i32) -> i32;
200    #[link_name = "llvm.hexagon.A2.sxth"]
201    fn hexagon_A2_sxth(_: i32) -> i32;
202    #[link_name = "llvm.hexagon.A2.sxtw"]
203    fn hexagon_A2_sxtw(_: i32) -> i64;
204    #[link_name = "llvm.hexagon.A2.tfr"]
205    fn hexagon_A2_tfr(_: i32) -> i32;
206    #[link_name = "llvm.hexagon.A2.tfrih"]
207    fn hexagon_A2_tfrih(_: i32, _: i32) -> i32;
208    #[link_name = "llvm.hexagon.A2.tfril"]
209    fn hexagon_A2_tfril(_: i32, _: i32) -> i32;
210    #[link_name = "llvm.hexagon.A2.tfrp"]
211    fn hexagon_A2_tfrp(_: i64) -> i64;
212    #[link_name = "llvm.hexagon.A2.tfrpi"]
213    fn hexagon_A2_tfrpi(_: i32) -> i64;
214    #[link_name = "llvm.hexagon.A2.tfrsi"]
215    fn hexagon_A2_tfrsi(_: i32) -> i32;
216    #[link_name = "llvm.hexagon.A2.vabsh"]
217    fn hexagon_A2_vabsh(_: i64) -> i64;
218    #[link_name = "llvm.hexagon.A2.vabshsat"]
219    fn hexagon_A2_vabshsat(_: i64) -> i64;
220    #[link_name = "llvm.hexagon.A2.vabsw"]
221    fn hexagon_A2_vabsw(_: i64) -> i64;
222    #[link_name = "llvm.hexagon.A2.vabswsat"]
223    fn hexagon_A2_vabswsat(_: i64) -> i64;
224    #[link_name = "llvm.hexagon.A2.vaddb.map"]
225    fn hexagon_A2_vaddb_map(_: i64, _: i64) -> i64;
226    #[link_name = "llvm.hexagon.A2.vaddh"]
227    fn hexagon_A2_vaddh(_: i64, _: i64) -> i64;
228    #[link_name = "llvm.hexagon.A2.vaddhs"]
229    fn hexagon_A2_vaddhs(_: i64, _: i64) -> i64;
230    #[link_name = "llvm.hexagon.A2.vaddub"]
231    fn hexagon_A2_vaddub(_: i64, _: i64) -> i64;
232    #[link_name = "llvm.hexagon.A2.vaddubs"]
233    fn hexagon_A2_vaddubs(_: i64, _: i64) -> i64;
234    #[link_name = "llvm.hexagon.A2.vadduhs"]
235    fn hexagon_A2_vadduhs(_: i64, _: i64) -> i64;
236    #[link_name = "llvm.hexagon.A2.vaddw"]
237    fn hexagon_A2_vaddw(_: i64, _: i64) -> i64;
238    #[link_name = "llvm.hexagon.A2.vaddws"]
239    fn hexagon_A2_vaddws(_: i64, _: i64) -> i64;
240    #[link_name = "llvm.hexagon.A2.vavgh"]
241    fn hexagon_A2_vavgh(_: i64, _: i64) -> i64;
242    #[link_name = "llvm.hexagon.A2.vavghcr"]
243    fn hexagon_A2_vavghcr(_: i64, _: i64) -> i64;
244    #[link_name = "llvm.hexagon.A2.vavghr"]
245    fn hexagon_A2_vavghr(_: i64, _: i64) -> i64;
246    #[link_name = "llvm.hexagon.A2.vavgub"]
247    fn hexagon_A2_vavgub(_: i64, _: i64) -> i64;
248    #[link_name = "llvm.hexagon.A2.vavgubr"]
249    fn hexagon_A2_vavgubr(_: i64, _: i64) -> i64;
250    #[link_name = "llvm.hexagon.A2.vavguh"]
251    fn hexagon_A2_vavguh(_: i64, _: i64) -> i64;
252    #[link_name = "llvm.hexagon.A2.vavguhr"]
253    fn hexagon_A2_vavguhr(_: i64, _: i64) -> i64;
254    #[link_name = "llvm.hexagon.A2.vavguw"]
255    fn hexagon_A2_vavguw(_: i64, _: i64) -> i64;
256    #[link_name = "llvm.hexagon.A2.vavguwr"]
257    fn hexagon_A2_vavguwr(_: i64, _: i64) -> i64;
258    #[link_name = "llvm.hexagon.A2.vavgw"]
259    fn hexagon_A2_vavgw(_: i64, _: i64) -> i64;
260    #[link_name = "llvm.hexagon.A2.vavgwcr"]
261    fn hexagon_A2_vavgwcr(_: i64, _: i64) -> i64;
262    #[link_name = "llvm.hexagon.A2.vavgwr"]
263    fn hexagon_A2_vavgwr(_: i64, _: i64) -> i64;
264    #[link_name = "llvm.hexagon.A2.vcmpbeq"]
265    fn hexagon_A2_vcmpbeq(_: i64, _: i64) -> i32;
266    #[link_name = "llvm.hexagon.A2.vcmpbgtu"]
267    fn hexagon_A2_vcmpbgtu(_: i64, _: i64) -> i32;
268    #[link_name = "llvm.hexagon.A2.vcmpheq"]
269    fn hexagon_A2_vcmpheq(_: i64, _: i64) -> i32;
270    #[link_name = "llvm.hexagon.A2.vcmphgt"]
271    fn hexagon_A2_vcmphgt(_: i64, _: i64) -> i32;
272    #[link_name = "llvm.hexagon.A2.vcmphgtu"]
273    fn hexagon_A2_vcmphgtu(_: i64, _: i64) -> i32;
274    #[link_name = "llvm.hexagon.A2.vcmpweq"]
275    fn hexagon_A2_vcmpweq(_: i64, _: i64) -> i32;
276    #[link_name = "llvm.hexagon.A2.vcmpwgt"]
277    fn hexagon_A2_vcmpwgt(_: i64, _: i64) -> i32;
278    #[link_name = "llvm.hexagon.A2.vcmpwgtu"]
279    fn hexagon_A2_vcmpwgtu(_: i64, _: i64) -> i32;
280    #[link_name = "llvm.hexagon.A2.vconj"]
281    fn hexagon_A2_vconj(_: i64) -> i64;
282    #[link_name = "llvm.hexagon.A2.vmaxb"]
283    fn hexagon_A2_vmaxb(_: i64, _: i64) -> i64;
284    #[link_name = "llvm.hexagon.A2.vmaxh"]
285    fn hexagon_A2_vmaxh(_: i64, _: i64) -> i64;
286    #[link_name = "llvm.hexagon.A2.vmaxub"]
287    fn hexagon_A2_vmaxub(_: i64, _: i64) -> i64;
288    #[link_name = "llvm.hexagon.A2.vmaxuh"]
289    fn hexagon_A2_vmaxuh(_: i64, _: i64) -> i64;
290    #[link_name = "llvm.hexagon.A2.vmaxuw"]
291    fn hexagon_A2_vmaxuw(_: i64, _: i64) -> i64;
292    #[link_name = "llvm.hexagon.A2.vmaxw"]
293    fn hexagon_A2_vmaxw(_: i64, _: i64) -> i64;
294    #[link_name = "llvm.hexagon.A2.vminb"]
295    fn hexagon_A2_vminb(_: i64, _: i64) -> i64;
296    #[link_name = "llvm.hexagon.A2.vminh"]
297    fn hexagon_A2_vminh(_: i64, _: i64) -> i64;
298    #[link_name = "llvm.hexagon.A2.vminub"]
299    fn hexagon_A2_vminub(_: i64, _: i64) -> i64;
300    #[link_name = "llvm.hexagon.A2.vminuh"]
301    fn hexagon_A2_vminuh(_: i64, _: i64) -> i64;
302    #[link_name = "llvm.hexagon.A2.vminuw"]
303    fn hexagon_A2_vminuw(_: i64, _: i64) -> i64;
304    #[link_name = "llvm.hexagon.A2.vminw"]
305    fn hexagon_A2_vminw(_: i64, _: i64) -> i64;
306    #[link_name = "llvm.hexagon.A2.vnavgh"]
307    fn hexagon_A2_vnavgh(_: i64, _: i64) -> i64;
308    #[link_name = "llvm.hexagon.A2.vnavghcr"]
309    fn hexagon_A2_vnavghcr(_: i64, _: i64) -> i64;
310    #[link_name = "llvm.hexagon.A2.vnavghr"]
311    fn hexagon_A2_vnavghr(_: i64, _: i64) -> i64;
312    #[link_name = "llvm.hexagon.A2.vnavgw"]
313    fn hexagon_A2_vnavgw(_: i64, _: i64) -> i64;
314    #[link_name = "llvm.hexagon.A2.vnavgwcr"]
315    fn hexagon_A2_vnavgwcr(_: i64, _: i64) -> i64;
316    #[link_name = "llvm.hexagon.A2.vnavgwr"]
317    fn hexagon_A2_vnavgwr(_: i64, _: i64) -> i64;
318    #[link_name = "llvm.hexagon.A2.vraddub"]
319    fn hexagon_A2_vraddub(_: i64, _: i64) -> i64;
320    #[link_name = "llvm.hexagon.A2.vraddub.acc"]
321    fn hexagon_A2_vraddub_acc(_: i64, _: i64, _: i64) -> i64;
322    #[link_name = "llvm.hexagon.A2.vrsadub"]
323    fn hexagon_A2_vrsadub(_: i64, _: i64) -> i64;
324    #[link_name = "llvm.hexagon.A2.vrsadub.acc"]
325    fn hexagon_A2_vrsadub_acc(_: i64, _: i64, _: i64) -> i64;
326    #[link_name = "llvm.hexagon.A2.vsubb.map"]
327    fn hexagon_A2_vsubb_map(_: i64, _: i64) -> i64;
328    #[link_name = "llvm.hexagon.A2.vsubh"]
329    fn hexagon_A2_vsubh(_: i64, _: i64) -> i64;
330    #[link_name = "llvm.hexagon.A2.vsubhs"]
331    fn hexagon_A2_vsubhs(_: i64, _: i64) -> i64;
332    #[link_name = "llvm.hexagon.A2.vsubub"]
333    fn hexagon_A2_vsubub(_: i64, _: i64) -> i64;
334    #[link_name = "llvm.hexagon.A2.vsububs"]
335    fn hexagon_A2_vsububs(_: i64, _: i64) -> i64;
336    #[link_name = "llvm.hexagon.A2.vsubuhs"]
337    fn hexagon_A2_vsubuhs(_: i64, _: i64) -> i64;
338    #[link_name = "llvm.hexagon.A2.vsubw"]
339    fn hexagon_A2_vsubw(_: i64, _: i64) -> i64;
340    #[link_name = "llvm.hexagon.A2.vsubws"]
341    fn hexagon_A2_vsubws(_: i64, _: i64) -> i64;
342    #[link_name = "llvm.hexagon.A2.xor"]
343    fn hexagon_A2_xor(_: i32, _: i32) -> i32;
344    #[link_name = "llvm.hexagon.A2.xorp"]
345    fn hexagon_A2_xorp(_: i64, _: i64) -> i64;
346    #[link_name = "llvm.hexagon.A2.zxtb"]
347    fn hexagon_A2_zxtb(_: i32) -> i32;
348    #[link_name = "llvm.hexagon.A2.zxth"]
349    fn hexagon_A2_zxth(_: i32) -> i32;
350    #[link_name = "llvm.hexagon.A4.andn"]
351    fn hexagon_A4_andn(_: i32, _: i32) -> i32;
352    #[link_name = "llvm.hexagon.A4.andnp"]
353    fn hexagon_A4_andnp(_: i64, _: i64) -> i64;
354    #[link_name = "llvm.hexagon.A4.bitsplit"]
355    fn hexagon_A4_bitsplit(_: i32, _: i32) -> i64;
356    #[link_name = "llvm.hexagon.A4.bitspliti"]
357    fn hexagon_A4_bitspliti(_: i32, _: i32) -> i64;
358    #[link_name = "llvm.hexagon.A4.boundscheck"]
359    fn hexagon_A4_boundscheck(_: i32, _: i64) -> i32;
360    #[link_name = "llvm.hexagon.A4.cmpbeq"]
361    fn hexagon_A4_cmpbeq(_: i32, _: i32) -> i32;
362    #[link_name = "llvm.hexagon.A4.cmpbeqi"]
363    fn hexagon_A4_cmpbeqi(_: i32, _: i32) -> i32;
364    #[link_name = "llvm.hexagon.A4.cmpbgt"]
365    fn hexagon_A4_cmpbgt(_: i32, _: i32) -> i32;
366    #[link_name = "llvm.hexagon.A4.cmpbgti"]
367    fn hexagon_A4_cmpbgti(_: i32, _: i32) -> i32;
368    #[link_name = "llvm.hexagon.A4.cmpbgtu"]
369    fn hexagon_A4_cmpbgtu(_: i32, _: i32) -> i32;
370    #[link_name = "llvm.hexagon.A4.cmpbgtui"]
371    fn hexagon_A4_cmpbgtui(_: i32, _: i32) -> i32;
372    #[link_name = "llvm.hexagon.A4.cmpheq"]
373    fn hexagon_A4_cmpheq(_: i32, _: i32) -> i32;
374    #[link_name = "llvm.hexagon.A4.cmpheqi"]
375    fn hexagon_A4_cmpheqi(_: i32, _: i32) -> i32;
376    #[link_name = "llvm.hexagon.A4.cmphgt"]
377    fn hexagon_A4_cmphgt(_: i32, _: i32) -> i32;
378    #[link_name = "llvm.hexagon.A4.cmphgti"]
379    fn hexagon_A4_cmphgti(_: i32, _: i32) -> i32;
380    #[link_name = "llvm.hexagon.A4.cmphgtu"]
381    fn hexagon_A4_cmphgtu(_: i32, _: i32) -> i32;
382    #[link_name = "llvm.hexagon.A4.cmphgtui"]
383    fn hexagon_A4_cmphgtui(_: i32, _: i32) -> i32;
384    #[link_name = "llvm.hexagon.A4.combineir"]
385    fn hexagon_A4_combineir(_: i32, _: i32) -> i64;
386    #[link_name = "llvm.hexagon.A4.combineri"]
387    fn hexagon_A4_combineri(_: i32, _: i32) -> i64;
388    #[link_name = "llvm.hexagon.A4.cround.ri"]
389    fn hexagon_A4_cround_ri(_: i32, _: i32) -> i32;
390    #[link_name = "llvm.hexagon.A4.cround.rr"]
391    fn hexagon_A4_cround_rr(_: i32, _: i32) -> i32;
392    #[link_name = "llvm.hexagon.A4.modwrapu"]
393    fn hexagon_A4_modwrapu(_: i32, _: i32) -> i32;
394    #[link_name = "llvm.hexagon.A4.orn"]
395    fn hexagon_A4_orn(_: i32, _: i32) -> i32;
396    #[link_name = "llvm.hexagon.A4.ornp"]
397    fn hexagon_A4_ornp(_: i64, _: i64) -> i64;
398    #[link_name = "llvm.hexagon.A4.rcmpeq"]
399    fn hexagon_A4_rcmpeq(_: i32, _: i32) -> i32;
400    #[link_name = "llvm.hexagon.A4.rcmpeqi"]
401    fn hexagon_A4_rcmpeqi(_: i32, _: i32) -> i32;
402    #[link_name = "llvm.hexagon.A4.rcmpneq"]
403    fn hexagon_A4_rcmpneq(_: i32, _: i32) -> i32;
404    #[link_name = "llvm.hexagon.A4.rcmpneqi"]
405    fn hexagon_A4_rcmpneqi(_: i32, _: i32) -> i32;
406    #[link_name = "llvm.hexagon.A4.round.ri"]
407    fn hexagon_A4_round_ri(_: i32, _: i32) -> i32;
408    #[link_name = "llvm.hexagon.A4.round.ri.sat"]
409    fn hexagon_A4_round_ri_sat(_: i32, _: i32) -> i32;
410    #[link_name = "llvm.hexagon.A4.round.rr"]
411    fn hexagon_A4_round_rr(_: i32, _: i32) -> i32;
412    #[link_name = "llvm.hexagon.A4.round.rr.sat"]
413    fn hexagon_A4_round_rr_sat(_: i32, _: i32) -> i32;
414    #[link_name = "llvm.hexagon.A4.tlbmatch"]
415    fn hexagon_A4_tlbmatch(_: i64, _: i32) -> i32;
416    #[link_name = "llvm.hexagon.A4.vcmpbeq.any"]
417    fn hexagon_A4_vcmpbeq_any(_: i64, _: i64) -> i32;
418    #[link_name = "llvm.hexagon.A4.vcmpbeqi"]
419    fn hexagon_A4_vcmpbeqi(_: i64, _: i32) -> i32;
420    #[link_name = "llvm.hexagon.A4.vcmpbgt"]
421    fn hexagon_A4_vcmpbgt(_: i64, _: i64) -> i32;
422    #[link_name = "llvm.hexagon.A4.vcmpbgti"]
423    fn hexagon_A4_vcmpbgti(_: i64, _: i32) -> i32;
424    #[link_name = "llvm.hexagon.A4.vcmpbgtui"]
425    fn hexagon_A4_vcmpbgtui(_: i64, _: i32) -> i32;
426    #[link_name = "llvm.hexagon.A4.vcmpheqi"]
427    fn hexagon_A4_vcmpheqi(_: i64, _: i32) -> i32;
428    #[link_name = "llvm.hexagon.A4.vcmphgti"]
429    fn hexagon_A4_vcmphgti(_: i64, _: i32) -> i32;
430    #[link_name = "llvm.hexagon.A4.vcmphgtui"]
431    fn hexagon_A4_vcmphgtui(_: i64, _: i32) -> i32;
432    #[link_name = "llvm.hexagon.A4.vcmpweqi"]
433    fn hexagon_A4_vcmpweqi(_: i64, _: i32) -> i32;
434    #[link_name = "llvm.hexagon.A4.vcmpwgti"]
435    fn hexagon_A4_vcmpwgti(_: i64, _: i32) -> i32;
436    #[link_name = "llvm.hexagon.A4.vcmpwgtui"]
437    fn hexagon_A4_vcmpwgtui(_: i64, _: i32) -> i32;
438    #[link_name = "llvm.hexagon.A4.vrmaxh"]
439    fn hexagon_A4_vrmaxh(_: i64, _: i64, _: i32) -> i64;
440    #[link_name = "llvm.hexagon.A4.vrmaxuh"]
441    fn hexagon_A4_vrmaxuh(_: i64, _: i64, _: i32) -> i64;
442    #[link_name = "llvm.hexagon.A4.vrmaxuw"]
443    fn hexagon_A4_vrmaxuw(_: i64, _: i64, _: i32) -> i64;
444    #[link_name = "llvm.hexagon.A4.vrmaxw"]
445    fn hexagon_A4_vrmaxw(_: i64, _: i64, _: i32) -> i64;
446    #[link_name = "llvm.hexagon.A4.vrminh"]
447    fn hexagon_A4_vrminh(_: i64, _: i64, _: i32) -> i64;
448    #[link_name = "llvm.hexagon.A4.vrminuh"]
449    fn hexagon_A4_vrminuh(_: i64, _: i64, _: i32) -> i64;
450    #[link_name = "llvm.hexagon.A4.vrminuw"]
451    fn hexagon_A4_vrminuw(_: i64, _: i64, _: i32) -> i64;
452    #[link_name = "llvm.hexagon.A4.vrminw"]
453    fn hexagon_A4_vrminw(_: i64, _: i64, _: i32) -> i64;
454    #[link_name = "llvm.hexagon.A5.vaddhubs"]
455    fn hexagon_A5_vaddhubs(_: i64, _: i64) -> i32;
456    #[link_name = "llvm.hexagon.C2.all8"]
457    fn hexagon_C2_all8(_: i32) -> i32;
458    #[link_name = "llvm.hexagon.C2.and"]
459    fn hexagon_C2_and(_: i32, _: i32) -> i32;
460    #[link_name = "llvm.hexagon.C2.andn"]
461    fn hexagon_C2_andn(_: i32, _: i32) -> i32;
462    #[link_name = "llvm.hexagon.C2.any8"]
463    fn hexagon_C2_any8(_: i32) -> i32;
464    #[link_name = "llvm.hexagon.C2.bitsclr"]
465    fn hexagon_C2_bitsclr(_: i32, _: i32) -> i32;
466    #[link_name = "llvm.hexagon.C2.bitsclri"]
467    fn hexagon_C2_bitsclri(_: i32, _: i32) -> i32;
468    #[link_name = "llvm.hexagon.C2.bitsset"]
469    fn hexagon_C2_bitsset(_: i32, _: i32) -> i32;
470    #[link_name = "llvm.hexagon.C2.cmpeq"]
471    fn hexagon_C2_cmpeq(_: i32, _: i32) -> i32;
472    #[link_name = "llvm.hexagon.C2.cmpeqi"]
473    fn hexagon_C2_cmpeqi(_: i32, _: i32) -> i32;
474    #[link_name = "llvm.hexagon.C2.cmpeqp"]
475    fn hexagon_C2_cmpeqp(_: i64, _: i64) -> i32;
476    #[link_name = "llvm.hexagon.C2.cmpgei"]
477    fn hexagon_C2_cmpgei(_: i32, _: i32) -> i32;
478    #[link_name = "llvm.hexagon.C2.cmpgeui"]
479    fn hexagon_C2_cmpgeui(_: i32, _: i32) -> i32;
480    #[link_name = "llvm.hexagon.C2.cmpgt"]
481    fn hexagon_C2_cmpgt(_: i32, _: i32) -> i32;
482    #[link_name = "llvm.hexagon.C2.cmpgti"]
483    fn hexagon_C2_cmpgti(_: i32, _: i32) -> i32;
484    #[link_name = "llvm.hexagon.C2.cmpgtp"]
485    fn hexagon_C2_cmpgtp(_: i64, _: i64) -> i32;
486    #[link_name = "llvm.hexagon.C2.cmpgtu"]
487    fn hexagon_C2_cmpgtu(_: i32, _: i32) -> i32;
488    #[link_name = "llvm.hexagon.C2.cmpgtui"]
489    fn hexagon_C2_cmpgtui(_: i32, _: i32) -> i32;
490    #[link_name = "llvm.hexagon.C2.cmpgtup"]
491    fn hexagon_C2_cmpgtup(_: i64, _: i64) -> i32;
492    #[link_name = "llvm.hexagon.C2.cmplt"]
493    fn hexagon_C2_cmplt(_: i32, _: i32) -> i32;
494    #[link_name = "llvm.hexagon.C2.cmpltu"]
495    fn hexagon_C2_cmpltu(_: i32, _: i32) -> i32;
496    #[link_name = "llvm.hexagon.C2.mask"]
497    fn hexagon_C2_mask(_: i32) -> i64;
498    #[link_name = "llvm.hexagon.C2.mux"]
499    fn hexagon_C2_mux(_: i32, _: i32, _: i32) -> i32;
500    #[link_name = "llvm.hexagon.C2.muxii"]
501    fn hexagon_C2_muxii(_: i32, _: i32, _: i32) -> i32;
502    #[link_name = "llvm.hexagon.C2.muxir"]
503    fn hexagon_C2_muxir(_: i32, _: i32, _: i32) -> i32;
504    #[link_name = "llvm.hexagon.C2.muxri"]
505    fn hexagon_C2_muxri(_: i32, _: i32, _: i32) -> i32;
506    #[link_name = "llvm.hexagon.C2.not"]
507    fn hexagon_C2_not(_: i32) -> i32;
508    #[link_name = "llvm.hexagon.C2.or"]
509    fn hexagon_C2_or(_: i32, _: i32) -> i32;
510    #[link_name = "llvm.hexagon.C2.orn"]
511    fn hexagon_C2_orn(_: i32, _: i32) -> i32;
512    #[link_name = "llvm.hexagon.C2.pxfer.map"]
513    fn hexagon_C2_pxfer_map(_: i32) -> i32;
514    #[link_name = "llvm.hexagon.C2.tfrpr"]
515    fn hexagon_C2_tfrpr(_: i32) -> i32;
516    #[link_name = "llvm.hexagon.C2.tfrrp"]
517    fn hexagon_C2_tfrrp(_: i32) -> i32;
518    #[link_name = "llvm.hexagon.C2.vitpack"]
519    fn hexagon_C2_vitpack(_: i32, _: i32) -> i32;
520    #[link_name = "llvm.hexagon.C2.vmux"]
521    fn hexagon_C2_vmux(_: i32, _: i64, _: i64) -> i64;
522    #[link_name = "llvm.hexagon.C2.xor"]
523    fn hexagon_C2_xor(_: i32, _: i32) -> i32;
524    #[link_name = "llvm.hexagon.C4.and.and"]
525    fn hexagon_C4_and_and(_: i32, _: i32, _: i32) -> i32;
526    #[link_name = "llvm.hexagon.C4.and.andn"]
527    fn hexagon_C4_and_andn(_: i32, _: i32, _: i32) -> i32;
528    #[link_name = "llvm.hexagon.C4.and.or"]
529    fn hexagon_C4_and_or(_: i32, _: i32, _: i32) -> i32;
530    #[link_name = "llvm.hexagon.C4.and.orn"]
531    fn hexagon_C4_and_orn(_: i32, _: i32, _: i32) -> i32;
532    #[link_name = "llvm.hexagon.C4.cmplte"]
533    fn hexagon_C4_cmplte(_: i32, _: i32) -> i32;
534    #[link_name = "llvm.hexagon.C4.cmpltei"]
535    fn hexagon_C4_cmpltei(_: i32, _: i32) -> i32;
536    #[link_name = "llvm.hexagon.C4.cmplteu"]
537    fn hexagon_C4_cmplteu(_: i32, _: i32) -> i32;
538    #[link_name = "llvm.hexagon.C4.cmplteui"]
539    fn hexagon_C4_cmplteui(_: i32, _: i32) -> i32;
540    #[link_name = "llvm.hexagon.C4.cmpneq"]
541    fn hexagon_C4_cmpneq(_: i32, _: i32) -> i32;
542    #[link_name = "llvm.hexagon.C4.cmpneqi"]
543    fn hexagon_C4_cmpneqi(_: i32, _: i32) -> i32;
544    #[link_name = "llvm.hexagon.C4.fastcorner9"]
545    fn hexagon_C4_fastcorner9(_: i32, _: i32) -> i32;
546    #[link_name = "llvm.hexagon.C4.fastcorner9.not"]
547    fn hexagon_C4_fastcorner9_not(_: i32, _: i32) -> i32;
548    #[link_name = "llvm.hexagon.C4.nbitsclr"]
549    fn hexagon_C4_nbitsclr(_: i32, _: i32) -> i32;
550    #[link_name = "llvm.hexagon.C4.nbitsclri"]
551    fn hexagon_C4_nbitsclri(_: i32, _: i32) -> i32;
552    #[link_name = "llvm.hexagon.C4.nbitsset"]
553    fn hexagon_C4_nbitsset(_: i32, _: i32) -> i32;
554    #[link_name = "llvm.hexagon.C4.or.and"]
555    fn hexagon_C4_or_and(_: i32, _: i32, _: i32) -> i32;
556    #[link_name = "llvm.hexagon.C4.or.andn"]
557    fn hexagon_C4_or_andn(_: i32, _: i32, _: i32) -> i32;
558    #[link_name = "llvm.hexagon.C4.or.or"]
559    fn hexagon_C4_or_or(_: i32, _: i32, _: i32) -> i32;
560    #[link_name = "llvm.hexagon.C4.or.orn"]
561    fn hexagon_C4_or_orn(_: i32, _: i32, _: i32) -> i32;
562    #[link_name = "llvm.hexagon.F2.conv.d2df"]
563    fn hexagon_F2_conv_d2df(_: i64) -> f64;
564    #[link_name = "llvm.hexagon.F2.conv.d2sf"]
565    fn hexagon_F2_conv_d2sf(_: i64) -> f32;
566    #[link_name = "llvm.hexagon.F2.conv.df2d"]
567    fn hexagon_F2_conv_df2d(_: f64) -> i64;
568    #[link_name = "llvm.hexagon.F2.conv.df2d.chop"]
569    fn hexagon_F2_conv_df2d_chop(_: f64) -> i64;
570    #[link_name = "llvm.hexagon.F2.conv.df2sf"]
571    fn hexagon_F2_conv_df2sf(_: f64) -> f32;
572    #[link_name = "llvm.hexagon.F2.conv.df2ud"]
573    fn hexagon_F2_conv_df2ud(_: f64) -> i64;
574    #[link_name = "llvm.hexagon.F2.conv.df2ud.chop"]
575    fn hexagon_F2_conv_df2ud_chop(_: f64) -> i64;
576    #[link_name = "llvm.hexagon.F2.conv.df2uw"]
577    fn hexagon_F2_conv_df2uw(_: f64) -> i32;
578    #[link_name = "llvm.hexagon.F2.conv.df2uw.chop"]
579    fn hexagon_F2_conv_df2uw_chop(_: f64) -> i32;
580    #[link_name = "llvm.hexagon.F2.conv.df2w"]
581    fn hexagon_F2_conv_df2w(_: f64) -> i32;
582    #[link_name = "llvm.hexagon.F2.conv.df2w.chop"]
583    fn hexagon_F2_conv_df2w_chop(_: f64) -> i32;
584    #[link_name = "llvm.hexagon.F2.conv.sf2d"]
585    fn hexagon_F2_conv_sf2d(_: f32) -> i64;
586    #[link_name = "llvm.hexagon.F2.conv.sf2d.chop"]
587    fn hexagon_F2_conv_sf2d_chop(_: f32) -> i64;
588    #[link_name = "llvm.hexagon.F2.conv.sf2df"]
589    fn hexagon_F2_conv_sf2df(_: f32) -> f64;
590    #[link_name = "llvm.hexagon.F2.conv.sf2ud"]
591    fn hexagon_F2_conv_sf2ud(_: f32) -> i64;
592    #[link_name = "llvm.hexagon.F2.conv.sf2ud.chop"]
593    fn hexagon_F2_conv_sf2ud_chop(_: f32) -> i64;
594    #[link_name = "llvm.hexagon.F2.conv.sf2uw"]
595    fn hexagon_F2_conv_sf2uw(_: f32) -> i32;
596    #[link_name = "llvm.hexagon.F2.conv.sf2uw.chop"]
597    fn hexagon_F2_conv_sf2uw_chop(_: f32) -> i32;
598    #[link_name = "llvm.hexagon.F2.conv.sf2w"]
599    fn hexagon_F2_conv_sf2w(_: f32) -> i32;
600    #[link_name = "llvm.hexagon.F2.conv.sf2w.chop"]
601    fn hexagon_F2_conv_sf2w_chop(_: f32) -> i32;
602    #[link_name = "llvm.hexagon.F2.conv.ud2df"]
603    fn hexagon_F2_conv_ud2df(_: i64) -> f64;
604    #[link_name = "llvm.hexagon.F2.conv.ud2sf"]
605    fn hexagon_F2_conv_ud2sf(_: i64) -> f32;
606    #[link_name = "llvm.hexagon.F2.conv.uw2df"]
607    fn hexagon_F2_conv_uw2df(_: i32) -> f64;
608    #[link_name = "llvm.hexagon.F2.conv.uw2sf"]
609    fn hexagon_F2_conv_uw2sf(_: i32) -> f32;
610    #[link_name = "llvm.hexagon.F2.conv.w2df"]
611    fn hexagon_F2_conv_w2df(_: i32) -> f64;
612    #[link_name = "llvm.hexagon.F2.conv.w2sf"]
613    fn hexagon_F2_conv_w2sf(_: i32) -> f32;
614    #[link_name = "llvm.hexagon.F2.dfclass"]
615    fn hexagon_F2_dfclass(_: f64, _: i32) -> i32;
616    #[link_name = "llvm.hexagon.F2.dfcmpeq"]
617    fn hexagon_F2_dfcmpeq(_: f64, _: f64) -> i32;
618    #[link_name = "llvm.hexagon.F2.dfcmpge"]
619    fn hexagon_F2_dfcmpge(_: f64, _: f64) -> i32;
620    #[link_name = "llvm.hexagon.F2.dfcmpgt"]
621    fn hexagon_F2_dfcmpgt(_: f64, _: f64) -> i32;
622    #[link_name = "llvm.hexagon.F2.dfcmpuo"]
623    fn hexagon_F2_dfcmpuo(_: f64, _: f64) -> i32;
624    #[link_name = "llvm.hexagon.F2.dfimm.n"]
625    fn hexagon_F2_dfimm_n(_: i32) -> f64;
626    #[link_name = "llvm.hexagon.F2.dfimm.p"]
627    fn hexagon_F2_dfimm_p(_: i32) -> f64;
628    #[link_name = "llvm.hexagon.F2.sfadd"]
629    fn hexagon_F2_sfadd(_: f32, _: f32) -> f32;
630    #[link_name = "llvm.hexagon.F2.sfclass"]
631    fn hexagon_F2_sfclass(_: f32, _: i32) -> i32;
632    #[link_name = "llvm.hexagon.F2.sfcmpeq"]
633    fn hexagon_F2_sfcmpeq(_: f32, _: f32) -> i32;
634    #[link_name = "llvm.hexagon.F2.sfcmpge"]
635    fn hexagon_F2_sfcmpge(_: f32, _: f32) -> i32;
636    #[link_name = "llvm.hexagon.F2.sfcmpgt"]
637    fn hexagon_F2_sfcmpgt(_: f32, _: f32) -> i32;
638    #[link_name = "llvm.hexagon.F2.sfcmpuo"]
639    fn hexagon_F2_sfcmpuo(_: f32, _: f32) -> i32;
640    #[link_name = "llvm.hexagon.F2.sffixupd"]
641    fn hexagon_F2_sffixupd(_: f32, _: f32) -> f32;
642    #[link_name = "llvm.hexagon.F2.sffixupn"]
643    fn hexagon_F2_sffixupn(_: f32, _: f32) -> f32;
644    #[link_name = "llvm.hexagon.F2.sffixupr"]
645    fn hexagon_F2_sffixupr(_: f32) -> f32;
646    #[link_name = "llvm.hexagon.F2.sffma"]
647    fn hexagon_F2_sffma(_: f32, _: f32, _: f32) -> f32;
648    #[link_name = "llvm.hexagon.F2.sffma.lib"]
649    fn hexagon_F2_sffma_lib(_: f32, _: f32, _: f32) -> f32;
650    #[link_name = "llvm.hexagon.F2.sffma.sc"]
651    fn hexagon_F2_sffma_sc(_: f32, _: f32, _: f32, _: i32) -> f32;
652    #[link_name = "llvm.hexagon.F2.sffms"]
653    fn hexagon_F2_sffms(_: f32, _: f32, _: f32) -> f32;
654    #[link_name = "llvm.hexagon.F2.sffms.lib"]
655    fn hexagon_F2_sffms_lib(_: f32, _: f32, _: f32) -> f32;
656    #[link_name = "llvm.hexagon.F2.sfimm.n"]
657    fn hexagon_F2_sfimm_n(_: i32) -> f32;
658    #[link_name = "llvm.hexagon.F2.sfimm.p"]
659    fn hexagon_F2_sfimm_p(_: i32) -> f32;
660    #[link_name = "llvm.hexagon.F2.sfmax"]
661    fn hexagon_F2_sfmax(_: f32, _: f32) -> f32;
662    #[link_name = "llvm.hexagon.F2.sfmin"]
663    fn hexagon_F2_sfmin(_: f32, _: f32) -> f32;
664    #[link_name = "llvm.hexagon.F2.sfmpy"]
665    fn hexagon_F2_sfmpy(_: f32, _: f32) -> f32;
666    #[link_name = "llvm.hexagon.F2.sfsub"]
667    fn hexagon_F2_sfsub(_: f32, _: f32) -> f32;
668    #[link_name = "llvm.hexagon.M2.acci"]
669    fn hexagon_M2_acci(_: i32, _: i32, _: i32) -> i32;
670    #[link_name = "llvm.hexagon.M2.accii"]
671    fn hexagon_M2_accii(_: i32, _: i32, _: i32) -> i32;
672    #[link_name = "llvm.hexagon.M2.cmaci.s0"]
673    fn hexagon_M2_cmaci_s0(_: i64, _: i32, _: i32) -> i64;
674    #[link_name = "llvm.hexagon.M2.cmacr.s0"]
675    fn hexagon_M2_cmacr_s0(_: i64, _: i32, _: i32) -> i64;
676    #[link_name = "llvm.hexagon.M2.cmacs.s0"]
677    fn hexagon_M2_cmacs_s0(_: i64, _: i32, _: i32) -> i64;
678    #[link_name = "llvm.hexagon.M2.cmacs.s1"]
679    fn hexagon_M2_cmacs_s1(_: i64, _: i32, _: i32) -> i64;
680    #[link_name = "llvm.hexagon.M2.cmacsc.s0"]
681    fn hexagon_M2_cmacsc_s0(_: i64, _: i32, _: i32) -> i64;
682    #[link_name = "llvm.hexagon.M2.cmacsc.s1"]
683    fn hexagon_M2_cmacsc_s1(_: i64, _: i32, _: i32) -> i64;
684    #[link_name = "llvm.hexagon.M2.cmpyi.s0"]
685    fn hexagon_M2_cmpyi_s0(_: i32, _: i32) -> i64;
686    #[link_name = "llvm.hexagon.M2.cmpyr.s0"]
687    fn hexagon_M2_cmpyr_s0(_: i32, _: i32) -> i64;
688    #[link_name = "llvm.hexagon.M2.cmpyrs.s0"]
689    fn hexagon_M2_cmpyrs_s0(_: i32, _: i32) -> i32;
690    #[link_name = "llvm.hexagon.M2.cmpyrs.s1"]
691    fn hexagon_M2_cmpyrs_s1(_: i32, _: i32) -> i32;
692    #[link_name = "llvm.hexagon.M2.cmpyrsc.s0"]
693    fn hexagon_M2_cmpyrsc_s0(_: i32, _: i32) -> i32;
694    #[link_name = "llvm.hexagon.M2.cmpyrsc.s1"]
695    fn hexagon_M2_cmpyrsc_s1(_: i32, _: i32) -> i32;
696    #[link_name = "llvm.hexagon.M2.cmpys.s0"]
697    fn hexagon_M2_cmpys_s0(_: i32, _: i32) -> i64;
698    #[link_name = "llvm.hexagon.M2.cmpys.s1"]
699    fn hexagon_M2_cmpys_s1(_: i32, _: i32) -> i64;
700    #[link_name = "llvm.hexagon.M2.cmpysc.s0"]
701    fn hexagon_M2_cmpysc_s0(_: i32, _: i32) -> i64;
702    #[link_name = "llvm.hexagon.M2.cmpysc.s1"]
703    fn hexagon_M2_cmpysc_s1(_: i32, _: i32) -> i64;
704    #[link_name = "llvm.hexagon.M2.cnacs.s0"]
705    fn hexagon_M2_cnacs_s0(_: i64, _: i32, _: i32) -> i64;
706    #[link_name = "llvm.hexagon.M2.cnacs.s1"]
707    fn hexagon_M2_cnacs_s1(_: i64, _: i32, _: i32) -> i64;
708    #[link_name = "llvm.hexagon.M2.cnacsc.s0"]
709    fn hexagon_M2_cnacsc_s0(_: i64, _: i32, _: i32) -> i64;
710    #[link_name = "llvm.hexagon.M2.cnacsc.s1"]
711    fn hexagon_M2_cnacsc_s1(_: i64, _: i32, _: i32) -> i64;
712    #[link_name = "llvm.hexagon.M2.dpmpyss.acc.s0"]
713    fn hexagon_M2_dpmpyss_acc_s0(_: i64, _: i32, _: i32) -> i64;
714    #[link_name = "llvm.hexagon.M2.dpmpyss.nac.s0"]
715    fn hexagon_M2_dpmpyss_nac_s0(_: i64, _: i32, _: i32) -> i64;
716    #[link_name = "llvm.hexagon.M2.dpmpyss.rnd.s0"]
717    fn hexagon_M2_dpmpyss_rnd_s0(_: i32, _: i32) -> i32;
718    #[link_name = "llvm.hexagon.M2.dpmpyss.s0"]
719    fn hexagon_M2_dpmpyss_s0(_: i32, _: i32) -> i64;
720    #[link_name = "llvm.hexagon.M2.dpmpyuu.acc.s0"]
721    fn hexagon_M2_dpmpyuu_acc_s0(_: i64, _: i32, _: i32) -> i64;
722    #[link_name = "llvm.hexagon.M2.dpmpyuu.nac.s0"]
723    fn hexagon_M2_dpmpyuu_nac_s0(_: i64, _: i32, _: i32) -> i64;
724    #[link_name = "llvm.hexagon.M2.dpmpyuu.s0"]
725    fn hexagon_M2_dpmpyuu_s0(_: i32, _: i32) -> i64;
726    #[link_name = "llvm.hexagon.M2.hmmpyh.rs1"]
727    fn hexagon_M2_hmmpyh_rs1(_: i32, _: i32) -> i32;
728    #[link_name = "llvm.hexagon.M2.hmmpyh.s1"]
729    fn hexagon_M2_hmmpyh_s1(_: i32, _: i32) -> i32;
730    #[link_name = "llvm.hexagon.M2.hmmpyl.rs1"]
731    fn hexagon_M2_hmmpyl_rs1(_: i32, _: i32) -> i32;
732    #[link_name = "llvm.hexagon.M2.hmmpyl.s1"]
733    fn hexagon_M2_hmmpyl_s1(_: i32, _: i32) -> i32;
734    #[link_name = "llvm.hexagon.M2.maci"]
735    fn hexagon_M2_maci(_: i32, _: i32, _: i32) -> i32;
736    #[link_name = "llvm.hexagon.M2.macsin"]
737    fn hexagon_M2_macsin(_: i32, _: i32, _: i32) -> i32;
738    #[link_name = "llvm.hexagon.M2.macsip"]
739    fn hexagon_M2_macsip(_: i32, _: i32, _: i32) -> i32;
740    #[link_name = "llvm.hexagon.M2.mmachs.rs0"]
741    fn hexagon_M2_mmachs_rs0(_: i64, _: i64, _: i64) -> i64;
742    #[link_name = "llvm.hexagon.M2.mmachs.rs1"]
743    fn hexagon_M2_mmachs_rs1(_: i64, _: i64, _: i64) -> i64;
744    #[link_name = "llvm.hexagon.M2.mmachs.s0"]
745    fn hexagon_M2_mmachs_s0(_: i64, _: i64, _: i64) -> i64;
746    #[link_name = "llvm.hexagon.M2.mmachs.s1"]
747    fn hexagon_M2_mmachs_s1(_: i64, _: i64, _: i64) -> i64;
748    #[link_name = "llvm.hexagon.M2.mmacls.rs0"]
749    fn hexagon_M2_mmacls_rs0(_: i64, _: i64, _: i64) -> i64;
750    #[link_name = "llvm.hexagon.M2.mmacls.rs1"]
751    fn hexagon_M2_mmacls_rs1(_: i64, _: i64, _: i64) -> i64;
752    #[link_name = "llvm.hexagon.M2.mmacls.s0"]
753    fn hexagon_M2_mmacls_s0(_: i64, _: i64, _: i64) -> i64;
754    #[link_name = "llvm.hexagon.M2.mmacls.s1"]
755    fn hexagon_M2_mmacls_s1(_: i64, _: i64, _: i64) -> i64;
756    #[link_name = "llvm.hexagon.M2.mmacuhs.rs0"]
757    fn hexagon_M2_mmacuhs_rs0(_: i64, _: i64, _: i64) -> i64;
758    #[link_name = "llvm.hexagon.M2.mmacuhs.rs1"]
759    fn hexagon_M2_mmacuhs_rs1(_: i64, _: i64, _: i64) -> i64;
760    #[link_name = "llvm.hexagon.M2.mmacuhs.s0"]
761    fn hexagon_M2_mmacuhs_s0(_: i64, _: i64, _: i64) -> i64;
762    #[link_name = "llvm.hexagon.M2.mmacuhs.s1"]
763    fn hexagon_M2_mmacuhs_s1(_: i64, _: i64, _: i64) -> i64;
764    #[link_name = "llvm.hexagon.M2.mmaculs.rs0"]
765    fn hexagon_M2_mmaculs_rs0(_: i64, _: i64, _: i64) -> i64;
766    #[link_name = "llvm.hexagon.M2.mmaculs.rs1"]
767    fn hexagon_M2_mmaculs_rs1(_: i64, _: i64, _: i64) -> i64;
768    #[link_name = "llvm.hexagon.M2.mmaculs.s0"]
769    fn hexagon_M2_mmaculs_s0(_: i64, _: i64, _: i64) -> i64;
770    #[link_name = "llvm.hexagon.M2.mmaculs.s1"]
771    fn hexagon_M2_mmaculs_s1(_: i64, _: i64, _: i64) -> i64;
772    #[link_name = "llvm.hexagon.M2.mmpyh.rs0"]
773    fn hexagon_M2_mmpyh_rs0(_: i64, _: i64) -> i64;
774    #[link_name = "llvm.hexagon.M2.mmpyh.rs1"]
775    fn hexagon_M2_mmpyh_rs1(_: i64, _: i64) -> i64;
776    #[link_name = "llvm.hexagon.M2.mmpyh.s0"]
777    fn hexagon_M2_mmpyh_s0(_: i64, _: i64) -> i64;
778    #[link_name = "llvm.hexagon.M2.mmpyh.s1"]
779    fn hexagon_M2_mmpyh_s1(_: i64, _: i64) -> i64;
780    #[link_name = "llvm.hexagon.M2.mmpyl.rs0"]
781    fn hexagon_M2_mmpyl_rs0(_: i64, _: i64) -> i64;
782    #[link_name = "llvm.hexagon.M2.mmpyl.rs1"]
783    fn hexagon_M2_mmpyl_rs1(_: i64, _: i64) -> i64;
784    #[link_name = "llvm.hexagon.M2.mmpyl.s0"]
785    fn hexagon_M2_mmpyl_s0(_: i64, _: i64) -> i64;
786    #[link_name = "llvm.hexagon.M2.mmpyl.s1"]
787    fn hexagon_M2_mmpyl_s1(_: i64, _: i64) -> i64;
788    #[link_name = "llvm.hexagon.M2.mmpyuh.rs0"]
789    fn hexagon_M2_mmpyuh_rs0(_: i64, _: i64) -> i64;
790    #[link_name = "llvm.hexagon.M2.mmpyuh.rs1"]
791    fn hexagon_M2_mmpyuh_rs1(_: i64, _: i64) -> i64;
792    #[link_name = "llvm.hexagon.M2.mmpyuh.s0"]
793    fn hexagon_M2_mmpyuh_s0(_: i64, _: i64) -> i64;
794    #[link_name = "llvm.hexagon.M2.mmpyuh.s1"]
795    fn hexagon_M2_mmpyuh_s1(_: i64, _: i64) -> i64;
796    #[link_name = "llvm.hexagon.M2.mmpyul.rs0"]
797    fn hexagon_M2_mmpyul_rs0(_: i64, _: i64) -> i64;
798    #[link_name = "llvm.hexagon.M2.mmpyul.rs1"]
799    fn hexagon_M2_mmpyul_rs1(_: i64, _: i64) -> i64;
800    #[link_name = "llvm.hexagon.M2.mmpyul.s0"]
801    fn hexagon_M2_mmpyul_s0(_: i64, _: i64) -> i64;
802    #[link_name = "llvm.hexagon.M2.mmpyul.s1"]
803    fn hexagon_M2_mmpyul_s1(_: i64, _: i64) -> i64;
804    #[link_name = "llvm.hexagon.M2.mpy.acc.hh.s0"]
805    fn hexagon_M2_mpy_acc_hh_s0(_: i32, _: i32, _: i32) -> i32;
806    #[link_name = "llvm.hexagon.M2.mpy.acc.hh.s1"]
807    fn hexagon_M2_mpy_acc_hh_s1(_: i32, _: i32, _: i32) -> i32;
808    #[link_name = "llvm.hexagon.M2.mpy.acc.hl.s0"]
809    fn hexagon_M2_mpy_acc_hl_s0(_: i32, _: i32, _: i32) -> i32;
810    #[link_name = "llvm.hexagon.M2.mpy.acc.hl.s1"]
811    fn hexagon_M2_mpy_acc_hl_s1(_: i32, _: i32, _: i32) -> i32;
812    #[link_name = "llvm.hexagon.M2.mpy.acc.lh.s0"]
813    fn hexagon_M2_mpy_acc_lh_s0(_: i32, _: i32, _: i32) -> i32;
814    #[link_name = "llvm.hexagon.M2.mpy.acc.lh.s1"]
815    fn hexagon_M2_mpy_acc_lh_s1(_: i32, _: i32, _: i32) -> i32;
816    #[link_name = "llvm.hexagon.M2.mpy.acc.ll.s0"]
817    fn hexagon_M2_mpy_acc_ll_s0(_: i32, _: i32, _: i32) -> i32;
818    #[link_name = "llvm.hexagon.M2.mpy.acc.ll.s1"]
819    fn hexagon_M2_mpy_acc_ll_s1(_: i32, _: i32, _: i32) -> i32;
820    #[link_name = "llvm.hexagon.M2.mpy.acc.sat.hh.s0"]
821    fn hexagon_M2_mpy_acc_sat_hh_s0(_: i32, _: i32, _: i32) -> i32;
822    #[link_name = "llvm.hexagon.M2.mpy.acc.sat.hh.s1"]
823    fn hexagon_M2_mpy_acc_sat_hh_s1(_: i32, _: i32, _: i32) -> i32;
824    #[link_name = "llvm.hexagon.M2.mpy.acc.sat.hl.s0"]
825    fn hexagon_M2_mpy_acc_sat_hl_s0(_: i32, _: i32, _: i32) -> i32;
826    #[link_name = "llvm.hexagon.M2.mpy.acc.sat.hl.s1"]
827    fn hexagon_M2_mpy_acc_sat_hl_s1(_: i32, _: i32, _: i32) -> i32;
828    #[link_name = "llvm.hexagon.M2.mpy.acc.sat.lh.s0"]
829    fn hexagon_M2_mpy_acc_sat_lh_s0(_: i32, _: i32, _: i32) -> i32;
830    #[link_name = "llvm.hexagon.M2.mpy.acc.sat.lh.s1"]
831    fn hexagon_M2_mpy_acc_sat_lh_s1(_: i32, _: i32, _: i32) -> i32;
832    #[link_name = "llvm.hexagon.M2.mpy.acc.sat.ll.s0"]
833    fn hexagon_M2_mpy_acc_sat_ll_s0(_: i32, _: i32, _: i32) -> i32;
834    #[link_name = "llvm.hexagon.M2.mpy.acc.sat.ll.s1"]
835    fn hexagon_M2_mpy_acc_sat_ll_s1(_: i32, _: i32, _: i32) -> i32;
836    #[link_name = "llvm.hexagon.M2.mpy.hh.s0"]
837    fn hexagon_M2_mpy_hh_s0(_: i32, _: i32) -> i32;
838    #[link_name = "llvm.hexagon.M2.mpy.hh.s1"]
839    fn hexagon_M2_mpy_hh_s1(_: i32, _: i32) -> i32;
840    #[link_name = "llvm.hexagon.M2.mpy.hl.s0"]
841    fn hexagon_M2_mpy_hl_s0(_: i32, _: i32) -> i32;
842    #[link_name = "llvm.hexagon.M2.mpy.hl.s1"]
843    fn hexagon_M2_mpy_hl_s1(_: i32, _: i32) -> i32;
844    #[link_name = "llvm.hexagon.M2.mpy.lh.s0"]
845    fn hexagon_M2_mpy_lh_s0(_: i32, _: i32) -> i32;
846    #[link_name = "llvm.hexagon.M2.mpy.lh.s1"]
847    fn hexagon_M2_mpy_lh_s1(_: i32, _: i32) -> i32;
848    #[link_name = "llvm.hexagon.M2.mpy.ll.s0"]
849    fn hexagon_M2_mpy_ll_s0(_: i32, _: i32) -> i32;
850    #[link_name = "llvm.hexagon.M2.mpy.ll.s1"]
851    fn hexagon_M2_mpy_ll_s1(_: i32, _: i32) -> i32;
852    #[link_name = "llvm.hexagon.M2.mpy.nac.hh.s0"]
853    fn hexagon_M2_mpy_nac_hh_s0(_: i32, _: i32, _: i32) -> i32;
854    #[link_name = "llvm.hexagon.M2.mpy.nac.hh.s1"]
855    fn hexagon_M2_mpy_nac_hh_s1(_: i32, _: i32, _: i32) -> i32;
856    #[link_name = "llvm.hexagon.M2.mpy.nac.hl.s0"]
857    fn hexagon_M2_mpy_nac_hl_s0(_: i32, _: i32, _: i32) -> i32;
858    #[link_name = "llvm.hexagon.M2.mpy.nac.hl.s1"]
859    fn hexagon_M2_mpy_nac_hl_s1(_: i32, _: i32, _: i32) -> i32;
860    #[link_name = "llvm.hexagon.M2.mpy.nac.lh.s0"]
861    fn hexagon_M2_mpy_nac_lh_s0(_: i32, _: i32, _: i32) -> i32;
862    #[link_name = "llvm.hexagon.M2.mpy.nac.lh.s1"]
863    fn hexagon_M2_mpy_nac_lh_s1(_: i32, _: i32, _: i32) -> i32;
864    #[link_name = "llvm.hexagon.M2.mpy.nac.ll.s0"]
865    fn hexagon_M2_mpy_nac_ll_s0(_: i32, _: i32, _: i32) -> i32;
866    #[link_name = "llvm.hexagon.M2.mpy.nac.ll.s1"]
867    fn hexagon_M2_mpy_nac_ll_s1(_: i32, _: i32, _: i32) -> i32;
868    #[link_name = "llvm.hexagon.M2.mpy.nac.sat.hh.s0"]
869    fn hexagon_M2_mpy_nac_sat_hh_s0(_: i32, _: i32, _: i32) -> i32;
870    #[link_name = "llvm.hexagon.M2.mpy.nac.sat.hh.s1"]
871    fn hexagon_M2_mpy_nac_sat_hh_s1(_: i32, _: i32, _: i32) -> i32;
872    #[link_name = "llvm.hexagon.M2.mpy.nac.sat.hl.s0"]
873    fn hexagon_M2_mpy_nac_sat_hl_s0(_: i32, _: i32, _: i32) -> i32;
874    #[link_name = "llvm.hexagon.M2.mpy.nac.sat.hl.s1"]
875    fn hexagon_M2_mpy_nac_sat_hl_s1(_: i32, _: i32, _: i32) -> i32;
876    #[link_name = "llvm.hexagon.M2.mpy.nac.sat.lh.s0"]
877    fn hexagon_M2_mpy_nac_sat_lh_s0(_: i32, _: i32, _: i32) -> i32;
878    #[link_name = "llvm.hexagon.M2.mpy.nac.sat.lh.s1"]
879    fn hexagon_M2_mpy_nac_sat_lh_s1(_: i32, _: i32, _: i32) -> i32;
880    #[link_name = "llvm.hexagon.M2.mpy.nac.sat.ll.s0"]
881    fn hexagon_M2_mpy_nac_sat_ll_s0(_: i32, _: i32, _: i32) -> i32;
882    #[link_name = "llvm.hexagon.M2.mpy.nac.sat.ll.s1"]
883    fn hexagon_M2_mpy_nac_sat_ll_s1(_: i32, _: i32, _: i32) -> i32;
884    #[link_name = "llvm.hexagon.M2.mpy.rnd.hh.s0"]
885    fn hexagon_M2_mpy_rnd_hh_s0(_: i32, _: i32) -> i32;
886    #[link_name = "llvm.hexagon.M2.mpy.rnd.hh.s1"]
887    fn hexagon_M2_mpy_rnd_hh_s1(_: i32, _: i32) -> i32;
888    #[link_name = "llvm.hexagon.M2.mpy.rnd.hl.s0"]
889    fn hexagon_M2_mpy_rnd_hl_s0(_: i32, _: i32) -> i32;
890    #[link_name = "llvm.hexagon.M2.mpy.rnd.hl.s1"]
891    fn hexagon_M2_mpy_rnd_hl_s1(_: i32, _: i32) -> i32;
892    #[link_name = "llvm.hexagon.M2.mpy.rnd.lh.s0"]
893    fn hexagon_M2_mpy_rnd_lh_s0(_: i32, _: i32) -> i32;
894    #[link_name = "llvm.hexagon.M2.mpy.rnd.lh.s1"]
895    fn hexagon_M2_mpy_rnd_lh_s1(_: i32, _: i32) -> i32;
896    #[link_name = "llvm.hexagon.M2.mpy.rnd.ll.s0"]
897    fn hexagon_M2_mpy_rnd_ll_s0(_: i32, _: i32) -> i32;
898    #[link_name = "llvm.hexagon.M2.mpy.rnd.ll.s1"]
899    fn hexagon_M2_mpy_rnd_ll_s1(_: i32, _: i32) -> i32;
900    #[link_name = "llvm.hexagon.M2.mpy.sat.hh.s0"]
901    fn hexagon_M2_mpy_sat_hh_s0(_: i32, _: i32) -> i32;
902    #[link_name = "llvm.hexagon.M2.mpy.sat.hh.s1"]
903    fn hexagon_M2_mpy_sat_hh_s1(_: i32, _: i32) -> i32;
904    #[link_name = "llvm.hexagon.M2.mpy.sat.hl.s0"]
905    fn hexagon_M2_mpy_sat_hl_s0(_: i32, _: i32) -> i32;
906    #[link_name = "llvm.hexagon.M2.mpy.sat.hl.s1"]
907    fn hexagon_M2_mpy_sat_hl_s1(_: i32, _: i32) -> i32;
908    #[link_name = "llvm.hexagon.M2.mpy.sat.lh.s0"]
909    fn hexagon_M2_mpy_sat_lh_s0(_: i32, _: i32) -> i32;
910    #[link_name = "llvm.hexagon.M2.mpy.sat.lh.s1"]
911    fn hexagon_M2_mpy_sat_lh_s1(_: i32, _: i32) -> i32;
912    #[link_name = "llvm.hexagon.M2.mpy.sat.ll.s0"]
913    fn hexagon_M2_mpy_sat_ll_s0(_: i32, _: i32) -> i32;
914    #[link_name = "llvm.hexagon.M2.mpy.sat.ll.s1"]
915    fn hexagon_M2_mpy_sat_ll_s1(_: i32, _: i32) -> i32;
916    #[link_name = "llvm.hexagon.M2.mpy.sat.rnd.hh.s0"]
917    fn hexagon_M2_mpy_sat_rnd_hh_s0(_: i32, _: i32) -> i32;
918    #[link_name = "llvm.hexagon.M2.mpy.sat.rnd.hh.s1"]
919    fn hexagon_M2_mpy_sat_rnd_hh_s1(_: i32, _: i32) -> i32;
920    #[link_name = "llvm.hexagon.M2.mpy.sat.rnd.hl.s0"]
921    fn hexagon_M2_mpy_sat_rnd_hl_s0(_: i32, _: i32) -> i32;
922    #[link_name = "llvm.hexagon.M2.mpy.sat.rnd.hl.s1"]
923    fn hexagon_M2_mpy_sat_rnd_hl_s1(_: i32, _: i32) -> i32;
924    #[link_name = "llvm.hexagon.M2.mpy.sat.rnd.lh.s0"]
925    fn hexagon_M2_mpy_sat_rnd_lh_s0(_: i32, _: i32) -> i32;
926    #[link_name = "llvm.hexagon.M2.mpy.sat.rnd.lh.s1"]
927    fn hexagon_M2_mpy_sat_rnd_lh_s1(_: i32, _: i32) -> i32;
928    #[link_name = "llvm.hexagon.M2.mpy.sat.rnd.ll.s0"]
929    fn hexagon_M2_mpy_sat_rnd_ll_s0(_: i32, _: i32) -> i32;
930    #[link_name = "llvm.hexagon.M2.mpy.sat.rnd.ll.s1"]
931    fn hexagon_M2_mpy_sat_rnd_ll_s1(_: i32, _: i32) -> i32;
932    #[link_name = "llvm.hexagon.M2.mpy.up"]
933    fn hexagon_M2_mpy_up(_: i32, _: i32) -> i32;
934    #[link_name = "llvm.hexagon.M2.mpy.up.s1"]
935    fn hexagon_M2_mpy_up_s1(_: i32, _: i32) -> i32;
936    #[link_name = "llvm.hexagon.M2.mpy.up.s1.sat"]
937    fn hexagon_M2_mpy_up_s1_sat(_: i32, _: i32) -> i32;
938    #[link_name = "llvm.hexagon.M2.mpyd.acc.hh.s0"]
939    fn hexagon_M2_mpyd_acc_hh_s0(_: i64, _: i32, _: i32) -> i64;
940    #[link_name = "llvm.hexagon.M2.mpyd.acc.hh.s1"]
941    fn hexagon_M2_mpyd_acc_hh_s1(_: i64, _: i32, _: i32) -> i64;
942    #[link_name = "llvm.hexagon.M2.mpyd.acc.hl.s0"]
943    fn hexagon_M2_mpyd_acc_hl_s0(_: i64, _: i32, _: i32) -> i64;
944    #[link_name = "llvm.hexagon.M2.mpyd.acc.hl.s1"]
945    fn hexagon_M2_mpyd_acc_hl_s1(_: i64, _: i32, _: i32) -> i64;
946    #[link_name = "llvm.hexagon.M2.mpyd.acc.lh.s0"]
947    fn hexagon_M2_mpyd_acc_lh_s0(_: i64, _: i32, _: i32) -> i64;
948    #[link_name = "llvm.hexagon.M2.mpyd.acc.lh.s1"]
949    fn hexagon_M2_mpyd_acc_lh_s1(_: i64, _: i32, _: i32) -> i64;
950    #[link_name = "llvm.hexagon.M2.mpyd.acc.ll.s0"]
951    fn hexagon_M2_mpyd_acc_ll_s0(_: i64, _: i32, _: i32) -> i64;
952    #[link_name = "llvm.hexagon.M2.mpyd.acc.ll.s1"]
953    fn hexagon_M2_mpyd_acc_ll_s1(_: i64, _: i32, _: i32) -> i64;
954    #[link_name = "llvm.hexagon.M2.mpyd.hh.s0"]
955    fn hexagon_M2_mpyd_hh_s0(_: i32, _: i32) -> i64;
956    #[link_name = "llvm.hexagon.M2.mpyd.hh.s1"]
957    fn hexagon_M2_mpyd_hh_s1(_: i32, _: i32) -> i64;
958    #[link_name = "llvm.hexagon.M2.mpyd.hl.s0"]
959    fn hexagon_M2_mpyd_hl_s0(_: i32, _: i32) -> i64;
960    #[link_name = "llvm.hexagon.M2.mpyd.hl.s1"]
961    fn hexagon_M2_mpyd_hl_s1(_: i32, _: i32) -> i64;
962    #[link_name = "llvm.hexagon.M2.mpyd.lh.s0"]
963    fn hexagon_M2_mpyd_lh_s0(_: i32, _: i32) -> i64;
964    #[link_name = "llvm.hexagon.M2.mpyd.lh.s1"]
965    fn hexagon_M2_mpyd_lh_s1(_: i32, _: i32) -> i64;
966    #[link_name = "llvm.hexagon.M2.mpyd.ll.s0"]
967    fn hexagon_M2_mpyd_ll_s0(_: i32, _: i32) -> i64;
968    #[link_name = "llvm.hexagon.M2.mpyd.ll.s1"]
969    fn hexagon_M2_mpyd_ll_s1(_: i32, _: i32) -> i64;
970    #[link_name = "llvm.hexagon.M2.mpyd.nac.hh.s0"]
971    fn hexagon_M2_mpyd_nac_hh_s0(_: i64, _: i32, _: i32) -> i64;
972    #[link_name = "llvm.hexagon.M2.mpyd.nac.hh.s1"]
973    fn hexagon_M2_mpyd_nac_hh_s1(_: i64, _: i32, _: i32) -> i64;
974    #[link_name = "llvm.hexagon.M2.mpyd.nac.hl.s0"]
975    fn hexagon_M2_mpyd_nac_hl_s0(_: i64, _: i32, _: i32) -> i64;
976    #[link_name = "llvm.hexagon.M2.mpyd.nac.hl.s1"]
977    fn hexagon_M2_mpyd_nac_hl_s1(_: i64, _: i32, _: i32) -> i64;
978    #[link_name = "llvm.hexagon.M2.mpyd.nac.lh.s0"]
979    fn hexagon_M2_mpyd_nac_lh_s0(_: i64, _: i32, _: i32) -> i64;
980    #[link_name = "llvm.hexagon.M2.mpyd.nac.lh.s1"]
981    fn hexagon_M2_mpyd_nac_lh_s1(_: i64, _: i32, _: i32) -> i64;
982    #[link_name = "llvm.hexagon.M2.mpyd.nac.ll.s0"]
983    fn hexagon_M2_mpyd_nac_ll_s0(_: i64, _: i32, _: i32) -> i64;
984    #[link_name = "llvm.hexagon.M2.mpyd.nac.ll.s1"]
985    fn hexagon_M2_mpyd_nac_ll_s1(_: i64, _: i32, _: i32) -> i64;
986    #[link_name = "llvm.hexagon.M2.mpyd.rnd.hh.s0"]
987    fn hexagon_M2_mpyd_rnd_hh_s0(_: i32, _: i32) -> i64;
988    #[link_name = "llvm.hexagon.M2.mpyd.rnd.hh.s1"]
989    fn hexagon_M2_mpyd_rnd_hh_s1(_: i32, _: i32) -> i64;
990    #[link_name = "llvm.hexagon.M2.mpyd.rnd.hl.s0"]
991    fn hexagon_M2_mpyd_rnd_hl_s0(_: i32, _: i32) -> i64;
992    #[link_name = "llvm.hexagon.M2.mpyd.rnd.hl.s1"]
993    fn hexagon_M2_mpyd_rnd_hl_s1(_: i32, _: i32) -> i64;
994    #[link_name = "llvm.hexagon.M2.mpyd.rnd.lh.s0"]
995    fn hexagon_M2_mpyd_rnd_lh_s0(_: i32, _: i32) -> i64;
996    #[link_name = "llvm.hexagon.M2.mpyd.rnd.lh.s1"]
997    fn hexagon_M2_mpyd_rnd_lh_s1(_: i32, _: i32) -> i64;
998    #[link_name = "llvm.hexagon.M2.mpyd.rnd.ll.s0"]
999    fn hexagon_M2_mpyd_rnd_ll_s0(_: i32, _: i32) -> i64;
1000    #[link_name = "llvm.hexagon.M2.mpyd.rnd.ll.s1"]
1001    fn hexagon_M2_mpyd_rnd_ll_s1(_: i32, _: i32) -> i64;
1002    #[link_name = "llvm.hexagon.M2.mpyi"]
1003    fn hexagon_M2_mpyi(_: i32, _: i32) -> i32;
1004    #[link_name = "llvm.hexagon.M2.mpysmi"]
1005    fn hexagon_M2_mpysmi(_: i32, _: i32) -> i32;
1006    #[link_name = "llvm.hexagon.M2.mpysu.up"]
1007    fn hexagon_M2_mpysu_up(_: i32, _: i32) -> i32;
1008    #[link_name = "llvm.hexagon.M2.mpyu.acc.hh.s0"]
1009    fn hexagon_M2_mpyu_acc_hh_s0(_: i32, _: i32, _: i32) -> i32;
1010    #[link_name = "llvm.hexagon.M2.mpyu.acc.hh.s1"]
1011    fn hexagon_M2_mpyu_acc_hh_s1(_: i32, _: i32, _: i32) -> i32;
1012    #[link_name = "llvm.hexagon.M2.mpyu.acc.hl.s0"]
1013    fn hexagon_M2_mpyu_acc_hl_s0(_: i32, _: i32, _: i32) -> i32;
1014    #[link_name = "llvm.hexagon.M2.mpyu.acc.hl.s1"]
1015    fn hexagon_M2_mpyu_acc_hl_s1(_: i32, _: i32, _: i32) -> i32;
1016    #[link_name = "llvm.hexagon.M2.mpyu.acc.lh.s0"]
1017    fn hexagon_M2_mpyu_acc_lh_s0(_: i32, _: i32, _: i32) -> i32;
1018    #[link_name = "llvm.hexagon.M2.mpyu.acc.lh.s1"]
1019    fn hexagon_M2_mpyu_acc_lh_s1(_: i32, _: i32, _: i32) -> i32;
1020    #[link_name = "llvm.hexagon.M2.mpyu.acc.ll.s0"]
1021    fn hexagon_M2_mpyu_acc_ll_s0(_: i32, _: i32, _: i32) -> i32;
1022    #[link_name = "llvm.hexagon.M2.mpyu.acc.ll.s1"]
1023    fn hexagon_M2_mpyu_acc_ll_s1(_: i32, _: i32, _: i32) -> i32;
1024    #[link_name = "llvm.hexagon.M2.mpyu.hh.s0"]
1025    fn hexagon_M2_mpyu_hh_s0(_: i32, _: i32) -> i32;
1026    #[link_name = "llvm.hexagon.M2.mpyu.hh.s1"]
1027    fn hexagon_M2_mpyu_hh_s1(_: i32, _: i32) -> i32;
1028    #[link_name = "llvm.hexagon.M2.mpyu.hl.s0"]
1029    fn hexagon_M2_mpyu_hl_s0(_: i32, _: i32) -> i32;
1030    #[link_name = "llvm.hexagon.M2.mpyu.hl.s1"]
1031    fn hexagon_M2_mpyu_hl_s1(_: i32, _: i32) -> i32;
1032    #[link_name = "llvm.hexagon.M2.mpyu.lh.s0"]
1033    fn hexagon_M2_mpyu_lh_s0(_: i32, _: i32) -> i32;
1034    #[link_name = "llvm.hexagon.M2.mpyu.lh.s1"]
1035    fn hexagon_M2_mpyu_lh_s1(_: i32, _: i32) -> i32;
1036    #[link_name = "llvm.hexagon.M2.mpyu.ll.s0"]
1037    fn hexagon_M2_mpyu_ll_s0(_: i32, _: i32) -> i32;
1038    #[link_name = "llvm.hexagon.M2.mpyu.ll.s1"]
1039    fn hexagon_M2_mpyu_ll_s1(_: i32, _: i32) -> i32;
1040    #[link_name = "llvm.hexagon.M2.mpyu.nac.hh.s0"]
1041    fn hexagon_M2_mpyu_nac_hh_s0(_: i32, _: i32, _: i32) -> i32;
1042    #[link_name = "llvm.hexagon.M2.mpyu.nac.hh.s1"]
1043    fn hexagon_M2_mpyu_nac_hh_s1(_: i32, _: i32, _: i32) -> i32;
1044    #[link_name = "llvm.hexagon.M2.mpyu.nac.hl.s0"]
1045    fn hexagon_M2_mpyu_nac_hl_s0(_: i32, _: i32, _: i32) -> i32;
1046    #[link_name = "llvm.hexagon.M2.mpyu.nac.hl.s1"]
1047    fn hexagon_M2_mpyu_nac_hl_s1(_: i32, _: i32, _: i32) -> i32;
1048    #[link_name = "llvm.hexagon.M2.mpyu.nac.lh.s0"]
1049    fn hexagon_M2_mpyu_nac_lh_s0(_: i32, _: i32, _: i32) -> i32;
1050    #[link_name = "llvm.hexagon.M2.mpyu.nac.lh.s1"]
1051    fn hexagon_M2_mpyu_nac_lh_s1(_: i32, _: i32, _: i32) -> i32;
1052    #[link_name = "llvm.hexagon.M2.mpyu.nac.ll.s0"]
1053    fn hexagon_M2_mpyu_nac_ll_s0(_: i32, _: i32, _: i32) -> i32;
1054    #[link_name = "llvm.hexagon.M2.mpyu.nac.ll.s1"]
1055    fn hexagon_M2_mpyu_nac_ll_s1(_: i32, _: i32, _: i32) -> i32;
1056    #[link_name = "llvm.hexagon.M2.mpyu.up"]
1057    fn hexagon_M2_mpyu_up(_: i32, _: i32) -> i32;
1058    #[link_name = "llvm.hexagon.M2.mpyud.acc.hh.s0"]
1059    fn hexagon_M2_mpyud_acc_hh_s0(_: i64, _: i32, _: i32) -> i64;
1060    #[link_name = "llvm.hexagon.M2.mpyud.acc.hh.s1"]
1061    fn hexagon_M2_mpyud_acc_hh_s1(_: i64, _: i32, _: i32) -> i64;
1062    #[link_name = "llvm.hexagon.M2.mpyud.acc.hl.s0"]
1063    fn hexagon_M2_mpyud_acc_hl_s0(_: i64, _: i32, _: i32) -> i64;
1064    #[link_name = "llvm.hexagon.M2.mpyud.acc.hl.s1"]
1065    fn hexagon_M2_mpyud_acc_hl_s1(_: i64, _: i32, _: i32) -> i64;
1066    #[link_name = "llvm.hexagon.M2.mpyud.acc.lh.s0"]
1067    fn hexagon_M2_mpyud_acc_lh_s0(_: i64, _: i32, _: i32) -> i64;
1068    #[link_name = "llvm.hexagon.M2.mpyud.acc.lh.s1"]
1069    fn hexagon_M2_mpyud_acc_lh_s1(_: i64, _: i32, _: i32) -> i64;
1070    #[link_name = "llvm.hexagon.M2.mpyud.acc.ll.s0"]
1071    fn hexagon_M2_mpyud_acc_ll_s0(_: i64, _: i32, _: i32) -> i64;
1072    #[link_name = "llvm.hexagon.M2.mpyud.acc.ll.s1"]
1073    fn hexagon_M2_mpyud_acc_ll_s1(_: i64, _: i32, _: i32) -> i64;
1074    #[link_name = "llvm.hexagon.M2.mpyud.hh.s0"]
1075    fn hexagon_M2_mpyud_hh_s0(_: i32, _: i32) -> i64;
1076    #[link_name = "llvm.hexagon.M2.mpyud.hh.s1"]
1077    fn hexagon_M2_mpyud_hh_s1(_: i32, _: i32) -> i64;
1078    #[link_name = "llvm.hexagon.M2.mpyud.hl.s0"]
1079    fn hexagon_M2_mpyud_hl_s0(_: i32, _: i32) -> i64;
1080    #[link_name = "llvm.hexagon.M2.mpyud.hl.s1"]
1081    fn hexagon_M2_mpyud_hl_s1(_: i32, _: i32) -> i64;
1082    #[link_name = "llvm.hexagon.M2.mpyud.lh.s0"]
1083    fn hexagon_M2_mpyud_lh_s0(_: i32, _: i32) -> i64;
1084    #[link_name = "llvm.hexagon.M2.mpyud.lh.s1"]
1085    fn hexagon_M2_mpyud_lh_s1(_: i32, _: i32) -> i64;
1086    #[link_name = "llvm.hexagon.M2.mpyud.ll.s0"]
1087    fn hexagon_M2_mpyud_ll_s0(_: i32, _: i32) -> i64;
1088    #[link_name = "llvm.hexagon.M2.mpyud.ll.s1"]
1089    fn hexagon_M2_mpyud_ll_s1(_: i32, _: i32) -> i64;
1090    #[link_name = "llvm.hexagon.M2.mpyud.nac.hh.s0"]
1091    fn hexagon_M2_mpyud_nac_hh_s0(_: i64, _: i32, _: i32) -> i64;
1092    #[link_name = "llvm.hexagon.M2.mpyud.nac.hh.s1"]
1093    fn hexagon_M2_mpyud_nac_hh_s1(_: i64, _: i32, _: i32) -> i64;
1094    #[link_name = "llvm.hexagon.M2.mpyud.nac.hl.s0"]
1095    fn hexagon_M2_mpyud_nac_hl_s0(_: i64, _: i32, _: i32) -> i64;
1096    #[link_name = "llvm.hexagon.M2.mpyud.nac.hl.s1"]
1097    fn hexagon_M2_mpyud_nac_hl_s1(_: i64, _: i32, _: i32) -> i64;
1098    #[link_name = "llvm.hexagon.M2.mpyud.nac.lh.s0"]
1099    fn hexagon_M2_mpyud_nac_lh_s0(_: i64, _: i32, _: i32) -> i64;
1100    #[link_name = "llvm.hexagon.M2.mpyud.nac.lh.s1"]
1101    fn hexagon_M2_mpyud_nac_lh_s1(_: i64, _: i32, _: i32) -> i64;
1102    #[link_name = "llvm.hexagon.M2.mpyud.nac.ll.s0"]
1103    fn hexagon_M2_mpyud_nac_ll_s0(_: i64, _: i32, _: i32) -> i64;
1104    #[link_name = "llvm.hexagon.M2.mpyud.nac.ll.s1"]
1105    fn hexagon_M2_mpyud_nac_ll_s1(_: i64, _: i32, _: i32) -> i64;
1106    #[link_name = "llvm.hexagon.M2.mpyui"]
1107    fn hexagon_M2_mpyui(_: i32, _: i32) -> i32;
1108    #[link_name = "llvm.hexagon.M2.nacci"]
1109    fn hexagon_M2_nacci(_: i32, _: i32, _: i32) -> i32;
1110    #[link_name = "llvm.hexagon.M2.naccii"]
1111    fn hexagon_M2_naccii(_: i32, _: i32, _: i32) -> i32;
1112    #[link_name = "llvm.hexagon.M2.subacc"]
1113    fn hexagon_M2_subacc(_: i32, _: i32, _: i32) -> i32;
1114    #[link_name = "llvm.hexagon.M2.vabsdiffh"]
1115    fn hexagon_M2_vabsdiffh(_: i64, _: i64) -> i64;
1116    #[link_name = "llvm.hexagon.M2.vabsdiffw"]
1117    fn hexagon_M2_vabsdiffw(_: i64, _: i64) -> i64;
1118    #[link_name = "llvm.hexagon.M2.vcmac.s0.sat.i"]
1119    fn hexagon_M2_vcmac_s0_sat_i(_: i64, _: i64, _: i64) -> i64;
1120    #[link_name = "llvm.hexagon.M2.vcmac.s0.sat.r"]
1121    fn hexagon_M2_vcmac_s0_sat_r(_: i64, _: i64, _: i64) -> i64;
1122    #[link_name = "llvm.hexagon.M2.vcmpy.s0.sat.i"]
1123    fn hexagon_M2_vcmpy_s0_sat_i(_: i64, _: i64) -> i64;
1124    #[link_name = "llvm.hexagon.M2.vcmpy.s0.sat.r"]
1125    fn hexagon_M2_vcmpy_s0_sat_r(_: i64, _: i64) -> i64;
1126    #[link_name = "llvm.hexagon.M2.vcmpy.s1.sat.i"]
1127    fn hexagon_M2_vcmpy_s1_sat_i(_: i64, _: i64) -> i64;
1128    #[link_name = "llvm.hexagon.M2.vcmpy.s1.sat.r"]
1129    fn hexagon_M2_vcmpy_s1_sat_r(_: i64, _: i64) -> i64;
1130    #[link_name = "llvm.hexagon.M2.vdmacs.s0"]
1131    fn hexagon_M2_vdmacs_s0(_: i64, _: i64, _: i64) -> i64;
1132    #[link_name = "llvm.hexagon.M2.vdmacs.s1"]
1133    fn hexagon_M2_vdmacs_s1(_: i64, _: i64, _: i64) -> i64;
1134    #[link_name = "llvm.hexagon.M2.vdmpyrs.s0"]
1135    fn hexagon_M2_vdmpyrs_s0(_: i64, _: i64) -> i32;
1136    #[link_name = "llvm.hexagon.M2.vdmpyrs.s1"]
1137    fn hexagon_M2_vdmpyrs_s1(_: i64, _: i64) -> i32;
1138    #[link_name = "llvm.hexagon.M2.vdmpys.s0"]
1139    fn hexagon_M2_vdmpys_s0(_: i64, _: i64) -> i64;
1140    #[link_name = "llvm.hexagon.M2.vdmpys.s1"]
1141    fn hexagon_M2_vdmpys_s1(_: i64, _: i64) -> i64;
1142    #[link_name = "llvm.hexagon.M2.vmac2"]
1143    fn hexagon_M2_vmac2(_: i64, _: i32, _: i32) -> i64;
1144    #[link_name = "llvm.hexagon.M2.vmac2es"]
1145    fn hexagon_M2_vmac2es(_: i64, _: i64, _: i64) -> i64;
1146    #[link_name = "llvm.hexagon.M2.vmac2es.s0"]
1147    fn hexagon_M2_vmac2es_s0(_: i64, _: i64, _: i64) -> i64;
1148    #[link_name = "llvm.hexagon.M2.vmac2es.s1"]
1149    fn hexagon_M2_vmac2es_s1(_: i64, _: i64, _: i64) -> i64;
1150    #[link_name = "llvm.hexagon.M2.vmac2s.s0"]
1151    fn hexagon_M2_vmac2s_s0(_: i64, _: i32, _: i32) -> i64;
1152    #[link_name = "llvm.hexagon.M2.vmac2s.s1"]
1153    fn hexagon_M2_vmac2s_s1(_: i64, _: i32, _: i32) -> i64;
1154    #[link_name = "llvm.hexagon.M2.vmac2su.s0"]
1155    fn hexagon_M2_vmac2su_s0(_: i64, _: i32, _: i32) -> i64;
1156    #[link_name = "llvm.hexagon.M2.vmac2su.s1"]
1157    fn hexagon_M2_vmac2su_s1(_: i64, _: i32, _: i32) -> i64;
1158    #[link_name = "llvm.hexagon.M2.vmpy2es.s0"]
1159    fn hexagon_M2_vmpy2es_s0(_: i64, _: i64) -> i64;
1160    #[link_name = "llvm.hexagon.M2.vmpy2es.s1"]
1161    fn hexagon_M2_vmpy2es_s1(_: i64, _: i64) -> i64;
1162    #[link_name = "llvm.hexagon.M2.vmpy2s.s0"]
1163    fn hexagon_M2_vmpy2s_s0(_: i32, _: i32) -> i64;
1164    #[link_name = "llvm.hexagon.M2.vmpy2s.s0pack"]
1165    fn hexagon_M2_vmpy2s_s0pack(_: i32, _: i32) -> i32;
1166    #[link_name = "llvm.hexagon.M2.vmpy2s.s1"]
1167    fn hexagon_M2_vmpy2s_s1(_: i32, _: i32) -> i64;
1168    #[link_name = "llvm.hexagon.M2.vmpy2s.s1pack"]
1169    fn hexagon_M2_vmpy2s_s1pack(_: i32, _: i32) -> i32;
1170    #[link_name = "llvm.hexagon.M2.vmpy2su.s0"]
1171    fn hexagon_M2_vmpy2su_s0(_: i32, _: i32) -> i64;
1172    #[link_name = "llvm.hexagon.M2.vmpy2su.s1"]
1173    fn hexagon_M2_vmpy2su_s1(_: i32, _: i32) -> i64;
1174    #[link_name = "llvm.hexagon.M2.vraddh"]
1175    fn hexagon_M2_vraddh(_: i64, _: i64) -> i32;
1176    #[link_name = "llvm.hexagon.M2.vradduh"]
1177    fn hexagon_M2_vradduh(_: i64, _: i64) -> i32;
1178    #[link_name = "llvm.hexagon.M2.vrcmaci.s0"]
1179    fn hexagon_M2_vrcmaci_s0(_: i64, _: i64, _: i64) -> i64;
1180    #[link_name = "llvm.hexagon.M2.vrcmaci.s0c"]
1181    fn hexagon_M2_vrcmaci_s0c(_: i64, _: i64, _: i64) -> i64;
1182    #[link_name = "llvm.hexagon.M2.vrcmacr.s0"]
1183    fn hexagon_M2_vrcmacr_s0(_: i64, _: i64, _: i64) -> i64;
1184    #[link_name = "llvm.hexagon.M2.vrcmacr.s0c"]
1185    fn hexagon_M2_vrcmacr_s0c(_: i64, _: i64, _: i64) -> i64;
1186    #[link_name = "llvm.hexagon.M2.vrcmpyi.s0"]
1187    fn hexagon_M2_vrcmpyi_s0(_: i64, _: i64) -> i64;
1188    #[link_name = "llvm.hexagon.M2.vrcmpyi.s0c"]
1189    fn hexagon_M2_vrcmpyi_s0c(_: i64, _: i64) -> i64;
1190    #[link_name = "llvm.hexagon.M2.vrcmpyr.s0"]
1191    fn hexagon_M2_vrcmpyr_s0(_: i64, _: i64) -> i64;
1192    #[link_name = "llvm.hexagon.M2.vrcmpyr.s0c"]
1193    fn hexagon_M2_vrcmpyr_s0c(_: i64, _: i64) -> i64;
1194    #[link_name = "llvm.hexagon.M2.vrcmpys.acc.s1"]
1195    fn hexagon_M2_vrcmpys_acc_s1(_: i64, _: i64, _: i32) -> i64;
1196    #[link_name = "llvm.hexagon.M2.vrcmpys.s1"]
1197    fn hexagon_M2_vrcmpys_s1(_: i64, _: i32) -> i64;
1198    #[link_name = "llvm.hexagon.M2.vrcmpys.s1rp"]
1199    fn hexagon_M2_vrcmpys_s1rp(_: i64, _: i32) -> i32;
1200    #[link_name = "llvm.hexagon.M2.vrmac.s0"]
1201    fn hexagon_M2_vrmac_s0(_: i64, _: i64, _: i64) -> i64;
1202    #[link_name = "llvm.hexagon.M2.vrmpy.s0"]
1203    fn hexagon_M2_vrmpy_s0(_: i64, _: i64) -> i64;
1204    #[link_name = "llvm.hexagon.M2.xor.xacc"]
1205    fn hexagon_M2_xor_xacc(_: i32, _: i32, _: i32) -> i32;
1206    #[link_name = "llvm.hexagon.M4.and.and"]
1207    fn hexagon_M4_and_and(_: i32, _: i32, _: i32) -> i32;
1208    #[link_name = "llvm.hexagon.M4.and.andn"]
1209    fn hexagon_M4_and_andn(_: i32, _: i32, _: i32) -> i32;
1210    #[link_name = "llvm.hexagon.M4.and.or"]
1211    fn hexagon_M4_and_or(_: i32, _: i32, _: i32) -> i32;
1212    #[link_name = "llvm.hexagon.M4.and.xor"]
1213    fn hexagon_M4_and_xor(_: i32, _: i32, _: i32) -> i32;
1214    #[link_name = "llvm.hexagon.M4.cmpyi.wh"]
1215    fn hexagon_M4_cmpyi_wh(_: i64, _: i32) -> i32;
1216    #[link_name = "llvm.hexagon.M4.cmpyi.whc"]
1217    fn hexagon_M4_cmpyi_whc(_: i64, _: i32) -> i32;
1218    #[link_name = "llvm.hexagon.M4.cmpyr.wh"]
1219    fn hexagon_M4_cmpyr_wh(_: i64, _: i32) -> i32;
1220    #[link_name = "llvm.hexagon.M4.cmpyr.whc"]
1221    fn hexagon_M4_cmpyr_whc(_: i64, _: i32) -> i32;
1222    #[link_name = "llvm.hexagon.M4.mac.up.s1.sat"]
1223    fn hexagon_M4_mac_up_s1_sat(_: i32, _: i32, _: i32) -> i32;
1224    #[link_name = "llvm.hexagon.M4.mpyri.addi"]
1225    fn hexagon_M4_mpyri_addi(_: i32, _: i32, _: i32) -> i32;
1226    #[link_name = "llvm.hexagon.M4.mpyri.addr"]
1227    fn hexagon_M4_mpyri_addr(_: i32, _: i32, _: i32) -> i32;
1228    #[link_name = "llvm.hexagon.M4.mpyri.addr.u2"]
1229    fn hexagon_M4_mpyri_addr_u2(_: i32, _: i32, _: i32) -> i32;
1230    #[link_name = "llvm.hexagon.M4.mpyrr.addi"]
1231    fn hexagon_M4_mpyrr_addi(_: i32, _: i32, _: i32) -> i32;
1232    #[link_name = "llvm.hexagon.M4.mpyrr.addr"]
1233    fn hexagon_M4_mpyrr_addr(_: i32, _: i32, _: i32) -> i32;
1234    #[link_name = "llvm.hexagon.M4.nac.up.s1.sat"]
1235    fn hexagon_M4_nac_up_s1_sat(_: i32, _: i32, _: i32) -> i32;
1236    #[link_name = "llvm.hexagon.M4.or.and"]
1237    fn hexagon_M4_or_and(_: i32, _: i32, _: i32) -> i32;
1238    #[link_name = "llvm.hexagon.M4.or.andn"]
1239    fn hexagon_M4_or_andn(_: i32, _: i32, _: i32) -> i32;
1240    #[link_name = "llvm.hexagon.M4.or.or"]
1241    fn hexagon_M4_or_or(_: i32, _: i32, _: i32) -> i32;
1242    #[link_name = "llvm.hexagon.M4.or.xor"]
1243    fn hexagon_M4_or_xor(_: i32, _: i32, _: i32) -> i32;
1244    #[link_name = "llvm.hexagon.M4.pmpyw"]
1245    fn hexagon_M4_pmpyw(_: i32, _: i32) -> i64;
1246    #[link_name = "llvm.hexagon.M4.pmpyw.acc"]
1247    fn hexagon_M4_pmpyw_acc(_: i64, _: i32, _: i32) -> i64;
1248    #[link_name = "llvm.hexagon.M4.vpmpyh"]
1249    fn hexagon_M4_vpmpyh(_: i32, _: i32) -> i64;
1250    #[link_name = "llvm.hexagon.M4.vpmpyh.acc"]
1251    fn hexagon_M4_vpmpyh_acc(_: i64, _: i32, _: i32) -> i64;
1252    #[link_name = "llvm.hexagon.M4.vrmpyeh.acc.s0"]
1253    fn hexagon_M4_vrmpyeh_acc_s0(_: i64, _: i64, _: i64) -> i64;
1254    #[link_name = "llvm.hexagon.M4.vrmpyeh.acc.s1"]
1255    fn hexagon_M4_vrmpyeh_acc_s1(_: i64, _: i64, _: i64) -> i64;
1256    #[link_name = "llvm.hexagon.M4.vrmpyeh.s0"]
1257    fn hexagon_M4_vrmpyeh_s0(_: i64, _: i64) -> i64;
1258    #[link_name = "llvm.hexagon.M4.vrmpyeh.s1"]
1259    fn hexagon_M4_vrmpyeh_s1(_: i64, _: i64) -> i64;
1260    #[link_name = "llvm.hexagon.M4.vrmpyoh.acc.s0"]
1261    fn hexagon_M4_vrmpyoh_acc_s0(_: i64, _: i64, _: i64) -> i64;
1262    #[link_name = "llvm.hexagon.M4.vrmpyoh.acc.s1"]
1263    fn hexagon_M4_vrmpyoh_acc_s1(_: i64, _: i64, _: i64) -> i64;
1264    #[link_name = "llvm.hexagon.M4.vrmpyoh.s0"]
1265    fn hexagon_M4_vrmpyoh_s0(_: i64, _: i64) -> i64;
1266    #[link_name = "llvm.hexagon.M4.vrmpyoh.s1"]
1267    fn hexagon_M4_vrmpyoh_s1(_: i64, _: i64) -> i64;
1268    #[link_name = "llvm.hexagon.M4.xor.and"]
1269    fn hexagon_M4_xor_and(_: i32, _: i32, _: i32) -> i32;
1270    #[link_name = "llvm.hexagon.M4.xor.andn"]
1271    fn hexagon_M4_xor_andn(_: i32, _: i32, _: i32) -> i32;
1272    #[link_name = "llvm.hexagon.M4.xor.or"]
1273    fn hexagon_M4_xor_or(_: i32, _: i32, _: i32) -> i32;
1274    #[link_name = "llvm.hexagon.M4.xor.xacc"]
1275    fn hexagon_M4_xor_xacc(_: i64, _: i64, _: i64) -> i64;
1276    #[link_name = "llvm.hexagon.M5.vdmacbsu"]
1277    fn hexagon_M5_vdmacbsu(_: i64, _: i64, _: i64) -> i64;
1278    #[link_name = "llvm.hexagon.M5.vdmpybsu"]
1279    fn hexagon_M5_vdmpybsu(_: i64, _: i64) -> i64;
1280    #[link_name = "llvm.hexagon.M5.vmacbsu"]
1281    fn hexagon_M5_vmacbsu(_: i64, _: i32, _: i32) -> i64;
1282    #[link_name = "llvm.hexagon.M5.vmacbuu"]
1283    fn hexagon_M5_vmacbuu(_: i64, _: i32, _: i32) -> i64;
1284    #[link_name = "llvm.hexagon.M5.vmpybsu"]
1285    fn hexagon_M5_vmpybsu(_: i32, _: i32) -> i64;
1286    #[link_name = "llvm.hexagon.M5.vmpybuu"]
1287    fn hexagon_M5_vmpybuu(_: i32, _: i32) -> i64;
1288    #[link_name = "llvm.hexagon.M5.vrmacbsu"]
1289    fn hexagon_M5_vrmacbsu(_: i64, _: i64, _: i64) -> i64;
1290    #[link_name = "llvm.hexagon.M5.vrmacbuu"]
1291    fn hexagon_M5_vrmacbuu(_: i64, _: i64, _: i64) -> i64;
1292    #[link_name = "llvm.hexagon.M5.vrmpybsu"]
1293    fn hexagon_M5_vrmpybsu(_: i64, _: i64) -> i64;
1294    #[link_name = "llvm.hexagon.M5.vrmpybuu"]
1295    fn hexagon_M5_vrmpybuu(_: i64, _: i64) -> i64;
1296    #[link_name = "llvm.hexagon.S2.addasl.rrri"]
1297    fn hexagon_S2_addasl_rrri(_: i32, _: i32, _: i32) -> i32;
1298    #[link_name = "llvm.hexagon.S2.asl.i.p"]
1299    fn hexagon_S2_asl_i_p(_: i64, _: i32) -> i64;
1300    #[link_name = "llvm.hexagon.S2.asl.i.p.acc"]
1301    fn hexagon_S2_asl_i_p_acc(_: i64, _: i64, _: i32) -> i64;
1302    #[link_name = "llvm.hexagon.S2.asl.i.p.and"]
1303    fn hexagon_S2_asl_i_p_and(_: i64, _: i64, _: i32) -> i64;
1304    #[link_name = "llvm.hexagon.S2.asl.i.p.nac"]
1305    fn hexagon_S2_asl_i_p_nac(_: i64, _: i64, _: i32) -> i64;
1306    #[link_name = "llvm.hexagon.S2.asl.i.p.or"]
1307    fn hexagon_S2_asl_i_p_or(_: i64, _: i64, _: i32) -> i64;
1308    #[link_name = "llvm.hexagon.S2.asl.i.p.xacc"]
1309    fn hexagon_S2_asl_i_p_xacc(_: i64, _: i64, _: i32) -> i64;
1310    #[link_name = "llvm.hexagon.S2.asl.i.r"]
1311    fn hexagon_S2_asl_i_r(_: i32, _: i32) -> i32;
1312    #[link_name = "llvm.hexagon.S2.asl.i.r.acc"]
1313    fn hexagon_S2_asl_i_r_acc(_: i32, _: i32, _: i32) -> i32;
1314    #[link_name = "llvm.hexagon.S2.asl.i.r.and"]
1315    fn hexagon_S2_asl_i_r_and(_: i32, _: i32, _: i32) -> i32;
1316    #[link_name = "llvm.hexagon.S2.asl.i.r.nac"]
1317    fn hexagon_S2_asl_i_r_nac(_: i32, _: i32, _: i32) -> i32;
1318    #[link_name = "llvm.hexagon.S2.asl.i.r.or"]
1319    fn hexagon_S2_asl_i_r_or(_: i32, _: i32, _: i32) -> i32;
1320    #[link_name = "llvm.hexagon.S2.asl.i.r.sat"]
1321    fn hexagon_S2_asl_i_r_sat(_: i32, _: i32) -> i32;
1322    #[link_name = "llvm.hexagon.S2.asl.i.r.xacc"]
1323    fn hexagon_S2_asl_i_r_xacc(_: i32, _: i32, _: i32) -> i32;
1324    #[link_name = "llvm.hexagon.S2.asl.i.vh"]
1325    fn hexagon_S2_asl_i_vh(_: i64, _: i32) -> i64;
1326    #[link_name = "llvm.hexagon.S2.asl.i.vw"]
1327    fn hexagon_S2_asl_i_vw(_: i64, _: i32) -> i64;
1328    #[link_name = "llvm.hexagon.S2.asl.r.p"]
1329    fn hexagon_S2_asl_r_p(_: i64, _: i32) -> i64;
1330    #[link_name = "llvm.hexagon.S2.asl.r.p.acc"]
1331    fn hexagon_S2_asl_r_p_acc(_: i64, _: i64, _: i32) -> i64;
1332    #[link_name = "llvm.hexagon.S2.asl.r.p.and"]
1333    fn hexagon_S2_asl_r_p_and(_: i64, _: i64, _: i32) -> i64;
1334    #[link_name = "llvm.hexagon.S2.asl.r.p.nac"]
1335    fn hexagon_S2_asl_r_p_nac(_: i64, _: i64, _: i32) -> i64;
1336    #[link_name = "llvm.hexagon.S2.asl.r.p.or"]
1337    fn hexagon_S2_asl_r_p_or(_: i64, _: i64, _: i32) -> i64;
1338    #[link_name = "llvm.hexagon.S2.asl.r.p.xor"]
1339    fn hexagon_S2_asl_r_p_xor(_: i64, _: i64, _: i32) -> i64;
1340    #[link_name = "llvm.hexagon.S2.asl.r.r"]
1341    fn hexagon_S2_asl_r_r(_: i32, _: i32) -> i32;
1342    #[link_name = "llvm.hexagon.S2.asl.r.r.acc"]
1343    fn hexagon_S2_asl_r_r_acc(_: i32, _: i32, _: i32) -> i32;
1344    #[link_name = "llvm.hexagon.S2.asl.r.r.and"]
1345    fn hexagon_S2_asl_r_r_and(_: i32, _: i32, _: i32) -> i32;
1346    #[link_name = "llvm.hexagon.S2.asl.r.r.nac"]
1347    fn hexagon_S2_asl_r_r_nac(_: i32, _: i32, _: i32) -> i32;
1348    #[link_name = "llvm.hexagon.S2.asl.r.r.or"]
1349    fn hexagon_S2_asl_r_r_or(_: i32, _: i32, _: i32) -> i32;
1350    #[link_name = "llvm.hexagon.S2.asl.r.r.sat"]
1351    fn hexagon_S2_asl_r_r_sat(_: i32, _: i32) -> i32;
1352    #[link_name = "llvm.hexagon.S2.asl.r.vh"]
1353    fn hexagon_S2_asl_r_vh(_: i64, _: i32) -> i64;
1354    #[link_name = "llvm.hexagon.S2.asl.r.vw"]
1355    fn hexagon_S2_asl_r_vw(_: i64, _: i32) -> i64;
1356    #[link_name = "llvm.hexagon.S2.asr.i.p"]
1357    fn hexagon_S2_asr_i_p(_: i64, _: i32) -> i64;
1358    #[link_name = "llvm.hexagon.S2.asr.i.p.acc"]
1359    fn hexagon_S2_asr_i_p_acc(_: i64, _: i64, _: i32) -> i64;
1360    #[link_name = "llvm.hexagon.S2.asr.i.p.and"]
1361    fn hexagon_S2_asr_i_p_and(_: i64, _: i64, _: i32) -> i64;
1362    #[link_name = "llvm.hexagon.S2.asr.i.p.nac"]
1363    fn hexagon_S2_asr_i_p_nac(_: i64, _: i64, _: i32) -> i64;
1364    #[link_name = "llvm.hexagon.S2.asr.i.p.or"]
1365    fn hexagon_S2_asr_i_p_or(_: i64, _: i64, _: i32) -> i64;
1366    #[link_name = "llvm.hexagon.S2.asr.i.p.rnd"]
1367    fn hexagon_S2_asr_i_p_rnd(_: i64, _: i32) -> i64;
1368    #[link_name = "llvm.hexagon.S2.asr.i.p.rnd.goodsyntax"]
1369    fn hexagon_S2_asr_i_p_rnd_goodsyntax(_: i64, _: i32) -> i64;
1370    #[link_name = "llvm.hexagon.S2.asr.i.r"]
1371    fn hexagon_S2_asr_i_r(_: i32, _: i32) -> i32;
1372    #[link_name = "llvm.hexagon.S2.asr.i.r.acc"]
1373    fn hexagon_S2_asr_i_r_acc(_: i32, _: i32, _: i32) -> i32;
1374    #[link_name = "llvm.hexagon.S2.asr.i.r.and"]
1375    fn hexagon_S2_asr_i_r_and(_: i32, _: i32, _: i32) -> i32;
1376    #[link_name = "llvm.hexagon.S2.asr.i.r.nac"]
1377    fn hexagon_S2_asr_i_r_nac(_: i32, _: i32, _: i32) -> i32;
1378    #[link_name = "llvm.hexagon.S2.asr.i.r.or"]
1379    fn hexagon_S2_asr_i_r_or(_: i32, _: i32, _: i32) -> i32;
1380    #[link_name = "llvm.hexagon.S2.asr.i.r.rnd"]
1381    fn hexagon_S2_asr_i_r_rnd(_: i32, _: i32) -> i32;
1382    #[link_name = "llvm.hexagon.S2.asr.i.r.rnd.goodsyntax"]
1383    fn hexagon_S2_asr_i_r_rnd_goodsyntax(_: i32, _: i32) -> i32;
1384    #[link_name = "llvm.hexagon.S2.asr.i.svw.trun"]
1385    fn hexagon_S2_asr_i_svw_trun(_: i64, _: i32) -> i32;
1386    #[link_name = "llvm.hexagon.S2.asr.i.vh"]
1387    fn hexagon_S2_asr_i_vh(_: i64, _: i32) -> i64;
1388    #[link_name = "llvm.hexagon.S2.asr.i.vw"]
1389    fn hexagon_S2_asr_i_vw(_: i64, _: i32) -> i64;
1390    #[link_name = "llvm.hexagon.S2.asr.r.p"]
1391    fn hexagon_S2_asr_r_p(_: i64, _: i32) -> i64;
1392    #[link_name = "llvm.hexagon.S2.asr.r.p.acc"]
1393    fn hexagon_S2_asr_r_p_acc(_: i64, _: i64, _: i32) -> i64;
1394    #[link_name = "llvm.hexagon.S2.asr.r.p.and"]
1395    fn hexagon_S2_asr_r_p_and(_: i64, _: i64, _: i32) -> i64;
1396    #[link_name = "llvm.hexagon.S2.asr.r.p.nac"]
1397    fn hexagon_S2_asr_r_p_nac(_: i64, _: i64, _: i32) -> i64;
1398    #[link_name = "llvm.hexagon.S2.asr.r.p.or"]
1399    fn hexagon_S2_asr_r_p_or(_: i64, _: i64, _: i32) -> i64;
1400    #[link_name = "llvm.hexagon.S2.asr.r.p.xor"]
1401    fn hexagon_S2_asr_r_p_xor(_: i64, _: i64, _: i32) -> i64;
1402    #[link_name = "llvm.hexagon.S2.asr.r.r"]
1403    fn hexagon_S2_asr_r_r(_: i32, _: i32) -> i32;
1404    #[link_name = "llvm.hexagon.S2.asr.r.r.acc"]
1405    fn hexagon_S2_asr_r_r_acc(_: i32, _: i32, _: i32) -> i32;
1406    #[link_name = "llvm.hexagon.S2.asr.r.r.and"]
1407    fn hexagon_S2_asr_r_r_and(_: i32, _: i32, _: i32) -> i32;
1408    #[link_name = "llvm.hexagon.S2.asr.r.r.nac"]
1409    fn hexagon_S2_asr_r_r_nac(_: i32, _: i32, _: i32) -> i32;
1410    #[link_name = "llvm.hexagon.S2.asr.r.r.or"]
1411    fn hexagon_S2_asr_r_r_or(_: i32, _: i32, _: i32) -> i32;
1412    #[link_name = "llvm.hexagon.S2.asr.r.r.sat"]
1413    fn hexagon_S2_asr_r_r_sat(_: i32, _: i32) -> i32;
1414    #[link_name = "llvm.hexagon.S2.asr.r.svw.trun"]
1415    fn hexagon_S2_asr_r_svw_trun(_: i64, _: i32) -> i32;
1416    #[link_name = "llvm.hexagon.S2.asr.r.vh"]
1417    fn hexagon_S2_asr_r_vh(_: i64, _: i32) -> i64;
1418    #[link_name = "llvm.hexagon.S2.asr.r.vw"]
1419    fn hexagon_S2_asr_r_vw(_: i64, _: i32) -> i64;
1420    #[link_name = "llvm.hexagon.S2.brev"]
1421    fn hexagon_S2_brev(_: i32) -> i32;
1422    #[link_name = "llvm.hexagon.S2.brevp"]
1423    fn hexagon_S2_brevp(_: i64) -> i64;
1424    #[link_name = "llvm.hexagon.S2.cl0"]
1425    fn hexagon_S2_cl0(_: i32) -> i32;
1426    #[link_name = "llvm.hexagon.S2.cl0p"]
1427    fn hexagon_S2_cl0p(_: i64) -> i32;
1428    #[link_name = "llvm.hexagon.S2.cl1"]
1429    fn hexagon_S2_cl1(_: i32) -> i32;
1430    #[link_name = "llvm.hexagon.S2.cl1p"]
1431    fn hexagon_S2_cl1p(_: i64) -> i32;
1432    #[link_name = "llvm.hexagon.S2.clb"]
1433    fn hexagon_S2_clb(_: i32) -> i32;
1434    #[link_name = "llvm.hexagon.S2.clbnorm"]
1435    fn hexagon_S2_clbnorm(_: i32) -> i32;
1436    #[link_name = "llvm.hexagon.S2.clbp"]
1437    fn hexagon_S2_clbp(_: i64) -> i32;
1438    #[link_name = "llvm.hexagon.S2.clrbit.i"]
1439    fn hexagon_S2_clrbit_i(_: i32, _: i32) -> i32;
1440    #[link_name = "llvm.hexagon.S2.clrbit.r"]
1441    fn hexagon_S2_clrbit_r(_: i32, _: i32) -> i32;
1442    #[link_name = "llvm.hexagon.S2.ct0"]
1443    fn hexagon_S2_ct0(_: i32) -> i32;
1444    #[link_name = "llvm.hexagon.S2.ct0p"]
1445    fn hexagon_S2_ct0p(_: i64) -> i32;
1446    #[link_name = "llvm.hexagon.S2.ct1"]
1447    fn hexagon_S2_ct1(_: i32) -> i32;
1448    #[link_name = "llvm.hexagon.S2.ct1p"]
1449    fn hexagon_S2_ct1p(_: i64) -> i32;
1450    #[link_name = "llvm.hexagon.S2.deinterleave"]
1451    fn hexagon_S2_deinterleave(_: i64) -> i64;
1452    #[link_name = "llvm.hexagon.S2.extractu"]
1453    fn hexagon_S2_extractu(_: i32, _: i32, _: i32) -> i32;
1454    #[link_name = "llvm.hexagon.S2.extractu.rp"]
1455    fn hexagon_S2_extractu_rp(_: i32, _: i64) -> i32;
1456    #[link_name = "llvm.hexagon.S2.extractup"]
1457    fn hexagon_S2_extractup(_: i64, _: i32, _: i32) -> i64;
1458    #[link_name = "llvm.hexagon.S2.extractup.rp"]
1459    fn hexagon_S2_extractup_rp(_: i64, _: i64) -> i64;
1460    #[link_name = "llvm.hexagon.S2.insert"]
1461    fn hexagon_S2_insert(_: i32, _: i32, _: i32, _: i32) -> i32;
1462    #[link_name = "llvm.hexagon.S2.insert.rp"]
1463    fn hexagon_S2_insert_rp(_: i32, _: i32, _: i64) -> i32;
1464    #[link_name = "llvm.hexagon.S2.insertp"]
1465    fn hexagon_S2_insertp(_: i64, _: i64, _: i32, _: i32) -> i64;
1466    #[link_name = "llvm.hexagon.S2.insertp.rp"]
1467    fn hexagon_S2_insertp_rp(_: i64, _: i64, _: i64) -> i64;
1468    #[link_name = "llvm.hexagon.S2.interleave"]
1469    fn hexagon_S2_interleave(_: i64) -> i64;
1470    #[link_name = "llvm.hexagon.S2.lfsp"]
1471    fn hexagon_S2_lfsp(_: i64, _: i64) -> i64;
1472    #[link_name = "llvm.hexagon.S2.lsl.r.p"]
1473    fn hexagon_S2_lsl_r_p(_: i64, _: i32) -> i64;
1474    #[link_name = "llvm.hexagon.S2.lsl.r.p.acc"]
1475    fn hexagon_S2_lsl_r_p_acc(_: i64, _: i64, _: i32) -> i64;
1476    #[link_name = "llvm.hexagon.S2.lsl.r.p.and"]
1477    fn hexagon_S2_lsl_r_p_and(_: i64, _: i64, _: i32) -> i64;
1478    #[link_name = "llvm.hexagon.S2.lsl.r.p.nac"]
1479    fn hexagon_S2_lsl_r_p_nac(_: i64, _: i64, _: i32) -> i64;
1480    #[link_name = "llvm.hexagon.S2.lsl.r.p.or"]
1481    fn hexagon_S2_lsl_r_p_or(_: i64, _: i64, _: i32) -> i64;
1482    #[link_name = "llvm.hexagon.S2.lsl.r.p.xor"]
1483    fn hexagon_S2_lsl_r_p_xor(_: i64, _: i64, _: i32) -> i64;
1484    #[link_name = "llvm.hexagon.S2.lsl.r.r"]
1485    fn hexagon_S2_lsl_r_r(_: i32, _: i32) -> i32;
1486    #[link_name = "llvm.hexagon.S2.lsl.r.r.acc"]
1487    fn hexagon_S2_lsl_r_r_acc(_: i32, _: i32, _: i32) -> i32;
1488    #[link_name = "llvm.hexagon.S2.lsl.r.r.and"]
1489    fn hexagon_S2_lsl_r_r_and(_: i32, _: i32, _: i32) -> i32;
1490    #[link_name = "llvm.hexagon.S2.lsl.r.r.nac"]
1491    fn hexagon_S2_lsl_r_r_nac(_: i32, _: i32, _: i32) -> i32;
1492    #[link_name = "llvm.hexagon.S2.lsl.r.r.or"]
1493    fn hexagon_S2_lsl_r_r_or(_: i32, _: i32, _: i32) -> i32;
1494    #[link_name = "llvm.hexagon.S2.lsl.r.vh"]
1495    fn hexagon_S2_lsl_r_vh(_: i64, _: i32) -> i64;
1496    #[link_name = "llvm.hexagon.S2.lsl.r.vw"]
1497    fn hexagon_S2_lsl_r_vw(_: i64, _: i32) -> i64;
1498    #[link_name = "llvm.hexagon.S2.lsr.i.p"]
1499    fn hexagon_S2_lsr_i_p(_: i64, _: i32) -> i64;
1500    #[link_name = "llvm.hexagon.S2.lsr.i.p.acc"]
1501    fn hexagon_S2_lsr_i_p_acc(_: i64, _: i64, _: i32) -> i64;
1502    #[link_name = "llvm.hexagon.S2.lsr.i.p.and"]
1503    fn hexagon_S2_lsr_i_p_and(_: i64, _: i64, _: i32) -> i64;
1504    #[link_name = "llvm.hexagon.S2.lsr.i.p.nac"]
1505    fn hexagon_S2_lsr_i_p_nac(_: i64, _: i64, _: i32) -> i64;
1506    #[link_name = "llvm.hexagon.S2.lsr.i.p.or"]
1507    fn hexagon_S2_lsr_i_p_or(_: i64, _: i64, _: i32) -> i64;
1508    #[link_name = "llvm.hexagon.S2.lsr.i.p.xacc"]
1509    fn hexagon_S2_lsr_i_p_xacc(_: i64, _: i64, _: i32) -> i64;
1510    #[link_name = "llvm.hexagon.S2.lsr.i.r"]
1511    fn hexagon_S2_lsr_i_r(_: i32, _: i32) -> i32;
1512    #[link_name = "llvm.hexagon.S2.lsr.i.r.acc"]
1513    fn hexagon_S2_lsr_i_r_acc(_: i32, _: i32, _: i32) -> i32;
1514    #[link_name = "llvm.hexagon.S2.lsr.i.r.and"]
1515    fn hexagon_S2_lsr_i_r_and(_: i32, _: i32, _: i32) -> i32;
1516    #[link_name = "llvm.hexagon.S2.lsr.i.r.nac"]
1517    fn hexagon_S2_lsr_i_r_nac(_: i32, _: i32, _: i32) -> i32;
1518    #[link_name = "llvm.hexagon.S2.lsr.i.r.or"]
1519    fn hexagon_S2_lsr_i_r_or(_: i32, _: i32, _: i32) -> i32;
1520    #[link_name = "llvm.hexagon.S2.lsr.i.r.xacc"]
1521    fn hexagon_S2_lsr_i_r_xacc(_: i32, _: i32, _: i32) -> i32;
1522    #[link_name = "llvm.hexagon.S2.lsr.i.vh"]
1523    fn hexagon_S2_lsr_i_vh(_: i64, _: i32) -> i64;
1524    #[link_name = "llvm.hexagon.S2.lsr.i.vw"]
1525    fn hexagon_S2_lsr_i_vw(_: i64, _: i32) -> i64;
1526    #[link_name = "llvm.hexagon.S2.lsr.r.p"]
1527    fn hexagon_S2_lsr_r_p(_: i64, _: i32) -> i64;
1528    #[link_name = "llvm.hexagon.S2.lsr.r.p.acc"]
1529    fn hexagon_S2_lsr_r_p_acc(_: i64, _: i64, _: i32) -> i64;
1530    #[link_name = "llvm.hexagon.S2.lsr.r.p.and"]
1531    fn hexagon_S2_lsr_r_p_and(_: i64, _: i64, _: i32) -> i64;
1532    #[link_name = "llvm.hexagon.S2.lsr.r.p.nac"]
1533    fn hexagon_S2_lsr_r_p_nac(_: i64, _: i64, _: i32) -> i64;
1534    #[link_name = "llvm.hexagon.S2.lsr.r.p.or"]
1535    fn hexagon_S2_lsr_r_p_or(_: i64, _: i64, _: i32) -> i64;
1536    #[link_name = "llvm.hexagon.S2.lsr.r.p.xor"]
1537    fn hexagon_S2_lsr_r_p_xor(_: i64, _: i64, _: i32) -> i64;
1538    #[link_name = "llvm.hexagon.S2.lsr.r.r"]
1539    fn hexagon_S2_lsr_r_r(_: i32, _: i32) -> i32;
1540    #[link_name = "llvm.hexagon.S2.lsr.r.r.acc"]
1541    fn hexagon_S2_lsr_r_r_acc(_: i32, _: i32, _: i32) -> i32;
1542    #[link_name = "llvm.hexagon.S2.lsr.r.r.and"]
1543    fn hexagon_S2_lsr_r_r_and(_: i32, _: i32, _: i32) -> i32;
1544    #[link_name = "llvm.hexagon.S2.lsr.r.r.nac"]
1545    fn hexagon_S2_lsr_r_r_nac(_: i32, _: i32, _: i32) -> i32;
1546    #[link_name = "llvm.hexagon.S2.lsr.r.r.or"]
1547    fn hexagon_S2_lsr_r_r_or(_: i32, _: i32, _: i32) -> i32;
1548    #[link_name = "llvm.hexagon.S2.lsr.r.vh"]
1549    fn hexagon_S2_lsr_r_vh(_: i64, _: i32) -> i64;
1550    #[link_name = "llvm.hexagon.S2.lsr.r.vw"]
1551    fn hexagon_S2_lsr_r_vw(_: i64, _: i32) -> i64;
1552    #[link_name = "llvm.hexagon.S2.packhl"]
1553    fn hexagon_S2_packhl(_: i32, _: i32) -> i64;
1554    #[link_name = "llvm.hexagon.S2.parityp"]
1555    fn hexagon_S2_parityp(_: i64, _: i64) -> i32;
1556    #[link_name = "llvm.hexagon.S2.setbit.i"]
1557    fn hexagon_S2_setbit_i(_: i32, _: i32) -> i32;
1558    #[link_name = "llvm.hexagon.S2.setbit.r"]
1559    fn hexagon_S2_setbit_r(_: i32, _: i32) -> i32;
1560    #[link_name = "llvm.hexagon.S2.shuffeb"]
1561    fn hexagon_S2_shuffeb(_: i64, _: i64) -> i64;
1562    #[link_name = "llvm.hexagon.S2.shuffeh"]
1563    fn hexagon_S2_shuffeh(_: i64, _: i64) -> i64;
1564    #[link_name = "llvm.hexagon.S2.shuffob"]
1565    fn hexagon_S2_shuffob(_: i64, _: i64) -> i64;
1566    #[link_name = "llvm.hexagon.S2.shuffoh"]
1567    fn hexagon_S2_shuffoh(_: i64, _: i64) -> i64;
1568    #[link_name = "llvm.hexagon.S2.svsathb"]
1569    fn hexagon_S2_svsathb(_: i32) -> i32;
1570    #[link_name = "llvm.hexagon.S2.svsathub"]
1571    fn hexagon_S2_svsathub(_: i32) -> i32;
1572    #[link_name = "llvm.hexagon.S2.tableidxb.goodsyntax"]
1573    fn hexagon_S2_tableidxb_goodsyntax(_: i32, _: i32, _: i32, _: i32) -> i32;
1574    #[link_name = "llvm.hexagon.S2.tableidxd.goodsyntax"]
1575    fn hexagon_S2_tableidxd_goodsyntax(_: i32, _: i32, _: i32, _: i32) -> i32;
1576    #[link_name = "llvm.hexagon.S2.tableidxh.goodsyntax"]
1577    fn hexagon_S2_tableidxh_goodsyntax(_: i32, _: i32, _: i32, _: i32) -> i32;
1578    #[link_name = "llvm.hexagon.S2.tableidxw.goodsyntax"]
1579    fn hexagon_S2_tableidxw_goodsyntax(_: i32, _: i32, _: i32, _: i32) -> i32;
1580    #[link_name = "llvm.hexagon.S2.togglebit.i"]
1581    fn hexagon_S2_togglebit_i(_: i32, _: i32) -> i32;
1582    #[link_name = "llvm.hexagon.S2.togglebit.r"]
1583    fn hexagon_S2_togglebit_r(_: i32, _: i32) -> i32;
1584    #[link_name = "llvm.hexagon.S2.tstbit.i"]
1585    fn hexagon_S2_tstbit_i(_: i32, _: i32) -> i32;
1586    #[link_name = "llvm.hexagon.S2.tstbit.r"]
1587    fn hexagon_S2_tstbit_r(_: i32, _: i32) -> i32;
1588    #[link_name = "llvm.hexagon.S2.valignib"]
1589    fn hexagon_S2_valignib(_: i64, _: i64, _: i32) -> i64;
1590    #[link_name = "llvm.hexagon.S2.valignrb"]
1591    fn hexagon_S2_valignrb(_: i64, _: i64, _: i32) -> i64;
1592    #[link_name = "llvm.hexagon.S2.vcnegh"]
1593    fn hexagon_S2_vcnegh(_: i64, _: i32) -> i64;
1594    #[link_name = "llvm.hexagon.S2.vcrotate"]
1595    fn hexagon_S2_vcrotate(_: i64, _: i32) -> i64;
1596    #[link_name = "llvm.hexagon.S2.vrcnegh"]
1597    fn hexagon_S2_vrcnegh(_: i64, _: i64, _: i32) -> i64;
1598    #[link_name = "llvm.hexagon.S2.vrndpackwh"]
1599    fn hexagon_S2_vrndpackwh(_: i64) -> i32;
1600    #[link_name = "llvm.hexagon.S2.vrndpackwhs"]
1601    fn hexagon_S2_vrndpackwhs(_: i64) -> i32;
1602    #[link_name = "llvm.hexagon.S2.vsathb"]
1603    fn hexagon_S2_vsathb(_: i64) -> i32;
1604    #[link_name = "llvm.hexagon.S2.vsathb.nopack"]
1605    fn hexagon_S2_vsathb_nopack(_: i64) -> i64;
1606    #[link_name = "llvm.hexagon.S2.vsathub"]
1607    fn hexagon_S2_vsathub(_: i64) -> i32;
1608    #[link_name = "llvm.hexagon.S2.vsathub.nopack"]
1609    fn hexagon_S2_vsathub_nopack(_: i64) -> i64;
1610    #[link_name = "llvm.hexagon.S2.vsatwh"]
1611    fn hexagon_S2_vsatwh(_: i64) -> i32;
1612    #[link_name = "llvm.hexagon.S2.vsatwh.nopack"]
1613    fn hexagon_S2_vsatwh_nopack(_: i64) -> i64;
1614    #[link_name = "llvm.hexagon.S2.vsatwuh"]
1615    fn hexagon_S2_vsatwuh(_: i64) -> i32;
1616    #[link_name = "llvm.hexagon.S2.vsatwuh.nopack"]
1617    fn hexagon_S2_vsatwuh_nopack(_: i64) -> i64;
1618    #[link_name = "llvm.hexagon.S2.vsplatrb"]
1619    fn hexagon_S2_vsplatrb(_: i32) -> i32;
1620    #[link_name = "llvm.hexagon.S2.vsplatrh"]
1621    fn hexagon_S2_vsplatrh(_: i32) -> i64;
1622    #[link_name = "llvm.hexagon.S2.vspliceib"]
1623    fn hexagon_S2_vspliceib(_: i64, _: i64, _: i32) -> i64;
1624    #[link_name = "llvm.hexagon.S2.vsplicerb"]
1625    fn hexagon_S2_vsplicerb(_: i64, _: i64, _: i32) -> i64;
1626    #[link_name = "llvm.hexagon.S2.vsxtbh"]
1627    fn hexagon_S2_vsxtbh(_: i32) -> i64;
1628    #[link_name = "llvm.hexagon.S2.vsxthw"]
1629    fn hexagon_S2_vsxthw(_: i32) -> i64;
1630    #[link_name = "llvm.hexagon.S2.vtrunehb"]
1631    fn hexagon_S2_vtrunehb(_: i64) -> i32;
1632    #[link_name = "llvm.hexagon.S2.vtrunewh"]
1633    fn hexagon_S2_vtrunewh(_: i64, _: i64) -> i64;
1634    #[link_name = "llvm.hexagon.S2.vtrunohb"]
1635    fn hexagon_S2_vtrunohb(_: i64) -> i32;
1636    #[link_name = "llvm.hexagon.S2.vtrunowh"]
1637    fn hexagon_S2_vtrunowh(_: i64, _: i64) -> i64;
1638    #[link_name = "llvm.hexagon.S2.vzxtbh"]
1639    fn hexagon_S2_vzxtbh(_: i32) -> i64;
1640    #[link_name = "llvm.hexagon.S2.vzxthw"]
1641    fn hexagon_S2_vzxthw(_: i32) -> i64;
1642    #[link_name = "llvm.hexagon.S4.addaddi"]
1643    fn hexagon_S4_addaddi(_: i32, _: i32, _: i32) -> i32;
1644    #[link_name = "llvm.hexagon.S4.addi.asl.ri"]
1645    fn hexagon_S4_addi_asl_ri(_: i32, _: i32, _: i32) -> i32;
1646    #[link_name = "llvm.hexagon.S4.addi.lsr.ri"]
1647    fn hexagon_S4_addi_lsr_ri(_: i32, _: i32, _: i32) -> i32;
1648    #[link_name = "llvm.hexagon.S4.andi.asl.ri"]
1649    fn hexagon_S4_andi_asl_ri(_: i32, _: i32, _: i32) -> i32;
1650    #[link_name = "llvm.hexagon.S4.andi.lsr.ri"]
1651    fn hexagon_S4_andi_lsr_ri(_: i32, _: i32, _: i32) -> i32;
1652    #[link_name = "llvm.hexagon.S4.clbaddi"]
1653    fn hexagon_S4_clbaddi(_: i32, _: i32) -> i32;
1654    #[link_name = "llvm.hexagon.S4.clbpaddi"]
1655    fn hexagon_S4_clbpaddi(_: i64, _: i32) -> i32;
1656    #[link_name = "llvm.hexagon.S4.clbpnorm"]
1657    fn hexagon_S4_clbpnorm(_: i64) -> i32;
1658    #[link_name = "llvm.hexagon.S4.extract"]
1659    fn hexagon_S4_extract(_: i32, _: i32, _: i32) -> i32;
1660    #[link_name = "llvm.hexagon.S4.extract.rp"]
1661    fn hexagon_S4_extract_rp(_: i32, _: i64) -> i32;
1662    #[link_name = "llvm.hexagon.S4.extractp"]
1663    fn hexagon_S4_extractp(_: i64, _: i32, _: i32) -> i64;
1664    #[link_name = "llvm.hexagon.S4.extractp.rp"]
1665    fn hexagon_S4_extractp_rp(_: i64, _: i64) -> i64;
1666    #[link_name = "llvm.hexagon.S4.lsli"]
1667    fn hexagon_S4_lsli(_: i32, _: i32) -> i32;
1668    #[link_name = "llvm.hexagon.S4.ntstbit.i"]
1669    fn hexagon_S4_ntstbit_i(_: i32, _: i32) -> i32;
1670    #[link_name = "llvm.hexagon.S4.ntstbit.r"]
1671    fn hexagon_S4_ntstbit_r(_: i32, _: i32) -> i32;
1672    #[link_name = "llvm.hexagon.S4.or.andi"]
1673    fn hexagon_S4_or_andi(_: i32, _: i32, _: i32) -> i32;
1674    #[link_name = "llvm.hexagon.S4.or.andix"]
1675    fn hexagon_S4_or_andix(_: i32, _: i32, _: i32) -> i32;
1676    #[link_name = "llvm.hexagon.S4.or.ori"]
1677    fn hexagon_S4_or_ori(_: i32, _: i32, _: i32) -> i32;
1678    #[link_name = "llvm.hexagon.S4.ori.asl.ri"]
1679    fn hexagon_S4_ori_asl_ri(_: i32, _: i32, _: i32) -> i32;
1680    #[link_name = "llvm.hexagon.S4.ori.lsr.ri"]
1681    fn hexagon_S4_ori_lsr_ri(_: i32, _: i32, _: i32) -> i32;
1682    #[link_name = "llvm.hexagon.S4.parity"]
1683    fn hexagon_S4_parity(_: i32, _: i32) -> i32;
1684    #[link_name = "llvm.hexagon.S4.subaddi"]
1685    fn hexagon_S4_subaddi(_: i32, _: i32, _: i32) -> i32;
1686    #[link_name = "llvm.hexagon.S4.subi.asl.ri"]
1687    fn hexagon_S4_subi_asl_ri(_: i32, _: i32, _: i32) -> i32;
1688    #[link_name = "llvm.hexagon.S4.subi.lsr.ri"]
1689    fn hexagon_S4_subi_lsr_ri(_: i32, _: i32, _: i32) -> i32;
1690    #[link_name = "llvm.hexagon.S4.vrcrotate"]
1691    fn hexagon_S4_vrcrotate(_: i64, _: i32, _: i32) -> i64;
1692    #[link_name = "llvm.hexagon.S4.vrcrotate.acc"]
1693    fn hexagon_S4_vrcrotate_acc(_: i64, _: i64, _: i32, _: i32) -> i64;
1694    #[link_name = "llvm.hexagon.S4.vxaddsubh"]
1695    fn hexagon_S4_vxaddsubh(_: i64, _: i64) -> i64;
1696    #[link_name = "llvm.hexagon.S4.vxaddsubhr"]
1697    fn hexagon_S4_vxaddsubhr(_: i64, _: i64) -> i64;
1698    #[link_name = "llvm.hexagon.S4.vxaddsubw"]
1699    fn hexagon_S4_vxaddsubw(_: i64, _: i64) -> i64;
1700    #[link_name = "llvm.hexagon.S4.vxsubaddh"]
1701    fn hexagon_S4_vxsubaddh(_: i64, _: i64) -> i64;
1702    #[link_name = "llvm.hexagon.S4.vxsubaddhr"]
1703    fn hexagon_S4_vxsubaddhr(_: i64, _: i64) -> i64;
1704    #[link_name = "llvm.hexagon.S4.vxsubaddw"]
1705    fn hexagon_S4_vxsubaddw(_: i64, _: i64) -> i64;
1706    #[link_name = "llvm.hexagon.S5.asrhub.rnd.sat.goodsyntax"]
1707    fn hexagon_S5_asrhub_rnd_sat_goodsyntax(_: i64, _: i32) -> i32;
1708    #[link_name = "llvm.hexagon.S5.asrhub.sat"]
1709    fn hexagon_S5_asrhub_sat(_: i64, _: i32) -> i32;
1710    #[link_name = "llvm.hexagon.S5.popcountp"]
1711    fn hexagon_S5_popcountp(_: i64) -> i32;
1712    #[link_name = "llvm.hexagon.S5.vasrhrnd.goodsyntax"]
1713    fn hexagon_S5_vasrhrnd_goodsyntax(_: i64, _: i32) -> i64;
1714    #[link_name = "llvm.hexagon.Y2.dccleana"]
1715    fn hexagon_Y2_dccleana(_: i32);
1716    #[link_name = "llvm.hexagon.Y2.dccleaninva"]
1717    fn hexagon_Y2_dccleaninva(_: i32);
1718    #[link_name = "llvm.hexagon.Y2.dcfetch"]
1719    fn hexagon_Y2_dcfetch(_: i32);
1720    #[link_name = "llvm.hexagon.Y2.dcinva"]
1721    fn hexagon_Y2_dcinva(_: i32);
1722    #[link_name = "llvm.hexagon.Y2.dczeroa"]
1723    fn hexagon_Y2_dczeroa(_: i32);
1724    #[link_name = "llvm.hexagon.Y4.l2fetch"]
1725    fn hexagon_Y4_l2fetch(_: i32, _: i32);
1726    #[link_name = "llvm.hexagon.Y5.l2fetch"]
1727    fn hexagon_Y5_l2fetch(_: i32, _: i64);
1728    #[link_name = "llvm.hexagon.S6.rol.i.p"]
1729    fn hexagon_S6_rol_i_p(_: i64, _: i32) -> i64;
1730    #[link_name = "llvm.hexagon.S6.rol.i.p.acc"]
1731    fn hexagon_S6_rol_i_p_acc(_: i64, _: i64, _: i32) -> i64;
1732    #[link_name = "llvm.hexagon.S6.rol.i.p.and"]
1733    fn hexagon_S6_rol_i_p_and(_: i64, _: i64, _: i32) -> i64;
1734    #[link_name = "llvm.hexagon.S6.rol.i.p.nac"]
1735    fn hexagon_S6_rol_i_p_nac(_: i64, _: i64, _: i32) -> i64;
1736    #[link_name = "llvm.hexagon.S6.rol.i.p.or"]
1737    fn hexagon_S6_rol_i_p_or(_: i64, _: i64, _: i32) -> i64;
1738    #[link_name = "llvm.hexagon.S6.rol.i.p.xacc"]
1739    fn hexagon_S6_rol_i_p_xacc(_: i64, _: i64, _: i32) -> i64;
1740    #[link_name = "llvm.hexagon.S6.rol.i.r"]
1741    fn hexagon_S6_rol_i_r(_: i32, _: i32) -> i32;
1742    #[link_name = "llvm.hexagon.S6.rol.i.r.acc"]
1743    fn hexagon_S6_rol_i_r_acc(_: i32, _: i32, _: i32) -> i32;
1744    #[link_name = "llvm.hexagon.S6.rol.i.r.and"]
1745    fn hexagon_S6_rol_i_r_and(_: i32, _: i32, _: i32) -> i32;
1746    #[link_name = "llvm.hexagon.S6.rol.i.r.nac"]
1747    fn hexagon_S6_rol_i_r_nac(_: i32, _: i32, _: i32) -> i32;
1748    #[link_name = "llvm.hexagon.S6.rol.i.r.or"]
1749    fn hexagon_S6_rol_i_r_or(_: i32, _: i32, _: i32) -> i32;
1750    #[link_name = "llvm.hexagon.S6.rol.i.r.xacc"]
1751    fn hexagon_S6_rol_i_r_xacc(_: i32, _: i32, _: i32) -> i32;
1752    #[link_name = "llvm.hexagon.M6.vabsdiffb"]
1753    fn hexagon_M6_vabsdiffb(_: i64, _: i64) -> i64;
1754    #[link_name = "llvm.hexagon.M6.vabsdiffub"]
1755    fn hexagon_M6_vabsdiffub(_: i64, _: i64) -> i64;
1756    #[link_name = "llvm.hexagon.S6.vsplatrbp"]
1757    fn hexagon_S6_vsplatrbp(_: i32) -> i64;
1758    #[link_name = "llvm.hexagon.S6.vtrunehb.ppp"]
1759    fn hexagon_S6_vtrunehb_ppp(_: i64, _: i64) -> i64;
1760    #[link_name = "llvm.hexagon.S6.vtrunohb.ppp"]
1761    fn hexagon_S6_vtrunohb_ppp(_: i64, _: i64) -> i64;
1762    #[link_name = "llvm.hexagon.A6.vcmpbeq.notany"]
1763    fn hexagon_A6_vcmpbeq_notany(_: i64, _: i64) -> i32;
1764    #[link_name = "llvm.hexagon.F2.dfadd"]
1765    fn hexagon_F2_dfadd(_: f64, _: f64) -> f64;
1766    #[link_name = "llvm.hexagon.F2.dfsub"]
1767    fn hexagon_F2_dfsub(_: f64, _: f64) -> f64;
1768    #[link_name = "llvm.hexagon.M2.mnaci"]
1769    fn hexagon_M2_mnaci(_: i32, _: i32, _: i32) -> i32;
1770    #[link_name = "llvm.hexagon.S2.mask"]
1771    fn hexagon_S2_mask(_: i32, _: i32) -> i32;
1772    #[link_name = "llvm.hexagon.A7.clip"]
1773    fn hexagon_A7_clip(_: i32, _: i32) -> i32;
1774    #[link_name = "llvm.hexagon.A7.croundd.ri"]
1775    fn hexagon_A7_croundd_ri(_: i64, _: i32) -> i64;
1776    #[link_name = "llvm.hexagon.A7.croundd.rr"]
1777    fn hexagon_A7_croundd_rr(_: i64, _: i32) -> i64;
1778    #[link_name = "llvm.hexagon.A7.vclip"]
1779    fn hexagon_A7_vclip(_: i64, _: i32) -> i64;
1780    #[link_name = "llvm.hexagon.F2.dfmax"]
1781    fn hexagon_F2_dfmax(_: f64, _: f64) -> f64;
1782    #[link_name = "llvm.hexagon.F2.dfmin"]
1783    fn hexagon_F2_dfmin(_: f64, _: f64) -> f64;
1784    #[link_name = "llvm.hexagon.F2.dfmpyfix"]
1785    fn hexagon_F2_dfmpyfix(_: f64, _: f64) -> f64;
1786    #[link_name = "llvm.hexagon.F2.dfmpyhh"]
1787    fn hexagon_F2_dfmpyhh(_: f64, _: f64, _: f64) -> f64;
1788    #[link_name = "llvm.hexagon.F2.dfmpylh"]
1789    fn hexagon_F2_dfmpylh(_: f64, _: f64, _: f64) -> f64;
1790    #[link_name = "llvm.hexagon.F2.dfmpyll"]
1791    fn hexagon_F2_dfmpyll(_: f64, _: f64) -> f64;
1792    #[link_name = "llvm.hexagon.M7.dcmpyiw"]
1793    fn hexagon_M7_dcmpyiw(_: i64, _: i64) -> i64;
1794    #[link_name = "llvm.hexagon.M7.dcmpyiw.acc"]
1795    fn hexagon_M7_dcmpyiw_acc(_: i64, _: i64, _: i64) -> i64;
1796    #[link_name = "llvm.hexagon.M7.dcmpyiwc"]
1797    fn hexagon_M7_dcmpyiwc(_: i64, _: i64) -> i64;
1798    #[link_name = "llvm.hexagon.M7.dcmpyiwc.acc"]
1799    fn hexagon_M7_dcmpyiwc_acc(_: i64, _: i64, _: i64) -> i64;
1800    #[link_name = "llvm.hexagon.M7.dcmpyrw"]
1801    fn hexagon_M7_dcmpyrw(_: i64, _: i64) -> i64;
1802    #[link_name = "llvm.hexagon.M7.dcmpyrw.acc"]
1803    fn hexagon_M7_dcmpyrw_acc(_: i64, _: i64, _: i64) -> i64;
1804    #[link_name = "llvm.hexagon.M7.dcmpyrwc"]
1805    fn hexagon_M7_dcmpyrwc(_: i64, _: i64) -> i64;
1806    #[link_name = "llvm.hexagon.M7.dcmpyrwc.acc"]
1807    fn hexagon_M7_dcmpyrwc_acc(_: i64, _: i64, _: i64) -> i64;
1808    #[link_name = "llvm.hexagon.M7.vdmpy"]
1809    fn hexagon_M7_vdmpy(_: i64, _: i64) -> i64;
1810    #[link_name = "llvm.hexagon.M7.vdmpy.acc"]
1811    fn hexagon_M7_vdmpy_acc(_: i64, _: i64, _: i64) -> i64;
1812    #[link_name = "llvm.hexagon.M7.wcmpyiw"]
1813    fn hexagon_M7_wcmpyiw(_: i64, _: i64) -> i32;
1814    #[link_name = "llvm.hexagon.M7.wcmpyiw.rnd"]
1815    fn hexagon_M7_wcmpyiw_rnd(_: i64, _: i64) -> i32;
1816    #[link_name = "llvm.hexagon.M7.wcmpyiwc"]
1817    fn hexagon_M7_wcmpyiwc(_: i64, _: i64) -> i32;
1818    #[link_name = "llvm.hexagon.M7.wcmpyiwc.rnd"]
1819    fn hexagon_M7_wcmpyiwc_rnd(_: i64, _: i64) -> i32;
1820    #[link_name = "llvm.hexagon.M7.wcmpyrw"]
1821    fn hexagon_M7_wcmpyrw(_: i64, _: i64) -> i32;
1822    #[link_name = "llvm.hexagon.M7.wcmpyrw.rnd"]
1823    fn hexagon_M7_wcmpyrw_rnd(_: i64, _: i64) -> i32;
1824    #[link_name = "llvm.hexagon.M7.wcmpyrwc"]
1825    fn hexagon_M7_wcmpyrwc(_: i64, _: i64) -> i32;
1826    #[link_name = "llvm.hexagon.M7.wcmpyrwc.rnd"]
1827    fn hexagon_M7_wcmpyrwc_rnd(_: i64, _: i64) -> i32;
1828    #[link_name = "llvm.hexagon.Y6.dmlink"]
1829    fn hexagon_Y6_dmlink(_: i32, _: i32);
1830    #[link_name = "llvm.hexagon.Y6.dmpause"]
1831    fn hexagon_Y6_dmpause() -> i32;
1832    #[link_name = "llvm.hexagon.Y6.dmpoll"]
1833    fn hexagon_Y6_dmpoll() -> i32;
1834    #[link_name = "llvm.hexagon.Y6.dmresume"]
1835    fn hexagon_Y6_dmresume(_: i32);
1836    #[link_name = "llvm.hexagon.Y6.dmstart"]
1837    fn hexagon_Y6_dmstart(_: i32);
1838    #[link_name = "llvm.hexagon.Y6.dmwait"]
1839    fn hexagon_Y6_dmwait() -> i32;
1840}
1841
1842/// `Rd32=abs(Rs32)`
1843///
1844/// Instruction Type: S_2op
1845/// Execution Slots: SLOT23
1846#[inline(always)]
1847#[cfg_attr(test, assert_instr(abs))]
1848#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1849pub unsafe fn Q6_R_abs_R(rs: i32) -> i32 {
1850    hexagon_A2_abs(rs)
1851}
1852
1853/// `Rdd32=abs(Rss32)`
1854///
1855/// Instruction Type: S_2op
1856/// Execution Slots: SLOT23
1857#[inline(always)]
1858#[cfg_attr(test, assert_instr(abs))]
1859#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1860pub unsafe fn Q6_P_abs_P(rss: i64) -> i64 {
1861    hexagon_A2_absp(rss)
1862}
1863
1864/// `Rd32=abs(Rs32):sat`
1865///
1866/// Instruction Type: S_2op
1867/// Execution Slots: SLOT23
1868#[inline(always)]
1869#[cfg_attr(test, assert_instr(abs))]
1870#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1871pub unsafe fn Q6_R_abs_R_sat(rs: i32) -> i32 {
1872    hexagon_A2_abssat(rs)
1873}
1874
1875/// `Rd32=add(Rs32,Rt32)`
1876///
1877/// Instruction Type: ALU32_3op
1878/// Execution Slots: SLOT0123
1879#[inline(always)]
1880#[cfg_attr(test, assert_instr(add))]
1881#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1882pub unsafe fn Q6_R_add_RR(rs: i32, rt: i32) -> i32 {
1883    hexagon_A2_add(rs, rt)
1884}
1885
1886/// `Rd32=add(Rt32.h,Rs32.h):<<16`
1887///
1888/// Instruction Type: ALU64
1889/// Execution Slots: SLOT23
1890#[inline(always)]
1891#[cfg_attr(test, assert_instr(add))]
1892#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1893pub unsafe fn Q6_R_add_RhRh_s16(rt: i32, rs: i32) -> i32 {
1894    hexagon_A2_addh_h16_hh(rt, rs)
1895}
1896
1897/// `Rd32=add(Rt32.h,Rs32.l):<<16`
1898///
1899/// Instruction Type: ALU64
1900/// Execution Slots: SLOT23
1901#[inline(always)]
1902#[cfg_attr(test, assert_instr(add))]
1903#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1904pub unsafe fn Q6_R_add_RhRl_s16(rt: i32, rs: i32) -> i32 {
1905    hexagon_A2_addh_h16_hl(rt, rs)
1906}
1907
1908/// `Rd32=add(Rt32.l,Rs32.h):<<16`
1909///
1910/// Instruction Type: ALU64
1911/// Execution Slots: SLOT23
1912#[inline(always)]
1913#[cfg_attr(test, assert_instr(add))]
1914#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1915pub unsafe fn Q6_R_add_RlRh_s16(rt: i32, rs: i32) -> i32 {
1916    hexagon_A2_addh_h16_lh(rt, rs)
1917}
1918
1919/// `Rd32=add(Rt32.l,Rs32.l):<<16`
1920///
1921/// Instruction Type: ALU64
1922/// Execution Slots: SLOT23
1923#[inline(always)]
1924#[cfg_attr(test, assert_instr(add))]
1925#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1926pub unsafe fn Q6_R_add_RlRl_s16(rt: i32, rs: i32) -> i32 {
1927    hexagon_A2_addh_h16_ll(rt, rs)
1928}
1929
1930/// `Rd32=add(Rt32.h,Rs32.h):sat:<<16`
1931///
1932/// Instruction Type: ALU64
1933/// Execution Slots: SLOT23
1934#[inline(always)]
1935#[cfg_attr(test, assert_instr(add))]
1936#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1937pub unsafe fn Q6_R_add_RhRh_sat_s16(rt: i32, rs: i32) -> i32 {
1938    hexagon_A2_addh_h16_sat_hh(rt, rs)
1939}
1940
1941/// `Rd32=add(Rt32.h,Rs32.l):sat:<<16`
1942///
1943/// Instruction Type: ALU64
1944/// Execution Slots: SLOT23
1945#[inline(always)]
1946#[cfg_attr(test, assert_instr(add))]
1947#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1948pub unsafe fn Q6_R_add_RhRl_sat_s16(rt: i32, rs: i32) -> i32 {
1949    hexagon_A2_addh_h16_sat_hl(rt, rs)
1950}
1951
1952/// `Rd32=add(Rt32.l,Rs32.h):sat:<<16`
1953///
1954/// Instruction Type: ALU64
1955/// Execution Slots: SLOT23
1956#[inline(always)]
1957#[cfg_attr(test, assert_instr(add))]
1958#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1959pub unsafe fn Q6_R_add_RlRh_sat_s16(rt: i32, rs: i32) -> i32 {
1960    hexagon_A2_addh_h16_sat_lh(rt, rs)
1961}
1962
1963/// `Rd32=add(Rt32.l,Rs32.l):sat:<<16`
1964///
1965/// Instruction Type: ALU64
1966/// Execution Slots: SLOT23
1967#[inline(always)]
1968#[cfg_attr(test, assert_instr(add))]
1969#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1970pub unsafe fn Q6_R_add_RlRl_sat_s16(rt: i32, rs: i32) -> i32 {
1971    hexagon_A2_addh_h16_sat_ll(rt, rs)
1972}
1973
1974/// `Rd32=add(Rt32.l,Rs32.h)`
1975///
1976/// Instruction Type: ALU64
1977/// Execution Slots: SLOT23
1978#[inline(always)]
1979#[cfg_attr(test, assert_instr(add))]
1980#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1981pub unsafe fn Q6_R_add_RlRh(rt: i32, rs: i32) -> i32 {
1982    hexagon_A2_addh_l16_hl(rt, rs)
1983}
1984
1985/// `Rd32=add(Rt32.l,Rs32.l)`
1986///
1987/// Instruction Type: ALU64
1988/// Execution Slots: SLOT23
1989#[inline(always)]
1990#[cfg_attr(test, assert_instr(add))]
1991#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1992pub unsafe fn Q6_R_add_RlRl(rt: i32, rs: i32) -> i32 {
1993    hexagon_A2_addh_l16_ll(rt, rs)
1994}
1995
1996/// `Rd32=add(Rt32.l,Rs32.h):sat`
1997///
1998/// Instruction Type: ALU64
1999/// Execution Slots: SLOT23
2000#[inline(always)]
2001#[cfg_attr(test, assert_instr(add))]
2002#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2003pub unsafe fn Q6_R_add_RlRh_sat(rt: i32, rs: i32) -> i32 {
2004    hexagon_A2_addh_l16_sat_hl(rt, rs)
2005}
2006
2007/// `Rd32=add(Rt32.l,Rs32.l):sat`
2008///
2009/// Instruction Type: ALU64
2010/// Execution Slots: SLOT23
2011#[inline(always)]
2012#[cfg_attr(test, assert_instr(add))]
2013#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2014pub unsafe fn Q6_R_add_RlRl_sat(rt: i32, rs: i32) -> i32 {
2015    hexagon_A2_addh_l16_sat_ll(rt, rs)
2016}
2017
2018/// `Rd32=add(Rs32,#s16)`
2019///
2020/// Instruction Type: ALU32_ADDI
2021/// Execution Slots: SLOT0123
2022#[inline(always)]
2023#[rustc_legacy_const_generics(1)]
2024#[cfg_attr(test, assert_instr(add, IS16 = 0))]
2025#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2026pub unsafe fn Q6_R_add_RI<const IS16: i32>(rs: i32) -> i32 {
2027    static_assert_simm_bits!(IS16, 16);
2028    hexagon_A2_addi(rs, IS16)
2029}
2030
2031/// `Rdd32=add(Rss32,Rtt32)`
2032///
2033/// Instruction Type: ALU64
2034/// Execution Slots: SLOT23
2035#[inline(always)]
2036#[cfg_attr(test, assert_instr(add))]
2037#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2038pub unsafe fn Q6_P_add_PP(rss: i64, rtt: i64) -> i64 {
2039    hexagon_A2_addp(rss, rtt)
2040}
2041
2042/// `Rdd32=add(Rss32,Rtt32):sat`
2043///
2044/// Instruction Type: ALU64
2045/// Execution Slots: SLOT23
2046#[inline(always)]
2047#[cfg_attr(test, assert_instr(add))]
2048#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2049pub unsafe fn Q6_P_add_PP_sat(rss: i64, rtt: i64) -> i64 {
2050    hexagon_A2_addpsat(rss, rtt)
2051}
2052
2053/// `Rd32=add(Rs32,Rt32):sat`
2054///
2055/// Instruction Type: ALU32_3op
2056/// Execution Slots: SLOT0123
2057#[inline(always)]
2058#[cfg_attr(test, assert_instr(add))]
2059#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2060pub unsafe fn Q6_R_add_RR_sat(rs: i32, rt: i32) -> i32 {
2061    hexagon_A2_addsat(rs, rt)
2062}
2063
2064/// `Rdd32=add(Rs32,Rtt32)`
2065///
2066/// Instruction Type: ALU64
2067/// Execution Slots: SLOT0123
2068#[inline(always)]
2069#[cfg_attr(test, assert_instr(add))]
2070#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2071pub unsafe fn Q6_P_add_RP(rs: i32, rtt: i64) -> i64 {
2072    hexagon_A2_addsp(rs, rtt)
2073}
2074
2075/// `Rd32=and(Rs32,Rt32)`
2076///
2077/// Instruction Type: ALU32_3op
2078/// Execution Slots: SLOT0123
2079#[inline(always)]
2080#[cfg_attr(test, assert_instr(and))]
2081#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2082pub unsafe fn Q6_R_and_RR(rs: i32, rt: i32) -> i32 {
2083    hexagon_A2_and(rs, rt)
2084}
2085
2086/// `Rd32=and(Rs32,#s10)`
2087///
2088/// Instruction Type: ALU32_2op
2089/// Execution Slots: SLOT0123
2090#[inline(always)]
2091#[rustc_legacy_const_generics(1)]
2092#[cfg_attr(test, assert_instr(and, IS10 = 0))]
2093#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2094pub unsafe fn Q6_R_and_RI<const IS10: i32>(rs: i32) -> i32 {
2095    static_assert_simm_bits!(IS10, 10);
2096    hexagon_A2_andir(rs, IS10)
2097}
2098
2099/// `Rdd32=and(Rss32,Rtt32)`
2100///
2101/// Instruction Type: ALU64
2102/// Execution Slots: SLOT23
2103#[inline(always)]
2104#[cfg_attr(test, assert_instr(and))]
2105#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2106pub unsafe fn Q6_P_and_PP(rss: i64, rtt: i64) -> i64 {
2107    hexagon_A2_andp(rss, rtt)
2108}
2109
2110/// `Rd32=aslh(Rs32)`
2111///
2112/// Instruction Type: ALU32_2op
2113/// Execution Slots: SLOT0123
2114#[inline(always)]
2115#[cfg_attr(test, assert_instr(aslh))]
2116#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2117pub unsafe fn Q6_R_aslh_R(rs: i32) -> i32 {
2118    hexagon_A2_aslh(rs)
2119}
2120
2121/// `Rd32=asrh(Rs32)`
2122///
2123/// Instruction Type: ALU32_2op
2124/// Execution Slots: SLOT0123
2125#[inline(always)]
2126#[cfg_attr(test, assert_instr(asrh))]
2127#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2128pub unsafe fn Q6_R_asrh_R(rs: i32) -> i32 {
2129    hexagon_A2_asrh(rs)
2130}
2131
2132/// `Rd32=combine(Rt32.h,Rs32.h)`
2133///
2134/// Instruction Type: ALU32_3op
2135/// Execution Slots: SLOT0123
2136#[inline(always)]
2137#[cfg_attr(test, assert_instr(combine))]
2138#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2139pub unsafe fn Q6_R_combine_RhRh(rt: i32, rs: i32) -> i32 {
2140    hexagon_A2_combine_hh(rt, rs)
2141}
2142
2143/// `Rd32=combine(Rt32.h,Rs32.l)`
2144///
2145/// Instruction Type: ALU32_3op
2146/// Execution Slots: SLOT0123
2147#[inline(always)]
2148#[cfg_attr(test, assert_instr(combine))]
2149#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2150pub unsafe fn Q6_R_combine_RhRl(rt: i32, rs: i32) -> i32 {
2151    hexagon_A2_combine_hl(rt, rs)
2152}
2153
2154/// `Rd32=combine(Rt32.l,Rs32.h)`
2155///
2156/// Instruction Type: ALU32_3op
2157/// Execution Slots: SLOT0123
2158#[inline(always)]
2159#[cfg_attr(test, assert_instr(combine))]
2160#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2161pub unsafe fn Q6_R_combine_RlRh(rt: i32, rs: i32) -> i32 {
2162    hexagon_A2_combine_lh(rt, rs)
2163}
2164
2165/// `Rd32=combine(Rt32.l,Rs32.l)`
2166///
2167/// Instruction Type: ALU32_3op
2168/// Execution Slots: SLOT0123
2169#[inline(always)]
2170#[cfg_attr(test, assert_instr(combine))]
2171#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2172pub unsafe fn Q6_R_combine_RlRl(rt: i32, rs: i32) -> i32 {
2173    hexagon_A2_combine_ll(rt, rs)
2174}
2175
2176/// `Rdd32=combine(#s8,#S8)`
2177///
2178/// Instruction Type: ALU32_2op
2179/// Execution Slots: SLOT0123
2180#[inline(always)]
2181#[rustc_legacy_const_generics(0, 1)]
2182#[cfg_attr(test, assert_instr(combine, IS8 = 0, IS8_2 = 0))]
2183#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2184pub unsafe fn Q6_P_combine_II<const IS8: i32, const IS8_2: i32>() -> i64 {
2185    static_assert_simm_bits!(IS8, 8);
2186    static_assert_simm_bits!(IS8_2, 8);
2187    hexagon_A2_combineii(IS8, IS8_2)
2188}
2189
2190/// `Rdd32=combine(Rs32,Rt32)`
2191///
2192/// Instruction Type: ALU32_3op
2193/// Execution Slots: SLOT0123
2194#[inline(always)]
2195#[cfg_attr(test, assert_instr(combine))]
2196#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2197pub unsafe fn Q6_P_combine_RR(rs: i32, rt: i32) -> i64 {
2198    hexagon_A2_combinew(rs, rt)
2199}
2200
2201/// `Rd32=max(Rs32,Rt32)`
2202///
2203/// Instruction Type: ALU64
2204/// Execution Slots: SLOT23
2205#[inline(always)]
2206#[cfg_attr(test, assert_instr(max))]
2207#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2208pub unsafe fn Q6_R_max_RR(rs: i32, rt: i32) -> i32 {
2209    hexagon_A2_max(rs, rt)
2210}
2211
2212/// `Rdd32=max(Rss32,Rtt32)`
2213///
2214/// Instruction Type: ALU64
2215/// Execution Slots: SLOT23
2216#[inline(always)]
2217#[cfg_attr(test, assert_instr(max))]
2218#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2219pub unsafe fn Q6_P_max_PP(rss: i64, rtt: i64) -> i64 {
2220    hexagon_A2_maxp(rss, rtt)
2221}
2222
2223/// `Rd32=maxu(Rs32,Rt32)`
2224///
2225/// Instruction Type: ALU64
2226/// Execution Slots: SLOT23
2227#[inline(always)]
2228#[cfg_attr(test, assert_instr(maxu))]
2229#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2230pub unsafe fn Q6_R_maxu_RR(rs: i32, rt: i32) -> i32 {
2231    hexagon_A2_maxu(rs, rt)
2232}
2233
2234/// `Rdd32=maxu(Rss32,Rtt32)`
2235///
2236/// Instruction Type: ALU64
2237/// Execution Slots: SLOT23
2238#[inline(always)]
2239#[cfg_attr(test, assert_instr(maxu))]
2240#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2241pub unsafe fn Q6_P_maxu_PP(rss: i64, rtt: i64) -> i64 {
2242    hexagon_A2_maxup(rss, rtt)
2243}
2244
2245/// `Rd32=min(Rt32,Rs32)`
2246///
2247/// Instruction Type: ALU64
2248/// Execution Slots: SLOT23
2249#[inline(always)]
2250#[cfg_attr(test, assert_instr(min))]
2251#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2252pub unsafe fn Q6_R_min_RR(rt: i32, rs: i32) -> i32 {
2253    hexagon_A2_min(rt, rs)
2254}
2255
2256/// `Rdd32=min(Rtt32,Rss32)`
2257///
2258/// Instruction Type: ALU64
2259/// Execution Slots: SLOT23
2260#[inline(always)]
2261#[cfg_attr(test, assert_instr(min))]
2262#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2263pub unsafe fn Q6_P_min_PP(rtt: i64, rss: i64) -> i64 {
2264    hexagon_A2_minp(rtt, rss)
2265}
2266
2267/// `Rd32=minu(Rt32,Rs32)`
2268///
2269/// Instruction Type: ALU64
2270/// Execution Slots: SLOT23
2271#[inline(always)]
2272#[cfg_attr(test, assert_instr(minu))]
2273#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2274pub unsafe fn Q6_R_minu_RR(rt: i32, rs: i32) -> i32 {
2275    hexagon_A2_minu(rt, rs)
2276}
2277
2278/// `Rdd32=minu(Rtt32,Rss32)`
2279///
2280/// Instruction Type: ALU64
2281/// Execution Slots: SLOT23
2282#[inline(always)]
2283#[cfg_attr(test, assert_instr(minu))]
2284#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2285pub unsafe fn Q6_P_minu_PP(rtt: i64, rss: i64) -> i64 {
2286    hexagon_A2_minup(rtt, rss)
2287}
2288
2289/// `Rd32=neg(Rs32)`
2290///
2291/// Instruction Type: ALU32_2op
2292/// Execution Slots: SLOT0123
2293#[inline(always)]
2294#[cfg_attr(test, assert_instr(neg))]
2295#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2296pub unsafe fn Q6_R_neg_R(rs: i32) -> i32 {
2297    hexagon_A2_neg(rs)
2298}
2299
2300/// `Rdd32=neg(Rss32)`
2301///
2302/// Instruction Type: S_2op
2303/// Execution Slots: SLOT23
2304#[inline(always)]
2305#[cfg_attr(test, assert_instr(neg))]
2306#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2307pub unsafe fn Q6_P_neg_P(rss: i64) -> i64 {
2308    hexagon_A2_negp(rss)
2309}
2310
2311/// `Rd32=neg(Rs32):sat`
2312///
2313/// Instruction Type: S_2op
2314/// Execution Slots: SLOT23
2315#[inline(always)]
2316#[cfg_attr(test, assert_instr(neg))]
2317#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2318pub unsafe fn Q6_R_neg_R_sat(rs: i32) -> i32 {
2319    hexagon_A2_negsat(rs)
2320}
2321
2322/// `Rd32=not(Rs32)`
2323///
2324/// Instruction Type: ALU32_2op
2325/// Execution Slots: SLOT0123
2326#[inline(always)]
2327#[cfg_attr(test, assert_instr(not))]
2328#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2329pub unsafe fn Q6_R_not_R(rs: i32) -> i32 {
2330    hexagon_A2_not(rs)
2331}
2332
2333/// `Rdd32=not(Rss32)`
2334///
2335/// Instruction Type: S_2op
2336/// Execution Slots: SLOT23
2337#[inline(always)]
2338#[cfg_attr(test, assert_instr(not))]
2339#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2340pub unsafe fn Q6_P_not_P(rss: i64) -> i64 {
2341    hexagon_A2_notp(rss)
2342}
2343
2344/// `Rd32=or(Rs32,Rt32)`
2345///
2346/// Instruction Type: ALU32_3op
2347/// Execution Slots: SLOT0123
2348#[inline(always)]
2349#[cfg_attr(test, assert_instr(or))]
2350#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2351pub unsafe fn Q6_R_or_RR(rs: i32, rt: i32) -> i32 {
2352    hexagon_A2_or(rs, rt)
2353}
2354
2355/// `Rd32=or(Rs32,#s10)`
2356///
2357/// Instruction Type: ALU32_2op
2358/// Execution Slots: SLOT0123
2359#[inline(always)]
2360#[rustc_legacy_const_generics(1)]
2361#[cfg_attr(test, assert_instr(or, IS10 = 0))]
2362#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2363pub unsafe fn Q6_R_or_RI<const IS10: i32>(rs: i32) -> i32 {
2364    static_assert_simm_bits!(IS10, 10);
2365    hexagon_A2_orir(rs, IS10)
2366}
2367
2368/// `Rdd32=or(Rss32,Rtt32)`
2369///
2370/// Instruction Type: ALU64
2371/// Execution Slots: SLOT23
2372#[inline(always)]
2373#[cfg_attr(test, assert_instr(or))]
2374#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2375pub unsafe fn Q6_P_or_PP(rss: i64, rtt: i64) -> i64 {
2376    hexagon_A2_orp(rss, rtt)
2377}
2378
2379/// `Rd32=round(Rss32):sat`
2380///
2381/// Instruction Type: S_2op
2382/// Execution Slots: SLOT23
2383#[inline(always)]
2384#[cfg_attr(test, assert_instr(round))]
2385#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2386pub unsafe fn Q6_R_round_P_sat(rss: i64) -> i32 {
2387    hexagon_A2_roundsat(rss)
2388}
2389
2390/// `Rd32=sat(Rss32)`
2391///
2392/// Instruction Type: S_2op
2393/// Execution Slots: SLOT23
2394#[inline(always)]
2395#[cfg_attr(test, assert_instr(sat))]
2396#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2397pub unsafe fn Q6_R_sat_P(rss: i64) -> i32 {
2398    hexagon_A2_sat(rss)
2399}
2400
2401/// `Rd32=satb(Rs32)`
2402///
2403/// Instruction Type: S_2op
2404/// Execution Slots: SLOT23
2405#[inline(always)]
2406#[cfg_attr(test, assert_instr(satb))]
2407#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2408pub unsafe fn Q6_R_satb_R(rs: i32) -> i32 {
2409    hexagon_A2_satb(rs)
2410}
2411
2412/// `Rd32=sath(Rs32)`
2413///
2414/// Instruction Type: S_2op
2415/// Execution Slots: SLOT23
2416#[inline(always)]
2417#[cfg_attr(test, assert_instr(sath))]
2418#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2419pub unsafe fn Q6_R_sath_R(rs: i32) -> i32 {
2420    hexagon_A2_sath(rs)
2421}
2422
2423/// `Rd32=satub(Rs32)`
2424///
2425/// Instruction Type: S_2op
2426/// Execution Slots: SLOT23
2427#[inline(always)]
2428#[cfg_attr(test, assert_instr(satub))]
2429#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2430pub unsafe fn Q6_R_satub_R(rs: i32) -> i32 {
2431    hexagon_A2_satub(rs)
2432}
2433
2434/// `Rd32=satuh(Rs32)`
2435///
2436/// Instruction Type: S_2op
2437/// Execution Slots: SLOT23
2438#[inline(always)]
2439#[cfg_attr(test, assert_instr(satuh))]
2440#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2441pub unsafe fn Q6_R_satuh_R(rs: i32) -> i32 {
2442    hexagon_A2_satuh(rs)
2443}
2444
2445/// `Rd32=sub(Rt32,Rs32)`
2446///
2447/// Instruction Type: ALU32_3op
2448/// Execution Slots: SLOT0123
2449#[inline(always)]
2450#[cfg_attr(test, assert_instr(sub))]
2451#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2452pub unsafe fn Q6_R_sub_RR(rt: i32, rs: i32) -> i32 {
2453    hexagon_A2_sub(rt, rs)
2454}
2455
2456/// `Rd32=sub(Rt32.h,Rs32.h):<<16`
2457///
2458/// Instruction Type: ALU64
2459/// Execution Slots: SLOT23
2460#[inline(always)]
2461#[cfg_attr(test, assert_instr(sub))]
2462#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2463pub unsafe fn Q6_R_sub_RhRh_s16(rt: i32, rs: i32) -> i32 {
2464    hexagon_A2_subh_h16_hh(rt, rs)
2465}
2466
2467/// `Rd32=sub(Rt32.h,Rs32.l):<<16`
2468///
2469/// Instruction Type: ALU64
2470/// Execution Slots: SLOT23
2471#[inline(always)]
2472#[cfg_attr(test, assert_instr(sub))]
2473#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2474pub unsafe fn Q6_R_sub_RhRl_s16(rt: i32, rs: i32) -> i32 {
2475    hexagon_A2_subh_h16_hl(rt, rs)
2476}
2477
2478/// `Rd32=sub(Rt32.l,Rs32.h):<<16`
2479///
2480/// Instruction Type: ALU64
2481/// Execution Slots: SLOT23
2482#[inline(always)]
2483#[cfg_attr(test, assert_instr(sub))]
2484#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2485pub unsafe fn Q6_R_sub_RlRh_s16(rt: i32, rs: i32) -> i32 {
2486    hexagon_A2_subh_h16_lh(rt, rs)
2487}
2488
2489/// `Rd32=sub(Rt32.l,Rs32.l):<<16`
2490///
2491/// Instruction Type: ALU64
2492/// Execution Slots: SLOT23
2493#[inline(always)]
2494#[cfg_attr(test, assert_instr(sub))]
2495#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2496pub unsafe fn Q6_R_sub_RlRl_s16(rt: i32, rs: i32) -> i32 {
2497    hexagon_A2_subh_h16_ll(rt, rs)
2498}
2499
2500/// `Rd32=sub(Rt32.h,Rs32.h):sat:<<16`
2501///
2502/// Instruction Type: ALU64
2503/// Execution Slots: SLOT23
2504#[inline(always)]
2505#[cfg_attr(test, assert_instr(sub))]
2506#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2507pub unsafe fn Q6_R_sub_RhRh_sat_s16(rt: i32, rs: i32) -> i32 {
2508    hexagon_A2_subh_h16_sat_hh(rt, rs)
2509}
2510
2511/// `Rd32=sub(Rt32.h,Rs32.l):sat:<<16`
2512///
2513/// Instruction Type: ALU64
2514/// Execution Slots: SLOT23
2515#[inline(always)]
2516#[cfg_attr(test, assert_instr(sub))]
2517#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2518pub unsafe fn Q6_R_sub_RhRl_sat_s16(rt: i32, rs: i32) -> i32 {
2519    hexagon_A2_subh_h16_sat_hl(rt, rs)
2520}
2521
2522/// `Rd32=sub(Rt32.l,Rs32.h):sat:<<16`
2523///
2524/// Instruction Type: ALU64
2525/// Execution Slots: SLOT23
2526#[inline(always)]
2527#[cfg_attr(test, assert_instr(sub))]
2528#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2529pub unsafe fn Q6_R_sub_RlRh_sat_s16(rt: i32, rs: i32) -> i32 {
2530    hexagon_A2_subh_h16_sat_lh(rt, rs)
2531}
2532
2533/// `Rd32=sub(Rt32.l,Rs32.l):sat:<<16`
2534///
2535/// Instruction Type: ALU64
2536/// Execution Slots: SLOT23
2537#[inline(always)]
2538#[cfg_attr(test, assert_instr(sub))]
2539#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2540pub unsafe fn Q6_R_sub_RlRl_sat_s16(rt: i32, rs: i32) -> i32 {
2541    hexagon_A2_subh_h16_sat_ll(rt, rs)
2542}
2543
2544/// `Rd32=sub(Rt32.l,Rs32.h)`
2545///
2546/// Instruction Type: ALU64
2547/// Execution Slots: SLOT23
2548#[inline(always)]
2549#[cfg_attr(test, assert_instr(sub))]
2550#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2551pub unsafe fn Q6_R_sub_RlRh(rt: i32, rs: i32) -> i32 {
2552    hexagon_A2_subh_l16_hl(rt, rs)
2553}
2554
2555/// `Rd32=sub(Rt32.l,Rs32.l)`
2556///
2557/// Instruction Type: ALU64
2558/// Execution Slots: SLOT23
2559#[inline(always)]
2560#[cfg_attr(test, assert_instr(sub))]
2561#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2562pub unsafe fn Q6_R_sub_RlRl(rt: i32, rs: i32) -> i32 {
2563    hexagon_A2_subh_l16_ll(rt, rs)
2564}
2565
2566/// `Rd32=sub(Rt32.l,Rs32.h):sat`
2567///
2568/// Instruction Type: ALU64
2569/// Execution Slots: SLOT23
2570#[inline(always)]
2571#[cfg_attr(test, assert_instr(sub))]
2572#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2573pub unsafe fn Q6_R_sub_RlRh_sat(rt: i32, rs: i32) -> i32 {
2574    hexagon_A2_subh_l16_sat_hl(rt, rs)
2575}
2576
2577/// `Rd32=sub(Rt32.l,Rs32.l):sat`
2578///
2579/// Instruction Type: ALU64
2580/// Execution Slots: SLOT23
2581#[inline(always)]
2582#[cfg_attr(test, assert_instr(sub))]
2583#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2584pub unsafe fn Q6_R_sub_RlRl_sat(rt: i32, rs: i32) -> i32 {
2585    hexagon_A2_subh_l16_sat_ll(rt, rs)
2586}
2587
2588/// `Rdd32=sub(Rtt32,Rss32)`
2589///
2590/// Instruction Type: ALU64
2591/// Execution Slots: SLOT23
2592#[inline(always)]
2593#[cfg_attr(test, assert_instr(sub))]
2594#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2595pub unsafe fn Q6_P_sub_PP(rtt: i64, rss: i64) -> i64 {
2596    hexagon_A2_subp(rtt, rss)
2597}
2598
2599/// `Rd32=sub(#s10,Rs32)`
2600///
2601/// Instruction Type: ALU32_2op
2602/// Execution Slots: SLOT0123
2603#[inline(always)]
2604#[rustc_legacy_const_generics(0)]
2605#[cfg_attr(test, assert_instr(sub, IS10 = 0))]
2606#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2607pub unsafe fn Q6_R_sub_IR<const IS10: i32>(rs: i32) -> i32 {
2608    static_assert_simm_bits!(IS10, 10);
2609    hexagon_A2_subri(IS10, rs)
2610}
2611
2612/// `Rd32=sub(Rt32,Rs32):sat`
2613///
2614/// Instruction Type: ALU32_3op
2615/// Execution Slots: SLOT0123
2616#[inline(always)]
2617#[cfg_attr(test, assert_instr(sub))]
2618#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2619pub unsafe fn Q6_R_sub_RR_sat(rt: i32, rs: i32) -> i32 {
2620    hexagon_A2_subsat(rt, rs)
2621}
2622
2623/// `Rd32=vaddh(Rs32,Rt32)`
2624///
2625/// Instruction Type: ALU32_3op
2626/// Execution Slots: SLOT0123
2627#[inline(always)]
2628#[cfg_attr(test, assert_instr(vaddh))]
2629#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2630pub unsafe fn Q6_R_vaddh_RR(rs: i32, rt: i32) -> i32 {
2631    hexagon_A2_svaddh(rs, rt)
2632}
2633
2634/// `Rd32=vaddh(Rs32,Rt32):sat`
2635///
2636/// Instruction Type: ALU32_3op
2637/// Execution Slots: SLOT0123
2638#[inline(always)]
2639#[cfg_attr(test, assert_instr(vaddh))]
2640#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2641pub unsafe fn Q6_R_vaddh_RR_sat(rs: i32, rt: i32) -> i32 {
2642    hexagon_A2_svaddhs(rs, rt)
2643}
2644
2645/// `Rd32=vadduh(Rs32,Rt32):sat`
2646///
2647/// Instruction Type: ALU32_3op
2648/// Execution Slots: SLOT0123
2649#[inline(always)]
2650#[cfg_attr(test, assert_instr(vadduh))]
2651#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2652pub unsafe fn Q6_R_vadduh_RR_sat(rs: i32, rt: i32) -> i32 {
2653    hexagon_A2_svadduhs(rs, rt)
2654}
2655
2656/// `Rd32=vavgh(Rs32,Rt32)`
2657///
2658/// Instruction Type: ALU32_3op
2659/// Execution Slots: SLOT0123
2660#[inline(always)]
2661#[cfg_attr(test, assert_instr(vavgh))]
2662#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2663pub unsafe fn Q6_R_vavgh_RR(rs: i32, rt: i32) -> i32 {
2664    hexagon_A2_svavgh(rs, rt)
2665}
2666
2667/// `Rd32=vavgh(Rs32,Rt32):rnd`
2668///
2669/// Instruction Type: ALU32_3op
2670/// Execution Slots: SLOT0123
2671#[inline(always)]
2672#[cfg_attr(test, assert_instr(vavgh))]
2673#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2674pub unsafe fn Q6_R_vavgh_RR_rnd(rs: i32, rt: i32) -> i32 {
2675    hexagon_A2_svavghs(rs, rt)
2676}
2677
2678/// `Rd32=vnavgh(Rt32,Rs32)`
2679///
2680/// Instruction Type: ALU32_3op
2681/// Execution Slots: SLOT0123
2682#[inline(always)]
2683#[cfg_attr(test, assert_instr(vnavgh))]
2684#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2685pub unsafe fn Q6_R_vnavgh_RR(rt: i32, rs: i32) -> i32 {
2686    hexagon_A2_svnavgh(rt, rs)
2687}
2688
2689/// `Rd32=vsubh(Rt32,Rs32)`
2690///
2691/// Instruction Type: ALU32_3op
2692/// Execution Slots: SLOT0123
2693#[inline(always)]
2694#[cfg_attr(test, assert_instr(vsubh))]
2695#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2696pub unsafe fn Q6_R_vsubh_RR(rt: i32, rs: i32) -> i32 {
2697    hexagon_A2_svsubh(rt, rs)
2698}
2699
2700/// `Rd32=vsubh(Rt32,Rs32):sat`
2701///
2702/// Instruction Type: ALU32_3op
2703/// Execution Slots: SLOT0123
2704#[inline(always)]
2705#[cfg_attr(test, assert_instr(vsubh))]
2706#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2707pub unsafe fn Q6_R_vsubh_RR_sat(rt: i32, rs: i32) -> i32 {
2708    hexagon_A2_svsubhs(rt, rs)
2709}
2710
2711/// `Rd32=vsubuh(Rt32,Rs32):sat`
2712///
2713/// Instruction Type: ALU32_3op
2714/// Execution Slots: SLOT0123
2715#[inline(always)]
2716#[cfg_attr(test, assert_instr(vsubuh))]
2717#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2718pub unsafe fn Q6_R_vsubuh_RR_sat(rt: i32, rs: i32) -> i32 {
2719    hexagon_A2_svsubuhs(rt, rs)
2720}
2721
2722/// `Rd32=swiz(Rs32)`
2723///
2724/// Instruction Type: S_2op
2725/// Execution Slots: SLOT23
2726#[inline(always)]
2727#[cfg_attr(test, assert_instr(swiz))]
2728#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2729pub unsafe fn Q6_R_swiz_R(rs: i32) -> i32 {
2730    hexagon_A2_swiz(rs)
2731}
2732
2733/// `Rd32=sxtb(Rs32)`
2734///
2735/// Instruction Type: ALU32_2op
2736/// Execution Slots: SLOT0123
2737#[inline(always)]
2738#[cfg_attr(test, assert_instr(sxtb))]
2739#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2740pub unsafe fn Q6_R_sxtb_R(rs: i32) -> i32 {
2741    hexagon_A2_sxtb(rs)
2742}
2743
2744/// `Rd32=sxth(Rs32)`
2745///
2746/// Instruction Type: ALU32_2op
2747/// Execution Slots: SLOT0123
2748#[inline(always)]
2749#[cfg_attr(test, assert_instr(sxth))]
2750#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2751pub unsafe fn Q6_R_sxth_R(rs: i32) -> i32 {
2752    hexagon_A2_sxth(rs)
2753}
2754
2755/// `Rdd32=sxtw(Rs32)`
2756///
2757/// Instruction Type: S_2op
2758/// Execution Slots: SLOT23
2759#[inline(always)]
2760#[cfg_attr(test, assert_instr(sxtw))]
2761#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2762pub unsafe fn Q6_P_sxtw_R(rs: i32) -> i64 {
2763    hexagon_A2_sxtw(rs)
2764}
2765
2766/// `Rd32=Rs32`
2767///
2768/// Instruction Type: ALU32_2op
2769/// Execution Slots: SLOT0123
2770#[inline(always)]
2771#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2772pub unsafe fn Q6_R_equals_R(rs: i32) -> i32 {
2773    hexagon_A2_tfr(rs)
2774}
2775
2776/// `Rx32.h=#u16`
2777///
2778/// Instruction Type: ALU32_2op
2779/// Execution Slots: SLOT0123
2780#[inline(always)]
2781#[rustc_legacy_const_generics(1)]
2782#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2783pub unsafe fn Q6_Rh_equals_I<const IU16: u32>(rx: i32) -> i32 {
2784    static_assert_uimm_bits!(IU16, 16);
2785    hexagon_A2_tfrih(rx, IU16 as i32)
2786}
2787
2788/// `Rx32.l=#u16`
2789///
2790/// Instruction Type: ALU32_2op
2791/// Execution Slots: SLOT0123
2792#[inline(always)]
2793#[rustc_legacy_const_generics(1)]
2794#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2795pub unsafe fn Q6_Rl_equals_I<const IU16: u32>(rx: i32) -> i32 {
2796    static_assert_uimm_bits!(IU16, 16);
2797    hexagon_A2_tfril(rx, IU16 as i32)
2798}
2799
2800/// `Rdd32=Rss32`
2801///
2802/// Instruction Type: ALU32_2op
2803/// Execution Slots: SLOT0123
2804#[inline(always)]
2805#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2806pub unsafe fn Q6_P_equals_P(rss: i64) -> i64 {
2807    hexagon_A2_tfrp(rss)
2808}
2809
2810/// `Rdd32=#s8`
2811///
2812/// Instruction Type: ALU64
2813/// Execution Slots: SLOT0123
2814#[inline(always)]
2815#[rustc_legacy_const_generics(0)]
2816#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2817pub unsafe fn Q6_P_equals_I<const IS8: i32>() -> i64 {
2818    static_assert_simm_bits!(IS8, 8);
2819    hexagon_A2_tfrpi(IS8)
2820}
2821
2822/// `Rd32=#s16`
2823///
2824/// Instruction Type: ALU32_2op
2825/// Execution Slots: SLOT0123
2826#[inline(always)]
2827#[rustc_legacy_const_generics(0)]
2828#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2829pub unsafe fn Q6_R_equals_I<const IS16: i32>() -> i32 {
2830    static_assert_simm_bits!(IS16, 16);
2831    hexagon_A2_tfrsi(IS16)
2832}
2833
2834/// `Rdd32=vabsh(Rss32)`
2835///
2836/// Instruction Type: S_2op
2837/// Execution Slots: SLOT23
2838#[inline(always)]
2839#[cfg_attr(test, assert_instr(vabsh))]
2840#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2841pub unsafe fn Q6_P_vabsh_P(rss: i64) -> i64 {
2842    hexagon_A2_vabsh(rss)
2843}
2844
2845/// `Rdd32=vabsh(Rss32):sat`
2846///
2847/// Instruction Type: S_2op
2848/// Execution Slots: SLOT23
2849#[inline(always)]
2850#[cfg_attr(test, assert_instr(vabsh))]
2851#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2852pub unsafe fn Q6_P_vabsh_P_sat(rss: i64) -> i64 {
2853    hexagon_A2_vabshsat(rss)
2854}
2855
2856/// `Rdd32=vabsw(Rss32)`
2857///
2858/// Instruction Type: S_2op
2859/// Execution Slots: SLOT23
2860#[inline(always)]
2861#[cfg_attr(test, assert_instr(vabsw))]
2862#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2863pub unsafe fn Q6_P_vabsw_P(rss: i64) -> i64 {
2864    hexagon_A2_vabsw(rss)
2865}
2866
2867/// `Rdd32=vabsw(Rss32):sat`
2868///
2869/// Instruction Type: S_2op
2870/// Execution Slots: SLOT23
2871#[inline(always)]
2872#[cfg_attr(test, assert_instr(vabsw))]
2873#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2874pub unsafe fn Q6_P_vabsw_P_sat(rss: i64) -> i64 {
2875    hexagon_A2_vabswsat(rss)
2876}
2877
2878/// `Rdd32=vaddb(Rss32,Rtt32)`
2879///
2880/// Instruction Type: MAPPING
2881/// Execution Slots: SLOT0123
2882#[inline(always)]
2883#[cfg_attr(test, assert_instr(vaddb))]
2884#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2885pub unsafe fn Q6_P_vaddb_PP(rss: i64, rtt: i64) -> i64 {
2886    hexagon_A2_vaddb_map(rss, rtt)
2887}
2888
2889/// `Rdd32=vaddh(Rss32,Rtt32)`
2890///
2891/// Instruction Type: ALU64
2892/// Execution Slots: SLOT23
2893#[inline(always)]
2894#[cfg_attr(test, assert_instr(vaddh))]
2895#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2896pub unsafe fn Q6_P_vaddh_PP(rss: i64, rtt: i64) -> i64 {
2897    hexagon_A2_vaddh(rss, rtt)
2898}
2899
2900/// `Rdd32=vaddh(Rss32,Rtt32):sat`
2901///
2902/// Instruction Type: ALU64
2903/// Execution Slots: SLOT23
2904#[inline(always)]
2905#[cfg_attr(test, assert_instr(vaddh))]
2906#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2907pub unsafe fn Q6_P_vaddh_PP_sat(rss: i64, rtt: i64) -> i64 {
2908    hexagon_A2_vaddhs(rss, rtt)
2909}
2910
2911/// `Rdd32=vaddub(Rss32,Rtt32)`
2912///
2913/// Instruction Type: ALU64
2914/// Execution Slots: SLOT23
2915#[inline(always)]
2916#[cfg_attr(test, assert_instr(vaddub))]
2917#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2918pub unsafe fn Q6_P_vaddub_PP(rss: i64, rtt: i64) -> i64 {
2919    hexagon_A2_vaddub(rss, rtt)
2920}
2921
2922/// `Rdd32=vaddub(Rss32,Rtt32):sat`
2923///
2924/// Instruction Type: ALU64
2925/// Execution Slots: SLOT23
2926#[inline(always)]
2927#[cfg_attr(test, assert_instr(vaddub))]
2928#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2929pub unsafe fn Q6_P_vaddub_PP_sat(rss: i64, rtt: i64) -> i64 {
2930    hexagon_A2_vaddubs(rss, rtt)
2931}
2932
2933/// `Rdd32=vadduh(Rss32,Rtt32):sat`
2934///
2935/// Instruction Type: ALU64
2936/// Execution Slots: SLOT23
2937#[inline(always)]
2938#[cfg_attr(test, assert_instr(vadduh))]
2939#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2940pub unsafe fn Q6_P_vadduh_PP_sat(rss: i64, rtt: i64) -> i64 {
2941    hexagon_A2_vadduhs(rss, rtt)
2942}
2943
2944/// `Rdd32=vaddw(Rss32,Rtt32)`
2945///
2946/// Instruction Type: ALU64
2947/// Execution Slots: SLOT23
2948#[inline(always)]
2949#[cfg_attr(test, assert_instr(vaddw))]
2950#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2951pub unsafe fn Q6_P_vaddw_PP(rss: i64, rtt: i64) -> i64 {
2952    hexagon_A2_vaddw(rss, rtt)
2953}
2954
2955/// `Rdd32=vaddw(Rss32,Rtt32):sat`
2956///
2957/// Instruction Type: ALU64
2958/// Execution Slots: SLOT23
2959#[inline(always)]
2960#[cfg_attr(test, assert_instr(vaddw))]
2961#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2962pub unsafe fn Q6_P_vaddw_PP_sat(rss: i64, rtt: i64) -> i64 {
2963    hexagon_A2_vaddws(rss, rtt)
2964}
2965
2966/// `Rdd32=vavgh(Rss32,Rtt32)`
2967///
2968/// Instruction Type: ALU64
2969/// Execution Slots: SLOT23
2970#[inline(always)]
2971#[cfg_attr(test, assert_instr(vavgh))]
2972#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2973pub unsafe fn Q6_P_vavgh_PP(rss: i64, rtt: i64) -> i64 {
2974    hexagon_A2_vavgh(rss, rtt)
2975}
2976
2977/// `Rdd32=vavgh(Rss32,Rtt32):crnd`
2978///
2979/// Instruction Type: ALU64
2980/// Execution Slots: SLOT23
2981#[inline(always)]
2982#[cfg_attr(test, assert_instr(vavgh))]
2983#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2984pub unsafe fn Q6_P_vavgh_PP_crnd(rss: i64, rtt: i64) -> i64 {
2985    hexagon_A2_vavghcr(rss, rtt)
2986}
2987
2988/// `Rdd32=vavgh(Rss32,Rtt32):rnd`
2989///
2990/// Instruction Type: ALU64
2991/// Execution Slots: SLOT23
2992#[inline(always)]
2993#[cfg_attr(test, assert_instr(vavgh))]
2994#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2995pub unsafe fn Q6_P_vavgh_PP_rnd(rss: i64, rtt: i64) -> i64 {
2996    hexagon_A2_vavghr(rss, rtt)
2997}
2998
2999/// `Rdd32=vavgub(Rss32,Rtt32)`
3000///
3001/// Instruction Type: ALU64
3002/// Execution Slots: SLOT23
3003#[inline(always)]
3004#[cfg_attr(test, assert_instr(vavgub))]
3005#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3006pub unsafe fn Q6_P_vavgub_PP(rss: i64, rtt: i64) -> i64 {
3007    hexagon_A2_vavgub(rss, rtt)
3008}
3009
3010/// `Rdd32=vavgub(Rss32,Rtt32):rnd`
3011///
3012/// Instruction Type: ALU64
3013/// Execution Slots: SLOT23
3014#[inline(always)]
3015#[cfg_attr(test, assert_instr(vavgub))]
3016#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3017pub unsafe fn Q6_P_vavgub_PP_rnd(rss: i64, rtt: i64) -> i64 {
3018    hexagon_A2_vavgubr(rss, rtt)
3019}
3020
3021/// `Rdd32=vavguh(Rss32,Rtt32)`
3022///
3023/// Instruction Type: ALU64
3024/// Execution Slots: SLOT23
3025#[inline(always)]
3026#[cfg_attr(test, assert_instr(vavguh))]
3027#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3028pub unsafe fn Q6_P_vavguh_PP(rss: i64, rtt: i64) -> i64 {
3029    hexagon_A2_vavguh(rss, rtt)
3030}
3031
3032/// `Rdd32=vavguh(Rss32,Rtt32):rnd`
3033///
3034/// Instruction Type: ALU64
3035/// Execution Slots: SLOT23
3036#[inline(always)]
3037#[cfg_attr(test, assert_instr(vavguh))]
3038#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3039pub unsafe fn Q6_P_vavguh_PP_rnd(rss: i64, rtt: i64) -> i64 {
3040    hexagon_A2_vavguhr(rss, rtt)
3041}
3042
3043/// `Rdd32=vavguw(Rss32,Rtt32)`
3044///
3045/// Instruction Type: ALU64
3046/// Execution Slots: SLOT23
3047#[inline(always)]
3048#[cfg_attr(test, assert_instr(vavguw))]
3049#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3050pub unsafe fn Q6_P_vavguw_PP(rss: i64, rtt: i64) -> i64 {
3051    hexagon_A2_vavguw(rss, rtt)
3052}
3053
3054/// `Rdd32=vavguw(Rss32,Rtt32):rnd`
3055///
3056/// Instruction Type: ALU64
3057/// Execution Slots: SLOT23
3058#[inline(always)]
3059#[cfg_attr(test, assert_instr(vavguw))]
3060#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3061pub unsafe fn Q6_P_vavguw_PP_rnd(rss: i64, rtt: i64) -> i64 {
3062    hexagon_A2_vavguwr(rss, rtt)
3063}
3064
3065/// `Rdd32=vavgw(Rss32,Rtt32)`
3066///
3067/// Instruction Type: ALU64
3068/// Execution Slots: SLOT23
3069#[inline(always)]
3070#[cfg_attr(test, assert_instr(vavgw))]
3071#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3072pub unsafe fn Q6_P_vavgw_PP(rss: i64, rtt: i64) -> i64 {
3073    hexagon_A2_vavgw(rss, rtt)
3074}
3075
3076/// `Rdd32=vavgw(Rss32,Rtt32):crnd`
3077///
3078/// Instruction Type: ALU64
3079/// Execution Slots: SLOT23
3080#[inline(always)]
3081#[cfg_attr(test, assert_instr(vavgw))]
3082#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3083pub unsafe fn Q6_P_vavgw_PP_crnd(rss: i64, rtt: i64) -> i64 {
3084    hexagon_A2_vavgwcr(rss, rtt)
3085}
3086
3087/// `Rdd32=vavgw(Rss32,Rtt32):rnd`
3088///
3089/// Instruction Type: ALU64
3090/// Execution Slots: SLOT23
3091#[inline(always)]
3092#[cfg_attr(test, assert_instr(vavgw))]
3093#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3094pub unsafe fn Q6_P_vavgw_PP_rnd(rss: i64, rtt: i64) -> i64 {
3095    hexagon_A2_vavgwr(rss, rtt)
3096}
3097
3098/// `Pd4=vcmpb.eq(Rss32,Rtt32)`
3099///
3100/// Instruction Type: ALU64
3101/// Execution Slots: SLOT23
3102#[inline(always)]
3103#[cfg_attr(test, assert_instr(vcmpb))]
3104#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3105pub unsafe fn Q6_p_vcmpb_eq_PP(rss: i64, rtt: i64) -> i32 {
3106    hexagon_A2_vcmpbeq(rss, rtt)
3107}
3108
3109/// `Pd4=vcmpb.gtu(Rss32,Rtt32)`
3110///
3111/// Instruction Type: ALU64
3112/// Execution Slots: SLOT23
3113#[inline(always)]
3114#[cfg_attr(test, assert_instr(vcmpb))]
3115#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3116pub unsafe fn Q6_p_vcmpb_gtu_PP(rss: i64, rtt: i64) -> i32 {
3117    hexagon_A2_vcmpbgtu(rss, rtt)
3118}
3119
3120/// `Pd4=vcmph.eq(Rss32,Rtt32)`
3121///
3122/// Instruction Type: ALU64
3123/// Execution Slots: SLOT23
3124#[inline(always)]
3125#[cfg_attr(test, assert_instr(vcmph))]
3126#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3127pub unsafe fn Q6_p_vcmph_eq_PP(rss: i64, rtt: i64) -> i32 {
3128    hexagon_A2_vcmpheq(rss, rtt)
3129}
3130
3131/// `Pd4=vcmph.gt(Rss32,Rtt32)`
3132///
3133/// Instruction Type: ALU64
3134/// Execution Slots: SLOT23
3135#[inline(always)]
3136#[cfg_attr(test, assert_instr(vcmph))]
3137#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3138pub unsafe fn Q6_p_vcmph_gt_PP(rss: i64, rtt: i64) -> i32 {
3139    hexagon_A2_vcmphgt(rss, rtt)
3140}
3141
3142/// `Pd4=vcmph.gtu(Rss32,Rtt32)`
3143///
3144/// Instruction Type: ALU64
3145/// Execution Slots: SLOT23
3146#[inline(always)]
3147#[cfg_attr(test, assert_instr(vcmph))]
3148#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3149pub unsafe fn Q6_p_vcmph_gtu_PP(rss: i64, rtt: i64) -> i32 {
3150    hexagon_A2_vcmphgtu(rss, rtt)
3151}
3152
3153/// `Pd4=vcmpw.eq(Rss32,Rtt32)`
3154///
3155/// Instruction Type: ALU64
3156/// Execution Slots: SLOT23
3157#[inline(always)]
3158#[cfg_attr(test, assert_instr(vcmpw))]
3159#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3160pub unsafe fn Q6_p_vcmpw_eq_PP(rss: i64, rtt: i64) -> i32 {
3161    hexagon_A2_vcmpweq(rss, rtt)
3162}
3163
3164/// `Pd4=vcmpw.gt(Rss32,Rtt32)`
3165///
3166/// Instruction Type: ALU64
3167/// Execution Slots: SLOT23
3168#[inline(always)]
3169#[cfg_attr(test, assert_instr(vcmpw))]
3170#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3171pub unsafe fn Q6_p_vcmpw_gt_PP(rss: i64, rtt: i64) -> i32 {
3172    hexagon_A2_vcmpwgt(rss, rtt)
3173}
3174
3175/// `Pd4=vcmpw.gtu(Rss32,Rtt32)`
3176///
3177/// Instruction Type: ALU64
3178/// Execution Slots: SLOT23
3179#[inline(always)]
3180#[cfg_attr(test, assert_instr(vcmpw))]
3181#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3182pub unsafe fn Q6_p_vcmpw_gtu_PP(rss: i64, rtt: i64) -> i32 {
3183    hexagon_A2_vcmpwgtu(rss, rtt)
3184}
3185
3186/// `Rdd32=vconj(Rss32):sat`
3187///
3188/// Instruction Type: S_2op
3189/// Execution Slots: SLOT23
3190#[inline(always)]
3191#[cfg_attr(test, assert_instr(vconj))]
3192#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3193pub unsafe fn Q6_P_vconj_P_sat(rss: i64) -> i64 {
3194    hexagon_A2_vconj(rss)
3195}
3196
3197/// `Rdd32=vmaxb(Rtt32,Rss32)`
3198///
3199/// Instruction Type: ALU64
3200/// Execution Slots: SLOT23
3201#[inline(always)]
3202#[cfg_attr(test, assert_instr(vmaxb))]
3203#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3204pub unsafe fn Q6_P_vmaxb_PP(rtt: i64, rss: i64) -> i64 {
3205    hexagon_A2_vmaxb(rtt, rss)
3206}
3207
3208/// `Rdd32=vmaxh(Rtt32,Rss32)`
3209///
3210/// Instruction Type: ALU64
3211/// Execution Slots: SLOT23
3212#[inline(always)]
3213#[cfg_attr(test, assert_instr(vmaxh))]
3214#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3215pub unsafe fn Q6_P_vmaxh_PP(rtt: i64, rss: i64) -> i64 {
3216    hexagon_A2_vmaxh(rtt, rss)
3217}
3218
3219/// `Rdd32=vmaxub(Rtt32,Rss32)`
3220///
3221/// Instruction Type: ALU64
3222/// Execution Slots: SLOT23
3223#[inline(always)]
3224#[cfg_attr(test, assert_instr(vmaxub))]
3225#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3226pub unsafe fn Q6_P_vmaxub_PP(rtt: i64, rss: i64) -> i64 {
3227    hexagon_A2_vmaxub(rtt, rss)
3228}
3229
3230/// `Rdd32=vmaxuh(Rtt32,Rss32)`
3231///
3232/// Instruction Type: ALU64
3233/// Execution Slots: SLOT23
3234#[inline(always)]
3235#[cfg_attr(test, assert_instr(vmaxuh))]
3236#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3237pub unsafe fn Q6_P_vmaxuh_PP(rtt: i64, rss: i64) -> i64 {
3238    hexagon_A2_vmaxuh(rtt, rss)
3239}
3240
3241/// `Rdd32=vmaxuw(Rtt32,Rss32)`
3242///
3243/// Instruction Type: ALU64
3244/// Execution Slots: SLOT23
3245#[inline(always)]
3246#[cfg_attr(test, assert_instr(vmaxuw))]
3247#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3248pub unsafe fn Q6_P_vmaxuw_PP(rtt: i64, rss: i64) -> i64 {
3249    hexagon_A2_vmaxuw(rtt, rss)
3250}
3251
3252/// `Rdd32=vmaxw(Rtt32,Rss32)`
3253///
3254/// Instruction Type: ALU64
3255/// Execution Slots: SLOT23
3256#[inline(always)]
3257#[cfg_attr(test, assert_instr(vmaxw))]
3258#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3259pub unsafe fn Q6_P_vmaxw_PP(rtt: i64, rss: i64) -> i64 {
3260    hexagon_A2_vmaxw(rtt, rss)
3261}
3262
3263/// `Rdd32=vminb(Rtt32,Rss32)`
3264///
3265/// Instruction Type: ALU64
3266/// Execution Slots: SLOT23
3267#[inline(always)]
3268#[cfg_attr(test, assert_instr(vminb))]
3269#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3270pub unsafe fn Q6_P_vminb_PP(rtt: i64, rss: i64) -> i64 {
3271    hexagon_A2_vminb(rtt, rss)
3272}
3273
3274/// `Rdd32=vminh(Rtt32,Rss32)`
3275///
3276/// Instruction Type: ALU64
3277/// Execution Slots: SLOT23
3278#[inline(always)]
3279#[cfg_attr(test, assert_instr(vminh))]
3280#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3281pub unsafe fn Q6_P_vminh_PP(rtt: i64, rss: i64) -> i64 {
3282    hexagon_A2_vminh(rtt, rss)
3283}
3284
3285/// `Rdd32=vminub(Rtt32,Rss32)`
3286///
3287/// Instruction Type: ALU64
3288/// Execution Slots: SLOT23
3289#[inline(always)]
3290#[cfg_attr(test, assert_instr(vminub))]
3291#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3292pub unsafe fn Q6_P_vminub_PP(rtt: i64, rss: i64) -> i64 {
3293    hexagon_A2_vminub(rtt, rss)
3294}
3295
3296/// `Rdd32=vminuh(Rtt32,Rss32)`
3297///
3298/// Instruction Type: ALU64
3299/// Execution Slots: SLOT23
3300#[inline(always)]
3301#[cfg_attr(test, assert_instr(vminuh))]
3302#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3303pub unsafe fn Q6_P_vminuh_PP(rtt: i64, rss: i64) -> i64 {
3304    hexagon_A2_vminuh(rtt, rss)
3305}
3306
3307/// `Rdd32=vminuw(Rtt32,Rss32)`
3308///
3309/// Instruction Type: ALU64
3310/// Execution Slots: SLOT23
3311#[inline(always)]
3312#[cfg_attr(test, assert_instr(vminuw))]
3313#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3314pub unsafe fn Q6_P_vminuw_PP(rtt: i64, rss: i64) -> i64 {
3315    hexagon_A2_vminuw(rtt, rss)
3316}
3317
3318/// `Rdd32=vminw(Rtt32,Rss32)`
3319///
3320/// Instruction Type: ALU64
3321/// Execution Slots: SLOT23
3322#[inline(always)]
3323#[cfg_attr(test, assert_instr(vminw))]
3324#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3325pub unsafe fn Q6_P_vminw_PP(rtt: i64, rss: i64) -> i64 {
3326    hexagon_A2_vminw(rtt, rss)
3327}
3328
3329/// `Rdd32=vnavgh(Rtt32,Rss32)`
3330///
3331/// Instruction Type: ALU64
3332/// Execution Slots: SLOT23
3333#[inline(always)]
3334#[cfg_attr(test, assert_instr(vnavgh))]
3335#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3336pub unsafe fn Q6_P_vnavgh_PP(rtt: i64, rss: i64) -> i64 {
3337    hexagon_A2_vnavgh(rtt, rss)
3338}
3339
3340/// `Rdd32=vnavgh(Rtt32,Rss32):crnd:sat`
3341///
3342/// Instruction Type: ALU64
3343/// Execution Slots: SLOT23
3344#[inline(always)]
3345#[cfg_attr(test, assert_instr(vnavgh))]
3346#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3347pub unsafe fn Q6_P_vnavgh_PP_crnd_sat(rtt: i64, rss: i64) -> i64 {
3348    hexagon_A2_vnavghcr(rtt, rss)
3349}
3350
3351/// `Rdd32=vnavgh(Rtt32,Rss32):rnd:sat`
3352///
3353/// Instruction Type: ALU64
3354/// Execution Slots: SLOT23
3355#[inline(always)]
3356#[cfg_attr(test, assert_instr(vnavgh))]
3357#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3358pub unsafe fn Q6_P_vnavgh_PP_rnd_sat(rtt: i64, rss: i64) -> i64 {
3359    hexagon_A2_vnavghr(rtt, rss)
3360}
3361
3362/// `Rdd32=vnavgw(Rtt32,Rss32)`
3363///
3364/// Instruction Type: ALU64
3365/// Execution Slots: SLOT23
3366#[inline(always)]
3367#[cfg_attr(test, assert_instr(vnavgw))]
3368#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3369pub unsafe fn Q6_P_vnavgw_PP(rtt: i64, rss: i64) -> i64 {
3370    hexagon_A2_vnavgw(rtt, rss)
3371}
3372
3373/// `Rdd32=vnavgw(Rtt32,Rss32):crnd:sat`
3374///
3375/// Instruction Type: ALU64
3376/// Execution Slots: SLOT23
3377#[inline(always)]
3378#[cfg_attr(test, assert_instr(vnavgw))]
3379#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3380pub unsafe fn Q6_P_vnavgw_PP_crnd_sat(rtt: i64, rss: i64) -> i64 {
3381    hexagon_A2_vnavgwcr(rtt, rss)
3382}
3383
3384/// `Rdd32=vnavgw(Rtt32,Rss32):rnd:sat`
3385///
3386/// Instruction Type: ALU64
3387/// Execution Slots: SLOT23
3388#[inline(always)]
3389#[cfg_attr(test, assert_instr(vnavgw))]
3390#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3391pub unsafe fn Q6_P_vnavgw_PP_rnd_sat(rtt: i64, rss: i64) -> i64 {
3392    hexagon_A2_vnavgwr(rtt, rss)
3393}
3394
3395/// `Rdd32=vraddub(Rss32,Rtt32)`
3396///
3397/// Instruction Type: M
3398/// Execution Slots: SLOT23
3399#[inline(always)]
3400#[cfg_attr(test, assert_instr(vraddub))]
3401#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3402pub unsafe fn Q6_P_vraddub_PP(rss: i64, rtt: i64) -> i64 {
3403    hexagon_A2_vraddub(rss, rtt)
3404}
3405
3406/// `Rxx32+=vraddub(Rss32,Rtt32)`
3407///
3408/// Instruction Type: M
3409/// Execution Slots: SLOT23
3410#[inline(always)]
3411#[cfg_attr(test, assert_instr(vraddub))]
3412#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3413pub unsafe fn Q6_P_vraddubacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
3414    hexagon_A2_vraddub_acc(rxx, rss, rtt)
3415}
3416
3417/// `Rdd32=vrsadub(Rss32,Rtt32)`
3418///
3419/// Instruction Type: M
3420/// Execution Slots: SLOT23
3421#[inline(always)]
3422#[cfg_attr(test, assert_instr(vrsadub))]
3423#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3424pub unsafe fn Q6_P_vrsadub_PP(rss: i64, rtt: i64) -> i64 {
3425    hexagon_A2_vrsadub(rss, rtt)
3426}
3427
3428/// `Rxx32+=vrsadub(Rss32,Rtt32)`
3429///
3430/// Instruction Type: M
3431/// Execution Slots: SLOT23
3432#[inline(always)]
3433#[cfg_attr(test, assert_instr(vrsadub))]
3434#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3435pub unsafe fn Q6_P_vrsadubacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
3436    hexagon_A2_vrsadub_acc(rxx, rss, rtt)
3437}
3438
3439/// `Rdd32=vsubb(Rss32,Rtt32)`
3440///
3441/// Instruction Type: MAPPING
3442/// Execution Slots: SLOT0123
3443#[inline(always)]
3444#[cfg_attr(test, assert_instr(vsubb))]
3445#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3446pub unsafe fn Q6_P_vsubb_PP(rss: i64, rtt: i64) -> i64 {
3447    hexagon_A2_vsubb_map(rss, rtt)
3448}
3449
3450/// `Rdd32=vsubh(Rtt32,Rss32)`
3451///
3452/// Instruction Type: ALU64
3453/// Execution Slots: SLOT23
3454#[inline(always)]
3455#[cfg_attr(test, assert_instr(vsubh))]
3456#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3457pub unsafe fn Q6_P_vsubh_PP(rtt: i64, rss: i64) -> i64 {
3458    hexagon_A2_vsubh(rtt, rss)
3459}
3460
3461/// `Rdd32=vsubh(Rtt32,Rss32):sat`
3462///
3463/// Instruction Type: ALU64
3464/// Execution Slots: SLOT23
3465#[inline(always)]
3466#[cfg_attr(test, assert_instr(vsubh))]
3467#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3468pub unsafe fn Q6_P_vsubh_PP_sat(rtt: i64, rss: i64) -> i64 {
3469    hexagon_A2_vsubhs(rtt, rss)
3470}
3471
3472/// `Rdd32=vsubub(Rtt32,Rss32)`
3473///
3474/// Instruction Type: ALU64
3475/// Execution Slots: SLOT23
3476#[inline(always)]
3477#[cfg_attr(test, assert_instr(vsubub))]
3478#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3479pub unsafe fn Q6_P_vsubub_PP(rtt: i64, rss: i64) -> i64 {
3480    hexagon_A2_vsubub(rtt, rss)
3481}
3482
3483/// `Rdd32=vsubub(Rtt32,Rss32):sat`
3484///
3485/// Instruction Type: ALU64
3486/// Execution Slots: SLOT23
3487#[inline(always)]
3488#[cfg_attr(test, assert_instr(vsubub))]
3489#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3490pub unsafe fn Q6_P_vsubub_PP_sat(rtt: i64, rss: i64) -> i64 {
3491    hexagon_A2_vsububs(rtt, rss)
3492}
3493
3494/// `Rdd32=vsubuh(Rtt32,Rss32):sat`
3495///
3496/// Instruction Type: ALU64
3497/// Execution Slots: SLOT23
3498#[inline(always)]
3499#[cfg_attr(test, assert_instr(vsubuh))]
3500#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3501pub unsafe fn Q6_P_vsubuh_PP_sat(rtt: i64, rss: i64) -> i64 {
3502    hexagon_A2_vsubuhs(rtt, rss)
3503}
3504
3505/// `Rdd32=vsubw(Rtt32,Rss32)`
3506///
3507/// Instruction Type: ALU64
3508/// Execution Slots: SLOT23
3509#[inline(always)]
3510#[cfg_attr(test, assert_instr(vsubw))]
3511#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3512pub unsafe fn Q6_P_vsubw_PP(rtt: i64, rss: i64) -> i64 {
3513    hexagon_A2_vsubw(rtt, rss)
3514}
3515
3516/// `Rdd32=vsubw(Rtt32,Rss32):sat`
3517///
3518/// Instruction Type: ALU64
3519/// Execution Slots: SLOT23
3520#[inline(always)]
3521#[cfg_attr(test, assert_instr(vsubw))]
3522#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3523pub unsafe fn Q6_P_vsubw_PP_sat(rtt: i64, rss: i64) -> i64 {
3524    hexagon_A2_vsubws(rtt, rss)
3525}
3526
3527/// `Rd32=xor(Rs32,Rt32)`
3528///
3529/// Instruction Type: ALU32_3op
3530/// Execution Slots: SLOT0123
3531#[inline(always)]
3532#[cfg_attr(test, assert_instr(xor))]
3533#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3534pub unsafe fn Q6_R_xor_RR(rs: i32, rt: i32) -> i32 {
3535    hexagon_A2_xor(rs, rt)
3536}
3537
3538/// `Rdd32=xor(Rss32,Rtt32)`
3539///
3540/// Instruction Type: ALU64
3541/// Execution Slots: SLOT23
3542#[inline(always)]
3543#[cfg_attr(test, assert_instr(xor))]
3544#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3545pub unsafe fn Q6_P_xor_PP(rss: i64, rtt: i64) -> i64 {
3546    hexagon_A2_xorp(rss, rtt)
3547}
3548
3549/// `Rd32=zxtb(Rs32)`
3550///
3551/// Instruction Type: ALU32_2op
3552/// Execution Slots: SLOT0123
3553#[inline(always)]
3554#[cfg_attr(test, assert_instr(zxtb))]
3555#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3556pub unsafe fn Q6_R_zxtb_R(rs: i32) -> i32 {
3557    hexagon_A2_zxtb(rs)
3558}
3559
3560/// `Rd32=zxth(Rs32)`
3561///
3562/// Instruction Type: ALU32_2op
3563/// Execution Slots: SLOT0123
3564#[inline(always)]
3565#[cfg_attr(test, assert_instr(zxth))]
3566#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3567pub unsafe fn Q6_R_zxth_R(rs: i32) -> i32 {
3568    hexagon_A2_zxth(rs)
3569}
3570
3571/// `Rd32=and(Rt32,~Rs32)`
3572///
3573/// Instruction Type: ALU32_3op
3574/// Execution Slots: SLOT0123
3575#[inline(always)]
3576#[cfg_attr(test, assert_instr(and))]
3577#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3578pub unsafe fn Q6_R_and_RnR(rt: i32, rs: i32) -> i32 {
3579    hexagon_A4_andn(rt, rs)
3580}
3581
3582/// `Rdd32=and(Rtt32,~Rss32)`
3583///
3584/// Instruction Type: ALU64
3585/// Execution Slots: SLOT23
3586#[inline(always)]
3587#[cfg_attr(test, assert_instr(and))]
3588#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3589pub unsafe fn Q6_P_and_PnP(rtt: i64, rss: i64) -> i64 {
3590    hexagon_A4_andnp(rtt, rss)
3591}
3592
3593/// `Rdd32=bitsplit(Rs32,Rt32)`
3594///
3595/// Instruction Type: ALU64
3596/// Execution Slots: SLOT23
3597#[inline(always)]
3598#[cfg_attr(test, assert_instr(bitsplit))]
3599#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3600pub unsafe fn Q6_P_bitsplit_RR(rs: i32, rt: i32) -> i64 {
3601    hexagon_A4_bitsplit(rs, rt)
3602}
3603
3604/// `Rdd32=bitsplit(Rs32,#u5)`
3605///
3606/// Instruction Type: S_2op
3607/// Execution Slots: SLOT23
3608#[inline(always)]
3609#[rustc_legacy_const_generics(1)]
3610#[cfg_attr(test, assert_instr(bitsplit, IU5 = 0))]
3611#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3612pub unsafe fn Q6_P_bitsplit_RI<const IU5: u32>(rs: i32) -> i64 {
3613    static_assert_uimm_bits!(IU5, 5);
3614    hexagon_A4_bitspliti(rs, IU5 as i32)
3615}
3616
3617/// `Pd4=boundscheck(Rs32,Rtt32)`
3618///
3619/// Instruction Type: ALU64
3620/// Execution Slots: SLOT0123
3621#[inline(always)]
3622#[cfg_attr(test, assert_instr(boundscheck))]
3623#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3624pub unsafe fn Q6_p_boundscheck_RP(rs: i32, rtt: i64) -> i32 {
3625    hexagon_A4_boundscheck(rs, rtt)
3626}
3627
3628/// `Pd4=cmpb.eq(Rs32,Rt32)`
3629///
3630/// Instruction Type: S_3op
3631/// Execution Slots: SLOT23
3632#[inline(always)]
3633#[cfg_attr(test, assert_instr(cmpb))]
3634#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3635pub unsafe fn Q6_p_cmpb_eq_RR(rs: i32, rt: i32) -> i32 {
3636    hexagon_A4_cmpbeq(rs, rt)
3637}
3638
3639/// `Pd4=cmpb.eq(Rs32,#u8)`
3640///
3641/// Instruction Type: ALU64
3642/// Execution Slots: SLOT23
3643#[inline(always)]
3644#[rustc_legacy_const_generics(1)]
3645#[cfg_attr(test, assert_instr(cmpb, IU8 = 0))]
3646#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3647pub unsafe fn Q6_p_cmpb_eq_RI<const IU8: u32>(rs: i32) -> i32 {
3648    static_assert_uimm_bits!(IU8, 8);
3649    hexagon_A4_cmpbeqi(rs, IU8 as i32)
3650}
3651
3652/// `Pd4=cmpb.gt(Rs32,Rt32)`
3653///
3654/// Instruction Type: S_3op
3655/// Execution Slots: SLOT23
3656#[inline(always)]
3657#[cfg_attr(test, assert_instr(cmpb))]
3658#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3659pub unsafe fn Q6_p_cmpb_gt_RR(rs: i32, rt: i32) -> i32 {
3660    hexagon_A4_cmpbgt(rs, rt)
3661}
3662
3663/// `Pd4=cmpb.gt(Rs32,#s8)`
3664///
3665/// Instruction Type: ALU64
3666/// Execution Slots: SLOT23
3667#[inline(always)]
3668#[rustc_legacy_const_generics(1)]
3669#[cfg_attr(test, assert_instr(cmpb, IS8 = 0))]
3670#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3671pub unsafe fn Q6_p_cmpb_gt_RI<const IS8: i32>(rs: i32) -> i32 {
3672    static_assert_simm_bits!(IS8, 8);
3673    hexagon_A4_cmpbgti(rs, IS8)
3674}
3675
3676/// `Pd4=cmpb.gtu(Rs32,Rt32)`
3677///
3678/// Instruction Type: S_3op
3679/// Execution Slots: SLOT23
3680#[inline(always)]
3681#[cfg_attr(test, assert_instr(cmpb))]
3682#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3683pub unsafe fn Q6_p_cmpb_gtu_RR(rs: i32, rt: i32) -> i32 {
3684    hexagon_A4_cmpbgtu(rs, rt)
3685}
3686
3687/// `Pd4=cmpb.gtu(Rs32,#u7)`
3688///
3689/// Instruction Type: ALU64
3690/// Execution Slots: SLOT23
3691#[inline(always)]
3692#[rustc_legacy_const_generics(1)]
3693#[cfg_attr(test, assert_instr(cmpb, IU7 = 0))]
3694#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3695pub unsafe fn Q6_p_cmpb_gtu_RI<const IU7: u32>(rs: i32) -> i32 {
3696    static_assert_uimm_bits!(IU7, 7);
3697    hexagon_A4_cmpbgtui(rs, IU7 as i32)
3698}
3699
3700/// `Pd4=cmph.eq(Rs32,Rt32)`
3701///
3702/// Instruction Type: S_3op
3703/// Execution Slots: SLOT23
3704#[inline(always)]
3705#[cfg_attr(test, assert_instr(cmph))]
3706#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3707pub unsafe fn Q6_p_cmph_eq_RR(rs: i32, rt: i32) -> i32 {
3708    hexagon_A4_cmpheq(rs, rt)
3709}
3710
3711/// `Pd4=cmph.eq(Rs32,#s8)`
3712///
3713/// Instruction Type: ALU64
3714/// Execution Slots: SLOT23
3715#[inline(always)]
3716#[rustc_legacy_const_generics(1)]
3717#[cfg_attr(test, assert_instr(cmph, IS8 = 0))]
3718#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3719pub unsafe fn Q6_p_cmph_eq_RI<const IS8: i32>(rs: i32) -> i32 {
3720    static_assert_simm_bits!(IS8, 8);
3721    hexagon_A4_cmpheqi(rs, IS8)
3722}
3723
3724/// `Pd4=cmph.gt(Rs32,Rt32)`
3725///
3726/// Instruction Type: S_3op
3727/// Execution Slots: SLOT23
3728#[inline(always)]
3729#[cfg_attr(test, assert_instr(cmph))]
3730#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3731pub unsafe fn Q6_p_cmph_gt_RR(rs: i32, rt: i32) -> i32 {
3732    hexagon_A4_cmphgt(rs, rt)
3733}
3734
3735/// `Pd4=cmph.gt(Rs32,#s8)`
3736///
3737/// Instruction Type: ALU64
3738/// Execution Slots: SLOT23
3739#[inline(always)]
3740#[rustc_legacy_const_generics(1)]
3741#[cfg_attr(test, assert_instr(cmph, IS8 = 0))]
3742#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3743pub unsafe fn Q6_p_cmph_gt_RI<const IS8: i32>(rs: i32) -> i32 {
3744    static_assert_simm_bits!(IS8, 8);
3745    hexagon_A4_cmphgti(rs, IS8)
3746}
3747
3748/// `Pd4=cmph.gtu(Rs32,Rt32)`
3749///
3750/// Instruction Type: S_3op
3751/// Execution Slots: SLOT23
3752#[inline(always)]
3753#[cfg_attr(test, assert_instr(cmph))]
3754#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3755pub unsafe fn Q6_p_cmph_gtu_RR(rs: i32, rt: i32) -> i32 {
3756    hexagon_A4_cmphgtu(rs, rt)
3757}
3758
3759/// `Pd4=cmph.gtu(Rs32,#u7)`
3760///
3761/// Instruction Type: ALU64
3762/// Execution Slots: SLOT23
3763#[inline(always)]
3764#[rustc_legacy_const_generics(1)]
3765#[cfg_attr(test, assert_instr(cmph, IU7 = 0))]
3766#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3767pub unsafe fn Q6_p_cmph_gtu_RI<const IU7: u32>(rs: i32) -> i32 {
3768    static_assert_uimm_bits!(IU7, 7);
3769    hexagon_A4_cmphgtui(rs, IU7 as i32)
3770}
3771
3772/// `Rdd32=combine(#s8,Rs32)`
3773///
3774/// Instruction Type: ALU32_2op
3775/// Execution Slots: SLOT0123
3776#[inline(always)]
3777#[rustc_legacy_const_generics(0)]
3778#[cfg_attr(test, assert_instr(combine, IS8 = 0))]
3779#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3780pub unsafe fn Q6_P_combine_IR<const IS8: i32>(rs: i32) -> i64 {
3781    static_assert_simm_bits!(IS8, 8);
3782    hexagon_A4_combineir(IS8, rs)
3783}
3784
3785/// `Rdd32=combine(Rs32,#s8)`
3786///
3787/// Instruction Type: ALU32_2op
3788/// Execution Slots: SLOT0123
3789#[inline(always)]
3790#[rustc_legacy_const_generics(1)]
3791#[cfg_attr(test, assert_instr(combine, IS8 = 0))]
3792#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3793pub unsafe fn Q6_P_combine_RI<const IS8: i32>(rs: i32) -> i64 {
3794    static_assert_simm_bits!(IS8, 8);
3795    hexagon_A4_combineri(rs, IS8)
3796}
3797
3798/// `Rd32=cround(Rs32,#u5)`
3799///
3800/// Instruction Type: S_2op
3801/// Execution Slots: SLOT23
3802#[inline(always)]
3803#[rustc_legacy_const_generics(1)]
3804#[cfg_attr(test, assert_instr(cround, IU5 = 0))]
3805#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3806pub unsafe fn Q6_R_cround_RI<const IU5: u32>(rs: i32) -> i32 {
3807    static_assert_uimm_bits!(IU5, 5);
3808    hexagon_A4_cround_ri(rs, IU5 as i32)
3809}
3810
3811/// `Rd32=cround(Rs32,Rt32)`
3812///
3813/// Instruction Type: S_3op
3814/// Execution Slots: SLOT23
3815#[inline(always)]
3816#[cfg_attr(test, assert_instr(cround))]
3817#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3818pub unsafe fn Q6_R_cround_RR(rs: i32, rt: i32) -> i32 {
3819    hexagon_A4_cround_rr(rs, rt)
3820}
3821
3822/// `Rd32=modwrap(Rs32,Rt32)`
3823///
3824/// Instruction Type: ALU64
3825/// Execution Slots: SLOT23
3826#[inline(always)]
3827#[cfg_attr(test, assert_instr(modwrap))]
3828#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3829pub unsafe fn Q6_R_modwrap_RR(rs: i32, rt: i32) -> i32 {
3830    hexagon_A4_modwrapu(rs, rt)
3831}
3832
3833/// `Rd32=or(Rt32,~Rs32)`
3834///
3835/// Instruction Type: ALU32_3op
3836/// Execution Slots: SLOT0123
3837#[inline(always)]
3838#[cfg_attr(test, assert_instr(or))]
3839#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3840pub unsafe fn Q6_R_or_RnR(rt: i32, rs: i32) -> i32 {
3841    hexagon_A4_orn(rt, rs)
3842}
3843
3844/// `Rdd32=or(Rtt32,~Rss32)`
3845///
3846/// Instruction Type: ALU64
3847/// Execution Slots: SLOT23
3848#[inline(always)]
3849#[cfg_attr(test, assert_instr(or))]
3850#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3851pub unsafe fn Q6_P_or_PnP(rtt: i64, rss: i64) -> i64 {
3852    hexagon_A4_ornp(rtt, rss)
3853}
3854
3855/// `Rd32=cmp.eq(Rs32,Rt32)`
3856///
3857/// Instruction Type: ALU32_3op
3858/// Execution Slots: SLOT0123
3859#[inline(always)]
3860#[cfg_attr(test, assert_instr(cmp))]
3861#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3862pub unsafe fn Q6_R_cmp_eq_RR(rs: i32, rt: i32) -> i32 {
3863    hexagon_A4_rcmpeq(rs, rt)
3864}
3865
3866/// `Rd32=cmp.eq(Rs32,#s8)`
3867///
3868/// Instruction Type: ALU32_2op
3869/// Execution Slots: SLOT0123
3870#[inline(always)]
3871#[rustc_legacy_const_generics(1)]
3872#[cfg_attr(test, assert_instr(cmp, IS8 = 0))]
3873#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3874pub unsafe fn Q6_R_cmp_eq_RI<const IS8: i32>(rs: i32) -> i32 {
3875    static_assert_simm_bits!(IS8, 8);
3876    hexagon_A4_rcmpeqi(rs, IS8)
3877}
3878
3879/// `Rd32=!cmp.eq(Rs32,Rt32)`
3880///
3881/// Instruction Type: ALU32_3op
3882/// Execution Slots: SLOT0123
3883#[inline(always)]
3884#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3885pub unsafe fn Q6_R_not_cmp_eq_RR(rs: i32, rt: i32) -> i32 {
3886    hexagon_A4_rcmpneq(rs, rt)
3887}
3888
3889/// `Rd32=!cmp.eq(Rs32,#s8)`
3890///
3891/// Instruction Type: ALU32_2op
3892/// Execution Slots: SLOT0123
3893#[inline(always)]
3894#[rustc_legacy_const_generics(1)]
3895#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3896pub unsafe fn Q6_R_not_cmp_eq_RI<const IS8: i32>(rs: i32) -> i32 {
3897    static_assert_simm_bits!(IS8, 8);
3898    hexagon_A4_rcmpneqi(rs, IS8)
3899}
3900
3901/// `Rd32=round(Rs32,#u5)`
3902///
3903/// Instruction Type: S_2op
3904/// Execution Slots: SLOT23
3905#[inline(always)]
3906#[rustc_legacy_const_generics(1)]
3907#[cfg_attr(test, assert_instr(round, IU5 = 0))]
3908#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3909pub unsafe fn Q6_R_round_RI<const IU5: u32>(rs: i32) -> i32 {
3910    static_assert_uimm_bits!(IU5, 5);
3911    hexagon_A4_round_ri(rs, IU5 as i32)
3912}
3913
3914/// `Rd32=round(Rs32,#u5):sat`
3915///
3916/// Instruction Type: S_2op
3917/// Execution Slots: SLOT23
3918#[inline(always)]
3919#[rustc_legacy_const_generics(1)]
3920#[cfg_attr(test, assert_instr(round, IU5 = 0))]
3921#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3922pub unsafe fn Q6_R_round_RI_sat<const IU5: u32>(rs: i32) -> i32 {
3923    static_assert_uimm_bits!(IU5, 5);
3924    hexagon_A4_round_ri_sat(rs, IU5 as i32)
3925}
3926
3927/// `Rd32=round(Rs32,Rt32)`
3928///
3929/// Instruction Type: S_3op
3930/// Execution Slots: SLOT23
3931#[inline(always)]
3932#[cfg_attr(test, assert_instr(round))]
3933#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3934pub unsafe fn Q6_R_round_RR(rs: i32, rt: i32) -> i32 {
3935    hexagon_A4_round_rr(rs, rt)
3936}
3937
3938/// `Rd32=round(Rs32,Rt32):sat`
3939///
3940/// Instruction Type: S_3op
3941/// Execution Slots: SLOT23
3942#[inline(always)]
3943#[cfg_attr(test, assert_instr(round))]
3944#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3945pub unsafe fn Q6_R_round_RR_sat(rs: i32, rt: i32) -> i32 {
3946    hexagon_A4_round_rr_sat(rs, rt)
3947}
3948
3949/// `Pd4=tlbmatch(Rss32,Rt32)`
3950///
3951/// Instruction Type: ALU64
3952/// Execution Slots: SLOT23
3953#[inline(always)]
3954#[cfg_attr(test, assert_instr(tlbmatch))]
3955#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3956pub unsafe fn Q6_p_tlbmatch_PR(rss: i64, rt: i32) -> i32 {
3957    hexagon_A4_tlbmatch(rss, rt)
3958}
3959
3960/// `Pd4=any8(vcmpb.eq(Rss32,Rtt32))`
3961///
3962/// Instruction Type: ALU64
3963/// Execution Slots: SLOT23
3964#[inline(always)]
3965#[cfg_attr(test, assert_instr(any8))]
3966#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3967pub unsafe fn Q6_p_any8_vcmpb_eq_PP(rss: i64, rtt: i64) -> i32 {
3968    hexagon_A4_vcmpbeq_any(rss, rtt)
3969}
3970
3971/// `Pd4=vcmpb.eq(Rss32,#u8)`
3972///
3973/// Instruction Type: ALU64
3974/// Execution Slots: SLOT23
3975#[inline(always)]
3976#[rustc_legacy_const_generics(1)]
3977#[cfg_attr(test, assert_instr(vcmpb, IU8 = 0))]
3978#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3979pub unsafe fn Q6_p_vcmpb_eq_PI<const IU8: u32>(rss: i64) -> i32 {
3980    static_assert_uimm_bits!(IU8, 8);
3981    hexagon_A4_vcmpbeqi(rss, IU8 as i32)
3982}
3983
3984/// `Pd4=vcmpb.gt(Rss32,Rtt32)`
3985///
3986/// Instruction Type: ALU64
3987/// Execution Slots: SLOT23
3988#[inline(always)]
3989#[cfg_attr(test, assert_instr(vcmpb))]
3990#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3991pub unsafe fn Q6_p_vcmpb_gt_PP(rss: i64, rtt: i64) -> i32 {
3992    hexagon_A4_vcmpbgt(rss, rtt)
3993}
3994
3995/// `Pd4=vcmpb.gt(Rss32,#s8)`
3996///
3997/// Instruction Type: ALU64
3998/// Execution Slots: SLOT23
3999#[inline(always)]
4000#[rustc_legacy_const_generics(1)]
4001#[cfg_attr(test, assert_instr(vcmpb, IS8 = 0))]
4002#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4003pub unsafe fn Q6_p_vcmpb_gt_PI<const IS8: i32>(rss: i64) -> i32 {
4004    static_assert_simm_bits!(IS8, 8);
4005    hexagon_A4_vcmpbgti(rss, IS8)
4006}
4007
4008/// `Pd4=vcmpb.gtu(Rss32,#u7)`
4009///
4010/// Instruction Type: ALU64
4011/// Execution Slots: SLOT23
4012#[inline(always)]
4013#[rustc_legacy_const_generics(1)]
4014#[cfg_attr(test, assert_instr(vcmpb, IU7 = 0))]
4015#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4016pub unsafe fn Q6_p_vcmpb_gtu_PI<const IU7: u32>(rss: i64) -> i32 {
4017    static_assert_uimm_bits!(IU7, 7);
4018    hexagon_A4_vcmpbgtui(rss, IU7 as i32)
4019}
4020
4021/// `Pd4=vcmph.eq(Rss32,#s8)`
4022///
4023/// Instruction Type: ALU64
4024/// Execution Slots: SLOT23
4025#[inline(always)]
4026#[rustc_legacy_const_generics(1)]
4027#[cfg_attr(test, assert_instr(vcmph, IS8 = 0))]
4028#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4029pub unsafe fn Q6_p_vcmph_eq_PI<const IS8: i32>(rss: i64) -> i32 {
4030    static_assert_simm_bits!(IS8, 8);
4031    hexagon_A4_vcmpheqi(rss, IS8)
4032}
4033
4034/// `Pd4=vcmph.gt(Rss32,#s8)`
4035///
4036/// Instruction Type: ALU64
4037/// Execution Slots: SLOT23
4038#[inline(always)]
4039#[rustc_legacy_const_generics(1)]
4040#[cfg_attr(test, assert_instr(vcmph, IS8 = 0))]
4041#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4042pub unsafe fn Q6_p_vcmph_gt_PI<const IS8: i32>(rss: i64) -> i32 {
4043    static_assert_simm_bits!(IS8, 8);
4044    hexagon_A4_vcmphgti(rss, IS8)
4045}
4046
4047/// `Pd4=vcmph.gtu(Rss32,#u7)`
4048///
4049/// Instruction Type: ALU64
4050/// Execution Slots: SLOT23
4051#[inline(always)]
4052#[rustc_legacy_const_generics(1)]
4053#[cfg_attr(test, assert_instr(vcmph, IU7 = 0))]
4054#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4055pub unsafe fn Q6_p_vcmph_gtu_PI<const IU7: u32>(rss: i64) -> i32 {
4056    static_assert_uimm_bits!(IU7, 7);
4057    hexagon_A4_vcmphgtui(rss, IU7 as i32)
4058}
4059
4060/// `Pd4=vcmpw.eq(Rss32,#s8)`
4061///
4062/// Instruction Type: ALU64
4063/// Execution Slots: SLOT23
4064#[inline(always)]
4065#[rustc_legacy_const_generics(1)]
4066#[cfg_attr(test, assert_instr(vcmpw, IS8 = 0))]
4067#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4068pub unsafe fn Q6_p_vcmpw_eq_PI<const IS8: i32>(rss: i64) -> i32 {
4069    static_assert_simm_bits!(IS8, 8);
4070    hexagon_A4_vcmpweqi(rss, IS8)
4071}
4072
4073/// `Pd4=vcmpw.gt(Rss32,#s8)`
4074///
4075/// Instruction Type: ALU64
4076/// Execution Slots: SLOT23
4077#[inline(always)]
4078#[rustc_legacy_const_generics(1)]
4079#[cfg_attr(test, assert_instr(vcmpw, IS8 = 0))]
4080#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4081pub unsafe fn Q6_p_vcmpw_gt_PI<const IS8: i32>(rss: i64) -> i32 {
4082    static_assert_simm_bits!(IS8, 8);
4083    hexagon_A4_vcmpwgti(rss, IS8)
4084}
4085
4086/// `Pd4=vcmpw.gtu(Rss32,#u7)`
4087///
4088/// Instruction Type: ALU64
4089/// Execution Slots: SLOT23
4090#[inline(always)]
4091#[rustc_legacy_const_generics(1)]
4092#[cfg_attr(test, assert_instr(vcmpw, IU7 = 0))]
4093#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4094pub unsafe fn Q6_p_vcmpw_gtu_PI<const IU7: u32>(rss: i64) -> i32 {
4095    static_assert_uimm_bits!(IU7, 7);
4096    hexagon_A4_vcmpwgtui(rss, IU7 as i32)
4097}
4098
4099/// `Rxx32=vrmaxh(Rss32,Ru32)`
4100///
4101/// Instruction Type: S_3op
4102/// Execution Slots: SLOT23
4103#[inline(always)]
4104#[cfg_attr(test, assert_instr(vrmaxh))]
4105#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4106pub unsafe fn Q6_P_vrmaxh_PR(rxx: i64, rss: i64, ru: i32) -> i64 {
4107    hexagon_A4_vrmaxh(rxx, rss, ru)
4108}
4109
4110/// `Rxx32=vrmaxuh(Rss32,Ru32)`
4111///
4112/// Instruction Type: S_3op
4113/// Execution Slots: SLOT23
4114#[inline(always)]
4115#[cfg_attr(test, assert_instr(vrmaxuh))]
4116#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4117pub unsafe fn Q6_P_vrmaxuh_PR(rxx: i64, rss: i64, ru: i32) -> i64 {
4118    hexagon_A4_vrmaxuh(rxx, rss, ru)
4119}
4120
4121/// `Rxx32=vrmaxuw(Rss32,Ru32)`
4122///
4123/// Instruction Type: S_3op
4124/// Execution Slots: SLOT23
4125#[inline(always)]
4126#[cfg_attr(test, assert_instr(vrmaxuw))]
4127#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4128pub unsafe fn Q6_P_vrmaxuw_PR(rxx: i64, rss: i64, ru: i32) -> i64 {
4129    hexagon_A4_vrmaxuw(rxx, rss, ru)
4130}
4131
4132/// `Rxx32=vrmaxw(Rss32,Ru32)`
4133///
4134/// Instruction Type: S_3op
4135/// Execution Slots: SLOT23
4136#[inline(always)]
4137#[cfg_attr(test, assert_instr(vrmaxw))]
4138#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4139pub unsafe fn Q6_P_vrmaxw_PR(rxx: i64, rss: i64, ru: i32) -> i64 {
4140    hexagon_A4_vrmaxw(rxx, rss, ru)
4141}
4142
4143/// `Rxx32=vrminh(Rss32,Ru32)`
4144///
4145/// Instruction Type: S_3op
4146/// Execution Slots: SLOT23
4147#[inline(always)]
4148#[cfg_attr(test, assert_instr(vrminh))]
4149#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4150pub unsafe fn Q6_P_vrminh_PR(rxx: i64, rss: i64, ru: i32) -> i64 {
4151    hexagon_A4_vrminh(rxx, rss, ru)
4152}
4153
4154/// `Rxx32=vrminuh(Rss32,Ru32)`
4155///
4156/// Instruction Type: S_3op
4157/// Execution Slots: SLOT23
4158#[inline(always)]
4159#[cfg_attr(test, assert_instr(vrminuh))]
4160#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4161pub unsafe fn Q6_P_vrminuh_PR(rxx: i64, rss: i64, ru: i32) -> i64 {
4162    hexagon_A4_vrminuh(rxx, rss, ru)
4163}
4164
4165/// `Rxx32=vrminuw(Rss32,Ru32)`
4166///
4167/// Instruction Type: S_3op
4168/// Execution Slots: SLOT23
4169#[inline(always)]
4170#[cfg_attr(test, assert_instr(vrminuw))]
4171#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4172pub unsafe fn Q6_P_vrminuw_PR(rxx: i64, rss: i64, ru: i32) -> i64 {
4173    hexagon_A4_vrminuw(rxx, rss, ru)
4174}
4175
4176/// `Rxx32=vrminw(Rss32,Ru32)`
4177///
4178/// Instruction Type: S_3op
4179/// Execution Slots: SLOT23
4180#[inline(always)]
4181#[cfg_attr(test, assert_instr(vrminw))]
4182#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4183pub unsafe fn Q6_P_vrminw_PR(rxx: i64, rss: i64, ru: i32) -> i64 {
4184    hexagon_A4_vrminw(rxx, rss, ru)
4185}
4186
4187/// `Rd32=vaddhub(Rss32,Rtt32):sat`
4188///
4189/// Instruction Type: S_3op
4190/// Execution Slots: SLOT23
4191#[inline(always)]
4192#[cfg_attr(test, assert_instr(vaddhub))]
4193#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4194pub unsafe fn Q6_R_vaddhub_PP_sat(rss: i64, rtt: i64) -> i32 {
4195    hexagon_A5_vaddhubs(rss, rtt)
4196}
4197
4198/// `Pd4=all8(Ps4)`
4199///
4200/// Instruction Type: CR
4201/// Execution Slots: SLOT23
4202#[inline(always)]
4203#[cfg_attr(test, assert_instr(all8))]
4204#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4205pub unsafe fn Q6_p_all8_p(ps: i32) -> i32 {
4206    hexagon_C2_all8(ps)
4207}
4208
4209/// `Pd4=and(Pt4,Ps4)`
4210///
4211/// Instruction Type: CR
4212/// Execution Slots: SLOT23
4213#[inline(always)]
4214#[cfg_attr(test, assert_instr(and))]
4215#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4216pub unsafe fn Q6_p_and_pp(pt: i32, ps: i32) -> i32 {
4217    hexagon_C2_and(pt, ps)
4218}
4219
4220/// `Pd4=and(Pt4,!Ps4)`
4221///
4222/// Instruction Type: CR
4223/// Execution Slots: SLOT23
4224#[inline(always)]
4225#[cfg_attr(test, assert_instr(and))]
4226#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4227pub unsafe fn Q6_p_and_pnp(pt: i32, ps: i32) -> i32 {
4228    hexagon_C2_andn(pt, ps)
4229}
4230
4231/// `Pd4=any8(Ps4)`
4232///
4233/// Instruction Type: CR
4234/// Execution Slots: SLOT23
4235#[inline(always)]
4236#[cfg_attr(test, assert_instr(any8))]
4237#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4238pub unsafe fn Q6_p_any8_p(ps: i32) -> i32 {
4239    hexagon_C2_any8(ps)
4240}
4241
4242/// `Pd4=bitsclr(Rs32,Rt32)`
4243///
4244/// Instruction Type: S_3op
4245/// Execution Slots: SLOT23
4246#[inline(always)]
4247#[cfg_attr(test, assert_instr(bitsclr))]
4248#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4249pub unsafe fn Q6_p_bitsclr_RR(rs: i32, rt: i32) -> i32 {
4250    hexagon_C2_bitsclr(rs, rt)
4251}
4252
4253/// `Pd4=bitsclr(Rs32,#u6)`
4254///
4255/// Instruction Type: S_2op
4256/// Execution Slots: SLOT23
4257#[inline(always)]
4258#[rustc_legacy_const_generics(1)]
4259#[cfg_attr(test, assert_instr(bitsclr, IU6 = 0))]
4260#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4261pub unsafe fn Q6_p_bitsclr_RI<const IU6: u32>(rs: i32) -> i32 {
4262    static_assert_uimm_bits!(IU6, 6);
4263    hexagon_C2_bitsclri(rs, IU6 as i32)
4264}
4265
4266/// `Pd4=bitsset(Rs32,Rt32)`
4267///
4268/// Instruction Type: S_3op
4269/// Execution Slots: SLOT23
4270#[inline(always)]
4271#[cfg_attr(test, assert_instr(bitsset))]
4272#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4273pub unsafe fn Q6_p_bitsset_RR(rs: i32, rt: i32) -> i32 {
4274    hexagon_C2_bitsset(rs, rt)
4275}
4276
4277/// `Pd4=cmp.eq(Rs32,Rt32)`
4278///
4279/// Instruction Type: ALU32_3op
4280/// Execution Slots: SLOT0123
4281#[inline(always)]
4282#[cfg_attr(test, assert_instr(cmp))]
4283#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4284pub unsafe fn Q6_p_cmp_eq_RR(rs: i32, rt: i32) -> i32 {
4285    hexagon_C2_cmpeq(rs, rt)
4286}
4287
4288/// `Pd4=cmp.eq(Rs32,#s10)`
4289///
4290/// Instruction Type: ALU32_2op
4291/// Execution Slots: SLOT0123
4292#[inline(always)]
4293#[rustc_legacy_const_generics(1)]
4294#[cfg_attr(test, assert_instr(cmp, IS10 = 0))]
4295#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4296pub unsafe fn Q6_p_cmp_eq_RI<const IS10: i32>(rs: i32) -> i32 {
4297    static_assert_simm_bits!(IS10, 10);
4298    hexagon_C2_cmpeqi(rs, IS10)
4299}
4300
4301/// `Pd4=cmp.eq(Rss32,Rtt32)`
4302///
4303/// Instruction Type: ALU64
4304/// Execution Slots: SLOT23
4305#[inline(always)]
4306#[cfg_attr(test, assert_instr(cmp))]
4307#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4308pub unsafe fn Q6_p_cmp_eq_PP(rss: i64, rtt: i64) -> i32 {
4309    hexagon_C2_cmpeqp(rss, rtt)
4310}
4311
4312/// `Pd4=cmp.ge(Rs32,#s8)`
4313///
4314/// Instruction Type: ALU32_2op
4315/// Execution Slots: SLOT0123
4316#[inline(always)]
4317#[rustc_legacy_const_generics(1)]
4318#[cfg_attr(test, assert_instr(cmp, IS8 = 0))]
4319#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4320pub unsafe fn Q6_p_cmp_ge_RI<const IS8: i32>(rs: i32) -> i32 {
4321    static_assert_simm_bits!(IS8, 8);
4322    hexagon_C2_cmpgei(rs, IS8)
4323}
4324
4325/// `Pd4=cmp.geu(Rs32,#u8)`
4326///
4327/// Instruction Type: ALU32_2op
4328/// Execution Slots: SLOT0123
4329#[inline(always)]
4330#[rustc_legacy_const_generics(1)]
4331#[cfg_attr(test, assert_instr(cmp, IU8 = 0))]
4332#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4333pub unsafe fn Q6_p_cmp_geu_RI<const IU8: u32>(rs: i32) -> i32 {
4334    static_assert_uimm_bits!(IU8, 8);
4335    hexagon_C2_cmpgeui(rs, IU8 as i32)
4336}
4337
4338/// `Pd4=cmp.gt(Rs32,Rt32)`
4339///
4340/// Instruction Type: ALU32_3op
4341/// Execution Slots: SLOT0123
4342#[inline(always)]
4343#[cfg_attr(test, assert_instr(cmp))]
4344#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4345pub unsafe fn Q6_p_cmp_gt_RR(rs: i32, rt: i32) -> i32 {
4346    hexagon_C2_cmpgt(rs, rt)
4347}
4348
4349/// `Pd4=cmp.gt(Rs32,#s10)`
4350///
4351/// Instruction Type: ALU32_2op
4352/// Execution Slots: SLOT0123
4353#[inline(always)]
4354#[rustc_legacy_const_generics(1)]
4355#[cfg_attr(test, assert_instr(cmp, IS10 = 0))]
4356#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4357pub unsafe fn Q6_p_cmp_gt_RI<const IS10: i32>(rs: i32) -> i32 {
4358    static_assert_simm_bits!(IS10, 10);
4359    hexagon_C2_cmpgti(rs, IS10)
4360}
4361
4362/// `Pd4=cmp.gt(Rss32,Rtt32)`
4363///
4364/// Instruction Type: ALU64
4365/// Execution Slots: SLOT23
4366#[inline(always)]
4367#[cfg_attr(test, assert_instr(cmp))]
4368#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4369pub unsafe fn Q6_p_cmp_gt_PP(rss: i64, rtt: i64) -> i32 {
4370    hexagon_C2_cmpgtp(rss, rtt)
4371}
4372
4373/// `Pd4=cmp.gtu(Rs32,Rt32)`
4374///
4375/// Instruction Type: ALU32_3op
4376/// Execution Slots: SLOT0123
4377#[inline(always)]
4378#[cfg_attr(test, assert_instr(cmp))]
4379#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4380pub unsafe fn Q6_p_cmp_gtu_RR(rs: i32, rt: i32) -> i32 {
4381    hexagon_C2_cmpgtu(rs, rt)
4382}
4383
4384/// `Pd4=cmp.gtu(Rs32,#u9)`
4385///
4386/// Instruction Type: ALU32_2op
4387/// Execution Slots: SLOT0123
4388#[inline(always)]
4389#[rustc_legacy_const_generics(1)]
4390#[cfg_attr(test, assert_instr(cmp, IU9 = 0))]
4391#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4392pub unsafe fn Q6_p_cmp_gtu_RI<const IU9: u32>(rs: i32) -> i32 {
4393    static_assert_uimm_bits!(IU9, 9);
4394    hexagon_C2_cmpgtui(rs, IU9 as i32)
4395}
4396
4397/// `Pd4=cmp.gtu(Rss32,Rtt32)`
4398///
4399/// Instruction Type: ALU64
4400/// Execution Slots: SLOT23
4401#[inline(always)]
4402#[cfg_attr(test, assert_instr(cmp))]
4403#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4404pub unsafe fn Q6_p_cmp_gtu_PP(rss: i64, rtt: i64) -> i32 {
4405    hexagon_C2_cmpgtup(rss, rtt)
4406}
4407
4408/// `Pd4=cmp.lt(Rs32,Rt32)`
4409///
4410/// Instruction Type: ALU32_3op
4411/// Execution Slots: SLOT0123
4412#[inline(always)]
4413#[cfg_attr(test, assert_instr(cmp))]
4414#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4415pub unsafe fn Q6_p_cmp_lt_RR(rs: i32, rt: i32) -> i32 {
4416    hexagon_C2_cmplt(rs, rt)
4417}
4418
4419/// `Pd4=cmp.ltu(Rs32,Rt32)`
4420///
4421/// Instruction Type: ALU32_3op
4422/// Execution Slots: SLOT0123
4423#[inline(always)]
4424#[cfg_attr(test, assert_instr(cmp))]
4425#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4426pub unsafe fn Q6_p_cmp_ltu_RR(rs: i32, rt: i32) -> i32 {
4427    hexagon_C2_cmpltu(rs, rt)
4428}
4429
4430/// `Rdd32=mask(Pt4)`
4431///
4432/// Instruction Type: S_2op
4433/// Execution Slots: SLOT23
4434#[inline(always)]
4435#[cfg_attr(test, assert_instr(mask))]
4436#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4437pub unsafe fn Q6_P_mask_p(pt: i32) -> i64 {
4438    hexagon_C2_mask(pt)
4439}
4440
4441/// `Rd32=mux(Pu4,Rs32,Rt32)`
4442///
4443/// Instruction Type: ALU32_3op
4444/// Execution Slots: SLOT0123
4445#[inline(always)]
4446#[cfg_attr(test, assert_instr(mux))]
4447#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4448pub unsafe fn Q6_R_mux_pRR(pu: i32, rs: i32, rt: i32) -> i32 {
4449    hexagon_C2_mux(pu, rs, rt)
4450}
4451
4452/// `Rd32=mux(Pu4,#s8,#S8)`
4453///
4454/// Instruction Type: ALU32_2op
4455/// Execution Slots: SLOT0123
4456#[inline(always)]
4457#[rustc_legacy_const_generics(1, 2)]
4458#[cfg_attr(test, assert_instr(mux, IS8 = 0, IS8_2 = 0))]
4459#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4460pub unsafe fn Q6_R_mux_pII<const IS8: i32, const IS8_2: i32>(pu: i32) -> i32 {
4461    static_assert_simm_bits!(IS8, 8);
4462    static_assert_simm_bits!(IS8_2, 8);
4463    hexagon_C2_muxii(pu, IS8, IS8_2)
4464}
4465
4466/// `Rd32=mux(Pu4,Rs32,#s8)`
4467///
4468/// Instruction Type: ALU32_2op
4469/// Execution Slots: SLOT0123
4470#[inline(always)]
4471#[rustc_legacy_const_generics(2)]
4472#[cfg_attr(test, assert_instr(mux, IS8 = 0))]
4473#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4474pub unsafe fn Q6_R_mux_pRI<const IS8: i32>(pu: i32, rs: i32) -> i32 {
4475    static_assert_simm_bits!(IS8, 8);
4476    hexagon_C2_muxir(pu, rs, IS8)
4477}
4478
4479/// `Rd32=mux(Pu4,#s8,Rs32)`
4480///
4481/// Instruction Type: ALU32_2op
4482/// Execution Slots: SLOT0123
4483#[inline(always)]
4484#[rustc_legacy_const_generics(1)]
4485#[cfg_attr(test, assert_instr(mux, IS8 = 0))]
4486#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4487pub unsafe fn Q6_R_mux_pIR<const IS8: i32>(pu: i32, rs: i32) -> i32 {
4488    static_assert_simm_bits!(IS8, 8);
4489    hexagon_C2_muxri(pu, IS8, rs)
4490}
4491
4492/// `Pd4=not(Ps4)`
4493///
4494/// Instruction Type: CR
4495/// Execution Slots: SLOT23
4496#[inline(always)]
4497#[cfg_attr(test, assert_instr(not))]
4498#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4499pub unsafe fn Q6_p_not_p(ps: i32) -> i32 {
4500    hexagon_C2_not(ps)
4501}
4502
4503/// `Pd4=or(Pt4,Ps4)`
4504///
4505/// Instruction Type: CR
4506/// Execution Slots: SLOT23
4507#[inline(always)]
4508#[cfg_attr(test, assert_instr(or))]
4509#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4510pub unsafe fn Q6_p_or_pp(pt: i32, ps: i32) -> i32 {
4511    hexagon_C2_or(pt, ps)
4512}
4513
4514/// `Pd4=or(Pt4,!Ps4)`
4515///
4516/// Instruction Type: CR
4517/// Execution Slots: SLOT23
4518#[inline(always)]
4519#[cfg_attr(test, assert_instr(or))]
4520#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4521pub unsafe fn Q6_p_or_pnp(pt: i32, ps: i32) -> i32 {
4522    hexagon_C2_orn(pt, ps)
4523}
4524
4525/// `Pd4=Ps4`
4526///
4527/// Instruction Type: MAPPING
4528/// Execution Slots: SLOT0123
4529#[inline(always)]
4530#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4531pub unsafe fn Q6_p_equals_p(ps: i32) -> i32 {
4532    hexagon_C2_pxfer_map(ps)
4533}
4534
4535/// `Rd32=Ps4`
4536///
4537/// Instruction Type: S_2op
4538/// Execution Slots: SLOT23
4539#[inline(always)]
4540#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4541pub unsafe fn Q6_R_equals_p(ps: i32) -> i32 {
4542    hexagon_C2_tfrpr(ps)
4543}
4544
4545/// `Pd4=Rs32`
4546///
4547/// Instruction Type: S_2op
4548/// Execution Slots: SLOT23
4549#[inline(always)]
4550#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4551pub unsafe fn Q6_p_equals_R(rs: i32) -> i32 {
4552    hexagon_C2_tfrrp(rs)
4553}
4554
4555/// `Rd32=vitpack(Ps4,Pt4)`
4556///
4557/// Instruction Type: S_2op
4558/// Execution Slots: SLOT23
4559#[inline(always)]
4560#[cfg_attr(test, assert_instr(vitpack))]
4561#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4562pub unsafe fn Q6_R_vitpack_pp(ps: i32, pt: i32) -> i32 {
4563    hexagon_C2_vitpack(ps, pt)
4564}
4565
4566/// `Rdd32=vmux(Pu4,Rss32,Rtt32)`
4567///
4568/// Instruction Type: ALU64
4569/// Execution Slots: SLOT23
4570#[inline(always)]
4571#[cfg_attr(test, assert_instr(vmux))]
4572#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4573pub unsafe fn Q6_P_vmux_pPP(pu: i32, rss: i64, rtt: i64) -> i64 {
4574    hexagon_C2_vmux(pu, rss, rtt)
4575}
4576
4577/// `Pd4=xor(Ps4,Pt4)`
4578///
4579/// Instruction Type: CR
4580/// Execution Slots: SLOT23
4581#[inline(always)]
4582#[cfg_attr(test, assert_instr(xor))]
4583#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4584pub unsafe fn Q6_p_xor_pp(ps: i32, pt: i32) -> i32 {
4585    hexagon_C2_xor(ps, pt)
4586}
4587
4588/// `Pd4=and(Ps4,and(Pt4,Pu4))`
4589///
4590/// Instruction Type: CR
4591/// Execution Slots: SLOT23
4592#[inline(always)]
4593#[cfg_attr(test, assert_instr(and))]
4594#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4595pub unsafe fn Q6_p_and_and_ppp(ps: i32, pt: i32, pu: i32) -> i32 {
4596    hexagon_C4_and_and(ps, pt, pu)
4597}
4598
4599/// `Pd4=and(Ps4,and(Pt4,!Pu4))`
4600///
4601/// Instruction Type: CR
4602/// Execution Slots: SLOT23
4603#[inline(always)]
4604#[cfg_attr(test, assert_instr(and))]
4605#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4606pub unsafe fn Q6_p_and_and_ppnp(ps: i32, pt: i32, pu: i32) -> i32 {
4607    hexagon_C4_and_andn(ps, pt, pu)
4608}
4609
4610/// `Pd4=and(Ps4,or(Pt4,Pu4))`
4611///
4612/// Instruction Type: CR
4613/// Execution Slots: SLOT23
4614#[inline(always)]
4615#[cfg_attr(test, assert_instr(and))]
4616#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4617pub unsafe fn Q6_p_and_or_ppp(ps: i32, pt: i32, pu: i32) -> i32 {
4618    hexagon_C4_and_or(ps, pt, pu)
4619}
4620
4621/// `Pd4=and(Ps4,or(Pt4,!Pu4))`
4622///
4623/// Instruction Type: CR
4624/// Execution Slots: SLOT23
4625#[inline(always)]
4626#[cfg_attr(test, assert_instr(and))]
4627#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4628pub unsafe fn Q6_p_and_or_ppnp(ps: i32, pt: i32, pu: i32) -> i32 {
4629    hexagon_C4_and_orn(ps, pt, pu)
4630}
4631
4632/// `Pd4=!cmp.gt(Rs32,Rt32)`
4633///
4634/// Instruction Type: ALU32_3op
4635/// Execution Slots: SLOT0123
4636#[inline(always)]
4637#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4638pub unsafe fn Q6_p_not_cmp_gt_RR(rs: i32, rt: i32) -> i32 {
4639    hexagon_C4_cmplte(rs, rt)
4640}
4641
4642/// `Pd4=!cmp.gt(Rs32,#s10)`
4643///
4644/// Instruction Type: ALU32_2op
4645/// Execution Slots: SLOT0123
4646#[inline(always)]
4647#[rustc_legacy_const_generics(1)]
4648#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4649pub unsafe fn Q6_p_not_cmp_gt_RI<const IS10: i32>(rs: i32) -> i32 {
4650    static_assert_simm_bits!(IS10, 10);
4651    hexagon_C4_cmpltei(rs, IS10)
4652}
4653
4654/// `Pd4=!cmp.gtu(Rs32,Rt32)`
4655///
4656/// Instruction Type: ALU32_3op
4657/// Execution Slots: SLOT0123
4658#[inline(always)]
4659#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4660pub unsafe fn Q6_p_not_cmp_gtu_RR(rs: i32, rt: i32) -> i32 {
4661    hexagon_C4_cmplteu(rs, rt)
4662}
4663
4664/// `Pd4=!cmp.gtu(Rs32,#u9)`
4665///
4666/// Instruction Type: ALU32_2op
4667/// Execution Slots: SLOT0123
4668#[inline(always)]
4669#[rustc_legacy_const_generics(1)]
4670#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4671pub unsafe fn Q6_p_not_cmp_gtu_RI<const IU9: u32>(rs: i32) -> i32 {
4672    static_assert_uimm_bits!(IU9, 9);
4673    hexagon_C4_cmplteui(rs, IU9 as i32)
4674}
4675
4676/// `Pd4=!cmp.eq(Rs32,Rt32)`
4677///
4678/// Instruction Type: ALU32_3op
4679/// Execution Slots: SLOT0123
4680#[inline(always)]
4681#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4682pub unsafe fn Q6_p_not_cmp_eq_RR(rs: i32, rt: i32) -> i32 {
4683    hexagon_C4_cmpneq(rs, rt)
4684}
4685
4686/// `Pd4=!cmp.eq(Rs32,#s10)`
4687///
4688/// Instruction Type: ALU32_2op
4689/// Execution Slots: SLOT0123
4690#[inline(always)]
4691#[rustc_legacy_const_generics(1)]
4692#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4693pub unsafe fn Q6_p_not_cmp_eq_RI<const IS10: i32>(rs: i32) -> i32 {
4694    static_assert_simm_bits!(IS10, 10);
4695    hexagon_C4_cmpneqi(rs, IS10)
4696}
4697
4698/// `Pd4=fastcorner9(Ps4,Pt4)`
4699///
4700/// Instruction Type: CR
4701/// Execution Slots: SLOT23
4702#[inline(always)]
4703#[cfg_attr(test, assert_instr(fastcorner9))]
4704#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4705pub unsafe fn Q6_p_fastcorner9_pp(ps: i32, pt: i32) -> i32 {
4706    hexagon_C4_fastcorner9(ps, pt)
4707}
4708
4709/// `Pd4=!fastcorner9(Ps4,Pt4)`
4710///
4711/// Instruction Type: CR
4712/// Execution Slots: SLOT23
4713#[inline(always)]
4714#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4715pub unsafe fn Q6_p_not_fastcorner9_pp(ps: i32, pt: i32) -> i32 {
4716    hexagon_C4_fastcorner9_not(ps, pt)
4717}
4718
4719/// `Pd4=!bitsclr(Rs32,Rt32)`
4720///
4721/// Instruction Type: S_3op
4722/// Execution Slots: SLOT23
4723#[inline(always)]
4724#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4725pub unsafe fn Q6_p_not_bitsclr_RR(rs: i32, rt: i32) -> i32 {
4726    hexagon_C4_nbitsclr(rs, rt)
4727}
4728
4729/// `Pd4=!bitsclr(Rs32,#u6)`
4730///
4731/// Instruction Type: S_2op
4732/// Execution Slots: SLOT23
4733#[inline(always)]
4734#[rustc_legacy_const_generics(1)]
4735#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4736pub unsafe fn Q6_p_not_bitsclr_RI<const IU6: u32>(rs: i32) -> i32 {
4737    static_assert_uimm_bits!(IU6, 6);
4738    hexagon_C4_nbitsclri(rs, IU6 as i32)
4739}
4740
4741/// `Pd4=!bitsset(Rs32,Rt32)`
4742///
4743/// Instruction Type: S_3op
4744/// Execution Slots: SLOT23
4745#[inline(always)]
4746#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4747pub unsafe fn Q6_p_not_bitsset_RR(rs: i32, rt: i32) -> i32 {
4748    hexagon_C4_nbitsset(rs, rt)
4749}
4750
4751/// `Pd4=or(Ps4,and(Pt4,Pu4))`
4752///
4753/// Instruction Type: CR
4754/// Execution Slots: SLOT23
4755#[inline(always)]
4756#[cfg_attr(test, assert_instr(or))]
4757#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4758pub unsafe fn Q6_p_or_and_ppp(ps: i32, pt: i32, pu: i32) -> i32 {
4759    hexagon_C4_or_and(ps, pt, pu)
4760}
4761
4762/// `Pd4=or(Ps4,and(Pt4,!Pu4))`
4763///
4764/// Instruction Type: CR
4765/// Execution Slots: SLOT23
4766#[inline(always)]
4767#[cfg_attr(test, assert_instr(or))]
4768#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4769pub unsafe fn Q6_p_or_and_ppnp(ps: i32, pt: i32, pu: i32) -> i32 {
4770    hexagon_C4_or_andn(ps, pt, pu)
4771}
4772
4773/// `Pd4=or(Ps4,or(Pt4,Pu4))`
4774///
4775/// Instruction Type: CR
4776/// Execution Slots: SLOT23
4777#[inline(always)]
4778#[cfg_attr(test, assert_instr(or))]
4779#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4780pub unsafe fn Q6_p_or_or_ppp(ps: i32, pt: i32, pu: i32) -> i32 {
4781    hexagon_C4_or_or(ps, pt, pu)
4782}
4783
4784/// `Pd4=or(Ps4,or(Pt4,!Pu4))`
4785///
4786/// Instruction Type: CR
4787/// Execution Slots: SLOT23
4788#[inline(always)]
4789#[cfg_attr(test, assert_instr(or))]
4790#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4791pub unsafe fn Q6_p_or_or_ppnp(ps: i32, pt: i32, pu: i32) -> i32 {
4792    hexagon_C4_or_orn(ps, pt, pu)
4793}
4794
4795/// `Rdd32=convert_d2df(Rss32)`
4796///
4797/// Instruction Type: S_2op
4798/// Execution Slots: SLOT23
4799#[inline(always)]
4800#[cfg_attr(test, assert_instr(convert_d2df))]
4801#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4802pub unsafe fn Q6_P_convert_d2df_P(rss: i64) -> f64 {
4803    hexagon_F2_conv_d2df(rss)
4804}
4805
4806/// `Rd32=convert_d2sf(Rss32)`
4807///
4808/// Instruction Type: S_2op
4809/// Execution Slots: SLOT23
4810#[inline(always)]
4811#[cfg_attr(test, assert_instr(convert_d2sf))]
4812#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4813pub unsafe fn Q6_R_convert_d2sf_P(rss: i64) -> f32 {
4814    hexagon_F2_conv_d2sf(rss)
4815}
4816
4817/// `Rdd32=convert_df2d(Rss32)`
4818///
4819/// Instruction Type: S_2op
4820/// Execution Slots: SLOT23
4821#[inline(always)]
4822#[cfg_attr(test, assert_instr(convert_df2d))]
4823#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4824pub unsafe fn Q6_P_convert_df2d_P(rss: f64) -> i64 {
4825    hexagon_F2_conv_df2d(rss)
4826}
4827
4828/// `Rdd32=convert_df2d(Rss32):chop`
4829///
4830/// Instruction Type: S_2op
4831/// Execution Slots: SLOT23
4832#[inline(always)]
4833#[cfg_attr(test, assert_instr(convert_df2d))]
4834#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4835pub unsafe fn Q6_P_convert_df2d_P_chop(rss: f64) -> i64 {
4836    hexagon_F2_conv_df2d_chop(rss)
4837}
4838
4839/// `Rd32=convert_df2sf(Rss32)`
4840///
4841/// Instruction Type: S_2op
4842/// Execution Slots: SLOT23
4843#[inline(always)]
4844#[cfg_attr(test, assert_instr(convert_df2sf))]
4845#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4846pub unsafe fn Q6_R_convert_df2sf_P(rss: f64) -> f32 {
4847    hexagon_F2_conv_df2sf(rss)
4848}
4849
4850/// `Rdd32=convert_df2ud(Rss32)`
4851///
4852/// Instruction Type: S_2op
4853/// Execution Slots: SLOT23
4854#[inline(always)]
4855#[cfg_attr(test, assert_instr(convert_df2ud))]
4856#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4857pub unsafe fn Q6_P_convert_df2ud_P(rss: f64) -> i64 {
4858    hexagon_F2_conv_df2ud(rss)
4859}
4860
4861/// `Rdd32=convert_df2ud(Rss32):chop`
4862///
4863/// Instruction Type: S_2op
4864/// Execution Slots: SLOT23
4865#[inline(always)]
4866#[cfg_attr(test, assert_instr(convert_df2ud))]
4867#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4868pub unsafe fn Q6_P_convert_df2ud_P_chop(rss: f64) -> i64 {
4869    hexagon_F2_conv_df2ud_chop(rss)
4870}
4871
4872/// `Rd32=convert_df2uw(Rss32)`
4873///
4874/// Instruction Type: S_2op
4875/// Execution Slots: SLOT23
4876#[inline(always)]
4877#[cfg_attr(test, assert_instr(convert_df2uw))]
4878#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4879pub unsafe fn Q6_R_convert_df2uw_P(rss: f64) -> i32 {
4880    hexagon_F2_conv_df2uw(rss)
4881}
4882
4883/// `Rd32=convert_df2uw(Rss32):chop`
4884///
4885/// Instruction Type: S_2op
4886/// Execution Slots: SLOT23
4887#[inline(always)]
4888#[cfg_attr(test, assert_instr(convert_df2uw))]
4889#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4890pub unsafe fn Q6_R_convert_df2uw_P_chop(rss: f64) -> i32 {
4891    hexagon_F2_conv_df2uw_chop(rss)
4892}
4893
4894/// `Rd32=convert_df2w(Rss32)`
4895///
4896/// Instruction Type: S_2op
4897/// Execution Slots: SLOT23
4898#[inline(always)]
4899#[cfg_attr(test, assert_instr(convert_df2w))]
4900#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4901pub unsafe fn Q6_R_convert_df2w_P(rss: f64) -> i32 {
4902    hexagon_F2_conv_df2w(rss)
4903}
4904
4905/// `Rd32=convert_df2w(Rss32):chop`
4906///
4907/// Instruction Type: S_2op
4908/// Execution Slots: SLOT23
4909#[inline(always)]
4910#[cfg_attr(test, assert_instr(convert_df2w))]
4911#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4912pub unsafe fn Q6_R_convert_df2w_P_chop(rss: f64) -> i32 {
4913    hexagon_F2_conv_df2w_chop(rss)
4914}
4915
4916/// `Rdd32=convert_sf2d(Rs32)`
4917///
4918/// Instruction Type: S_2op
4919/// Execution Slots: SLOT23
4920#[inline(always)]
4921#[cfg_attr(test, assert_instr(convert_sf2d))]
4922#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4923pub unsafe fn Q6_P_convert_sf2d_R(rs: f32) -> i64 {
4924    hexagon_F2_conv_sf2d(rs)
4925}
4926
4927/// `Rdd32=convert_sf2d(Rs32):chop`
4928///
4929/// Instruction Type: S_2op
4930/// Execution Slots: SLOT23
4931#[inline(always)]
4932#[cfg_attr(test, assert_instr(convert_sf2d))]
4933#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4934pub unsafe fn Q6_P_convert_sf2d_R_chop(rs: f32) -> i64 {
4935    hexagon_F2_conv_sf2d_chop(rs)
4936}
4937
4938/// `Rdd32=convert_sf2df(Rs32)`
4939///
4940/// Instruction Type: S_2op
4941/// Execution Slots: SLOT23
4942#[inline(always)]
4943#[cfg_attr(test, assert_instr(convert_sf2df))]
4944#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4945pub unsafe fn Q6_P_convert_sf2df_R(rs: f32) -> f64 {
4946    hexagon_F2_conv_sf2df(rs)
4947}
4948
4949/// `Rdd32=convert_sf2ud(Rs32)`
4950///
4951/// Instruction Type: S_2op
4952/// Execution Slots: SLOT23
4953#[inline(always)]
4954#[cfg_attr(test, assert_instr(convert_sf2ud))]
4955#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4956pub unsafe fn Q6_P_convert_sf2ud_R(rs: f32) -> i64 {
4957    hexagon_F2_conv_sf2ud(rs)
4958}
4959
4960/// `Rdd32=convert_sf2ud(Rs32):chop`
4961///
4962/// Instruction Type: S_2op
4963/// Execution Slots: SLOT23
4964#[inline(always)]
4965#[cfg_attr(test, assert_instr(convert_sf2ud))]
4966#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4967pub unsafe fn Q6_P_convert_sf2ud_R_chop(rs: f32) -> i64 {
4968    hexagon_F2_conv_sf2ud_chop(rs)
4969}
4970
4971/// `Rd32=convert_sf2uw(Rs32)`
4972///
4973/// Instruction Type: S_2op
4974/// Execution Slots: SLOT23
4975#[inline(always)]
4976#[cfg_attr(test, assert_instr(convert_sf2uw))]
4977#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4978pub unsafe fn Q6_R_convert_sf2uw_R(rs: f32) -> i32 {
4979    hexagon_F2_conv_sf2uw(rs)
4980}
4981
4982/// `Rd32=convert_sf2uw(Rs32):chop`
4983///
4984/// Instruction Type: S_2op
4985/// Execution Slots: SLOT23
4986#[inline(always)]
4987#[cfg_attr(test, assert_instr(convert_sf2uw))]
4988#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4989pub unsafe fn Q6_R_convert_sf2uw_R_chop(rs: f32) -> i32 {
4990    hexagon_F2_conv_sf2uw_chop(rs)
4991}
4992
4993/// `Rd32=convert_sf2w(Rs32)`
4994///
4995/// Instruction Type: S_2op
4996/// Execution Slots: SLOT23
4997#[inline(always)]
4998#[cfg_attr(test, assert_instr(convert_sf2w))]
4999#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5000pub unsafe fn Q6_R_convert_sf2w_R(rs: f32) -> i32 {
5001    hexagon_F2_conv_sf2w(rs)
5002}
5003
5004/// `Rd32=convert_sf2w(Rs32):chop`
5005///
5006/// Instruction Type: S_2op
5007/// Execution Slots: SLOT23
5008#[inline(always)]
5009#[cfg_attr(test, assert_instr(convert_sf2w))]
5010#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5011pub unsafe fn Q6_R_convert_sf2w_R_chop(rs: f32) -> i32 {
5012    hexagon_F2_conv_sf2w_chop(rs)
5013}
5014
5015/// `Rdd32=convert_ud2df(Rss32)`
5016///
5017/// Instruction Type: S_2op
5018/// Execution Slots: SLOT23
5019#[inline(always)]
5020#[cfg_attr(test, assert_instr(convert_ud2df))]
5021#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5022pub unsafe fn Q6_P_convert_ud2df_P(rss: i64) -> f64 {
5023    hexagon_F2_conv_ud2df(rss)
5024}
5025
5026/// `Rd32=convert_ud2sf(Rss32)`
5027///
5028/// Instruction Type: S_2op
5029/// Execution Slots: SLOT23
5030#[inline(always)]
5031#[cfg_attr(test, assert_instr(convert_ud2sf))]
5032#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5033pub unsafe fn Q6_R_convert_ud2sf_P(rss: i64) -> f32 {
5034    hexagon_F2_conv_ud2sf(rss)
5035}
5036
5037/// `Rdd32=convert_uw2df(Rs32)`
5038///
5039/// Instruction Type: S_2op
5040/// Execution Slots: SLOT23
5041#[inline(always)]
5042#[cfg_attr(test, assert_instr(convert_uw2df))]
5043#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5044pub unsafe fn Q6_P_convert_uw2df_R(rs: i32) -> f64 {
5045    hexagon_F2_conv_uw2df(rs)
5046}
5047
5048/// `Rd32=convert_uw2sf(Rs32)`
5049///
5050/// Instruction Type: S_2op
5051/// Execution Slots: SLOT23
5052#[inline(always)]
5053#[cfg_attr(test, assert_instr(convert_uw2sf))]
5054#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5055pub unsafe fn Q6_R_convert_uw2sf_R(rs: i32) -> f32 {
5056    hexagon_F2_conv_uw2sf(rs)
5057}
5058
5059/// `Rdd32=convert_w2df(Rs32)`
5060///
5061/// Instruction Type: S_2op
5062/// Execution Slots: SLOT23
5063#[inline(always)]
5064#[cfg_attr(test, assert_instr(convert_w2df))]
5065#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5066pub unsafe fn Q6_P_convert_w2df_R(rs: i32) -> f64 {
5067    hexagon_F2_conv_w2df(rs)
5068}
5069
5070/// `Rd32=convert_w2sf(Rs32)`
5071///
5072/// Instruction Type: S_2op
5073/// Execution Slots: SLOT23
5074#[inline(always)]
5075#[cfg_attr(test, assert_instr(convert_w2sf))]
5076#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5077pub unsafe fn Q6_R_convert_w2sf_R(rs: i32) -> f32 {
5078    hexagon_F2_conv_w2sf(rs)
5079}
5080
5081/// `Pd4=dfclass(Rss32,#u5)`
5082///
5083/// Instruction Type: ALU64
5084/// Execution Slots: SLOT23
5085#[inline(always)]
5086#[rustc_legacy_const_generics(1)]
5087#[cfg_attr(test, assert_instr(dfclass, IU5 = 0))]
5088#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5089pub unsafe fn Q6_p_dfclass_PI<const IU5: u32>(rss: f64) -> i32 {
5090    static_assert_uimm_bits!(IU5, 5);
5091    hexagon_F2_dfclass(rss, IU5 as i32)
5092}
5093
5094/// `Pd4=dfcmp.eq(Rss32,Rtt32)`
5095///
5096/// Instruction Type: ALU64
5097/// Execution Slots: SLOT23
5098#[inline(always)]
5099#[cfg_attr(test, assert_instr(dfcmp))]
5100#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5101pub unsafe fn Q6_p_dfcmp_eq_PP(rss: f64, rtt: f64) -> i32 {
5102    hexagon_F2_dfcmpeq(rss, rtt)
5103}
5104
5105/// `Pd4=dfcmp.ge(Rss32,Rtt32)`
5106///
5107/// Instruction Type: ALU64
5108/// Execution Slots: SLOT23
5109#[inline(always)]
5110#[cfg_attr(test, assert_instr(dfcmp))]
5111#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5112pub unsafe fn Q6_p_dfcmp_ge_PP(rss: f64, rtt: f64) -> i32 {
5113    hexagon_F2_dfcmpge(rss, rtt)
5114}
5115
5116/// `Pd4=dfcmp.gt(Rss32,Rtt32)`
5117///
5118/// Instruction Type: ALU64
5119/// Execution Slots: SLOT23
5120#[inline(always)]
5121#[cfg_attr(test, assert_instr(dfcmp))]
5122#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5123pub unsafe fn Q6_p_dfcmp_gt_PP(rss: f64, rtt: f64) -> i32 {
5124    hexagon_F2_dfcmpgt(rss, rtt)
5125}
5126
5127/// `Pd4=dfcmp.uo(Rss32,Rtt32)`
5128///
5129/// Instruction Type: ALU64
5130/// Execution Slots: SLOT23
5131#[inline(always)]
5132#[cfg_attr(test, assert_instr(dfcmp))]
5133#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5134pub unsafe fn Q6_p_dfcmp_uo_PP(rss: f64, rtt: f64) -> i32 {
5135    hexagon_F2_dfcmpuo(rss, rtt)
5136}
5137
5138/// `Rdd32=dfmake(#u10):neg`
5139///
5140/// Instruction Type: ALU64
5141/// Execution Slots: SLOT23
5142#[inline(always)]
5143#[rustc_legacy_const_generics(0)]
5144#[cfg_attr(test, assert_instr(dfmake, IU10 = 0))]
5145#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5146pub unsafe fn Q6_P_dfmake_I_neg<const IU10: u32>() -> f64 {
5147    static_assert_uimm_bits!(IU10, 10);
5148    hexagon_F2_dfimm_n(IU10 as i32)
5149}
5150
5151/// `Rdd32=dfmake(#u10):pos`
5152///
5153/// Instruction Type: ALU64
5154/// Execution Slots: SLOT23
5155#[inline(always)]
5156#[rustc_legacy_const_generics(0)]
5157#[cfg_attr(test, assert_instr(dfmake, IU10 = 0))]
5158#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5159pub unsafe fn Q6_P_dfmake_I_pos<const IU10: u32>() -> f64 {
5160    static_assert_uimm_bits!(IU10, 10);
5161    hexagon_F2_dfimm_p(IU10 as i32)
5162}
5163
5164/// `Rd32=sfadd(Rs32,Rt32)`
5165///
5166/// Instruction Type: M
5167/// Execution Slots: SLOT23
5168#[inline(always)]
5169#[cfg_attr(test, assert_instr(sfadd))]
5170#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5171pub unsafe fn Q6_R_sfadd_RR(rs: f32, rt: f32) -> f32 {
5172    hexagon_F2_sfadd(rs, rt)
5173}
5174
5175/// `Pd4=sfclass(Rs32,#u5)`
5176///
5177/// Instruction Type: S_2op
5178/// Execution Slots: SLOT23
5179#[inline(always)]
5180#[rustc_legacy_const_generics(1)]
5181#[cfg_attr(test, assert_instr(sfclass, IU5 = 0))]
5182#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5183pub unsafe fn Q6_p_sfclass_RI<const IU5: u32>(rs: f32) -> i32 {
5184    static_assert_uimm_bits!(IU5, 5);
5185    hexagon_F2_sfclass(rs, IU5 as i32)
5186}
5187
5188/// `Pd4=sfcmp.eq(Rs32,Rt32)`
5189///
5190/// Instruction Type: S_3op
5191/// Execution Slots: SLOT23
5192#[inline(always)]
5193#[cfg_attr(test, assert_instr(sfcmp))]
5194#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5195pub unsafe fn Q6_p_sfcmp_eq_RR(rs: f32, rt: f32) -> i32 {
5196    hexagon_F2_sfcmpeq(rs, rt)
5197}
5198
5199/// `Pd4=sfcmp.ge(Rs32,Rt32)`
5200///
5201/// Instruction Type: S_3op
5202/// Execution Slots: SLOT23
5203#[inline(always)]
5204#[cfg_attr(test, assert_instr(sfcmp))]
5205#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5206pub unsafe fn Q6_p_sfcmp_ge_RR(rs: f32, rt: f32) -> i32 {
5207    hexagon_F2_sfcmpge(rs, rt)
5208}
5209
5210/// `Pd4=sfcmp.gt(Rs32,Rt32)`
5211///
5212/// Instruction Type: S_3op
5213/// Execution Slots: SLOT23
5214#[inline(always)]
5215#[cfg_attr(test, assert_instr(sfcmp))]
5216#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5217pub unsafe fn Q6_p_sfcmp_gt_RR(rs: f32, rt: f32) -> i32 {
5218    hexagon_F2_sfcmpgt(rs, rt)
5219}
5220
5221/// `Pd4=sfcmp.uo(Rs32,Rt32)`
5222///
5223/// Instruction Type: S_3op
5224/// Execution Slots: SLOT23
5225#[inline(always)]
5226#[cfg_attr(test, assert_instr(sfcmp))]
5227#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5228pub unsafe fn Q6_p_sfcmp_uo_RR(rs: f32, rt: f32) -> i32 {
5229    hexagon_F2_sfcmpuo(rs, rt)
5230}
5231
5232/// `Rd32=sffixupd(Rs32,Rt32)`
5233///
5234/// Instruction Type: M
5235/// Execution Slots: SLOT23
5236#[inline(always)]
5237#[cfg_attr(test, assert_instr(sffixupd))]
5238#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5239pub unsafe fn Q6_R_sffixupd_RR(rs: f32, rt: f32) -> f32 {
5240    hexagon_F2_sffixupd(rs, rt)
5241}
5242
5243/// `Rd32=sffixupn(Rs32,Rt32)`
5244///
5245/// Instruction Type: M
5246/// Execution Slots: SLOT23
5247#[inline(always)]
5248#[cfg_attr(test, assert_instr(sffixupn))]
5249#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5250pub unsafe fn Q6_R_sffixupn_RR(rs: f32, rt: f32) -> f32 {
5251    hexagon_F2_sffixupn(rs, rt)
5252}
5253
5254/// `Rd32=sffixupr(Rs32)`
5255///
5256/// Instruction Type: S_2op
5257/// Execution Slots: SLOT23
5258#[inline(always)]
5259#[cfg_attr(test, assert_instr(sffixupr))]
5260#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5261pub unsafe fn Q6_R_sffixupr_R(rs: f32) -> f32 {
5262    hexagon_F2_sffixupr(rs)
5263}
5264
5265/// `Rx32+=sfmpy(Rs32,Rt32)`
5266///
5267/// Instruction Type: M
5268/// Execution Slots: SLOT23
5269#[inline(always)]
5270#[cfg_attr(test, assert_instr(sfmpy))]
5271#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5272pub unsafe fn Q6_R_sfmpyacc_RR(rx: f32, rs: f32, rt: f32) -> f32 {
5273    hexagon_F2_sffma(rx, rs, rt)
5274}
5275
5276/// `Rx32+=sfmpy(Rs32,Rt32):lib`
5277///
5278/// Instruction Type: M
5279/// Execution Slots: SLOT23
5280#[inline(always)]
5281#[cfg_attr(test, assert_instr(sfmpy))]
5282#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5283pub unsafe fn Q6_R_sfmpyacc_RR_lib(rx: f32, rs: f32, rt: f32) -> f32 {
5284    hexagon_F2_sffma_lib(rx, rs, rt)
5285}
5286
5287/// `Rx32+=sfmpy(Rs32,Rt32,Pu4):scale`
5288///
5289/// Instruction Type: M
5290/// Execution Slots: SLOT23
5291#[inline(always)]
5292#[cfg_attr(test, assert_instr(sfmpy))]
5293#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5294pub unsafe fn Q6_R_sfmpyacc_RRp_scale(rx: f32, rs: f32, rt: f32, pu: i32) -> f32 {
5295    hexagon_F2_sffma_sc(rx, rs, rt, pu)
5296}
5297
5298/// `Rx32-=sfmpy(Rs32,Rt32)`
5299///
5300/// Instruction Type: M
5301/// Execution Slots: SLOT23
5302#[inline(always)]
5303#[cfg_attr(test, assert_instr(sfmpy))]
5304#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5305pub unsafe fn Q6_R_sfmpynac_RR(rx: f32, rs: f32, rt: f32) -> f32 {
5306    hexagon_F2_sffms(rx, rs, rt)
5307}
5308
5309/// `Rx32-=sfmpy(Rs32,Rt32):lib`
5310///
5311/// Instruction Type: M
5312/// Execution Slots: SLOT23
5313#[inline(always)]
5314#[cfg_attr(test, assert_instr(sfmpy))]
5315#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5316pub unsafe fn Q6_R_sfmpynac_RR_lib(rx: f32, rs: f32, rt: f32) -> f32 {
5317    hexagon_F2_sffms_lib(rx, rs, rt)
5318}
5319
5320/// `Rd32=sfmake(#u10):neg`
5321///
5322/// Instruction Type: ALU64
5323/// Execution Slots: SLOT23
5324#[inline(always)]
5325#[rustc_legacy_const_generics(0)]
5326#[cfg_attr(test, assert_instr(sfmake, IU10 = 0))]
5327#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5328pub unsafe fn Q6_R_sfmake_I_neg<const IU10: u32>() -> f32 {
5329    static_assert_uimm_bits!(IU10, 10);
5330    hexagon_F2_sfimm_n(IU10 as i32)
5331}
5332
5333/// `Rd32=sfmake(#u10):pos`
5334///
5335/// Instruction Type: ALU64
5336/// Execution Slots: SLOT23
5337#[inline(always)]
5338#[rustc_legacy_const_generics(0)]
5339#[cfg_attr(test, assert_instr(sfmake, IU10 = 0))]
5340#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5341pub unsafe fn Q6_R_sfmake_I_pos<const IU10: u32>() -> f32 {
5342    static_assert_uimm_bits!(IU10, 10);
5343    hexagon_F2_sfimm_p(IU10 as i32)
5344}
5345
5346/// `Rd32=sfmax(Rs32,Rt32)`
5347///
5348/// Instruction Type: M
5349/// Execution Slots: SLOT23
5350#[inline(always)]
5351#[cfg_attr(test, assert_instr(sfmax))]
5352#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5353pub unsafe fn Q6_R_sfmax_RR(rs: f32, rt: f32) -> f32 {
5354    hexagon_F2_sfmax(rs, rt)
5355}
5356
5357/// `Rd32=sfmin(Rs32,Rt32)`
5358///
5359/// Instruction Type: M
5360/// Execution Slots: SLOT23
5361#[inline(always)]
5362#[cfg_attr(test, assert_instr(sfmin))]
5363#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5364pub unsafe fn Q6_R_sfmin_RR(rs: f32, rt: f32) -> f32 {
5365    hexagon_F2_sfmin(rs, rt)
5366}
5367
5368/// `Rd32=sfmpy(Rs32,Rt32)`
5369///
5370/// Instruction Type: M
5371/// Execution Slots: SLOT23
5372#[inline(always)]
5373#[cfg_attr(test, assert_instr(sfmpy))]
5374#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5375pub unsafe fn Q6_R_sfmpy_RR(rs: f32, rt: f32) -> f32 {
5376    hexagon_F2_sfmpy(rs, rt)
5377}
5378
5379/// `Rd32=sfsub(Rs32,Rt32)`
5380///
5381/// Instruction Type: M
5382/// Execution Slots: SLOT23
5383#[inline(always)]
5384#[cfg_attr(test, assert_instr(sfsub))]
5385#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5386pub unsafe fn Q6_R_sfsub_RR(rs: f32, rt: f32) -> f32 {
5387    hexagon_F2_sfsub(rs, rt)
5388}
5389
5390/// `Rx32+=add(Rs32,Rt32)`
5391///
5392/// Instruction Type: M
5393/// Execution Slots: SLOT23
5394#[inline(always)]
5395#[cfg_attr(test, assert_instr(add))]
5396#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5397pub unsafe fn Q6_R_addacc_RR(rx: i32, rs: i32, rt: i32) -> i32 {
5398    hexagon_M2_acci(rx, rs, rt)
5399}
5400
5401/// `Rx32+=add(Rs32,#s8)`
5402///
5403/// Instruction Type: M
5404/// Execution Slots: SLOT23
5405#[inline(always)]
5406#[rustc_legacy_const_generics(2)]
5407#[cfg_attr(test, assert_instr(add, IS8 = 0))]
5408#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5409pub unsafe fn Q6_R_addacc_RI<const IS8: i32>(rx: i32, rs: i32) -> i32 {
5410    static_assert_simm_bits!(IS8, 8);
5411    hexagon_M2_accii(rx, rs, IS8)
5412}
5413
5414/// `Rxx32+=cmpyi(Rs32,Rt32)`
5415///
5416/// Instruction Type: M
5417/// Execution Slots: SLOT23
5418#[inline(always)]
5419#[cfg_attr(test, assert_instr(cmpyi))]
5420#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5421pub unsafe fn Q6_P_cmpyiacc_RR(rxx: i64, rs: i32, rt: i32) -> i64 {
5422    hexagon_M2_cmaci_s0(rxx, rs, rt)
5423}
5424
5425/// `Rxx32+=cmpyr(Rs32,Rt32)`
5426///
5427/// Instruction Type: M
5428/// Execution Slots: SLOT23
5429#[inline(always)]
5430#[cfg_attr(test, assert_instr(cmpyr))]
5431#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5432pub unsafe fn Q6_P_cmpyracc_RR(rxx: i64, rs: i32, rt: i32) -> i64 {
5433    hexagon_M2_cmacr_s0(rxx, rs, rt)
5434}
5435
5436/// `Rxx32+=cmpy(Rs32,Rt32):sat`
5437///
5438/// Instruction Type: M
5439/// Execution Slots: SLOT23
5440#[inline(always)]
5441#[cfg_attr(test, assert_instr(cmpy))]
5442#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5443pub unsafe fn Q6_P_cmpyacc_RR_sat(rxx: i64, rs: i32, rt: i32) -> i64 {
5444    hexagon_M2_cmacs_s0(rxx, rs, rt)
5445}
5446
5447/// `Rxx32+=cmpy(Rs32,Rt32):<<1:sat`
5448///
5449/// Instruction Type: M
5450/// Execution Slots: SLOT23
5451#[inline(always)]
5452#[cfg_attr(test, assert_instr(cmpy))]
5453#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5454pub unsafe fn Q6_P_cmpyacc_RR_s1_sat(rxx: i64, rs: i32, rt: i32) -> i64 {
5455    hexagon_M2_cmacs_s1(rxx, rs, rt)
5456}
5457
5458/// `Rxx32+=cmpy(Rs32,Rt32*):sat`
5459///
5460/// Instruction Type: M
5461/// Execution Slots: SLOT23
5462#[inline(always)]
5463#[cfg_attr(test, assert_instr(cmpy))]
5464#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5465pub unsafe fn Q6_P_cmpyacc_RR_conj_sat(rxx: i64, rs: i32, rt: i32) -> i64 {
5466    hexagon_M2_cmacsc_s0(rxx, rs, rt)
5467}
5468
5469/// `Rxx32+=cmpy(Rs32,Rt32*):<<1:sat`
5470///
5471/// Instruction Type: M
5472/// Execution Slots: SLOT23
5473#[inline(always)]
5474#[cfg_attr(test, assert_instr(cmpy))]
5475#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5476pub unsafe fn Q6_P_cmpyacc_RR_conj_s1_sat(rxx: i64, rs: i32, rt: i32) -> i64 {
5477    hexagon_M2_cmacsc_s1(rxx, rs, rt)
5478}
5479
5480/// `Rdd32=cmpyi(Rs32,Rt32)`
5481///
5482/// Instruction Type: M
5483/// Execution Slots: SLOT23
5484#[inline(always)]
5485#[cfg_attr(test, assert_instr(cmpyi))]
5486#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5487pub unsafe fn Q6_P_cmpyi_RR(rs: i32, rt: i32) -> i64 {
5488    hexagon_M2_cmpyi_s0(rs, rt)
5489}
5490
5491/// `Rdd32=cmpyr(Rs32,Rt32)`
5492///
5493/// Instruction Type: M
5494/// Execution Slots: SLOT23
5495#[inline(always)]
5496#[cfg_attr(test, assert_instr(cmpyr))]
5497#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5498pub unsafe fn Q6_P_cmpyr_RR(rs: i32, rt: i32) -> i64 {
5499    hexagon_M2_cmpyr_s0(rs, rt)
5500}
5501
5502/// `Rd32=cmpy(Rs32,Rt32):rnd:sat`
5503///
5504/// Instruction Type: M
5505/// Execution Slots: SLOT23
5506#[inline(always)]
5507#[cfg_attr(test, assert_instr(cmpy))]
5508#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5509pub unsafe fn Q6_R_cmpy_RR_rnd_sat(rs: i32, rt: i32) -> i32 {
5510    hexagon_M2_cmpyrs_s0(rs, rt)
5511}
5512
5513/// `Rd32=cmpy(Rs32,Rt32):<<1:rnd:sat`
5514///
5515/// Instruction Type: M
5516/// Execution Slots: SLOT23
5517#[inline(always)]
5518#[cfg_attr(test, assert_instr(cmpy))]
5519#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5520pub unsafe fn Q6_R_cmpy_RR_s1_rnd_sat(rs: i32, rt: i32) -> i32 {
5521    hexagon_M2_cmpyrs_s1(rs, rt)
5522}
5523
5524/// `Rd32=cmpy(Rs32,Rt32*):rnd:sat`
5525///
5526/// Instruction Type: M
5527/// Execution Slots: SLOT23
5528#[inline(always)]
5529#[cfg_attr(test, assert_instr(cmpy))]
5530#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5531pub unsafe fn Q6_R_cmpy_RR_conj_rnd_sat(rs: i32, rt: i32) -> i32 {
5532    hexagon_M2_cmpyrsc_s0(rs, rt)
5533}
5534
5535/// `Rd32=cmpy(Rs32,Rt32*):<<1:rnd:sat`
5536///
5537/// Instruction Type: M
5538/// Execution Slots: SLOT23
5539#[inline(always)]
5540#[cfg_attr(test, assert_instr(cmpy))]
5541#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5542pub unsafe fn Q6_R_cmpy_RR_conj_s1_rnd_sat(rs: i32, rt: i32) -> i32 {
5543    hexagon_M2_cmpyrsc_s1(rs, rt)
5544}
5545
5546/// `Rdd32=cmpy(Rs32,Rt32):sat`
5547///
5548/// Instruction Type: M
5549/// Execution Slots: SLOT23
5550#[inline(always)]
5551#[cfg_attr(test, assert_instr(cmpy))]
5552#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5553pub unsafe fn Q6_P_cmpy_RR_sat(rs: i32, rt: i32) -> i64 {
5554    hexagon_M2_cmpys_s0(rs, rt)
5555}
5556
5557/// `Rdd32=cmpy(Rs32,Rt32):<<1:sat`
5558///
5559/// Instruction Type: M
5560/// Execution Slots: SLOT23
5561#[inline(always)]
5562#[cfg_attr(test, assert_instr(cmpy))]
5563#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5564pub unsafe fn Q6_P_cmpy_RR_s1_sat(rs: i32, rt: i32) -> i64 {
5565    hexagon_M2_cmpys_s1(rs, rt)
5566}
5567
5568/// `Rdd32=cmpy(Rs32,Rt32*):sat`
5569///
5570/// Instruction Type: M
5571/// Execution Slots: SLOT23
5572#[inline(always)]
5573#[cfg_attr(test, assert_instr(cmpy))]
5574#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5575pub unsafe fn Q6_P_cmpy_RR_conj_sat(rs: i32, rt: i32) -> i64 {
5576    hexagon_M2_cmpysc_s0(rs, rt)
5577}
5578
5579/// `Rdd32=cmpy(Rs32,Rt32*):<<1:sat`
5580///
5581/// Instruction Type: M
5582/// Execution Slots: SLOT23
5583#[inline(always)]
5584#[cfg_attr(test, assert_instr(cmpy))]
5585#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5586pub unsafe fn Q6_P_cmpy_RR_conj_s1_sat(rs: i32, rt: i32) -> i64 {
5587    hexagon_M2_cmpysc_s1(rs, rt)
5588}
5589
5590/// `Rxx32-=cmpy(Rs32,Rt32):sat`
5591///
5592/// Instruction Type: M
5593/// Execution Slots: SLOT23
5594#[inline(always)]
5595#[cfg_attr(test, assert_instr(cmpy))]
5596#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5597pub unsafe fn Q6_P_cmpynac_RR_sat(rxx: i64, rs: i32, rt: i32) -> i64 {
5598    hexagon_M2_cnacs_s0(rxx, rs, rt)
5599}
5600
5601/// `Rxx32-=cmpy(Rs32,Rt32):<<1:sat`
5602///
5603/// Instruction Type: M
5604/// Execution Slots: SLOT23
5605#[inline(always)]
5606#[cfg_attr(test, assert_instr(cmpy))]
5607#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5608pub unsafe fn Q6_P_cmpynac_RR_s1_sat(rxx: i64, rs: i32, rt: i32) -> i64 {
5609    hexagon_M2_cnacs_s1(rxx, rs, rt)
5610}
5611
5612/// `Rxx32-=cmpy(Rs32,Rt32*):sat`
5613///
5614/// Instruction Type: M
5615/// Execution Slots: SLOT23
5616#[inline(always)]
5617#[cfg_attr(test, assert_instr(cmpy))]
5618#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5619pub unsafe fn Q6_P_cmpynac_RR_conj_sat(rxx: i64, rs: i32, rt: i32) -> i64 {
5620    hexagon_M2_cnacsc_s0(rxx, rs, rt)
5621}
5622
5623/// `Rxx32-=cmpy(Rs32,Rt32*):<<1:sat`
5624///
5625/// Instruction Type: M
5626/// Execution Slots: SLOT23
5627#[inline(always)]
5628#[cfg_attr(test, assert_instr(cmpy))]
5629#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5630pub unsafe fn Q6_P_cmpynac_RR_conj_s1_sat(rxx: i64, rs: i32, rt: i32) -> i64 {
5631    hexagon_M2_cnacsc_s1(rxx, rs, rt)
5632}
5633
5634/// `Rxx32+=mpy(Rs32,Rt32)`
5635///
5636/// Instruction Type: M
5637/// Execution Slots: SLOT23
5638#[inline(always)]
5639#[cfg_attr(test, assert_instr(mpy))]
5640#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5641pub unsafe fn Q6_P_mpyacc_RR(rxx: i64, rs: i32, rt: i32) -> i64 {
5642    hexagon_M2_dpmpyss_acc_s0(rxx, rs, rt)
5643}
5644
5645/// `Rxx32-=mpy(Rs32,Rt32)`
5646///
5647/// Instruction Type: M
5648/// Execution Slots: SLOT23
5649#[inline(always)]
5650#[cfg_attr(test, assert_instr(mpy))]
5651#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5652pub unsafe fn Q6_P_mpynac_RR(rxx: i64, rs: i32, rt: i32) -> i64 {
5653    hexagon_M2_dpmpyss_nac_s0(rxx, rs, rt)
5654}
5655
5656/// `Rd32=mpy(Rs32,Rt32):rnd`
5657///
5658/// Instruction Type: M
5659/// Execution Slots: SLOT23
5660#[inline(always)]
5661#[cfg_attr(test, assert_instr(mpy))]
5662#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5663pub unsafe fn Q6_R_mpy_RR_rnd(rs: i32, rt: i32) -> i32 {
5664    hexagon_M2_dpmpyss_rnd_s0(rs, rt)
5665}
5666
5667/// `Rdd32=mpy(Rs32,Rt32)`
5668///
5669/// Instruction Type: M
5670/// Execution Slots: SLOT23
5671#[inline(always)]
5672#[cfg_attr(test, assert_instr(mpy))]
5673#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5674pub unsafe fn Q6_P_mpy_RR(rs: i32, rt: i32) -> i64 {
5675    hexagon_M2_dpmpyss_s0(rs, rt)
5676}
5677
5678/// `Rxx32+=mpyu(Rs32,Rt32)`
5679///
5680/// Instruction Type: M
5681/// Execution Slots: SLOT23
5682#[inline(always)]
5683#[cfg_attr(test, assert_instr(mpyu))]
5684#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5685pub unsafe fn Q6_P_mpyuacc_RR(rxx: i64, rs: i32, rt: i32) -> i64 {
5686    hexagon_M2_dpmpyuu_acc_s0(rxx, rs, rt)
5687}
5688
5689/// `Rxx32-=mpyu(Rs32,Rt32)`
5690///
5691/// Instruction Type: M
5692/// Execution Slots: SLOT23
5693#[inline(always)]
5694#[cfg_attr(test, assert_instr(mpyu))]
5695#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5696pub unsafe fn Q6_P_mpyunac_RR(rxx: i64, rs: i32, rt: i32) -> i64 {
5697    hexagon_M2_dpmpyuu_nac_s0(rxx, rs, rt)
5698}
5699
5700/// `Rdd32=mpyu(Rs32,Rt32)`
5701///
5702/// Instruction Type: M
5703/// Execution Slots: SLOT23
5704#[inline(always)]
5705#[cfg_attr(test, assert_instr(mpyu))]
5706#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5707pub unsafe fn Q6_P_mpyu_RR(rs: i32, rt: i32) -> i64 {
5708    hexagon_M2_dpmpyuu_s0(rs, rt)
5709}
5710
5711/// `Rd32=mpy(Rs32,Rt32.h):<<1:rnd:sat`
5712///
5713/// Instruction Type: M
5714/// Execution Slots: SLOT23
5715#[inline(always)]
5716#[cfg_attr(test, assert_instr(mpy))]
5717#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5718pub unsafe fn Q6_R_mpy_RRh_s1_rnd_sat(rs: i32, rt: i32) -> i32 {
5719    hexagon_M2_hmmpyh_rs1(rs, rt)
5720}
5721
5722/// `Rd32=mpy(Rs32,Rt32.h):<<1:sat`
5723///
5724/// Instruction Type: M
5725/// Execution Slots: SLOT23
5726#[inline(always)]
5727#[cfg_attr(test, assert_instr(mpy))]
5728#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5729pub unsafe fn Q6_R_mpy_RRh_s1_sat(rs: i32, rt: i32) -> i32 {
5730    hexagon_M2_hmmpyh_s1(rs, rt)
5731}
5732
5733/// `Rd32=mpy(Rs32,Rt32.l):<<1:rnd:sat`
5734///
5735/// Instruction Type: M
5736/// Execution Slots: SLOT23
5737#[inline(always)]
5738#[cfg_attr(test, assert_instr(mpy))]
5739#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5740pub unsafe fn Q6_R_mpy_RRl_s1_rnd_sat(rs: i32, rt: i32) -> i32 {
5741    hexagon_M2_hmmpyl_rs1(rs, rt)
5742}
5743
5744/// `Rd32=mpy(Rs32,Rt32.l):<<1:sat`
5745///
5746/// Instruction Type: M
5747/// Execution Slots: SLOT23
5748#[inline(always)]
5749#[cfg_attr(test, assert_instr(mpy))]
5750#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5751pub unsafe fn Q6_R_mpy_RRl_s1_sat(rs: i32, rt: i32) -> i32 {
5752    hexagon_M2_hmmpyl_s1(rs, rt)
5753}
5754
5755/// `Rx32+=mpyi(Rs32,Rt32)`
5756///
5757/// Instruction Type: M
5758/// Execution Slots: SLOT23
5759#[inline(always)]
5760#[cfg_attr(test, assert_instr(mpyi))]
5761#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5762pub unsafe fn Q6_R_mpyiacc_RR(rx: i32, rs: i32, rt: i32) -> i32 {
5763    hexagon_M2_maci(rx, rs, rt)
5764}
5765
5766/// `Rx32-=mpyi(Rs32,#u8)`
5767///
5768/// Instruction Type: M
5769/// Execution Slots: SLOT23
5770#[inline(always)]
5771#[rustc_legacy_const_generics(2)]
5772#[cfg_attr(test, assert_instr(mpyi, IU8 = 0))]
5773#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5774pub unsafe fn Q6_R_mpyinac_RI<const IU8: u32>(rx: i32, rs: i32) -> i32 {
5775    static_assert_uimm_bits!(IU8, 8);
5776    hexagon_M2_macsin(rx, rs, IU8 as i32)
5777}
5778
5779/// `Rx32+=mpyi(Rs32,#u8)`
5780///
5781/// Instruction Type: M
5782/// Execution Slots: SLOT23
5783#[inline(always)]
5784#[rustc_legacy_const_generics(2)]
5785#[cfg_attr(test, assert_instr(mpyi, IU8 = 0))]
5786#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5787pub unsafe fn Q6_R_mpyiacc_RI<const IU8: u32>(rx: i32, rs: i32) -> i32 {
5788    static_assert_uimm_bits!(IU8, 8);
5789    hexagon_M2_macsip(rx, rs, IU8 as i32)
5790}
5791
5792/// `Rxx32+=vmpywoh(Rss32,Rtt32):rnd:sat`
5793///
5794/// Instruction Type: M
5795/// Execution Slots: SLOT23
5796#[inline(always)]
5797#[cfg_attr(test, assert_instr(vmpywoh))]
5798#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5799pub unsafe fn Q6_P_vmpywohacc_PP_rnd_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
5800    hexagon_M2_mmachs_rs0(rxx, rss, rtt)
5801}
5802
5803/// `Rxx32+=vmpywoh(Rss32,Rtt32):<<1:rnd:sat`
5804///
5805/// Instruction Type: M
5806/// Execution Slots: SLOT23
5807#[inline(always)]
5808#[cfg_attr(test, assert_instr(vmpywoh))]
5809#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5810pub unsafe fn Q6_P_vmpywohacc_PP_s1_rnd_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
5811    hexagon_M2_mmachs_rs1(rxx, rss, rtt)
5812}
5813
5814/// `Rxx32+=vmpywoh(Rss32,Rtt32):sat`
5815///
5816/// Instruction Type: M
5817/// Execution Slots: SLOT23
5818#[inline(always)]
5819#[cfg_attr(test, assert_instr(vmpywoh))]
5820#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5821pub unsafe fn Q6_P_vmpywohacc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
5822    hexagon_M2_mmachs_s0(rxx, rss, rtt)
5823}
5824
5825/// `Rxx32+=vmpywoh(Rss32,Rtt32):<<1:sat`
5826///
5827/// Instruction Type: M
5828/// Execution Slots: SLOT23
5829#[inline(always)]
5830#[cfg_attr(test, assert_instr(vmpywoh))]
5831#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5832pub unsafe fn Q6_P_vmpywohacc_PP_s1_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
5833    hexagon_M2_mmachs_s1(rxx, rss, rtt)
5834}
5835
5836/// `Rxx32+=vmpyweh(Rss32,Rtt32):rnd:sat`
5837///
5838/// Instruction Type: M
5839/// Execution Slots: SLOT23
5840#[inline(always)]
5841#[cfg_attr(test, assert_instr(vmpyweh))]
5842#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5843pub unsafe fn Q6_P_vmpywehacc_PP_rnd_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
5844    hexagon_M2_mmacls_rs0(rxx, rss, rtt)
5845}
5846
5847/// `Rxx32+=vmpyweh(Rss32,Rtt32):<<1:rnd:sat`
5848///
5849/// Instruction Type: M
5850/// Execution Slots: SLOT23
5851#[inline(always)]
5852#[cfg_attr(test, assert_instr(vmpyweh))]
5853#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5854pub unsafe fn Q6_P_vmpywehacc_PP_s1_rnd_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
5855    hexagon_M2_mmacls_rs1(rxx, rss, rtt)
5856}
5857
5858/// `Rxx32+=vmpyweh(Rss32,Rtt32):sat`
5859///
5860/// Instruction Type: M
5861/// Execution Slots: SLOT23
5862#[inline(always)]
5863#[cfg_attr(test, assert_instr(vmpyweh))]
5864#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5865pub unsafe fn Q6_P_vmpywehacc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
5866    hexagon_M2_mmacls_s0(rxx, rss, rtt)
5867}
5868
5869/// `Rxx32+=vmpyweh(Rss32,Rtt32):<<1:sat`
5870///
5871/// Instruction Type: M
5872/// Execution Slots: SLOT23
5873#[inline(always)]
5874#[cfg_attr(test, assert_instr(vmpyweh))]
5875#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5876pub unsafe fn Q6_P_vmpywehacc_PP_s1_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
5877    hexagon_M2_mmacls_s1(rxx, rss, rtt)
5878}
5879
5880/// `Rxx32+=vmpywouh(Rss32,Rtt32):rnd:sat`
5881///
5882/// Instruction Type: M
5883/// Execution Slots: SLOT23
5884#[inline(always)]
5885#[cfg_attr(test, assert_instr(vmpywouh))]
5886#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5887pub unsafe fn Q6_P_vmpywouhacc_PP_rnd_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
5888    hexagon_M2_mmacuhs_rs0(rxx, rss, rtt)
5889}
5890
5891/// `Rxx32+=vmpywouh(Rss32,Rtt32):<<1:rnd:sat`
5892///
5893/// Instruction Type: M
5894/// Execution Slots: SLOT23
5895#[inline(always)]
5896#[cfg_attr(test, assert_instr(vmpywouh))]
5897#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5898pub unsafe fn Q6_P_vmpywouhacc_PP_s1_rnd_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
5899    hexagon_M2_mmacuhs_rs1(rxx, rss, rtt)
5900}
5901
5902/// `Rxx32+=vmpywouh(Rss32,Rtt32):sat`
5903///
5904/// Instruction Type: M
5905/// Execution Slots: SLOT23
5906#[inline(always)]
5907#[cfg_attr(test, assert_instr(vmpywouh))]
5908#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5909pub unsafe fn Q6_P_vmpywouhacc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
5910    hexagon_M2_mmacuhs_s0(rxx, rss, rtt)
5911}
5912
5913/// `Rxx32+=vmpywouh(Rss32,Rtt32):<<1:sat`
5914///
5915/// Instruction Type: M
5916/// Execution Slots: SLOT23
5917#[inline(always)]
5918#[cfg_attr(test, assert_instr(vmpywouh))]
5919#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5920pub unsafe fn Q6_P_vmpywouhacc_PP_s1_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
5921    hexagon_M2_mmacuhs_s1(rxx, rss, rtt)
5922}
5923
5924/// `Rxx32+=vmpyweuh(Rss32,Rtt32):rnd:sat`
5925///
5926/// Instruction Type: M
5927/// Execution Slots: SLOT23
5928#[inline(always)]
5929#[cfg_attr(test, assert_instr(vmpyweuh))]
5930#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5931pub unsafe fn Q6_P_vmpyweuhacc_PP_rnd_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
5932    hexagon_M2_mmaculs_rs0(rxx, rss, rtt)
5933}
5934
5935/// `Rxx32+=vmpyweuh(Rss32,Rtt32):<<1:rnd:sat`
5936///
5937/// Instruction Type: M
5938/// Execution Slots: SLOT23
5939#[inline(always)]
5940#[cfg_attr(test, assert_instr(vmpyweuh))]
5941#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5942pub unsafe fn Q6_P_vmpyweuhacc_PP_s1_rnd_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
5943    hexagon_M2_mmaculs_rs1(rxx, rss, rtt)
5944}
5945
5946/// `Rxx32+=vmpyweuh(Rss32,Rtt32):sat`
5947///
5948/// Instruction Type: M
5949/// Execution Slots: SLOT23
5950#[inline(always)]
5951#[cfg_attr(test, assert_instr(vmpyweuh))]
5952#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5953pub unsafe fn Q6_P_vmpyweuhacc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
5954    hexagon_M2_mmaculs_s0(rxx, rss, rtt)
5955}
5956
5957/// `Rxx32+=vmpyweuh(Rss32,Rtt32):<<1:sat`
5958///
5959/// Instruction Type: M
5960/// Execution Slots: SLOT23
5961#[inline(always)]
5962#[cfg_attr(test, assert_instr(vmpyweuh))]
5963#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5964pub unsafe fn Q6_P_vmpyweuhacc_PP_s1_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
5965    hexagon_M2_mmaculs_s1(rxx, rss, rtt)
5966}
5967
5968/// `Rdd32=vmpywoh(Rss32,Rtt32):rnd:sat`
5969///
5970/// Instruction Type: M
5971/// Execution Slots: SLOT23
5972#[inline(always)]
5973#[cfg_attr(test, assert_instr(vmpywoh))]
5974#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5975pub unsafe fn Q6_P_vmpywoh_PP_rnd_sat(rss: i64, rtt: i64) -> i64 {
5976    hexagon_M2_mmpyh_rs0(rss, rtt)
5977}
5978
5979/// `Rdd32=vmpywoh(Rss32,Rtt32):<<1:rnd:sat`
5980///
5981/// Instruction Type: M
5982/// Execution Slots: SLOT23
5983#[inline(always)]
5984#[cfg_attr(test, assert_instr(vmpywoh))]
5985#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5986pub unsafe fn Q6_P_vmpywoh_PP_s1_rnd_sat(rss: i64, rtt: i64) -> i64 {
5987    hexagon_M2_mmpyh_rs1(rss, rtt)
5988}
5989
5990/// `Rdd32=vmpywoh(Rss32,Rtt32):sat`
5991///
5992/// Instruction Type: M
5993/// Execution Slots: SLOT23
5994#[inline(always)]
5995#[cfg_attr(test, assert_instr(vmpywoh))]
5996#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5997pub unsafe fn Q6_P_vmpywoh_PP_sat(rss: i64, rtt: i64) -> i64 {
5998    hexagon_M2_mmpyh_s0(rss, rtt)
5999}
6000
6001/// `Rdd32=vmpywoh(Rss32,Rtt32):<<1:sat`
6002///
6003/// Instruction Type: M
6004/// Execution Slots: SLOT23
6005#[inline(always)]
6006#[cfg_attr(test, assert_instr(vmpywoh))]
6007#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6008pub unsafe fn Q6_P_vmpywoh_PP_s1_sat(rss: i64, rtt: i64) -> i64 {
6009    hexagon_M2_mmpyh_s1(rss, rtt)
6010}
6011
6012/// `Rdd32=vmpyweh(Rss32,Rtt32):rnd:sat`
6013///
6014/// Instruction Type: M
6015/// Execution Slots: SLOT23
6016#[inline(always)]
6017#[cfg_attr(test, assert_instr(vmpyweh))]
6018#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6019pub unsafe fn Q6_P_vmpyweh_PP_rnd_sat(rss: i64, rtt: i64) -> i64 {
6020    hexagon_M2_mmpyl_rs0(rss, rtt)
6021}
6022
6023/// `Rdd32=vmpyweh(Rss32,Rtt32):<<1:rnd:sat`
6024///
6025/// Instruction Type: M
6026/// Execution Slots: SLOT23
6027#[inline(always)]
6028#[cfg_attr(test, assert_instr(vmpyweh))]
6029#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6030pub unsafe fn Q6_P_vmpyweh_PP_s1_rnd_sat(rss: i64, rtt: i64) -> i64 {
6031    hexagon_M2_mmpyl_rs1(rss, rtt)
6032}
6033
6034/// `Rdd32=vmpyweh(Rss32,Rtt32):sat`
6035///
6036/// Instruction Type: M
6037/// Execution Slots: SLOT23
6038#[inline(always)]
6039#[cfg_attr(test, assert_instr(vmpyweh))]
6040#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6041pub unsafe fn Q6_P_vmpyweh_PP_sat(rss: i64, rtt: i64) -> i64 {
6042    hexagon_M2_mmpyl_s0(rss, rtt)
6043}
6044
6045/// `Rdd32=vmpyweh(Rss32,Rtt32):<<1:sat`
6046///
6047/// Instruction Type: M
6048/// Execution Slots: SLOT23
6049#[inline(always)]
6050#[cfg_attr(test, assert_instr(vmpyweh))]
6051#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6052pub unsafe fn Q6_P_vmpyweh_PP_s1_sat(rss: i64, rtt: i64) -> i64 {
6053    hexagon_M2_mmpyl_s1(rss, rtt)
6054}
6055
6056/// `Rdd32=vmpywouh(Rss32,Rtt32):rnd:sat`
6057///
6058/// Instruction Type: M
6059/// Execution Slots: SLOT23
6060#[inline(always)]
6061#[cfg_attr(test, assert_instr(vmpywouh))]
6062#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6063pub unsafe fn Q6_P_vmpywouh_PP_rnd_sat(rss: i64, rtt: i64) -> i64 {
6064    hexagon_M2_mmpyuh_rs0(rss, rtt)
6065}
6066
6067/// `Rdd32=vmpywouh(Rss32,Rtt32):<<1:rnd:sat`
6068///
6069/// Instruction Type: M
6070/// Execution Slots: SLOT23
6071#[inline(always)]
6072#[cfg_attr(test, assert_instr(vmpywouh))]
6073#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6074pub unsafe fn Q6_P_vmpywouh_PP_s1_rnd_sat(rss: i64, rtt: i64) -> i64 {
6075    hexagon_M2_mmpyuh_rs1(rss, rtt)
6076}
6077
6078/// `Rdd32=vmpywouh(Rss32,Rtt32):sat`
6079///
6080/// Instruction Type: M
6081/// Execution Slots: SLOT23
6082#[inline(always)]
6083#[cfg_attr(test, assert_instr(vmpywouh))]
6084#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6085pub unsafe fn Q6_P_vmpywouh_PP_sat(rss: i64, rtt: i64) -> i64 {
6086    hexagon_M2_mmpyuh_s0(rss, rtt)
6087}
6088
6089/// `Rdd32=vmpywouh(Rss32,Rtt32):<<1:sat`
6090///
6091/// Instruction Type: M
6092/// Execution Slots: SLOT23
6093#[inline(always)]
6094#[cfg_attr(test, assert_instr(vmpywouh))]
6095#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6096pub unsafe fn Q6_P_vmpywouh_PP_s1_sat(rss: i64, rtt: i64) -> i64 {
6097    hexagon_M2_mmpyuh_s1(rss, rtt)
6098}
6099
6100/// `Rdd32=vmpyweuh(Rss32,Rtt32):rnd:sat`
6101///
6102/// Instruction Type: M
6103/// Execution Slots: SLOT23
6104#[inline(always)]
6105#[cfg_attr(test, assert_instr(vmpyweuh))]
6106#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6107pub unsafe fn Q6_P_vmpyweuh_PP_rnd_sat(rss: i64, rtt: i64) -> i64 {
6108    hexagon_M2_mmpyul_rs0(rss, rtt)
6109}
6110
6111/// `Rdd32=vmpyweuh(Rss32,Rtt32):<<1:rnd:sat`
6112///
6113/// Instruction Type: M
6114/// Execution Slots: SLOT23
6115#[inline(always)]
6116#[cfg_attr(test, assert_instr(vmpyweuh))]
6117#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6118pub unsafe fn Q6_P_vmpyweuh_PP_s1_rnd_sat(rss: i64, rtt: i64) -> i64 {
6119    hexagon_M2_mmpyul_rs1(rss, rtt)
6120}
6121
6122/// `Rdd32=vmpyweuh(Rss32,Rtt32):sat`
6123///
6124/// Instruction Type: M
6125/// Execution Slots: SLOT23
6126#[inline(always)]
6127#[cfg_attr(test, assert_instr(vmpyweuh))]
6128#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6129pub unsafe fn Q6_P_vmpyweuh_PP_sat(rss: i64, rtt: i64) -> i64 {
6130    hexagon_M2_mmpyul_s0(rss, rtt)
6131}
6132
6133/// `Rdd32=vmpyweuh(Rss32,Rtt32):<<1:sat`
6134///
6135/// Instruction Type: M
6136/// Execution Slots: SLOT23
6137#[inline(always)]
6138#[cfg_attr(test, assert_instr(vmpyweuh))]
6139#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6140pub unsafe fn Q6_P_vmpyweuh_PP_s1_sat(rss: i64, rtt: i64) -> i64 {
6141    hexagon_M2_mmpyul_s1(rss, rtt)
6142}
6143
6144/// `Rx32+=mpy(Rs32.h,Rt32.h)`
6145///
6146/// Instruction Type: M
6147/// Execution Slots: SLOT23
6148#[inline(always)]
6149#[cfg_attr(test, assert_instr(mpy))]
6150#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6151pub unsafe fn Q6_R_mpyacc_RhRh(rx: i32, rs: i32, rt: i32) -> i32 {
6152    hexagon_M2_mpy_acc_hh_s0(rx, rs, rt)
6153}
6154
6155/// `Rx32+=mpy(Rs32.h,Rt32.h):<<1`
6156///
6157/// Instruction Type: M
6158/// Execution Slots: SLOT23
6159#[inline(always)]
6160#[cfg_attr(test, assert_instr(mpy))]
6161#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6162pub unsafe fn Q6_R_mpyacc_RhRh_s1(rx: i32, rs: i32, rt: i32) -> i32 {
6163    hexagon_M2_mpy_acc_hh_s1(rx, rs, rt)
6164}
6165
6166/// `Rx32+=mpy(Rs32.h,Rt32.l)`
6167///
6168/// Instruction Type: M
6169/// Execution Slots: SLOT23
6170#[inline(always)]
6171#[cfg_attr(test, assert_instr(mpy))]
6172#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6173pub unsafe fn Q6_R_mpyacc_RhRl(rx: i32, rs: i32, rt: i32) -> i32 {
6174    hexagon_M2_mpy_acc_hl_s0(rx, rs, rt)
6175}
6176
6177/// `Rx32+=mpy(Rs32.h,Rt32.l):<<1`
6178///
6179/// Instruction Type: M
6180/// Execution Slots: SLOT23
6181#[inline(always)]
6182#[cfg_attr(test, assert_instr(mpy))]
6183#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6184pub unsafe fn Q6_R_mpyacc_RhRl_s1(rx: i32, rs: i32, rt: i32) -> i32 {
6185    hexagon_M2_mpy_acc_hl_s1(rx, rs, rt)
6186}
6187
6188/// `Rx32+=mpy(Rs32.l,Rt32.h)`
6189///
6190/// Instruction Type: M
6191/// Execution Slots: SLOT23
6192#[inline(always)]
6193#[cfg_attr(test, assert_instr(mpy))]
6194#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6195pub unsafe fn Q6_R_mpyacc_RlRh(rx: i32, rs: i32, rt: i32) -> i32 {
6196    hexagon_M2_mpy_acc_lh_s0(rx, rs, rt)
6197}
6198
6199/// `Rx32+=mpy(Rs32.l,Rt32.h):<<1`
6200///
6201/// Instruction Type: M
6202/// Execution Slots: SLOT23
6203#[inline(always)]
6204#[cfg_attr(test, assert_instr(mpy))]
6205#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6206pub unsafe fn Q6_R_mpyacc_RlRh_s1(rx: i32, rs: i32, rt: i32) -> i32 {
6207    hexagon_M2_mpy_acc_lh_s1(rx, rs, rt)
6208}
6209
6210/// `Rx32+=mpy(Rs32.l,Rt32.l)`
6211///
6212/// Instruction Type: M
6213/// Execution Slots: SLOT23
6214#[inline(always)]
6215#[cfg_attr(test, assert_instr(mpy))]
6216#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6217pub unsafe fn Q6_R_mpyacc_RlRl(rx: i32, rs: i32, rt: i32) -> i32 {
6218    hexagon_M2_mpy_acc_ll_s0(rx, rs, rt)
6219}
6220
6221/// `Rx32+=mpy(Rs32.l,Rt32.l):<<1`
6222///
6223/// Instruction Type: M
6224/// Execution Slots: SLOT23
6225#[inline(always)]
6226#[cfg_attr(test, assert_instr(mpy))]
6227#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6228pub unsafe fn Q6_R_mpyacc_RlRl_s1(rx: i32, rs: i32, rt: i32) -> i32 {
6229    hexagon_M2_mpy_acc_ll_s1(rx, rs, rt)
6230}
6231
6232/// `Rx32+=mpy(Rs32.h,Rt32.h):sat`
6233///
6234/// Instruction Type: M
6235/// Execution Slots: SLOT23
6236#[inline(always)]
6237#[cfg_attr(test, assert_instr(mpy))]
6238#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6239pub unsafe fn Q6_R_mpyacc_RhRh_sat(rx: i32, rs: i32, rt: i32) -> i32 {
6240    hexagon_M2_mpy_acc_sat_hh_s0(rx, rs, rt)
6241}
6242
6243/// `Rx32+=mpy(Rs32.h,Rt32.h):<<1:sat`
6244///
6245/// Instruction Type: M
6246/// Execution Slots: SLOT23
6247#[inline(always)]
6248#[cfg_attr(test, assert_instr(mpy))]
6249#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6250pub unsafe fn Q6_R_mpyacc_RhRh_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 {
6251    hexagon_M2_mpy_acc_sat_hh_s1(rx, rs, rt)
6252}
6253
6254/// `Rx32+=mpy(Rs32.h,Rt32.l):sat`
6255///
6256/// Instruction Type: M
6257/// Execution Slots: SLOT23
6258#[inline(always)]
6259#[cfg_attr(test, assert_instr(mpy))]
6260#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6261pub unsafe fn Q6_R_mpyacc_RhRl_sat(rx: i32, rs: i32, rt: i32) -> i32 {
6262    hexagon_M2_mpy_acc_sat_hl_s0(rx, rs, rt)
6263}
6264
6265/// `Rx32+=mpy(Rs32.h,Rt32.l):<<1:sat`
6266///
6267/// Instruction Type: M
6268/// Execution Slots: SLOT23
6269#[inline(always)]
6270#[cfg_attr(test, assert_instr(mpy))]
6271#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6272pub unsafe fn Q6_R_mpyacc_RhRl_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 {
6273    hexagon_M2_mpy_acc_sat_hl_s1(rx, rs, rt)
6274}
6275
6276/// `Rx32+=mpy(Rs32.l,Rt32.h):sat`
6277///
6278/// Instruction Type: M
6279/// Execution Slots: SLOT23
6280#[inline(always)]
6281#[cfg_attr(test, assert_instr(mpy))]
6282#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6283pub unsafe fn Q6_R_mpyacc_RlRh_sat(rx: i32, rs: i32, rt: i32) -> i32 {
6284    hexagon_M2_mpy_acc_sat_lh_s0(rx, rs, rt)
6285}
6286
6287/// `Rx32+=mpy(Rs32.l,Rt32.h):<<1:sat`
6288///
6289/// Instruction Type: M
6290/// Execution Slots: SLOT23
6291#[inline(always)]
6292#[cfg_attr(test, assert_instr(mpy))]
6293#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6294pub unsafe fn Q6_R_mpyacc_RlRh_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 {
6295    hexagon_M2_mpy_acc_sat_lh_s1(rx, rs, rt)
6296}
6297
6298/// `Rx32+=mpy(Rs32.l,Rt32.l):sat`
6299///
6300/// Instruction Type: M
6301/// Execution Slots: SLOT23
6302#[inline(always)]
6303#[cfg_attr(test, assert_instr(mpy))]
6304#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6305pub unsafe fn Q6_R_mpyacc_RlRl_sat(rx: i32, rs: i32, rt: i32) -> i32 {
6306    hexagon_M2_mpy_acc_sat_ll_s0(rx, rs, rt)
6307}
6308
6309/// `Rx32+=mpy(Rs32.l,Rt32.l):<<1:sat`
6310///
6311/// Instruction Type: M
6312/// Execution Slots: SLOT23
6313#[inline(always)]
6314#[cfg_attr(test, assert_instr(mpy))]
6315#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6316pub unsafe fn Q6_R_mpyacc_RlRl_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 {
6317    hexagon_M2_mpy_acc_sat_ll_s1(rx, rs, rt)
6318}
6319
6320/// `Rd32=mpy(Rs32.h,Rt32.h)`
6321///
6322/// Instruction Type: M
6323/// Execution Slots: SLOT23
6324#[inline(always)]
6325#[cfg_attr(test, assert_instr(mpy))]
6326#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6327pub unsafe fn Q6_R_mpy_RhRh(rs: i32, rt: i32) -> i32 {
6328    hexagon_M2_mpy_hh_s0(rs, rt)
6329}
6330
6331/// `Rd32=mpy(Rs32.h,Rt32.h):<<1`
6332///
6333/// Instruction Type: M
6334/// Execution Slots: SLOT23
6335#[inline(always)]
6336#[cfg_attr(test, assert_instr(mpy))]
6337#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6338pub unsafe fn Q6_R_mpy_RhRh_s1(rs: i32, rt: i32) -> i32 {
6339    hexagon_M2_mpy_hh_s1(rs, rt)
6340}
6341
6342/// `Rd32=mpy(Rs32.h,Rt32.l)`
6343///
6344/// Instruction Type: M
6345/// Execution Slots: SLOT23
6346#[inline(always)]
6347#[cfg_attr(test, assert_instr(mpy))]
6348#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6349pub unsafe fn Q6_R_mpy_RhRl(rs: i32, rt: i32) -> i32 {
6350    hexagon_M2_mpy_hl_s0(rs, rt)
6351}
6352
6353/// `Rd32=mpy(Rs32.h,Rt32.l):<<1`
6354///
6355/// Instruction Type: M
6356/// Execution Slots: SLOT23
6357#[inline(always)]
6358#[cfg_attr(test, assert_instr(mpy))]
6359#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6360pub unsafe fn Q6_R_mpy_RhRl_s1(rs: i32, rt: i32) -> i32 {
6361    hexagon_M2_mpy_hl_s1(rs, rt)
6362}
6363
6364/// `Rd32=mpy(Rs32.l,Rt32.h)`
6365///
6366/// Instruction Type: M
6367/// Execution Slots: SLOT23
6368#[inline(always)]
6369#[cfg_attr(test, assert_instr(mpy))]
6370#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6371pub unsafe fn Q6_R_mpy_RlRh(rs: i32, rt: i32) -> i32 {
6372    hexagon_M2_mpy_lh_s0(rs, rt)
6373}
6374
6375/// `Rd32=mpy(Rs32.l,Rt32.h):<<1`
6376///
6377/// Instruction Type: M
6378/// Execution Slots: SLOT23
6379#[inline(always)]
6380#[cfg_attr(test, assert_instr(mpy))]
6381#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6382pub unsafe fn Q6_R_mpy_RlRh_s1(rs: i32, rt: i32) -> i32 {
6383    hexagon_M2_mpy_lh_s1(rs, rt)
6384}
6385
6386/// `Rd32=mpy(Rs32.l,Rt32.l)`
6387///
6388/// Instruction Type: M
6389/// Execution Slots: SLOT23
6390#[inline(always)]
6391#[cfg_attr(test, assert_instr(mpy))]
6392#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6393pub unsafe fn Q6_R_mpy_RlRl(rs: i32, rt: i32) -> i32 {
6394    hexagon_M2_mpy_ll_s0(rs, rt)
6395}
6396
6397/// `Rd32=mpy(Rs32.l,Rt32.l):<<1`
6398///
6399/// Instruction Type: M
6400/// Execution Slots: SLOT23
6401#[inline(always)]
6402#[cfg_attr(test, assert_instr(mpy))]
6403#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6404pub unsafe fn Q6_R_mpy_RlRl_s1(rs: i32, rt: i32) -> i32 {
6405    hexagon_M2_mpy_ll_s1(rs, rt)
6406}
6407
6408/// `Rx32-=mpy(Rs32.h,Rt32.h)`
6409///
6410/// Instruction Type: M
6411/// Execution Slots: SLOT23
6412#[inline(always)]
6413#[cfg_attr(test, assert_instr(mpy))]
6414#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6415pub unsafe fn Q6_R_mpynac_RhRh(rx: i32, rs: i32, rt: i32) -> i32 {
6416    hexagon_M2_mpy_nac_hh_s0(rx, rs, rt)
6417}
6418
6419/// `Rx32-=mpy(Rs32.h,Rt32.h):<<1`
6420///
6421/// Instruction Type: M
6422/// Execution Slots: SLOT23
6423#[inline(always)]
6424#[cfg_attr(test, assert_instr(mpy))]
6425#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6426pub unsafe fn Q6_R_mpynac_RhRh_s1(rx: i32, rs: i32, rt: i32) -> i32 {
6427    hexagon_M2_mpy_nac_hh_s1(rx, rs, rt)
6428}
6429
6430/// `Rx32-=mpy(Rs32.h,Rt32.l)`
6431///
6432/// Instruction Type: M
6433/// Execution Slots: SLOT23
6434#[inline(always)]
6435#[cfg_attr(test, assert_instr(mpy))]
6436#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6437pub unsafe fn Q6_R_mpynac_RhRl(rx: i32, rs: i32, rt: i32) -> i32 {
6438    hexagon_M2_mpy_nac_hl_s0(rx, rs, rt)
6439}
6440
6441/// `Rx32-=mpy(Rs32.h,Rt32.l):<<1`
6442///
6443/// Instruction Type: M
6444/// Execution Slots: SLOT23
6445#[inline(always)]
6446#[cfg_attr(test, assert_instr(mpy))]
6447#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6448pub unsafe fn Q6_R_mpynac_RhRl_s1(rx: i32, rs: i32, rt: i32) -> i32 {
6449    hexagon_M2_mpy_nac_hl_s1(rx, rs, rt)
6450}
6451
6452/// `Rx32-=mpy(Rs32.l,Rt32.h)`
6453///
6454/// Instruction Type: M
6455/// Execution Slots: SLOT23
6456#[inline(always)]
6457#[cfg_attr(test, assert_instr(mpy))]
6458#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6459pub unsafe fn Q6_R_mpynac_RlRh(rx: i32, rs: i32, rt: i32) -> i32 {
6460    hexagon_M2_mpy_nac_lh_s0(rx, rs, rt)
6461}
6462
6463/// `Rx32-=mpy(Rs32.l,Rt32.h):<<1`
6464///
6465/// Instruction Type: M
6466/// Execution Slots: SLOT23
6467#[inline(always)]
6468#[cfg_attr(test, assert_instr(mpy))]
6469#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6470pub unsafe fn Q6_R_mpynac_RlRh_s1(rx: i32, rs: i32, rt: i32) -> i32 {
6471    hexagon_M2_mpy_nac_lh_s1(rx, rs, rt)
6472}
6473
6474/// `Rx32-=mpy(Rs32.l,Rt32.l)`
6475///
6476/// Instruction Type: M
6477/// Execution Slots: SLOT23
6478#[inline(always)]
6479#[cfg_attr(test, assert_instr(mpy))]
6480#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6481pub unsafe fn Q6_R_mpynac_RlRl(rx: i32, rs: i32, rt: i32) -> i32 {
6482    hexagon_M2_mpy_nac_ll_s0(rx, rs, rt)
6483}
6484
6485/// `Rx32-=mpy(Rs32.l,Rt32.l):<<1`
6486///
6487/// Instruction Type: M
6488/// Execution Slots: SLOT23
6489#[inline(always)]
6490#[cfg_attr(test, assert_instr(mpy))]
6491#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6492pub unsafe fn Q6_R_mpynac_RlRl_s1(rx: i32, rs: i32, rt: i32) -> i32 {
6493    hexagon_M2_mpy_nac_ll_s1(rx, rs, rt)
6494}
6495
6496/// `Rx32-=mpy(Rs32.h,Rt32.h):sat`
6497///
6498/// Instruction Type: M
6499/// Execution Slots: SLOT23
6500#[inline(always)]
6501#[cfg_attr(test, assert_instr(mpy))]
6502#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6503pub unsafe fn Q6_R_mpynac_RhRh_sat(rx: i32, rs: i32, rt: i32) -> i32 {
6504    hexagon_M2_mpy_nac_sat_hh_s0(rx, rs, rt)
6505}
6506
6507/// `Rx32-=mpy(Rs32.h,Rt32.h):<<1:sat`
6508///
6509/// Instruction Type: M
6510/// Execution Slots: SLOT23
6511#[inline(always)]
6512#[cfg_attr(test, assert_instr(mpy))]
6513#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6514pub unsafe fn Q6_R_mpynac_RhRh_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 {
6515    hexagon_M2_mpy_nac_sat_hh_s1(rx, rs, rt)
6516}
6517
6518/// `Rx32-=mpy(Rs32.h,Rt32.l):sat`
6519///
6520/// Instruction Type: M
6521/// Execution Slots: SLOT23
6522#[inline(always)]
6523#[cfg_attr(test, assert_instr(mpy))]
6524#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6525pub unsafe fn Q6_R_mpynac_RhRl_sat(rx: i32, rs: i32, rt: i32) -> i32 {
6526    hexagon_M2_mpy_nac_sat_hl_s0(rx, rs, rt)
6527}
6528
6529/// `Rx32-=mpy(Rs32.h,Rt32.l):<<1:sat`
6530///
6531/// Instruction Type: M
6532/// Execution Slots: SLOT23
6533#[inline(always)]
6534#[cfg_attr(test, assert_instr(mpy))]
6535#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6536pub unsafe fn Q6_R_mpynac_RhRl_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 {
6537    hexagon_M2_mpy_nac_sat_hl_s1(rx, rs, rt)
6538}
6539
6540/// `Rx32-=mpy(Rs32.l,Rt32.h):sat`
6541///
6542/// Instruction Type: M
6543/// Execution Slots: SLOT23
6544#[inline(always)]
6545#[cfg_attr(test, assert_instr(mpy))]
6546#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6547pub unsafe fn Q6_R_mpynac_RlRh_sat(rx: i32, rs: i32, rt: i32) -> i32 {
6548    hexagon_M2_mpy_nac_sat_lh_s0(rx, rs, rt)
6549}
6550
6551/// `Rx32-=mpy(Rs32.l,Rt32.h):<<1:sat`
6552///
6553/// Instruction Type: M
6554/// Execution Slots: SLOT23
6555#[inline(always)]
6556#[cfg_attr(test, assert_instr(mpy))]
6557#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6558pub unsafe fn Q6_R_mpynac_RlRh_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 {
6559    hexagon_M2_mpy_nac_sat_lh_s1(rx, rs, rt)
6560}
6561
6562/// `Rx32-=mpy(Rs32.l,Rt32.l):sat`
6563///
6564/// Instruction Type: M
6565/// Execution Slots: SLOT23
6566#[inline(always)]
6567#[cfg_attr(test, assert_instr(mpy))]
6568#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6569pub unsafe fn Q6_R_mpynac_RlRl_sat(rx: i32, rs: i32, rt: i32) -> i32 {
6570    hexagon_M2_mpy_nac_sat_ll_s0(rx, rs, rt)
6571}
6572
6573/// `Rx32-=mpy(Rs32.l,Rt32.l):<<1:sat`
6574///
6575/// Instruction Type: M
6576/// Execution Slots: SLOT23
6577#[inline(always)]
6578#[cfg_attr(test, assert_instr(mpy))]
6579#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6580pub unsafe fn Q6_R_mpynac_RlRl_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 {
6581    hexagon_M2_mpy_nac_sat_ll_s1(rx, rs, rt)
6582}
6583
6584/// `Rd32=mpy(Rs32.h,Rt32.h):rnd`
6585///
6586/// Instruction Type: M
6587/// Execution Slots: SLOT23
6588#[inline(always)]
6589#[cfg_attr(test, assert_instr(mpy))]
6590#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6591pub unsafe fn Q6_R_mpy_RhRh_rnd(rs: i32, rt: i32) -> i32 {
6592    hexagon_M2_mpy_rnd_hh_s0(rs, rt)
6593}
6594
6595/// `Rd32=mpy(Rs32.h,Rt32.h):<<1:rnd`
6596///
6597/// Instruction Type: M
6598/// Execution Slots: SLOT23
6599#[inline(always)]
6600#[cfg_attr(test, assert_instr(mpy))]
6601#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6602pub unsafe fn Q6_R_mpy_RhRh_s1_rnd(rs: i32, rt: i32) -> i32 {
6603    hexagon_M2_mpy_rnd_hh_s1(rs, rt)
6604}
6605
6606/// `Rd32=mpy(Rs32.h,Rt32.l):rnd`
6607///
6608/// Instruction Type: M
6609/// Execution Slots: SLOT23
6610#[inline(always)]
6611#[cfg_attr(test, assert_instr(mpy))]
6612#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6613pub unsafe fn Q6_R_mpy_RhRl_rnd(rs: i32, rt: i32) -> i32 {
6614    hexagon_M2_mpy_rnd_hl_s0(rs, rt)
6615}
6616
6617/// `Rd32=mpy(Rs32.h,Rt32.l):<<1:rnd`
6618///
6619/// Instruction Type: M
6620/// Execution Slots: SLOT23
6621#[inline(always)]
6622#[cfg_attr(test, assert_instr(mpy))]
6623#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6624pub unsafe fn Q6_R_mpy_RhRl_s1_rnd(rs: i32, rt: i32) -> i32 {
6625    hexagon_M2_mpy_rnd_hl_s1(rs, rt)
6626}
6627
6628/// `Rd32=mpy(Rs32.l,Rt32.h):rnd`
6629///
6630/// Instruction Type: M
6631/// Execution Slots: SLOT23
6632#[inline(always)]
6633#[cfg_attr(test, assert_instr(mpy))]
6634#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6635pub unsafe fn Q6_R_mpy_RlRh_rnd(rs: i32, rt: i32) -> i32 {
6636    hexagon_M2_mpy_rnd_lh_s0(rs, rt)
6637}
6638
6639/// `Rd32=mpy(Rs32.l,Rt32.h):<<1:rnd`
6640///
6641/// Instruction Type: M
6642/// Execution Slots: SLOT23
6643#[inline(always)]
6644#[cfg_attr(test, assert_instr(mpy))]
6645#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6646pub unsafe fn Q6_R_mpy_RlRh_s1_rnd(rs: i32, rt: i32) -> i32 {
6647    hexagon_M2_mpy_rnd_lh_s1(rs, rt)
6648}
6649
6650/// `Rd32=mpy(Rs32.l,Rt32.l):rnd`
6651///
6652/// Instruction Type: M
6653/// Execution Slots: SLOT23
6654#[inline(always)]
6655#[cfg_attr(test, assert_instr(mpy))]
6656#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6657pub unsafe fn Q6_R_mpy_RlRl_rnd(rs: i32, rt: i32) -> i32 {
6658    hexagon_M2_mpy_rnd_ll_s0(rs, rt)
6659}
6660
6661/// `Rd32=mpy(Rs32.l,Rt32.l):<<1:rnd`
6662///
6663/// Instruction Type: M
6664/// Execution Slots: SLOT23
6665#[inline(always)]
6666#[cfg_attr(test, assert_instr(mpy))]
6667#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6668pub unsafe fn Q6_R_mpy_RlRl_s1_rnd(rs: i32, rt: i32) -> i32 {
6669    hexagon_M2_mpy_rnd_ll_s1(rs, rt)
6670}
6671
6672/// `Rd32=mpy(Rs32.h,Rt32.h):sat`
6673///
6674/// Instruction Type: M
6675/// Execution Slots: SLOT23
6676#[inline(always)]
6677#[cfg_attr(test, assert_instr(mpy))]
6678#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6679pub unsafe fn Q6_R_mpy_RhRh_sat(rs: i32, rt: i32) -> i32 {
6680    hexagon_M2_mpy_sat_hh_s0(rs, rt)
6681}
6682
6683/// `Rd32=mpy(Rs32.h,Rt32.h):<<1:sat`
6684///
6685/// Instruction Type: M
6686/// Execution Slots: SLOT23
6687#[inline(always)]
6688#[cfg_attr(test, assert_instr(mpy))]
6689#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6690pub unsafe fn Q6_R_mpy_RhRh_s1_sat(rs: i32, rt: i32) -> i32 {
6691    hexagon_M2_mpy_sat_hh_s1(rs, rt)
6692}
6693
6694/// `Rd32=mpy(Rs32.h,Rt32.l):sat`
6695///
6696/// Instruction Type: M
6697/// Execution Slots: SLOT23
6698#[inline(always)]
6699#[cfg_attr(test, assert_instr(mpy))]
6700#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6701pub unsafe fn Q6_R_mpy_RhRl_sat(rs: i32, rt: i32) -> i32 {
6702    hexagon_M2_mpy_sat_hl_s0(rs, rt)
6703}
6704
6705/// `Rd32=mpy(Rs32.h,Rt32.l):<<1:sat`
6706///
6707/// Instruction Type: M
6708/// Execution Slots: SLOT23
6709#[inline(always)]
6710#[cfg_attr(test, assert_instr(mpy))]
6711#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6712pub unsafe fn Q6_R_mpy_RhRl_s1_sat(rs: i32, rt: i32) -> i32 {
6713    hexagon_M2_mpy_sat_hl_s1(rs, rt)
6714}
6715
6716/// `Rd32=mpy(Rs32.l,Rt32.h):sat`
6717///
6718/// Instruction Type: M
6719/// Execution Slots: SLOT23
6720#[inline(always)]
6721#[cfg_attr(test, assert_instr(mpy))]
6722#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6723pub unsafe fn Q6_R_mpy_RlRh_sat(rs: i32, rt: i32) -> i32 {
6724    hexagon_M2_mpy_sat_lh_s0(rs, rt)
6725}
6726
6727/// `Rd32=mpy(Rs32.l,Rt32.h):<<1:sat`
6728///
6729/// Instruction Type: M
6730/// Execution Slots: SLOT23
6731#[inline(always)]
6732#[cfg_attr(test, assert_instr(mpy))]
6733#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6734pub unsafe fn Q6_R_mpy_RlRh_s1_sat(rs: i32, rt: i32) -> i32 {
6735    hexagon_M2_mpy_sat_lh_s1(rs, rt)
6736}
6737
6738/// `Rd32=mpy(Rs32.l,Rt32.l):sat`
6739///
6740/// Instruction Type: M
6741/// Execution Slots: SLOT23
6742#[inline(always)]
6743#[cfg_attr(test, assert_instr(mpy))]
6744#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6745pub unsafe fn Q6_R_mpy_RlRl_sat(rs: i32, rt: i32) -> i32 {
6746    hexagon_M2_mpy_sat_ll_s0(rs, rt)
6747}
6748
6749/// `Rd32=mpy(Rs32.l,Rt32.l):<<1:sat`
6750///
6751/// Instruction Type: M
6752/// Execution Slots: SLOT23
6753#[inline(always)]
6754#[cfg_attr(test, assert_instr(mpy))]
6755#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6756pub unsafe fn Q6_R_mpy_RlRl_s1_sat(rs: i32, rt: i32) -> i32 {
6757    hexagon_M2_mpy_sat_ll_s1(rs, rt)
6758}
6759
6760/// `Rd32=mpy(Rs32.h,Rt32.h):rnd:sat`
6761///
6762/// Instruction Type: M
6763/// Execution Slots: SLOT23
6764#[inline(always)]
6765#[cfg_attr(test, assert_instr(mpy))]
6766#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6767pub unsafe fn Q6_R_mpy_RhRh_rnd_sat(rs: i32, rt: i32) -> i32 {
6768    hexagon_M2_mpy_sat_rnd_hh_s0(rs, rt)
6769}
6770
6771/// `Rd32=mpy(Rs32.h,Rt32.h):<<1:rnd:sat`
6772///
6773/// Instruction Type: M
6774/// Execution Slots: SLOT23
6775#[inline(always)]
6776#[cfg_attr(test, assert_instr(mpy))]
6777#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6778pub unsafe fn Q6_R_mpy_RhRh_s1_rnd_sat(rs: i32, rt: i32) -> i32 {
6779    hexagon_M2_mpy_sat_rnd_hh_s1(rs, rt)
6780}
6781
6782/// `Rd32=mpy(Rs32.h,Rt32.l):rnd:sat`
6783///
6784/// Instruction Type: M
6785/// Execution Slots: SLOT23
6786#[inline(always)]
6787#[cfg_attr(test, assert_instr(mpy))]
6788#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6789pub unsafe fn Q6_R_mpy_RhRl_rnd_sat(rs: i32, rt: i32) -> i32 {
6790    hexagon_M2_mpy_sat_rnd_hl_s0(rs, rt)
6791}
6792
6793/// `Rd32=mpy(Rs32.h,Rt32.l):<<1:rnd:sat`
6794///
6795/// Instruction Type: M
6796/// Execution Slots: SLOT23
6797#[inline(always)]
6798#[cfg_attr(test, assert_instr(mpy))]
6799#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6800pub unsafe fn Q6_R_mpy_RhRl_s1_rnd_sat(rs: i32, rt: i32) -> i32 {
6801    hexagon_M2_mpy_sat_rnd_hl_s1(rs, rt)
6802}
6803
6804/// `Rd32=mpy(Rs32.l,Rt32.h):rnd:sat`
6805///
6806/// Instruction Type: M
6807/// Execution Slots: SLOT23
6808#[inline(always)]
6809#[cfg_attr(test, assert_instr(mpy))]
6810#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6811pub unsafe fn Q6_R_mpy_RlRh_rnd_sat(rs: i32, rt: i32) -> i32 {
6812    hexagon_M2_mpy_sat_rnd_lh_s0(rs, rt)
6813}
6814
6815/// `Rd32=mpy(Rs32.l,Rt32.h):<<1:rnd:sat`
6816///
6817/// Instruction Type: M
6818/// Execution Slots: SLOT23
6819#[inline(always)]
6820#[cfg_attr(test, assert_instr(mpy))]
6821#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6822pub unsafe fn Q6_R_mpy_RlRh_s1_rnd_sat(rs: i32, rt: i32) -> i32 {
6823    hexagon_M2_mpy_sat_rnd_lh_s1(rs, rt)
6824}
6825
6826/// `Rd32=mpy(Rs32.l,Rt32.l):rnd:sat`
6827///
6828/// Instruction Type: M
6829/// Execution Slots: SLOT23
6830#[inline(always)]
6831#[cfg_attr(test, assert_instr(mpy))]
6832#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6833pub unsafe fn Q6_R_mpy_RlRl_rnd_sat(rs: i32, rt: i32) -> i32 {
6834    hexagon_M2_mpy_sat_rnd_ll_s0(rs, rt)
6835}
6836
6837/// `Rd32=mpy(Rs32.l,Rt32.l):<<1:rnd:sat`
6838///
6839/// Instruction Type: M
6840/// Execution Slots: SLOT23
6841#[inline(always)]
6842#[cfg_attr(test, assert_instr(mpy))]
6843#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6844pub unsafe fn Q6_R_mpy_RlRl_s1_rnd_sat(rs: i32, rt: i32) -> i32 {
6845    hexagon_M2_mpy_sat_rnd_ll_s1(rs, rt)
6846}
6847
6848/// `Rd32=mpy(Rs32,Rt32)`
6849///
6850/// Instruction Type: M
6851/// Execution Slots: SLOT23
6852#[inline(always)]
6853#[cfg_attr(test, assert_instr(mpy))]
6854#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6855pub unsafe fn Q6_R_mpy_RR(rs: i32, rt: i32) -> i32 {
6856    hexagon_M2_mpy_up(rs, rt)
6857}
6858
6859/// `Rd32=mpy(Rs32,Rt32):<<1`
6860///
6861/// Instruction Type: M
6862/// Execution Slots: SLOT23
6863#[inline(always)]
6864#[cfg_attr(test, assert_instr(mpy))]
6865#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6866pub unsafe fn Q6_R_mpy_RR_s1(rs: i32, rt: i32) -> i32 {
6867    hexagon_M2_mpy_up_s1(rs, rt)
6868}
6869
6870/// `Rd32=mpy(Rs32,Rt32):<<1:sat`
6871///
6872/// Instruction Type: M
6873/// Execution Slots: SLOT23
6874#[inline(always)]
6875#[cfg_attr(test, assert_instr(mpy))]
6876#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6877pub unsafe fn Q6_R_mpy_RR_s1_sat(rs: i32, rt: i32) -> i32 {
6878    hexagon_M2_mpy_up_s1_sat(rs, rt)
6879}
6880
6881/// `Rxx32+=mpy(Rs32.h,Rt32.h)`
6882///
6883/// Instruction Type: M
6884/// Execution Slots: SLOT23
6885#[inline(always)]
6886#[cfg_attr(test, assert_instr(mpy))]
6887#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6888pub unsafe fn Q6_P_mpyacc_RhRh(rxx: i64, rs: i32, rt: i32) -> i64 {
6889    hexagon_M2_mpyd_acc_hh_s0(rxx, rs, rt)
6890}
6891
6892/// `Rxx32+=mpy(Rs32.h,Rt32.h):<<1`
6893///
6894/// Instruction Type: M
6895/// Execution Slots: SLOT23
6896#[inline(always)]
6897#[cfg_attr(test, assert_instr(mpy))]
6898#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6899pub unsafe fn Q6_P_mpyacc_RhRh_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
6900    hexagon_M2_mpyd_acc_hh_s1(rxx, rs, rt)
6901}
6902
6903/// `Rxx32+=mpy(Rs32.h,Rt32.l)`
6904///
6905/// Instruction Type: M
6906/// Execution Slots: SLOT23
6907#[inline(always)]
6908#[cfg_attr(test, assert_instr(mpy))]
6909#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6910pub unsafe fn Q6_P_mpyacc_RhRl(rxx: i64, rs: i32, rt: i32) -> i64 {
6911    hexagon_M2_mpyd_acc_hl_s0(rxx, rs, rt)
6912}
6913
6914/// `Rxx32+=mpy(Rs32.h,Rt32.l):<<1`
6915///
6916/// Instruction Type: M
6917/// Execution Slots: SLOT23
6918#[inline(always)]
6919#[cfg_attr(test, assert_instr(mpy))]
6920#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6921pub unsafe fn Q6_P_mpyacc_RhRl_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
6922    hexagon_M2_mpyd_acc_hl_s1(rxx, rs, rt)
6923}
6924
6925/// `Rxx32+=mpy(Rs32.l,Rt32.h)`
6926///
6927/// Instruction Type: M
6928/// Execution Slots: SLOT23
6929#[inline(always)]
6930#[cfg_attr(test, assert_instr(mpy))]
6931#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6932pub unsafe fn Q6_P_mpyacc_RlRh(rxx: i64, rs: i32, rt: i32) -> i64 {
6933    hexagon_M2_mpyd_acc_lh_s0(rxx, rs, rt)
6934}
6935
6936/// `Rxx32+=mpy(Rs32.l,Rt32.h):<<1`
6937///
6938/// Instruction Type: M
6939/// Execution Slots: SLOT23
6940#[inline(always)]
6941#[cfg_attr(test, assert_instr(mpy))]
6942#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6943pub unsafe fn Q6_P_mpyacc_RlRh_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
6944    hexagon_M2_mpyd_acc_lh_s1(rxx, rs, rt)
6945}
6946
6947/// `Rxx32+=mpy(Rs32.l,Rt32.l)`
6948///
6949/// Instruction Type: M
6950/// Execution Slots: SLOT23
6951#[inline(always)]
6952#[cfg_attr(test, assert_instr(mpy))]
6953#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6954pub unsafe fn Q6_P_mpyacc_RlRl(rxx: i64, rs: i32, rt: i32) -> i64 {
6955    hexagon_M2_mpyd_acc_ll_s0(rxx, rs, rt)
6956}
6957
6958/// `Rxx32+=mpy(Rs32.l,Rt32.l):<<1`
6959///
6960/// Instruction Type: M
6961/// Execution Slots: SLOT23
6962#[inline(always)]
6963#[cfg_attr(test, assert_instr(mpy))]
6964#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6965pub unsafe fn Q6_P_mpyacc_RlRl_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
6966    hexagon_M2_mpyd_acc_ll_s1(rxx, rs, rt)
6967}
6968
6969/// `Rdd32=mpy(Rs32.h,Rt32.h)`
6970///
6971/// Instruction Type: M
6972/// Execution Slots: SLOT23
6973#[inline(always)]
6974#[cfg_attr(test, assert_instr(mpy))]
6975#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6976pub unsafe fn Q6_P_mpy_RhRh(rs: i32, rt: i32) -> i64 {
6977    hexagon_M2_mpyd_hh_s0(rs, rt)
6978}
6979
6980/// `Rdd32=mpy(Rs32.h,Rt32.h):<<1`
6981///
6982/// Instruction Type: M
6983/// Execution Slots: SLOT23
6984#[inline(always)]
6985#[cfg_attr(test, assert_instr(mpy))]
6986#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6987pub unsafe fn Q6_P_mpy_RhRh_s1(rs: i32, rt: i32) -> i64 {
6988    hexagon_M2_mpyd_hh_s1(rs, rt)
6989}
6990
6991/// `Rdd32=mpy(Rs32.h,Rt32.l)`
6992///
6993/// Instruction Type: M
6994/// Execution Slots: SLOT23
6995#[inline(always)]
6996#[cfg_attr(test, assert_instr(mpy))]
6997#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6998pub unsafe fn Q6_P_mpy_RhRl(rs: i32, rt: i32) -> i64 {
6999    hexagon_M2_mpyd_hl_s0(rs, rt)
7000}
7001
7002/// `Rdd32=mpy(Rs32.h,Rt32.l):<<1`
7003///
7004/// Instruction Type: M
7005/// Execution Slots: SLOT23
7006#[inline(always)]
7007#[cfg_attr(test, assert_instr(mpy))]
7008#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7009pub unsafe fn Q6_P_mpy_RhRl_s1(rs: i32, rt: i32) -> i64 {
7010    hexagon_M2_mpyd_hl_s1(rs, rt)
7011}
7012
7013/// `Rdd32=mpy(Rs32.l,Rt32.h)`
7014///
7015/// Instruction Type: M
7016/// Execution Slots: SLOT23
7017#[inline(always)]
7018#[cfg_attr(test, assert_instr(mpy))]
7019#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7020pub unsafe fn Q6_P_mpy_RlRh(rs: i32, rt: i32) -> i64 {
7021    hexagon_M2_mpyd_lh_s0(rs, rt)
7022}
7023
7024/// `Rdd32=mpy(Rs32.l,Rt32.h):<<1`
7025///
7026/// Instruction Type: M
7027/// Execution Slots: SLOT23
7028#[inline(always)]
7029#[cfg_attr(test, assert_instr(mpy))]
7030#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7031pub unsafe fn Q6_P_mpy_RlRh_s1(rs: i32, rt: i32) -> i64 {
7032    hexagon_M2_mpyd_lh_s1(rs, rt)
7033}
7034
7035/// `Rdd32=mpy(Rs32.l,Rt32.l)`
7036///
7037/// Instruction Type: M
7038/// Execution Slots: SLOT23
7039#[inline(always)]
7040#[cfg_attr(test, assert_instr(mpy))]
7041#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7042pub unsafe fn Q6_P_mpy_RlRl(rs: i32, rt: i32) -> i64 {
7043    hexagon_M2_mpyd_ll_s0(rs, rt)
7044}
7045
7046/// `Rdd32=mpy(Rs32.l,Rt32.l):<<1`
7047///
7048/// Instruction Type: M
7049/// Execution Slots: SLOT23
7050#[inline(always)]
7051#[cfg_attr(test, assert_instr(mpy))]
7052#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7053pub unsafe fn Q6_P_mpy_RlRl_s1(rs: i32, rt: i32) -> i64 {
7054    hexagon_M2_mpyd_ll_s1(rs, rt)
7055}
7056
7057/// `Rxx32-=mpy(Rs32.h,Rt32.h)`
7058///
7059/// Instruction Type: M
7060/// Execution Slots: SLOT23
7061#[inline(always)]
7062#[cfg_attr(test, assert_instr(mpy))]
7063#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7064pub unsafe fn Q6_P_mpynac_RhRh(rxx: i64, rs: i32, rt: i32) -> i64 {
7065    hexagon_M2_mpyd_nac_hh_s0(rxx, rs, rt)
7066}
7067
7068/// `Rxx32-=mpy(Rs32.h,Rt32.h):<<1`
7069///
7070/// Instruction Type: M
7071/// Execution Slots: SLOT23
7072#[inline(always)]
7073#[cfg_attr(test, assert_instr(mpy))]
7074#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7075pub unsafe fn Q6_P_mpynac_RhRh_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
7076    hexagon_M2_mpyd_nac_hh_s1(rxx, rs, rt)
7077}
7078
7079/// `Rxx32-=mpy(Rs32.h,Rt32.l)`
7080///
7081/// Instruction Type: M
7082/// Execution Slots: SLOT23
7083#[inline(always)]
7084#[cfg_attr(test, assert_instr(mpy))]
7085#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7086pub unsafe fn Q6_P_mpynac_RhRl(rxx: i64, rs: i32, rt: i32) -> i64 {
7087    hexagon_M2_mpyd_nac_hl_s0(rxx, rs, rt)
7088}
7089
7090/// `Rxx32-=mpy(Rs32.h,Rt32.l):<<1`
7091///
7092/// Instruction Type: M
7093/// Execution Slots: SLOT23
7094#[inline(always)]
7095#[cfg_attr(test, assert_instr(mpy))]
7096#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7097pub unsafe fn Q6_P_mpynac_RhRl_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
7098    hexagon_M2_mpyd_nac_hl_s1(rxx, rs, rt)
7099}
7100
7101/// `Rxx32-=mpy(Rs32.l,Rt32.h)`
7102///
7103/// Instruction Type: M
7104/// Execution Slots: SLOT23
7105#[inline(always)]
7106#[cfg_attr(test, assert_instr(mpy))]
7107#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7108pub unsafe fn Q6_P_mpynac_RlRh(rxx: i64, rs: i32, rt: i32) -> i64 {
7109    hexagon_M2_mpyd_nac_lh_s0(rxx, rs, rt)
7110}
7111
7112/// `Rxx32-=mpy(Rs32.l,Rt32.h):<<1`
7113///
7114/// Instruction Type: M
7115/// Execution Slots: SLOT23
7116#[inline(always)]
7117#[cfg_attr(test, assert_instr(mpy))]
7118#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7119pub unsafe fn Q6_P_mpynac_RlRh_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
7120    hexagon_M2_mpyd_nac_lh_s1(rxx, rs, rt)
7121}
7122
7123/// `Rxx32-=mpy(Rs32.l,Rt32.l)`
7124///
7125/// Instruction Type: M
7126/// Execution Slots: SLOT23
7127#[inline(always)]
7128#[cfg_attr(test, assert_instr(mpy))]
7129#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7130pub unsafe fn Q6_P_mpynac_RlRl(rxx: i64, rs: i32, rt: i32) -> i64 {
7131    hexagon_M2_mpyd_nac_ll_s0(rxx, rs, rt)
7132}
7133
7134/// `Rxx32-=mpy(Rs32.l,Rt32.l):<<1`
7135///
7136/// Instruction Type: M
7137/// Execution Slots: SLOT23
7138#[inline(always)]
7139#[cfg_attr(test, assert_instr(mpy))]
7140#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7141pub unsafe fn Q6_P_mpynac_RlRl_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
7142    hexagon_M2_mpyd_nac_ll_s1(rxx, rs, rt)
7143}
7144
7145/// `Rdd32=mpy(Rs32.h,Rt32.h):rnd`
7146///
7147/// Instruction Type: M
7148/// Execution Slots: SLOT23
7149#[inline(always)]
7150#[cfg_attr(test, assert_instr(mpy))]
7151#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7152pub unsafe fn Q6_P_mpy_RhRh_rnd(rs: i32, rt: i32) -> i64 {
7153    hexagon_M2_mpyd_rnd_hh_s0(rs, rt)
7154}
7155
7156/// `Rdd32=mpy(Rs32.h,Rt32.h):<<1:rnd`
7157///
7158/// Instruction Type: M
7159/// Execution Slots: SLOT23
7160#[inline(always)]
7161#[cfg_attr(test, assert_instr(mpy))]
7162#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7163pub unsafe fn Q6_P_mpy_RhRh_s1_rnd(rs: i32, rt: i32) -> i64 {
7164    hexagon_M2_mpyd_rnd_hh_s1(rs, rt)
7165}
7166
7167/// `Rdd32=mpy(Rs32.h,Rt32.l):rnd`
7168///
7169/// Instruction Type: M
7170/// Execution Slots: SLOT23
7171#[inline(always)]
7172#[cfg_attr(test, assert_instr(mpy))]
7173#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7174pub unsafe fn Q6_P_mpy_RhRl_rnd(rs: i32, rt: i32) -> i64 {
7175    hexagon_M2_mpyd_rnd_hl_s0(rs, rt)
7176}
7177
7178/// `Rdd32=mpy(Rs32.h,Rt32.l):<<1:rnd`
7179///
7180/// Instruction Type: M
7181/// Execution Slots: SLOT23
7182#[inline(always)]
7183#[cfg_attr(test, assert_instr(mpy))]
7184#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7185pub unsafe fn Q6_P_mpy_RhRl_s1_rnd(rs: i32, rt: i32) -> i64 {
7186    hexagon_M2_mpyd_rnd_hl_s1(rs, rt)
7187}
7188
7189/// `Rdd32=mpy(Rs32.l,Rt32.h):rnd`
7190///
7191/// Instruction Type: M
7192/// Execution Slots: SLOT23
7193#[inline(always)]
7194#[cfg_attr(test, assert_instr(mpy))]
7195#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7196pub unsafe fn Q6_P_mpy_RlRh_rnd(rs: i32, rt: i32) -> i64 {
7197    hexagon_M2_mpyd_rnd_lh_s0(rs, rt)
7198}
7199
7200/// `Rdd32=mpy(Rs32.l,Rt32.h):<<1:rnd`
7201///
7202/// Instruction Type: M
7203/// Execution Slots: SLOT23
7204#[inline(always)]
7205#[cfg_attr(test, assert_instr(mpy))]
7206#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7207pub unsafe fn Q6_P_mpy_RlRh_s1_rnd(rs: i32, rt: i32) -> i64 {
7208    hexagon_M2_mpyd_rnd_lh_s1(rs, rt)
7209}
7210
7211/// `Rdd32=mpy(Rs32.l,Rt32.l):rnd`
7212///
7213/// Instruction Type: M
7214/// Execution Slots: SLOT23
7215#[inline(always)]
7216#[cfg_attr(test, assert_instr(mpy))]
7217#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7218pub unsafe fn Q6_P_mpy_RlRl_rnd(rs: i32, rt: i32) -> i64 {
7219    hexagon_M2_mpyd_rnd_ll_s0(rs, rt)
7220}
7221
7222/// `Rdd32=mpy(Rs32.l,Rt32.l):<<1:rnd`
7223///
7224/// Instruction Type: M
7225/// Execution Slots: SLOT23
7226#[inline(always)]
7227#[cfg_attr(test, assert_instr(mpy))]
7228#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7229pub unsafe fn Q6_P_mpy_RlRl_s1_rnd(rs: i32, rt: i32) -> i64 {
7230    hexagon_M2_mpyd_rnd_ll_s1(rs, rt)
7231}
7232
7233/// `Rd32=mpyi(Rs32,Rt32)`
7234///
7235/// Instruction Type: M
7236/// Execution Slots: SLOT23
7237#[inline(always)]
7238#[cfg_attr(test, assert_instr(mpyi))]
7239#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7240pub unsafe fn Q6_R_mpyi_RR(rs: i32, rt: i32) -> i32 {
7241    hexagon_M2_mpyi(rs, rt)
7242}
7243
7244/// `Rd32=mpyi(Rs32,#m9)`
7245///
7246/// Instruction Type: M
7247/// Execution Slots: SLOT0123
7248#[inline(always)]
7249#[cfg_attr(test, assert_instr(mpyi))]
7250#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7251pub unsafe fn Q6_R_mpyi_RI(rs: i32, im9: i32) -> i32 {
7252    hexagon_M2_mpysmi(rs, im9)
7253}
7254
7255/// `Rd32=mpysu(Rs32,Rt32)`
7256///
7257/// Instruction Type: M
7258/// Execution Slots: SLOT23
7259#[inline(always)]
7260#[cfg_attr(test, assert_instr(mpysu))]
7261#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7262pub unsafe fn Q6_R_mpysu_RR(rs: i32, rt: i32) -> i32 {
7263    hexagon_M2_mpysu_up(rs, rt)
7264}
7265
7266/// `Rx32+=mpyu(Rs32.h,Rt32.h)`
7267///
7268/// Instruction Type: M
7269/// Execution Slots: SLOT23
7270#[inline(always)]
7271#[cfg_attr(test, assert_instr(mpyu))]
7272#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7273pub unsafe fn Q6_R_mpyuacc_RhRh(rx: i32, rs: i32, rt: i32) -> i32 {
7274    hexagon_M2_mpyu_acc_hh_s0(rx, rs, rt)
7275}
7276
7277/// `Rx32+=mpyu(Rs32.h,Rt32.h):<<1`
7278///
7279/// Instruction Type: M
7280/// Execution Slots: SLOT23
7281#[inline(always)]
7282#[cfg_attr(test, assert_instr(mpyu))]
7283#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7284pub unsafe fn Q6_R_mpyuacc_RhRh_s1(rx: i32, rs: i32, rt: i32) -> i32 {
7285    hexagon_M2_mpyu_acc_hh_s1(rx, rs, rt)
7286}
7287
7288/// `Rx32+=mpyu(Rs32.h,Rt32.l)`
7289///
7290/// Instruction Type: M
7291/// Execution Slots: SLOT23
7292#[inline(always)]
7293#[cfg_attr(test, assert_instr(mpyu))]
7294#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7295pub unsafe fn Q6_R_mpyuacc_RhRl(rx: i32, rs: i32, rt: i32) -> i32 {
7296    hexagon_M2_mpyu_acc_hl_s0(rx, rs, rt)
7297}
7298
7299/// `Rx32+=mpyu(Rs32.h,Rt32.l):<<1`
7300///
7301/// Instruction Type: M
7302/// Execution Slots: SLOT23
7303#[inline(always)]
7304#[cfg_attr(test, assert_instr(mpyu))]
7305#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7306pub unsafe fn Q6_R_mpyuacc_RhRl_s1(rx: i32, rs: i32, rt: i32) -> i32 {
7307    hexagon_M2_mpyu_acc_hl_s1(rx, rs, rt)
7308}
7309
7310/// `Rx32+=mpyu(Rs32.l,Rt32.h)`
7311///
7312/// Instruction Type: M
7313/// Execution Slots: SLOT23
7314#[inline(always)]
7315#[cfg_attr(test, assert_instr(mpyu))]
7316#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7317pub unsafe fn Q6_R_mpyuacc_RlRh(rx: i32, rs: i32, rt: i32) -> i32 {
7318    hexagon_M2_mpyu_acc_lh_s0(rx, rs, rt)
7319}
7320
7321/// `Rx32+=mpyu(Rs32.l,Rt32.h):<<1`
7322///
7323/// Instruction Type: M
7324/// Execution Slots: SLOT23
7325#[inline(always)]
7326#[cfg_attr(test, assert_instr(mpyu))]
7327#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7328pub unsafe fn Q6_R_mpyuacc_RlRh_s1(rx: i32, rs: i32, rt: i32) -> i32 {
7329    hexagon_M2_mpyu_acc_lh_s1(rx, rs, rt)
7330}
7331
7332/// `Rx32+=mpyu(Rs32.l,Rt32.l)`
7333///
7334/// Instruction Type: M
7335/// Execution Slots: SLOT23
7336#[inline(always)]
7337#[cfg_attr(test, assert_instr(mpyu))]
7338#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7339pub unsafe fn Q6_R_mpyuacc_RlRl(rx: i32, rs: i32, rt: i32) -> i32 {
7340    hexagon_M2_mpyu_acc_ll_s0(rx, rs, rt)
7341}
7342
7343/// `Rx32+=mpyu(Rs32.l,Rt32.l):<<1`
7344///
7345/// Instruction Type: M
7346/// Execution Slots: SLOT23
7347#[inline(always)]
7348#[cfg_attr(test, assert_instr(mpyu))]
7349#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7350pub unsafe fn Q6_R_mpyuacc_RlRl_s1(rx: i32, rs: i32, rt: i32) -> i32 {
7351    hexagon_M2_mpyu_acc_ll_s1(rx, rs, rt)
7352}
7353
7354/// `Rd32=mpyu(Rs32.h,Rt32.h)`
7355///
7356/// Instruction Type: M
7357/// Execution Slots: SLOT23
7358#[inline(always)]
7359#[cfg_attr(test, assert_instr(mpyu))]
7360#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7361pub unsafe fn Q6_R_mpyu_RhRh(rs: i32, rt: i32) -> i32 {
7362    hexagon_M2_mpyu_hh_s0(rs, rt)
7363}
7364
7365/// `Rd32=mpyu(Rs32.h,Rt32.h):<<1`
7366///
7367/// Instruction Type: M
7368/// Execution Slots: SLOT23
7369#[inline(always)]
7370#[cfg_attr(test, assert_instr(mpyu))]
7371#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7372pub unsafe fn Q6_R_mpyu_RhRh_s1(rs: i32, rt: i32) -> i32 {
7373    hexagon_M2_mpyu_hh_s1(rs, rt)
7374}
7375
7376/// `Rd32=mpyu(Rs32.h,Rt32.l)`
7377///
7378/// Instruction Type: M
7379/// Execution Slots: SLOT23
7380#[inline(always)]
7381#[cfg_attr(test, assert_instr(mpyu))]
7382#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7383pub unsafe fn Q6_R_mpyu_RhRl(rs: i32, rt: i32) -> i32 {
7384    hexagon_M2_mpyu_hl_s0(rs, rt)
7385}
7386
7387/// `Rd32=mpyu(Rs32.h,Rt32.l):<<1`
7388///
7389/// Instruction Type: M
7390/// Execution Slots: SLOT23
7391#[inline(always)]
7392#[cfg_attr(test, assert_instr(mpyu))]
7393#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7394pub unsafe fn Q6_R_mpyu_RhRl_s1(rs: i32, rt: i32) -> i32 {
7395    hexagon_M2_mpyu_hl_s1(rs, rt)
7396}
7397
7398/// `Rd32=mpyu(Rs32.l,Rt32.h)`
7399///
7400/// Instruction Type: M
7401/// Execution Slots: SLOT23
7402#[inline(always)]
7403#[cfg_attr(test, assert_instr(mpyu))]
7404#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7405pub unsafe fn Q6_R_mpyu_RlRh(rs: i32, rt: i32) -> i32 {
7406    hexagon_M2_mpyu_lh_s0(rs, rt)
7407}
7408
7409/// `Rd32=mpyu(Rs32.l,Rt32.h):<<1`
7410///
7411/// Instruction Type: M
7412/// Execution Slots: SLOT23
7413#[inline(always)]
7414#[cfg_attr(test, assert_instr(mpyu))]
7415#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7416pub unsafe fn Q6_R_mpyu_RlRh_s1(rs: i32, rt: i32) -> i32 {
7417    hexagon_M2_mpyu_lh_s1(rs, rt)
7418}
7419
7420/// `Rd32=mpyu(Rs32.l,Rt32.l)`
7421///
7422/// Instruction Type: M
7423/// Execution Slots: SLOT23
7424#[inline(always)]
7425#[cfg_attr(test, assert_instr(mpyu))]
7426#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7427pub unsafe fn Q6_R_mpyu_RlRl(rs: i32, rt: i32) -> i32 {
7428    hexagon_M2_mpyu_ll_s0(rs, rt)
7429}
7430
7431/// `Rd32=mpyu(Rs32.l,Rt32.l):<<1`
7432///
7433/// Instruction Type: M
7434/// Execution Slots: SLOT23
7435#[inline(always)]
7436#[cfg_attr(test, assert_instr(mpyu))]
7437#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7438pub unsafe fn Q6_R_mpyu_RlRl_s1(rs: i32, rt: i32) -> i32 {
7439    hexagon_M2_mpyu_ll_s1(rs, rt)
7440}
7441
7442/// `Rx32-=mpyu(Rs32.h,Rt32.h)`
7443///
7444/// Instruction Type: M
7445/// Execution Slots: SLOT23
7446#[inline(always)]
7447#[cfg_attr(test, assert_instr(mpyu))]
7448#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7449pub unsafe fn Q6_R_mpyunac_RhRh(rx: i32, rs: i32, rt: i32) -> i32 {
7450    hexagon_M2_mpyu_nac_hh_s0(rx, rs, rt)
7451}
7452
7453/// `Rx32-=mpyu(Rs32.h,Rt32.h):<<1`
7454///
7455/// Instruction Type: M
7456/// Execution Slots: SLOT23
7457#[inline(always)]
7458#[cfg_attr(test, assert_instr(mpyu))]
7459#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7460pub unsafe fn Q6_R_mpyunac_RhRh_s1(rx: i32, rs: i32, rt: i32) -> i32 {
7461    hexagon_M2_mpyu_nac_hh_s1(rx, rs, rt)
7462}
7463
7464/// `Rx32-=mpyu(Rs32.h,Rt32.l)`
7465///
7466/// Instruction Type: M
7467/// Execution Slots: SLOT23
7468#[inline(always)]
7469#[cfg_attr(test, assert_instr(mpyu))]
7470#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7471pub unsafe fn Q6_R_mpyunac_RhRl(rx: i32, rs: i32, rt: i32) -> i32 {
7472    hexagon_M2_mpyu_nac_hl_s0(rx, rs, rt)
7473}
7474
7475/// `Rx32-=mpyu(Rs32.h,Rt32.l):<<1`
7476///
7477/// Instruction Type: M
7478/// Execution Slots: SLOT23
7479#[inline(always)]
7480#[cfg_attr(test, assert_instr(mpyu))]
7481#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7482pub unsafe fn Q6_R_mpyunac_RhRl_s1(rx: i32, rs: i32, rt: i32) -> i32 {
7483    hexagon_M2_mpyu_nac_hl_s1(rx, rs, rt)
7484}
7485
7486/// `Rx32-=mpyu(Rs32.l,Rt32.h)`
7487///
7488/// Instruction Type: M
7489/// Execution Slots: SLOT23
7490#[inline(always)]
7491#[cfg_attr(test, assert_instr(mpyu))]
7492#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7493pub unsafe fn Q6_R_mpyunac_RlRh(rx: i32, rs: i32, rt: i32) -> i32 {
7494    hexagon_M2_mpyu_nac_lh_s0(rx, rs, rt)
7495}
7496
7497/// `Rx32-=mpyu(Rs32.l,Rt32.h):<<1`
7498///
7499/// Instruction Type: M
7500/// Execution Slots: SLOT23
7501#[inline(always)]
7502#[cfg_attr(test, assert_instr(mpyu))]
7503#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7504pub unsafe fn Q6_R_mpyunac_RlRh_s1(rx: i32, rs: i32, rt: i32) -> i32 {
7505    hexagon_M2_mpyu_nac_lh_s1(rx, rs, rt)
7506}
7507
7508/// `Rx32-=mpyu(Rs32.l,Rt32.l)`
7509///
7510/// Instruction Type: M
7511/// Execution Slots: SLOT23
7512#[inline(always)]
7513#[cfg_attr(test, assert_instr(mpyu))]
7514#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7515pub unsafe fn Q6_R_mpyunac_RlRl(rx: i32, rs: i32, rt: i32) -> i32 {
7516    hexagon_M2_mpyu_nac_ll_s0(rx, rs, rt)
7517}
7518
7519/// `Rx32-=mpyu(Rs32.l,Rt32.l):<<1`
7520///
7521/// Instruction Type: M
7522/// Execution Slots: SLOT23
7523#[inline(always)]
7524#[cfg_attr(test, assert_instr(mpyu))]
7525#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7526pub unsafe fn Q6_R_mpyunac_RlRl_s1(rx: i32, rs: i32, rt: i32) -> i32 {
7527    hexagon_M2_mpyu_nac_ll_s1(rx, rs, rt)
7528}
7529
7530/// `Rd32=mpyu(Rs32,Rt32)`
7531///
7532/// Instruction Type: M
7533/// Execution Slots: SLOT23
7534#[inline(always)]
7535#[cfg_attr(test, assert_instr(mpyu))]
7536#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7537pub unsafe fn Q6_R_mpyu_RR(rs: i32, rt: i32) -> i32 {
7538    hexagon_M2_mpyu_up(rs, rt)
7539}
7540
7541/// `Rxx32+=mpyu(Rs32.h,Rt32.h)`
7542///
7543/// Instruction Type: M
7544/// Execution Slots: SLOT23
7545#[inline(always)]
7546#[cfg_attr(test, assert_instr(mpyu))]
7547#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7548pub unsafe fn Q6_P_mpyuacc_RhRh(rxx: i64, rs: i32, rt: i32) -> i64 {
7549    hexagon_M2_mpyud_acc_hh_s0(rxx, rs, rt)
7550}
7551
7552/// `Rxx32+=mpyu(Rs32.h,Rt32.h):<<1`
7553///
7554/// Instruction Type: M
7555/// Execution Slots: SLOT23
7556#[inline(always)]
7557#[cfg_attr(test, assert_instr(mpyu))]
7558#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7559pub unsafe fn Q6_P_mpyuacc_RhRh_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
7560    hexagon_M2_mpyud_acc_hh_s1(rxx, rs, rt)
7561}
7562
7563/// `Rxx32+=mpyu(Rs32.h,Rt32.l)`
7564///
7565/// Instruction Type: M
7566/// Execution Slots: SLOT23
7567#[inline(always)]
7568#[cfg_attr(test, assert_instr(mpyu))]
7569#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7570pub unsafe fn Q6_P_mpyuacc_RhRl(rxx: i64, rs: i32, rt: i32) -> i64 {
7571    hexagon_M2_mpyud_acc_hl_s0(rxx, rs, rt)
7572}
7573
7574/// `Rxx32+=mpyu(Rs32.h,Rt32.l):<<1`
7575///
7576/// Instruction Type: M
7577/// Execution Slots: SLOT23
7578#[inline(always)]
7579#[cfg_attr(test, assert_instr(mpyu))]
7580#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7581pub unsafe fn Q6_P_mpyuacc_RhRl_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
7582    hexagon_M2_mpyud_acc_hl_s1(rxx, rs, rt)
7583}
7584
7585/// `Rxx32+=mpyu(Rs32.l,Rt32.h)`
7586///
7587/// Instruction Type: M
7588/// Execution Slots: SLOT23
7589#[inline(always)]
7590#[cfg_attr(test, assert_instr(mpyu))]
7591#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7592pub unsafe fn Q6_P_mpyuacc_RlRh(rxx: i64, rs: i32, rt: i32) -> i64 {
7593    hexagon_M2_mpyud_acc_lh_s0(rxx, rs, rt)
7594}
7595
7596/// `Rxx32+=mpyu(Rs32.l,Rt32.h):<<1`
7597///
7598/// Instruction Type: M
7599/// Execution Slots: SLOT23
7600#[inline(always)]
7601#[cfg_attr(test, assert_instr(mpyu))]
7602#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7603pub unsafe fn Q6_P_mpyuacc_RlRh_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
7604    hexagon_M2_mpyud_acc_lh_s1(rxx, rs, rt)
7605}
7606
7607/// `Rxx32+=mpyu(Rs32.l,Rt32.l)`
7608///
7609/// Instruction Type: M
7610/// Execution Slots: SLOT23
7611#[inline(always)]
7612#[cfg_attr(test, assert_instr(mpyu))]
7613#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7614pub unsafe fn Q6_P_mpyuacc_RlRl(rxx: i64, rs: i32, rt: i32) -> i64 {
7615    hexagon_M2_mpyud_acc_ll_s0(rxx, rs, rt)
7616}
7617
7618/// `Rxx32+=mpyu(Rs32.l,Rt32.l):<<1`
7619///
7620/// Instruction Type: M
7621/// Execution Slots: SLOT23
7622#[inline(always)]
7623#[cfg_attr(test, assert_instr(mpyu))]
7624#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7625pub unsafe fn Q6_P_mpyuacc_RlRl_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
7626    hexagon_M2_mpyud_acc_ll_s1(rxx, rs, rt)
7627}
7628
7629/// `Rdd32=mpyu(Rs32.h,Rt32.h)`
7630///
7631/// Instruction Type: M
7632/// Execution Slots: SLOT23
7633#[inline(always)]
7634#[cfg_attr(test, assert_instr(mpyu))]
7635#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7636pub unsafe fn Q6_P_mpyu_RhRh(rs: i32, rt: i32) -> i64 {
7637    hexagon_M2_mpyud_hh_s0(rs, rt)
7638}
7639
7640/// `Rdd32=mpyu(Rs32.h,Rt32.h):<<1`
7641///
7642/// Instruction Type: M
7643/// Execution Slots: SLOT23
7644#[inline(always)]
7645#[cfg_attr(test, assert_instr(mpyu))]
7646#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7647pub unsafe fn Q6_P_mpyu_RhRh_s1(rs: i32, rt: i32) -> i64 {
7648    hexagon_M2_mpyud_hh_s1(rs, rt)
7649}
7650
7651/// `Rdd32=mpyu(Rs32.h,Rt32.l)`
7652///
7653/// Instruction Type: M
7654/// Execution Slots: SLOT23
7655#[inline(always)]
7656#[cfg_attr(test, assert_instr(mpyu))]
7657#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7658pub unsafe fn Q6_P_mpyu_RhRl(rs: i32, rt: i32) -> i64 {
7659    hexagon_M2_mpyud_hl_s0(rs, rt)
7660}
7661
7662/// `Rdd32=mpyu(Rs32.h,Rt32.l):<<1`
7663///
7664/// Instruction Type: M
7665/// Execution Slots: SLOT23
7666#[inline(always)]
7667#[cfg_attr(test, assert_instr(mpyu))]
7668#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7669pub unsafe fn Q6_P_mpyu_RhRl_s1(rs: i32, rt: i32) -> i64 {
7670    hexagon_M2_mpyud_hl_s1(rs, rt)
7671}
7672
7673/// `Rdd32=mpyu(Rs32.l,Rt32.h)`
7674///
7675/// Instruction Type: M
7676/// Execution Slots: SLOT23
7677#[inline(always)]
7678#[cfg_attr(test, assert_instr(mpyu))]
7679#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7680pub unsafe fn Q6_P_mpyu_RlRh(rs: i32, rt: i32) -> i64 {
7681    hexagon_M2_mpyud_lh_s0(rs, rt)
7682}
7683
7684/// `Rdd32=mpyu(Rs32.l,Rt32.h):<<1`
7685///
7686/// Instruction Type: M
7687/// Execution Slots: SLOT23
7688#[inline(always)]
7689#[cfg_attr(test, assert_instr(mpyu))]
7690#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7691pub unsafe fn Q6_P_mpyu_RlRh_s1(rs: i32, rt: i32) -> i64 {
7692    hexagon_M2_mpyud_lh_s1(rs, rt)
7693}
7694
7695/// `Rdd32=mpyu(Rs32.l,Rt32.l)`
7696///
7697/// Instruction Type: M
7698/// Execution Slots: SLOT23
7699#[inline(always)]
7700#[cfg_attr(test, assert_instr(mpyu))]
7701#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7702pub unsafe fn Q6_P_mpyu_RlRl(rs: i32, rt: i32) -> i64 {
7703    hexagon_M2_mpyud_ll_s0(rs, rt)
7704}
7705
7706/// `Rdd32=mpyu(Rs32.l,Rt32.l):<<1`
7707///
7708/// Instruction Type: M
7709/// Execution Slots: SLOT23
7710#[inline(always)]
7711#[cfg_attr(test, assert_instr(mpyu))]
7712#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7713pub unsafe fn Q6_P_mpyu_RlRl_s1(rs: i32, rt: i32) -> i64 {
7714    hexagon_M2_mpyud_ll_s1(rs, rt)
7715}
7716
7717/// `Rxx32-=mpyu(Rs32.h,Rt32.h)`
7718///
7719/// Instruction Type: M
7720/// Execution Slots: SLOT23
7721#[inline(always)]
7722#[cfg_attr(test, assert_instr(mpyu))]
7723#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7724pub unsafe fn Q6_P_mpyunac_RhRh(rxx: i64, rs: i32, rt: i32) -> i64 {
7725    hexagon_M2_mpyud_nac_hh_s0(rxx, rs, rt)
7726}
7727
7728/// `Rxx32-=mpyu(Rs32.h,Rt32.h):<<1`
7729///
7730/// Instruction Type: M
7731/// Execution Slots: SLOT23
7732#[inline(always)]
7733#[cfg_attr(test, assert_instr(mpyu))]
7734#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7735pub unsafe fn Q6_P_mpyunac_RhRh_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
7736    hexagon_M2_mpyud_nac_hh_s1(rxx, rs, rt)
7737}
7738
7739/// `Rxx32-=mpyu(Rs32.h,Rt32.l)`
7740///
7741/// Instruction Type: M
7742/// Execution Slots: SLOT23
7743#[inline(always)]
7744#[cfg_attr(test, assert_instr(mpyu))]
7745#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7746pub unsafe fn Q6_P_mpyunac_RhRl(rxx: i64, rs: i32, rt: i32) -> i64 {
7747    hexagon_M2_mpyud_nac_hl_s0(rxx, rs, rt)
7748}
7749
7750/// `Rxx32-=mpyu(Rs32.h,Rt32.l):<<1`
7751///
7752/// Instruction Type: M
7753/// Execution Slots: SLOT23
7754#[inline(always)]
7755#[cfg_attr(test, assert_instr(mpyu))]
7756#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7757pub unsafe fn Q6_P_mpyunac_RhRl_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
7758    hexagon_M2_mpyud_nac_hl_s1(rxx, rs, rt)
7759}
7760
7761/// `Rxx32-=mpyu(Rs32.l,Rt32.h)`
7762///
7763/// Instruction Type: M
7764/// Execution Slots: SLOT23
7765#[inline(always)]
7766#[cfg_attr(test, assert_instr(mpyu))]
7767#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7768pub unsafe fn Q6_P_mpyunac_RlRh(rxx: i64, rs: i32, rt: i32) -> i64 {
7769    hexagon_M2_mpyud_nac_lh_s0(rxx, rs, rt)
7770}
7771
7772/// `Rxx32-=mpyu(Rs32.l,Rt32.h):<<1`
7773///
7774/// Instruction Type: M
7775/// Execution Slots: SLOT23
7776#[inline(always)]
7777#[cfg_attr(test, assert_instr(mpyu))]
7778#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7779pub unsafe fn Q6_P_mpyunac_RlRh_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
7780    hexagon_M2_mpyud_nac_lh_s1(rxx, rs, rt)
7781}
7782
7783/// `Rxx32-=mpyu(Rs32.l,Rt32.l)`
7784///
7785/// Instruction Type: M
7786/// Execution Slots: SLOT23
7787#[inline(always)]
7788#[cfg_attr(test, assert_instr(mpyu))]
7789#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7790pub unsafe fn Q6_P_mpyunac_RlRl(rxx: i64, rs: i32, rt: i32) -> i64 {
7791    hexagon_M2_mpyud_nac_ll_s0(rxx, rs, rt)
7792}
7793
7794/// `Rxx32-=mpyu(Rs32.l,Rt32.l):<<1`
7795///
7796/// Instruction Type: M
7797/// Execution Slots: SLOT23
7798#[inline(always)]
7799#[cfg_attr(test, assert_instr(mpyu))]
7800#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7801pub unsafe fn Q6_P_mpyunac_RlRl_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
7802    hexagon_M2_mpyud_nac_ll_s1(rxx, rs, rt)
7803}
7804
7805/// `Rd32=mpyui(Rs32,Rt32)`
7806///
7807/// Instruction Type: M
7808/// Execution Slots: SLOT0123
7809#[inline(always)]
7810#[cfg_attr(test, assert_instr(mpyui))]
7811#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7812pub unsafe fn Q6_R_mpyui_RR(rs: i32, rt: i32) -> i32 {
7813    hexagon_M2_mpyui(rs, rt)
7814}
7815
7816/// `Rx32-=add(Rs32,Rt32)`
7817///
7818/// Instruction Type: M
7819/// Execution Slots: SLOT23
7820#[inline(always)]
7821#[cfg_attr(test, assert_instr(add))]
7822#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7823pub unsafe fn Q6_R_addnac_RR(rx: i32, rs: i32, rt: i32) -> i32 {
7824    hexagon_M2_nacci(rx, rs, rt)
7825}
7826
7827/// `Rx32-=add(Rs32,#s8)`
7828///
7829/// Instruction Type: M
7830/// Execution Slots: SLOT23
7831#[inline(always)]
7832#[rustc_legacy_const_generics(2)]
7833#[cfg_attr(test, assert_instr(add, IS8 = 0))]
7834#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7835pub unsafe fn Q6_R_addnac_RI<const IS8: i32>(rx: i32, rs: i32) -> i32 {
7836    static_assert_simm_bits!(IS8, 8);
7837    hexagon_M2_naccii(rx, rs, IS8)
7838}
7839
7840/// `Rx32+=sub(Rt32,Rs32)`
7841///
7842/// Instruction Type: M
7843/// Execution Slots: SLOT23
7844#[inline(always)]
7845#[cfg_attr(test, assert_instr(sub))]
7846#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7847pub unsafe fn Q6_R_subacc_RR(rx: i32, rt: i32, rs: i32) -> i32 {
7848    hexagon_M2_subacc(rx, rt, rs)
7849}
7850
7851/// `Rdd32=vabsdiffh(Rtt32,Rss32)`
7852///
7853/// Instruction Type: M
7854/// Execution Slots: SLOT23
7855#[inline(always)]
7856#[cfg_attr(test, assert_instr(vabsdiffh))]
7857#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7858pub unsafe fn Q6_P_vabsdiffh_PP(rtt: i64, rss: i64) -> i64 {
7859    hexagon_M2_vabsdiffh(rtt, rss)
7860}
7861
7862/// `Rdd32=vabsdiffw(Rtt32,Rss32)`
7863///
7864/// Instruction Type: M
7865/// Execution Slots: SLOT23
7866#[inline(always)]
7867#[cfg_attr(test, assert_instr(vabsdiffw))]
7868#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7869pub unsafe fn Q6_P_vabsdiffw_PP(rtt: i64, rss: i64) -> i64 {
7870    hexagon_M2_vabsdiffw(rtt, rss)
7871}
7872
7873/// `Rxx32+=vcmpyi(Rss32,Rtt32):sat`
7874///
7875/// Instruction Type: M
7876/// Execution Slots: SLOT23
7877#[inline(always)]
7878#[cfg_attr(test, assert_instr(vcmpyi))]
7879#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7880pub unsafe fn Q6_P_vcmpyiacc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
7881    hexagon_M2_vcmac_s0_sat_i(rxx, rss, rtt)
7882}
7883
7884/// `Rxx32+=vcmpyr(Rss32,Rtt32):sat`
7885///
7886/// Instruction Type: M
7887/// Execution Slots: SLOT23
7888#[inline(always)]
7889#[cfg_attr(test, assert_instr(vcmpyr))]
7890#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7891pub unsafe fn Q6_P_vcmpyracc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
7892    hexagon_M2_vcmac_s0_sat_r(rxx, rss, rtt)
7893}
7894
7895/// `Rdd32=vcmpyi(Rss32,Rtt32):sat`
7896///
7897/// Instruction Type: M
7898/// Execution Slots: SLOT23
7899#[inline(always)]
7900#[cfg_attr(test, assert_instr(vcmpyi))]
7901#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7902pub unsafe fn Q6_P_vcmpyi_PP_sat(rss: i64, rtt: i64) -> i64 {
7903    hexagon_M2_vcmpy_s0_sat_i(rss, rtt)
7904}
7905
7906/// `Rdd32=vcmpyr(Rss32,Rtt32):sat`
7907///
7908/// Instruction Type: M
7909/// Execution Slots: SLOT23
7910#[inline(always)]
7911#[cfg_attr(test, assert_instr(vcmpyr))]
7912#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7913pub unsafe fn Q6_P_vcmpyr_PP_sat(rss: i64, rtt: i64) -> i64 {
7914    hexagon_M2_vcmpy_s0_sat_r(rss, rtt)
7915}
7916
7917/// `Rdd32=vcmpyi(Rss32,Rtt32):<<1:sat`
7918///
7919/// Instruction Type: M
7920/// Execution Slots: SLOT23
7921#[inline(always)]
7922#[cfg_attr(test, assert_instr(vcmpyi))]
7923#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7924pub unsafe fn Q6_P_vcmpyi_PP_s1_sat(rss: i64, rtt: i64) -> i64 {
7925    hexagon_M2_vcmpy_s1_sat_i(rss, rtt)
7926}
7927
7928/// `Rdd32=vcmpyr(Rss32,Rtt32):<<1:sat`
7929///
7930/// Instruction Type: M
7931/// Execution Slots: SLOT23
7932#[inline(always)]
7933#[cfg_attr(test, assert_instr(vcmpyr))]
7934#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7935pub unsafe fn Q6_P_vcmpyr_PP_s1_sat(rss: i64, rtt: i64) -> i64 {
7936    hexagon_M2_vcmpy_s1_sat_r(rss, rtt)
7937}
7938
7939/// `Rxx32+=vdmpy(Rss32,Rtt32):sat`
7940///
7941/// Instruction Type: M
7942/// Execution Slots: SLOT23
7943#[inline(always)]
7944#[cfg_attr(test, assert_instr(vdmpy))]
7945#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7946pub unsafe fn Q6_P_vdmpyacc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
7947    hexagon_M2_vdmacs_s0(rxx, rss, rtt)
7948}
7949
7950/// `Rxx32+=vdmpy(Rss32,Rtt32):<<1:sat`
7951///
7952/// Instruction Type: M
7953/// Execution Slots: SLOT23
7954#[inline(always)]
7955#[cfg_attr(test, assert_instr(vdmpy))]
7956#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7957pub unsafe fn Q6_P_vdmpyacc_PP_s1_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
7958    hexagon_M2_vdmacs_s1(rxx, rss, rtt)
7959}
7960
7961/// `Rd32=vdmpy(Rss32,Rtt32):rnd:sat`
7962///
7963/// Instruction Type: M
7964/// Execution Slots: SLOT23
7965#[inline(always)]
7966#[cfg_attr(test, assert_instr(vdmpy))]
7967#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7968pub unsafe fn Q6_R_vdmpy_PP_rnd_sat(rss: i64, rtt: i64) -> i32 {
7969    hexagon_M2_vdmpyrs_s0(rss, rtt)
7970}
7971
7972/// `Rd32=vdmpy(Rss32,Rtt32):<<1:rnd:sat`
7973///
7974/// Instruction Type: M
7975/// Execution Slots: SLOT23
7976#[inline(always)]
7977#[cfg_attr(test, assert_instr(vdmpy))]
7978#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7979pub unsafe fn Q6_R_vdmpy_PP_s1_rnd_sat(rss: i64, rtt: i64) -> i32 {
7980    hexagon_M2_vdmpyrs_s1(rss, rtt)
7981}
7982
7983/// `Rdd32=vdmpy(Rss32,Rtt32):sat`
7984///
7985/// Instruction Type: M
7986/// Execution Slots: SLOT23
7987#[inline(always)]
7988#[cfg_attr(test, assert_instr(vdmpy))]
7989#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7990pub unsafe fn Q6_P_vdmpy_PP_sat(rss: i64, rtt: i64) -> i64 {
7991    hexagon_M2_vdmpys_s0(rss, rtt)
7992}
7993
7994/// `Rdd32=vdmpy(Rss32,Rtt32):<<1:sat`
7995///
7996/// Instruction Type: M
7997/// Execution Slots: SLOT23
7998#[inline(always)]
7999#[cfg_attr(test, assert_instr(vdmpy))]
8000#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8001pub unsafe fn Q6_P_vdmpy_PP_s1_sat(rss: i64, rtt: i64) -> i64 {
8002    hexagon_M2_vdmpys_s1(rss, rtt)
8003}
8004
8005/// `Rxx32+=vmpyh(Rs32,Rt32)`
8006///
8007/// Instruction Type: M
8008/// Execution Slots: SLOT23
8009#[inline(always)]
8010#[cfg_attr(test, assert_instr(vmpyh))]
8011#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8012pub unsafe fn Q6_P_vmpyhacc_RR(rxx: i64, rs: i32, rt: i32) -> i64 {
8013    hexagon_M2_vmac2(rxx, rs, rt)
8014}
8015
8016/// `Rxx32+=vmpyeh(Rss32,Rtt32)`
8017///
8018/// Instruction Type: M
8019/// Execution Slots: SLOT23
8020#[inline(always)]
8021#[cfg_attr(test, assert_instr(vmpyeh))]
8022#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8023pub unsafe fn Q6_P_vmpyehacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
8024    hexagon_M2_vmac2es(rxx, rss, rtt)
8025}
8026
8027/// `Rxx32+=vmpyeh(Rss32,Rtt32):sat`
8028///
8029/// Instruction Type: M
8030/// Execution Slots: SLOT23
8031#[inline(always)]
8032#[cfg_attr(test, assert_instr(vmpyeh))]
8033#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8034pub unsafe fn Q6_P_vmpyehacc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
8035    hexagon_M2_vmac2es_s0(rxx, rss, rtt)
8036}
8037
8038/// `Rxx32+=vmpyeh(Rss32,Rtt32):<<1:sat`
8039///
8040/// Instruction Type: M
8041/// Execution Slots: SLOT23
8042#[inline(always)]
8043#[cfg_attr(test, assert_instr(vmpyeh))]
8044#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8045pub unsafe fn Q6_P_vmpyehacc_PP_s1_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
8046    hexagon_M2_vmac2es_s1(rxx, rss, rtt)
8047}
8048
8049/// `Rxx32+=vmpyh(Rs32,Rt32):sat`
8050///
8051/// Instruction Type: M
8052/// Execution Slots: SLOT23
8053#[inline(always)]
8054#[cfg_attr(test, assert_instr(vmpyh))]
8055#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8056pub unsafe fn Q6_P_vmpyhacc_RR_sat(rxx: i64, rs: i32, rt: i32) -> i64 {
8057    hexagon_M2_vmac2s_s0(rxx, rs, rt)
8058}
8059
8060/// `Rxx32+=vmpyh(Rs32,Rt32):<<1:sat`
8061///
8062/// Instruction Type: M
8063/// Execution Slots: SLOT23
8064#[inline(always)]
8065#[cfg_attr(test, assert_instr(vmpyh))]
8066#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8067pub unsafe fn Q6_P_vmpyhacc_RR_s1_sat(rxx: i64, rs: i32, rt: i32) -> i64 {
8068    hexagon_M2_vmac2s_s1(rxx, rs, rt)
8069}
8070
8071/// `Rxx32+=vmpyhsu(Rs32,Rt32):sat`
8072///
8073/// Instruction Type: M
8074/// Execution Slots: SLOT23
8075#[inline(always)]
8076#[cfg_attr(test, assert_instr(vmpyhsu))]
8077#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8078pub unsafe fn Q6_P_vmpyhsuacc_RR_sat(rxx: i64, rs: i32, rt: i32) -> i64 {
8079    hexagon_M2_vmac2su_s0(rxx, rs, rt)
8080}
8081
8082/// `Rxx32+=vmpyhsu(Rs32,Rt32):<<1:sat`
8083///
8084/// Instruction Type: M
8085/// Execution Slots: SLOT23
8086#[inline(always)]
8087#[cfg_attr(test, assert_instr(vmpyhsu))]
8088#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8089pub unsafe fn Q6_P_vmpyhsuacc_RR_s1_sat(rxx: i64, rs: i32, rt: i32) -> i64 {
8090    hexagon_M2_vmac2su_s1(rxx, rs, rt)
8091}
8092
8093/// `Rdd32=vmpyeh(Rss32,Rtt32):sat`
8094///
8095/// Instruction Type: M
8096/// Execution Slots: SLOT23
8097#[inline(always)]
8098#[cfg_attr(test, assert_instr(vmpyeh))]
8099#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8100pub unsafe fn Q6_P_vmpyeh_PP_sat(rss: i64, rtt: i64) -> i64 {
8101    hexagon_M2_vmpy2es_s0(rss, rtt)
8102}
8103
8104/// `Rdd32=vmpyeh(Rss32,Rtt32):<<1:sat`
8105///
8106/// Instruction Type: M
8107/// Execution Slots: SLOT23
8108#[inline(always)]
8109#[cfg_attr(test, assert_instr(vmpyeh))]
8110#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8111pub unsafe fn Q6_P_vmpyeh_PP_s1_sat(rss: i64, rtt: i64) -> i64 {
8112    hexagon_M2_vmpy2es_s1(rss, rtt)
8113}
8114
8115/// `Rdd32=vmpyh(Rs32,Rt32):sat`
8116///
8117/// Instruction Type: M
8118/// Execution Slots: SLOT23
8119#[inline(always)]
8120#[cfg_attr(test, assert_instr(vmpyh))]
8121#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8122pub unsafe fn Q6_P_vmpyh_RR_sat(rs: i32, rt: i32) -> i64 {
8123    hexagon_M2_vmpy2s_s0(rs, rt)
8124}
8125
8126/// `Rd32=vmpyh(Rs32,Rt32):rnd:sat`
8127///
8128/// Instruction Type: M
8129/// Execution Slots: SLOT23
8130#[inline(always)]
8131#[cfg_attr(test, assert_instr(vmpyh))]
8132#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8133pub unsafe fn Q6_R_vmpyh_RR_rnd_sat(rs: i32, rt: i32) -> i32 {
8134    hexagon_M2_vmpy2s_s0pack(rs, rt)
8135}
8136
8137/// `Rdd32=vmpyh(Rs32,Rt32):<<1:sat`
8138///
8139/// Instruction Type: M
8140/// Execution Slots: SLOT23
8141#[inline(always)]
8142#[cfg_attr(test, assert_instr(vmpyh))]
8143#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8144pub unsafe fn Q6_P_vmpyh_RR_s1_sat(rs: i32, rt: i32) -> i64 {
8145    hexagon_M2_vmpy2s_s1(rs, rt)
8146}
8147
8148/// `Rd32=vmpyh(Rs32,Rt32):<<1:rnd:sat`
8149///
8150/// Instruction Type: M
8151/// Execution Slots: SLOT23
8152#[inline(always)]
8153#[cfg_attr(test, assert_instr(vmpyh))]
8154#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8155pub unsafe fn Q6_R_vmpyh_RR_s1_rnd_sat(rs: i32, rt: i32) -> i32 {
8156    hexagon_M2_vmpy2s_s1pack(rs, rt)
8157}
8158
8159/// `Rdd32=vmpyhsu(Rs32,Rt32):sat`
8160///
8161/// Instruction Type: M
8162/// Execution Slots: SLOT23
8163#[inline(always)]
8164#[cfg_attr(test, assert_instr(vmpyhsu))]
8165#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8166pub unsafe fn Q6_P_vmpyhsu_RR_sat(rs: i32, rt: i32) -> i64 {
8167    hexagon_M2_vmpy2su_s0(rs, rt)
8168}
8169
8170/// `Rdd32=vmpyhsu(Rs32,Rt32):<<1:sat`
8171///
8172/// Instruction Type: M
8173/// Execution Slots: SLOT23
8174#[inline(always)]
8175#[cfg_attr(test, assert_instr(vmpyhsu))]
8176#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8177pub unsafe fn Q6_P_vmpyhsu_RR_s1_sat(rs: i32, rt: i32) -> i64 {
8178    hexagon_M2_vmpy2su_s1(rs, rt)
8179}
8180
8181/// `Rd32=vraddh(Rss32,Rtt32)`
8182///
8183/// Instruction Type: M
8184/// Execution Slots: SLOT23
8185#[inline(always)]
8186#[cfg_attr(test, assert_instr(vraddh))]
8187#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8188pub unsafe fn Q6_R_vraddh_PP(rss: i64, rtt: i64) -> i32 {
8189    hexagon_M2_vraddh(rss, rtt)
8190}
8191
8192/// `Rd32=vradduh(Rss32,Rtt32)`
8193///
8194/// Instruction Type: M
8195/// Execution Slots: SLOT23
8196#[inline(always)]
8197#[cfg_attr(test, assert_instr(vradduh))]
8198#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8199pub unsafe fn Q6_R_vradduh_PP(rss: i64, rtt: i64) -> i32 {
8200    hexagon_M2_vradduh(rss, rtt)
8201}
8202
8203/// `Rxx32+=vrcmpyi(Rss32,Rtt32)`
8204///
8205/// Instruction Type: M
8206/// Execution Slots: SLOT23
8207#[inline(always)]
8208#[cfg_attr(test, assert_instr(vrcmpyi))]
8209#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8210pub unsafe fn Q6_P_vrcmpyiacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
8211    hexagon_M2_vrcmaci_s0(rxx, rss, rtt)
8212}
8213
8214/// `Rxx32+=vrcmpyi(Rss32,Rtt32*)`
8215///
8216/// Instruction Type: M
8217/// Execution Slots: SLOT23
8218#[inline(always)]
8219#[cfg_attr(test, assert_instr(vrcmpyi))]
8220#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8221pub unsafe fn Q6_P_vrcmpyiacc_PP_conj(rxx: i64, rss: i64, rtt: i64) -> i64 {
8222    hexagon_M2_vrcmaci_s0c(rxx, rss, rtt)
8223}
8224
8225/// `Rxx32+=vrcmpyr(Rss32,Rtt32)`
8226///
8227/// Instruction Type: M
8228/// Execution Slots: SLOT23
8229#[inline(always)]
8230#[cfg_attr(test, assert_instr(vrcmpyr))]
8231#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8232pub unsafe fn Q6_P_vrcmpyracc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
8233    hexagon_M2_vrcmacr_s0(rxx, rss, rtt)
8234}
8235
8236/// `Rxx32+=vrcmpyr(Rss32,Rtt32*)`
8237///
8238/// Instruction Type: M
8239/// Execution Slots: SLOT23
8240#[inline(always)]
8241#[cfg_attr(test, assert_instr(vrcmpyr))]
8242#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8243pub unsafe fn Q6_P_vrcmpyracc_PP_conj(rxx: i64, rss: i64, rtt: i64) -> i64 {
8244    hexagon_M2_vrcmacr_s0c(rxx, rss, rtt)
8245}
8246
8247/// `Rdd32=vrcmpyi(Rss32,Rtt32)`
8248///
8249/// Instruction Type: M
8250/// Execution Slots: SLOT23
8251#[inline(always)]
8252#[cfg_attr(test, assert_instr(vrcmpyi))]
8253#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8254pub unsafe fn Q6_P_vrcmpyi_PP(rss: i64, rtt: i64) -> i64 {
8255    hexagon_M2_vrcmpyi_s0(rss, rtt)
8256}
8257
8258/// `Rdd32=vrcmpyi(Rss32,Rtt32*)`
8259///
8260/// Instruction Type: M
8261/// Execution Slots: SLOT23
8262#[inline(always)]
8263#[cfg_attr(test, assert_instr(vrcmpyi))]
8264#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8265pub unsafe fn Q6_P_vrcmpyi_PP_conj(rss: i64, rtt: i64) -> i64 {
8266    hexagon_M2_vrcmpyi_s0c(rss, rtt)
8267}
8268
8269/// `Rdd32=vrcmpyr(Rss32,Rtt32)`
8270///
8271/// Instruction Type: M
8272/// Execution Slots: SLOT23
8273#[inline(always)]
8274#[cfg_attr(test, assert_instr(vrcmpyr))]
8275#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8276pub unsafe fn Q6_P_vrcmpyr_PP(rss: i64, rtt: i64) -> i64 {
8277    hexagon_M2_vrcmpyr_s0(rss, rtt)
8278}
8279
8280/// `Rdd32=vrcmpyr(Rss32,Rtt32*)`
8281///
8282/// Instruction Type: M
8283/// Execution Slots: SLOT23
8284#[inline(always)]
8285#[cfg_attr(test, assert_instr(vrcmpyr))]
8286#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8287pub unsafe fn Q6_P_vrcmpyr_PP_conj(rss: i64, rtt: i64) -> i64 {
8288    hexagon_M2_vrcmpyr_s0c(rss, rtt)
8289}
8290
8291/// `Rxx32+=vrcmpys(Rss32,Rt32):<<1:sat`
8292///
8293/// Instruction Type: M
8294/// Execution Slots: SLOT0123
8295#[inline(always)]
8296#[cfg_attr(test, assert_instr(vrcmpys))]
8297#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8298pub unsafe fn Q6_P_vrcmpysacc_PR_s1_sat(rxx: i64, rss: i64, rt: i32) -> i64 {
8299    hexagon_M2_vrcmpys_acc_s1(rxx, rss, rt)
8300}
8301
8302/// `Rdd32=vrcmpys(Rss32,Rt32):<<1:sat`
8303///
8304/// Instruction Type: M
8305/// Execution Slots: SLOT0123
8306#[inline(always)]
8307#[cfg_attr(test, assert_instr(vrcmpys))]
8308#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8309pub unsafe fn Q6_P_vrcmpys_PR_s1_sat(rss: i64, rt: i32) -> i64 {
8310    hexagon_M2_vrcmpys_s1(rss, rt)
8311}
8312
8313/// `Rd32=vrcmpys(Rss32,Rt32):<<1:rnd:sat`
8314///
8315/// Instruction Type: M
8316/// Execution Slots: SLOT0123
8317#[inline(always)]
8318#[cfg_attr(test, assert_instr(vrcmpys))]
8319#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8320pub unsafe fn Q6_R_vrcmpys_PR_s1_rnd_sat(rss: i64, rt: i32) -> i32 {
8321    hexagon_M2_vrcmpys_s1rp(rss, rt)
8322}
8323
8324/// `Rxx32+=vrmpyh(Rss32,Rtt32)`
8325///
8326/// Instruction Type: M
8327/// Execution Slots: SLOT23
8328#[inline(always)]
8329#[cfg_attr(test, assert_instr(vrmpyh))]
8330#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8331pub unsafe fn Q6_P_vrmpyhacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
8332    hexagon_M2_vrmac_s0(rxx, rss, rtt)
8333}
8334
8335/// `Rdd32=vrmpyh(Rss32,Rtt32)`
8336///
8337/// Instruction Type: M
8338/// Execution Slots: SLOT23
8339#[inline(always)]
8340#[cfg_attr(test, assert_instr(vrmpyh))]
8341#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8342pub unsafe fn Q6_P_vrmpyh_PP(rss: i64, rtt: i64) -> i64 {
8343    hexagon_M2_vrmpy_s0(rss, rtt)
8344}
8345
8346/// `Rx32^=xor(Rs32,Rt32)`
8347///
8348/// Instruction Type: M
8349/// Execution Slots: SLOT23
8350#[inline(always)]
8351#[cfg_attr(test, assert_instr(xor))]
8352#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8353pub unsafe fn Q6_R_xorxacc_RR(rx: i32, rs: i32, rt: i32) -> i32 {
8354    hexagon_M2_xor_xacc(rx, rs, rt)
8355}
8356
8357/// `Rx32&=and(Rs32,Rt32)`
8358///
8359/// Instruction Type: M
8360/// Execution Slots: SLOT23
8361#[inline(always)]
8362#[cfg_attr(test, assert_instr(and))]
8363#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8364pub unsafe fn Q6_R_andand_RR(rx: i32, rs: i32, rt: i32) -> i32 {
8365    hexagon_M4_and_and(rx, rs, rt)
8366}
8367
8368/// `Rx32&=and(Rs32,~Rt32)`
8369///
8370/// Instruction Type: M
8371/// Execution Slots: SLOT23
8372#[inline(always)]
8373#[cfg_attr(test, assert_instr(and))]
8374#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8375pub unsafe fn Q6_R_andand_RnR(rx: i32, rs: i32, rt: i32) -> i32 {
8376    hexagon_M4_and_andn(rx, rs, rt)
8377}
8378
8379/// `Rx32&=or(Rs32,Rt32)`
8380///
8381/// Instruction Type: M
8382/// Execution Slots: SLOT23
8383#[inline(always)]
8384#[cfg_attr(test, assert_instr(or))]
8385#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8386pub unsafe fn Q6_R_orand_RR(rx: i32, rs: i32, rt: i32) -> i32 {
8387    hexagon_M4_and_or(rx, rs, rt)
8388}
8389
8390/// `Rx32&=xor(Rs32,Rt32)`
8391///
8392/// Instruction Type: M
8393/// Execution Slots: SLOT23
8394#[inline(always)]
8395#[cfg_attr(test, assert_instr(xor))]
8396#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8397pub unsafe fn Q6_R_xorand_RR(rx: i32, rs: i32, rt: i32) -> i32 {
8398    hexagon_M4_and_xor(rx, rs, rt)
8399}
8400
8401/// `Rd32=cmpyiwh(Rss32,Rt32):<<1:rnd:sat`
8402///
8403/// Instruction Type: S_3op
8404/// Execution Slots: SLOT23
8405#[inline(always)]
8406#[cfg_attr(test, assert_instr(cmpyiwh))]
8407#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8408pub unsafe fn Q6_R_cmpyiwh_PR_s1_rnd_sat(rss: i64, rt: i32) -> i32 {
8409    hexagon_M4_cmpyi_wh(rss, rt)
8410}
8411
8412/// `Rd32=cmpyiwh(Rss32,Rt32*):<<1:rnd:sat`
8413///
8414/// Instruction Type: S_3op
8415/// Execution Slots: SLOT23
8416#[inline(always)]
8417#[cfg_attr(test, assert_instr(cmpyiwh))]
8418#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8419pub unsafe fn Q6_R_cmpyiwh_PR_conj_s1_rnd_sat(rss: i64, rt: i32) -> i32 {
8420    hexagon_M4_cmpyi_whc(rss, rt)
8421}
8422
8423/// `Rd32=cmpyrwh(Rss32,Rt32):<<1:rnd:sat`
8424///
8425/// Instruction Type: S_3op
8426/// Execution Slots: SLOT23
8427#[inline(always)]
8428#[cfg_attr(test, assert_instr(cmpyrwh))]
8429#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8430pub unsafe fn Q6_R_cmpyrwh_PR_s1_rnd_sat(rss: i64, rt: i32) -> i32 {
8431    hexagon_M4_cmpyr_wh(rss, rt)
8432}
8433
8434/// `Rd32=cmpyrwh(Rss32,Rt32*):<<1:rnd:sat`
8435///
8436/// Instruction Type: S_3op
8437/// Execution Slots: SLOT23
8438#[inline(always)]
8439#[cfg_attr(test, assert_instr(cmpyrwh))]
8440#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8441pub unsafe fn Q6_R_cmpyrwh_PR_conj_s1_rnd_sat(rss: i64, rt: i32) -> i32 {
8442    hexagon_M4_cmpyr_whc(rss, rt)
8443}
8444
8445/// `Rx32+=mpy(Rs32,Rt32):<<1:sat`
8446///
8447/// Instruction Type: M
8448/// Execution Slots: SLOT23
8449#[inline(always)]
8450#[cfg_attr(test, assert_instr(mpy))]
8451#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8452pub unsafe fn Q6_R_mpyacc_RR_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 {
8453    hexagon_M4_mac_up_s1_sat(rx, rs, rt)
8454}
8455
8456/// `Rd32=add(#u6,mpyi(Rs32,#U6))`
8457///
8458/// Instruction Type: ALU64
8459/// Execution Slots: SLOT23
8460#[inline(always)]
8461#[rustc_legacy_const_generics(0, 2)]
8462#[cfg_attr(test, assert_instr(add, IU6 = 0, IU6_2 = 0))]
8463#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8464pub unsafe fn Q6_R_add_mpyi_IRI<const IU6: u32, const IU6_2: u32>(rs: i32) -> i32 {
8465    static_assert_uimm_bits!(IU6, 6);
8466    static_assert_uimm_bits!(IU6_2, 6);
8467    hexagon_M4_mpyri_addi(IU6 as i32, rs, IU6_2 as i32)
8468}
8469
8470/// `Rd32=add(Ru32,mpyi(Rs32,#u6))`
8471///
8472/// Instruction Type: ALU64
8473/// Execution Slots: SLOT23
8474#[inline(always)]
8475#[rustc_legacy_const_generics(2)]
8476#[cfg_attr(test, assert_instr(add, IU6 = 0))]
8477#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8478pub unsafe fn Q6_R_add_mpyi_RRI<const IU6: u32>(ru: i32, rs: i32) -> i32 {
8479    static_assert_uimm_bits!(IU6, 6);
8480    hexagon_M4_mpyri_addr(ru, rs, IU6 as i32)
8481}
8482
8483/// `Rd32=add(Ru32,mpyi(#u6:2,Rs32))`
8484///
8485/// Instruction Type: ALU64
8486/// Execution Slots: SLOT23
8487#[inline(always)]
8488#[rustc_legacy_const_generics(1)]
8489#[cfg_attr(test, assert_instr(add, IU6_2 = 0))]
8490#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8491pub unsafe fn Q6_R_add_mpyi_RIR<const IU6_2: u32>(ru: i32, rs: i32) -> i32 {
8492    static_assert_uimm_bits!(IU6_2, 6);
8493    hexagon_M4_mpyri_addr_u2(ru, IU6_2 as i32, rs)
8494}
8495
8496/// `Rd32=add(#u6,mpyi(Rs32,Rt32))`
8497///
8498/// Instruction Type: ALU64
8499/// Execution Slots: SLOT23
8500#[inline(always)]
8501#[rustc_legacy_const_generics(0)]
8502#[cfg_attr(test, assert_instr(add, IU6 = 0))]
8503#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8504pub unsafe fn Q6_R_add_mpyi_IRR<const IU6: u32>(rs: i32, rt: i32) -> i32 {
8505    static_assert_uimm_bits!(IU6, 6);
8506    hexagon_M4_mpyrr_addi(IU6 as i32, rs, rt)
8507}
8508
8509/// `Ry32=add(Ru32,mpyi(Ry32,Rs32))`
8510///
8511/// Instruction Type: M
8512/// Execution Slots: SLOT23
8513#[inline(always)]
8514#[cfg_attr(test, assert_instr(add))]
8515#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8516pub unsafe fn Q6_R_add_mpyi_RRR(ru: i32, ry: i32, rs: i32) -> i32 {
8517    hexagon_M4_mpyrr_addr(ru, ry, rs)
8518}
8519
8520/// `Rx32-=mpy(Rs32,Rt32):<<1:sat`
8521///
8522/// Instruction Type: M
8523/// Execution Slots: SLOT23
8524#[inline(always)]
8525#[cfg_attr(test, assert_instr(mpy))]
8526#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8527pub unsafe fn Q6_R_mpynac_RR_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 {
8528    hexagon_M4_nac_up_s1_sat(rx, rs, rt)
8529}
8530
8531/// `Rx32|=and(Rs32,Rt32)`
8532///
8533/// Instruction Type: M
8534/// Execution Slots: SLOT23
8535#[inline(always)]
8536#[cfg_attr(test, assert_instr(and))]
8537#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8538pub unsafe fn Q6_R_andor_RR(rx: i32, rs: i32, rt: i32) -> i32 {
8539    hexagon_M4_or_and(rx, rs, rt)
8540}
8541
8542/// `Rx32|=and(Rs32,~Rt32)`
8543///
8544/// Instruction Type: M
8545/// Execution Slots: SLOT23
8546#[inline(always)]
8547#[cfg_attr(test, assert_instr(and))]
8548#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8549pub unsafe fn Q6_R_andor_RnR(rx: i32, rs: i32, rt: i32) -> i32 {
8550    hexagon_M4_or_andn(rx, rs, rt)
8551}
8552
8553/// `Rx32|=or(Rs32,Rt32)`
8554///
8555/// Instruction Type: M
8556/// Execution Slots: SLOT23
8557#[inline(always)]
8558#[cfg_attr(test, assert_instr(or))]
8559#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8560pub unsafe fn Q6_R_oror_RR(rx: i32, rs: i32, rt: i32) -> i32 {
8561    hexagon_M4_or_or(rx, rs, rt)
8562}
8563
8564/// `Rx32|=xor(Rs32,Rt32)`
8565///
8566/// Instruction Type: M
8567/// Execution Slots: SLOT23
8568#[inline(always)]
8569#[cfg_attr(test, assert_instr(xor))]
8570#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8571pub unsafe fn Q6_R_xoror_RR(rx: i32, rs: i32, rt: i32) -> i32 {
8572    hexagon_M4_or_xor(rx, rs, rt)
8573}
8574
8575/// `Rdd32=pmpyw(Rs32,Rt32)`
8576///
8577/// Instruction Type: M
8578/// Execution Slots: SLOT23
8579#[inline(always)]
8580#[cfg_attr(test, assert_instr(pmpyw))]
8581#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8582pub unsafe fn Q6_P_pmpyw_RR(rs: i32, rt: i32) -> i64 {
8583    hexagon_M4_pmpyw(rs, rt)
8584}
8585
8586/// `Rxx32^=pmpyw(Rs32,Rt32)`
8587///
8588/// Instruction Type: M
8589/// Execution Slots: SLOT23
8590#[inline(always)]
8591#[cfg_attr(test, assert_instr(pmpyw))]
8592#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8593pub unsafe fn Q6_P_pmpywxacc_RR(rxx: i64, rs: i32, rt: i32) -> i64 {
8594    hexagon_M4_pmpyw_acc(rxx, rs, rt)
8595}
8596
8597/// `Rdd32=vpmpyh(Rs32,Rt32)`
8598///
8599/// Instruction Type: M
8600/// Execution Slots: SLOT23
8601#[inline(always)]
8602#[cfg_attr(test, assert_instr(vpmpyh))]
8603#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8604pub unsafe fn Q6_P_vpmpyh_RR(rs: i32, rt: i32) -> i64 {
8605    hexagon_M4_vpmpyh(rs, rt)
8606}
8607
8608/// `Rxx32^=vpmpyh(Rs32,Rt32)`
8609///
8610/// Instruction Type: M
8611/// Execution Slots: SLOT23
8612#[inline(always)]
8613#[cfg_attr(test, assert_instr(vpmpyh))]
8614#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8615pub unsafe fn Q6_P_vpmpyhxacc_RR(rxx: i64, rs: i32, rt: i32) -> i64 {
8616    hexagon_M4_vpmpyh_acc(rxx, rs, rt)
8617}
8618
8619/// `Rxx32+=vrmpyweh(Rss32,Rtt32)`
8620///
8621/// Instruction Type: M
8622/// Execution Slots: SLOT23
8623#[inline(always)]
8624#[cfg_attr(test, assert_instr(vrmpyweh))]
8625#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8626pub unsafe fn Q6_P_vrmpywehacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
8627    hexagon_M4_vrmpyeh_acc_s0(rxx, rss, rtt)
8628}
8629
8630/// `Rxx32+=vrmpyweh(Rss32,Rtt32):<<1`
8631///
8632/// Instruction Type: M
8633/// Execution Slots: SLOT23
8634#[inline(always)]
8635#[cfg_attr(test, assert_instr(vrmpyweh))]
8636#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8637pub unsafe fn Q6_P_vrmpywehacc_PP_s1(rxx: i64, rss: i64, rtt: i64) -> i64 {
8638    hexagon_M4_vrmpyeh_acc_s1(rxx, rss, rtt)
8639}
8640
8641/// `Rdd32=vrmpyweh(Rss32,Rtt32)`
8642///
8643/// Instruction Type: M
8644/// Execution Slots: SLOT23
8645#[inline(always)]
8646#[cfg_attr(test, assert_instr(vrmpyweh))]
8647#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8648pub unsafe fn Q6_P_vrmpyweh_PP(rss: i64, rtt: i64) -> i64 {
8649    hexagon_M4_vrmpyeh_s0(rss, rtt)
8650}
8651
8652/// `Rdd32=vrmpyweh(Rss32,Rtt32):<<1`
8653///
8654/// Instruction Type: M
8655/// Execution Slots: SLOT23
8656#[inline(always)]
8657#[cfg_attr(test, assert_instr(vrmpyweh))]
8658#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8659pub unsafe fn Q6_P_vrmpyweh_PP_s1(rss: i64, rtt: i64) -> i64 {
8660    hexagon_M4_vrmpyeh_s1(rss, rtt)
8661}
8662
8663/// `Rxx32+=vrmpywoh(Rss32,Rtt32)`
8664///
8665/// Instruction Type: M
8666/// Execution Slots: SLOT23
8667#[inline(always)]
8668#[cfg_attr(test, assert_instr(vrmpywoh))]
8669#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8670pub unsafe fn Q6_P_vrmpywohacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
8671    hexagon_M4_vrmpyoh_acc_s0(rxx, rss, rtt)
8672}
8673
8674/// `Rxx32+=vrmpywoh(Rss32,Rtt32):<<1`
8675///
8676/// Instruction Type: M
8677/// Execution Slots: SLOT23
8678#[inline(always)]
8679#[cfg_attr(test, assert_instr(vrmpywoh))]
8680#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8681pub unsafe fn Q6_P_vrmpywohacc_PP_s1(rxx: i64, rss: i64, rtt: i64) -> i64 {
8682    hexagon_M4_vrmpyoh_acc_s1(rxx, rss, rtt)
8683}
8684
8685/// `Rdd32=vrmpywoh(Rss32,Rtt32)`
8686///
8687/// Instruction Type: M
8688/// Execution Slots: SLOT23
8689#[inline(always)]
8690#[cfg_attr(test, assert_instr(vrmpywoh))]
8691#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8692pub unsafe fn Q6_P_vrmpywoh_PP(rss: i64, rtt: i64) -> i64 {
8693    hexagon_M4_vrmpyoh_s0(rss, rtt)
8694}
8695
8696/// `Rdd32=vrmpywoh(Rss32,Rtt32):<<1`
8697///
8698/// Instruction Type: M
8699/// Execution Slots: SLOT23
8700#[inline(always)]
8701#[cfg_attr(test, assert_instr(vrmpywoh))]
8702#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8703pub unsafe fn Q6_P_vrmpywoh_PP_s1(rss: i64, rtt: i64) -> i64 {
8704    hexagon_M4_vrmpyoh_s1(rss, rtt)
8705}
8706
8707/// `Rx32^=and(Rs32,Rt32)`
8708///
8709/// Instruction Type: M
8710/// Execution Slots: SLOT23
8711#[inline(always)]
8712#[cfg_attr(test, assert_instr(and))]
8713#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8714pub unsafe fn Q6_R_andxacc_RR(rx: i32, rs: i32, rt: i32) -> i32 {
8715    hexagon_M4_xor_and(rx, rs, rt)
8716}
8717
8718/// `Rx32^=and(Rs32,~Rt32)`
8719///
8720/// Instruction Type: M
8721/// Execution Slots: SLOT23
8722#[inline(always)]
8723#[cfg_attr(test, assert_instr(and))]
8724#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8725pub unsafe fn Q6_R_andxacc_RnR(rx: i32, rs: i32, rt: i32) -> i32 {
8726    hexagon_M4_xor_andn(rx, rs, rt)
8727}
8728
8729/// `Rx32^=or(Rs32,Rt32)`
8730///
8731/// Instruction Type: M
8732/// Execution Slots: SLOT23
8733#[inline(always)]
8734#[cfg_attr(test, assert_instr(or))]
8735#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8736pub unsafe fn Q6_R_orxacc_RR(rx: i32, rs: i32, rt: i32) -> i32 {
8737    hexagon_M4_xor_or(rx, rs, rt)
8738}
8739
8740/// `Rxx32^=xor(Rss32,Rtt32)`
8741///
8742/// Instruction Type: S_3op
8743/// Execution Slots: SLOT23
8744#[inline(always)]
8745#[cfg_attr(test, assert_instr(xor))]
8746#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8747pub unsafe fn Q6_P_xorxacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
8748    hexagon_M4_xor_xacc(rxx, rss, rtt)
8749}
8750
8751/// `Rxx32+=vdmpybsu(Rss32,Rtt32):sat`
8752///
8753/// Instruction Type: M
8754/// Execution Slots: SLOT23
8755#[inline(always)]
8756#[cfg_attr(test, assert_instr(vdmpybsu))]
8757#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8758pub unsafe fn Q6_P_vdmpybsuacc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
8759    hexagon_M5_vdmacbsu(rxx, rss, rtt)
8760}
8761
8762/// `Rdd32=vdmpybsu(Rss32,Rtt32):sat`
8763///
8764/// Instruction Type: M
8765/// Execution Slots: SLOT23
8766#[inline(always)]
8767#[cfg_attr(test, assert_instr(vdmpybsu))]
8768#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8769pub unsafe fn Q6_P_vdmpybsu_PP_sat(rss: i64, rtt: i64) -> i64 {
8770    hexagon_M5_vdmpybsu(rss, rtt)
8771}
8772
8773/// `Rxx32+=vmpybsu(Rs32,Rt32)`
8774///
8775/// Instruction Type: M
8776/// Execution Slots: SLOT23
8777#[inline(always)]
8778#[cfg_attr(test, assert_instr(vmpybsu))]
8779#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8780pub unsafe fn Q6_P_vmpybsuacc_RR(rxx: i64, rs: i32, rt: i32) -> i64 {
8781    hexagon_M5_vmacbsu(rxx, rs, rt)
8782}
8783
8784/// `Rxx32+=vmpybu(Rs32,Rt32)`
8785///
8786/// Instruction Type: M
8787/// Execution Slots: SLOT23
8788#[inline(always)]
8789#[cfg_attr(test, assert_instr(vmpybu))]
8790#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8791pub unsafe fn Q6_P_vmpybuacc_RR(rxx: i64, rs: i32, rt: i32) -> i64 {
8792    hexagon_M5_vmacbuu(rxx, rs, rt)
8793}
8794
8795/// `Rdd32=vmpybsu(Rs32,Rt32)`
8796///
8797/// Instruction Type: M
8798/// Execution Slots: SLOT23
8799#[inline(always)]
8800#[cfg_attr(test, assert_instr(vmpybsu))]
8801#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8802pub unsafe fn Q6_P_vmpybsu_RR(rs: i32, rt: i32) -> i64 {
8803    hexagon_M5_vmpybsu(rs, rt)
8804}
8805
8806/// `Rdd32=vmpybu(Rs32,Rt32)`
8807///
8808/// Instruction Type: M
8809/// Execution Slots: SLOT23
8810#[inline(always)]
8811#[cfg_attr(test, assert_instr(vmpybu))]
8812#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8813pub unsafe fn Q6_P_vmpybu_RR(rs: i32, rt: i32) -> i64 {
8814    hexagon_M5_vmpybuu(rs, rt)
8815}
8816
8817/// `Rxx32+=vrmpybsu(Rss32,Rtt32)`
8818///
8819/// Instruction Type: M
8820/// Execution Slots: SLOT23
8821#[inline(always)]
8822#[cfg_attr(test, assert_instr(vrmpybsu))]
8823#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8824pub unsafe fn Q6_P_vrmpybsuacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
8825    hexagon_M5_vrmacbsu(rxx, rss, rtt)
8826}
8827
8828/// `Rxx32+=vrmpybu(Rss32,Rtt32)`
8829///
8830/// Instruction Type: M
8831/// Execution Slots: SLOT23
8832#[inline(always)]
8833#[cfg_attr(test, assert_instr(vrmpybu))]
8834#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8835pub unsafe fn Q6_P_vrmpybuacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
8836    hexagon_M5_vrmacbuu(rxx, rss, rtt)
8837}
8838
8839/// `Rdd32=vrmpybsu(Rss32,Rtt32)`
8840///
8841/// Instruction Type: M
8842/// Execution Slots: SLOT23
8843#[inline(always)]
8844#[cfg_attr(test, assert_instr(vrmpybsu))]
8845#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8846pub unsafe fn Q6_P_vrmpybsu_PP(rss: i64, rtt: i64) -> i64 {
8847    hexagon_M5_vrmpybsu(rss, rtt)
8848}
8849
8850/// `Rdd32=vrmpybu(Rss32,Rtt32)`
8851///
8852/// Instruction Type: M
8853/// Execution Slots: SLOT23
8854#[inline(always)]
8855#[cfg_attr(test, assert_instr(vrmpybu))]
8856#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8857pub unsafe fn Q6_P_vrmpybu_PP(rss: i64, rtt: i64) -> i64 {
8858    hexagon_M5_vrmpybuu(rss, rtt)
8859}
8860
8861/// `Rd32=addasl(Rt32,Rs32,#u3)`
8862///
8863/// Instruction Type: S_3op
8864/// Execution Slots: SLOT23
8865#[inline(always)]
8866#[rustc_legacy_const_generics(2)]
8867#[cfg_attr(test, assert_instr(addasl, IU3 = 0))]
8868#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8869pub unsafe fn Q6_R_addasl_RRI<const IU3: u32>(rt: i32, rs: i32) -> i32 {
8870    static_assert_uimm_bits!(IU3, 3);
8871    hexagon_S2_addasl_rrri(rt, rs, IU3 as i32)
8872}
8873
8874/// `Rdd32=asl(Rss32,#u6)`
8875///
8876/// Instruction Type: S_2op
8877/// Execution Slots: SLOT23
8878#[inline(always)]
8879#[rustc_legacy_const_generics(1)]
8880#[cfg_attr(test, assert_instr(asl, IU6 = 0))]
8881#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8882pub unsafe fn Q6_P_asl_PI<const IU6: u32>(rss: i64) -> i64 {
8883    static_assert_uimm_bits!(IU6, 6);
8884    hexagon_S2_asl_i_p(rss, IU6 as i32)
8885}
8886
8887/// `Rxx32+=asl(Rss32,#u6)`
8888///
8889/// Instruction Type: S_2op
8890/// Execution Slots: SLOT23
8891#[inline(always)]
8892#[rustc_legacy_const_generics(2)]
8893#[cfg_attr(test, assert_instr(asl, IU6 = 0))]
8894#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8895pub unsafe fn Q6_P_aslacc_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
8896    static_assert_uimm_bits!(IU6, 6);
8897    hexagon_S2_asl_i_p_acc(rxx, rss, IU6 as i32)
8898}
8899
8900/// `Rxx32&=asl(Rss32,#u6)`
8901///
8902/// Instruction Type: S_2op
8903/// Execution Slots: SLOT23
8904#[inline(always)]
8905#[rustc_legacy_const_generics(2)]
8906#[cfg_attr(test, assert_instr(asl, IU6 = 0))]
8907#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8908pub unsafe fn Q6_P_asland_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
8909    static_assert_uimm_bits!(IU6, 6);
8910    hexagon_S2_asl_i_p_and(rxx, rss, IU6 as i32)
8911}
8912
8913/// `Rxx32-=asl(Rss32,#u6)`
8914///
8915/// Instruction Type: S_2op
8916/// Execution Slots: SLOT23
8917#[inline(always)]
8918#[rustc_legacy_const_generics(2)]
8919#[cfg_attr(test, assert_instr(asl, IU6 = 0))]
8920#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8921pub unsafe fn Q6_P_aslnac_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
8922    static_assert_uimm_bits!(IU6, 6);
8923    hexagon_S2_asl_i_p_nac(rxx, rss, IU6 as i32)
8924}
8925
8926/// `Rxx32|=asl(Rss32,#u6)`
8927///
8928/// Instruction Type: S_2op
8929/// Execution Slots: SLOT23
8930#[inline(always)]
8931#[rustc_legacy_const_generics(2)]
8932#[cfg_attr(test, assert_instr(asl, IU6 = 0))]
8933#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8934pub unsafe fn Q6_P_aslor_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
8935    static_assert_uimm_bits!(IU6, 6);
8936    hexagon_S2_asl_i_p_or(rxx, rss, IU6 as i32)
8937}
8938
8939/// `Rxx32^=asl(Rss32,#u6)`
8940///
8941/// Instruction Type: S_2op
8942/// Execution Slots: SLOT23
8943#[inline(always)]
8944#[rustc_legacy_const_generics(2)]
8945#[cfg_attr(test, assert_instr(asl, IU6 = 0))]
8946#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8947pub unsafe fn Q6_P_aslxacc_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
8948    static_assert_uimm_bits!(IU6, 6);
8949    hexagon_S2_asl_i_p_xacc(rxx, rss, IU6 as i32)
8950}
8951
8952/// `Rd32=asl(Rs32,#u5)`
8953///
8954/// Instruction Type: S_2op
8955/// Execution Slots: SLOT23
8956#[inline(always)]
8957#[rustc_legacy_const_generics(1)]
8958#[cfg_attr(test, assert_instr(asl, IU5 = 0))]
8959#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8960pub unsafe fn Q6_R_asl_RI<const IU5: u32>(rs: i32) -> i32 {
8961    static_assert_uimm_bits!(IU5, 5);
8962    hexagon_S2_asl_i_r(rs, IU5 as i32)
8963}
8964
8965/// `Rx32+=asl(Rs32,#u5)`
8966///
8967/// Instruction Type: S_2op
8968/// Execution Slots: SLOT23
8969#[inline(always)]
8970#[rustc_legacy_const_generics(2)]
8971#[cfg_attr(test, assert_instr(asl, IU5 = 0))]
8972#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8973pub unsafe fn Q6_R_aslacc_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
8974    static_assert_uimm_bits!(IU5, 5);
8975    hexagon_S2_asl_i_r_acc(rx, rs, IU5 as i32)
8976}
8977
8978/// `Rx32&=asl(Rs32,#u5)`
8979///
8980/// Instruction Type: S_2op
8981/// Execution Slots: SLOT23
8982#[inline(always)]
8983#[rustc_legacy_const_generics(2)]
8984#[cfg_attr(test, assert_instr(asl, IU5 = 0))]
8985#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8986pub unsafe fn Q6_R_asland_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
8987    static_assert_uimm_bits!(IU5, 5);
8988    hexagon_S2_asl_i_r_and(rx, rs, IU5 as i32)
8989}
8990
8991/// `Rx32-=asl(Rs32,#u5)`
8992///
8993/// Instruction Type: S_2op
8994/// Execution Slots: SLOT23
8995#[inline(always)]
8996#[rustc_legacy_const_generics(2)]
8997#[cfg_attr(test, assert_instr(asl, IU5 = 0))]
8998#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8999pub unsafe fn Q6_R_aslnac_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
9000    static_assert_uimm_bits!(IU5, 5);
9001    hexagon_S2_asl_i_r_nac(rx, rs, IU5 as i32)
9002}
9003
9004/// `Rx32|=asl(Rs32,#u5)`
9005///
9006/// Instruction Type: S_2op
9007/// Execution Slots: SLOT23
9008#[inline(always)]
9009#[rustc_legacy_const_generics(2)]
9010#[cfg_attr(test, assert_instr(asl, IU5 = 0))]
9011#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9012pub unsafe fn Q6_R_aslor_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
9013    static_assert_uimm_bits!(IU5, 5);
9014    hexagon_S2_asl_i_r_or(rx, rs, IU5 as i32)
9015}
9016
9017/// `Rd32=asl(Rs32,#u5):sat`
9018///
9019/// Instruction Type: S_2op
9020/// Execution Slots: SLOT23
9021#[inline(always)]
9022#[rustc_legacy_const_generics(1)]
9023#[cfg_attr(test, assert_instr(asl, IU5 = 0))]
9024#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9025pub unsafe fn Q6_R_asl_RI_sat<const IU5: u32>(rs: i32) -> i32 {
9026    static_assert_uimm_bits!(IU5, 5);
9027    hexagon_S2_asl_i_r_sat(rs, IU5 as i32)
9028}
9029
9030/// `Rx32^=asl(Rs32,#u5)`
9031///
9032/// Instruction Type: S_2op
9033/// Execution Slots: SLOT23
9034#[inline(always)]
9035#[rustc_legacy_const_generics(2)]
9036#[cfg_attr(test, assert_instr(asl, IU5 = 0))]
9037#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9038pub unsafe fn Q6_R_aslxacc_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
9039    static_assert_uimm_bits!(IU5, 5);
9040    hexagon_S2_asl_i_r_xacc(rx, rs, IU5 as i32)
9041}
9042
9043/// `Rdd32=vaslh(Rss32,#u4)`
9044///
9045/// Instruction Type: S_2op
9046/// Execution Slots: SLOT23
9047#[inline(always)]
9048#[rustc_legacy_const_generics(1)]
9049#[cfg_attr(test, assert_instr(vaslh, IU4 = 0))]
9050#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9051pub unsafe fn Q6_P_vaslh_PI<const IU4: u32>(rss: i64) -> i64 {
9052    static_assert_uimm_bits!(IU4, 4);
9053    hexagon_S2_asl_i_vh(rss, IU4 as i32)
9054}
9055
9056/// `Rdd32=vaslw(Rss32,#u5)`
9057///
9058/// Instruction Type: S_2op
9059/// Execution Slots: SLOT23
9060#[inline(always)]
9061#[rustc_legacy_const_generics(1)]
9062#[cfg_attr(test, assert_instr(vaslw, IU5 = 0))]
9063#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9064pub unsafe fn Q6_P_vaslw_PI<const IU5: u32>(rss: i64) -> i64 {
9065    static_assert_uimm_bits!(IU5, 5);
9066    hexagon_S2_asl_i_vw(rss, IU5 as i32)
9067}
9068
9069/// `Rdd32=asl(Rss32,Rt32)`
9070///
9071/// Instruction Type: S_3op
9072/// Execution Slots: SLOT23
9073#[inline(always)]
9074#[cfg_attr(test, assert_instr(asl))]
9075#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9076pub unsafe fn Q6_P_asl_PR(rss: i64, rt: i32) -> i64 {
9077    hexagon_S2_asl_r_p(rss, rt)
9078}
9079
9080/// `Rxx32+=asl(Rss32,Rt32)`
9081///
9082/// Instruction Type: S_3op
9083/// Execution Slots: SLOT23
9084#[inline(always)]
9085#[cfg_attr(test, assert_instr(asl))]
9086#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9087pub unsafe fn Q6_P_aslacc_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
9088    hexagon_S2_asl_r_p_acc(rxx, rss, rt)
9089}
9090
9091/// `Rxx32&=asl(Rss32,Rt32)`
9092///
9093/// Instruction Type: S_3op
9094/// Execution Slots: SLOT23
9095#[inline(always)]
9096#[cfg_attr(test, assert_instr(asl))]
9097#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9098pub unsafe fn Q6_P_asland_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
9099    hexagon_S2_asl_r_p_and(rxx, rss, rt)
9100}
9101
9102/// `Rxx32-=asl(Rss32,Rt32)`
9103///
9104/// Instruction Type: S_3op
9105/// Execution Slots: SLOT23
9106#[inline(always)]
9107#[cfg_attr(test, assert_instr(asl))]
9108#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9109pub unsafe fn Q6_P_aslnac_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
9110    hexagon_S2_asl_r_p_nac(rxx, rss, rt)
9111}
9112
9113/// `Rxx32|=asl(Rss32,Rt32)`
9114///
9115/// Instruction Type: S_3op
9116/// Execution Slots: SLOT23
9117#[inline(always)]
9118#[cfg_attr(test, assert_instr(asl))]
9119#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9120pub unsafe fn Q6_P_aslor_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
9121    hexagon_S2_asl_r_p_or(rxx, rss, rt)
9122}
9123
9124/// `Rxx32^=asl(Rss32,Rt32)`
9125///
9126/// Instruction Type: S_3op
9127/// Execution Slots: SLOT23
9128#[inline(always)]
9129#[cfg_attr(test, assert_instr(asl))]
9130#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9131pub unsafe fn Q6_P_aslxacc_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
9132    hexagon_S2_asl_r_p_xor(rxx, rss, rt)
9133}
9134
9135/// `Rd32=asl(Rs32,Rt32)`
9136///
9137/// Instruction Type: S_3op
9138/// Execution Slots: SLOT23
9139#[inline(always)]
9140#[cfg_attr(test, assert_instr(asl))]
9141#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9142pub unsafe fn Q6_R_asl_RR(rs: i32, rt: i32) -> i32 {
9143    hexagon_S2_asl_r_r(rs, rt)
9144}
9145
9146/// `Rx32+=asl(Rs32,Rt32)`
9147///
9148/// Instruction Type: S_3op
9149/// Execution Slots: SLOT23
9150#[inline(always)]
9151#[cfg_attr(test, assert_instr(asl))]
9152#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9153pub unsafe fn Q6_R_aslacc_RR(rx: i32, rs: i32, rt: i32) -> i32 {
9154    hexagon_S2_asl_r_r_acc(rx, rs, rt)
9155}
9156
9157/// `Rx32&=asl(Rs32,Rt32)`
9158///
9159/// Instruction Type: S_3op
9160/// Execution Slots: SLOT23
9161#[inline(always)]
9162#[cfg_attr(test, assert_instr(asl))]
9163#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9164pub unsafe fn Q6_R_asland_RR(rx: i32, rs: i32, rt: i32) -> i32 {
9165    hexagon_S2_asl_r_r_and(rx, rs, rt)
9166}
9167
9168/// `Rx32-=asl(Rs32,Rt32)`
9169///
9170/// Instruction Type: S_3op
9171/// Execution Slots: SLOT23
9172#[inline(always)]
9173#[cfg_attr(test, assert_instr(asl))]
9174#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9175pub unsafe fn Q6_R_aslnac_RR(rx: i32, rs: i32, rt: i32) -> i32 {
9176    hexagon_S2_asl_r_r_nac(rx, rs, rt)
9177}
9178
9179/// `Rx32|=asl(Rs32,Rt32)`
9180///
9181/// Instruction Type: S_3op
9182/// Execution Slots: SLOT23
9183#[inline(always)]
9184#[cfg_attr(test, assert_instr(asl))]
9185#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9186pub unsafe fn Q6_R_aslor_RR(rx: i32, rs: i32, rt: i32) -> i32 {
9187    hexagon_S2_asl_r_r_or(rx, rs, rt)
9188}
9189
9190/// `Rd32=asl(Rs32,Rt32):sat`
9191///
9192/// Instruction Type: S_3op
9193/// Execution Slots: SLOT23
9194#[inline(always)]
9195#[cfg_attr(test, assert_instr(asl))]
9196#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9197pub unsafe fn Q6_R_asl_RR_sat(rs: i32, rt: i32) -> i32 {
9198    hexagon_S2_asl_r_r_sat(rs, rt)
9199}
9200
9201/// `Rdd32=vaslh(Rss32,Rt32)`
9202///
9203/// Instruction Type: S_3op
9204/// Execution Slots: SLOT23
9205#[inline(always)]
9206#[cfg_attr(test, assert_instr(vaslh))]
9207#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9208pub unsafe fn Q6_P_vaslh_PR(rss: i64, rt: i32) -> i64 {
9209    hexagon_S2_asl_r_vh(rss, rt)
9210}
9211
9212/// `Rdd32=vaslw(Rss32,Rt32)`
9213///
9214/// Instruction Type: S_3op
9215/// Execution Slots: SLOT23
9216#[inline(always)]
9217#[cfg_attr(test, assert_instr(vaslw))]
9218#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9219pub unsafe fn Q6_P_vaslw_PR(rss: i64, rt: i32) -> i64 {
9220    hexagon_S2_asl_r_vw(rss, rt)
9221}
9222
9223/// `Rdd32=asr(Rss32,#u6)`
9224///
9225/// Instruction Type: S_2op
9226/// Execution Slots: SLOT23
9227#[inline(always)]
9228#[rustc_legacy_const_generics(1)]
9229#[cfg_attr(test, assert_instr(asr, IU6 = 0))]
9230#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9231pub unsafe fn Q6_P_asr_PI<const IU6: u32>(rss: i64) -> i64 {
9232    static_assert_uimm_bits!(IU6, 6);
9233    hexagon_S2_asr_i_p(rss, IU6 as i32)
9234}
9235
9236/// `Rxx32+=asr(Rss32,#u6)`
9237///
9238/// Instruction Type: S_2op
9239/// Execution Slots: SLOT23
9240#[inline(always)]
9241#[rustc_legacy_const_generics(2)]
9242#[cfg_attr(test, assert_instr(asr, IU6 = 0))]
9243#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9244pub unsafe fn Q6_P_asracc_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
9245    static_assert_uimm_bits!(IU6, 6);
9246    hexagon_S2_asr_i_p_acc(rxx, rss, IU6 as i32)
9247}
9248
9249/// `Rxx32&=asr(Rss32,#u6)`
9250///
9251/// Instruction Type: S_2op
9252/// Execution Slots: SLOT23
9253#[inline(always)]
9254#[rustc_legacy_const_generics(2)]
9255#[cfg_attr(test, assert_instr(asr, IU6 = 0))]
9256#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9257pub unsafe fn Q6_P_asrand_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
9258    static_assert_uimm_bits!(IU6, 6);
9259    hexagon_S2_asr_i_p_and(rxx, rss, IU6 as i32)
9260}
9261
9262/// `Rxx32-=asr(Rss32,#u6)`
9263///
9264/// Instruction Type: S_2op
9265/// Execution Slots: SLOT23
9266#[inline(always)]
9267#[rustc_legacy_const_generics(2)]
9268#[cfg_attr(test, assert_instr(asr, IU6 = 0))]
9269#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9270pub unsafe fn Q6_P_asrnac_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
9271    static_assert_uimm_bits!(IU6, 6);
9272    hexagon_S2_asr_i_p_nac(rxx, rss, IU6 as i32)
9273}
9274
9275/// `Rxx32|=asr(Rss32,#u6)`
9276///
9277/// Instruction Type: S_2op
9278/// Execution Slots: SLOT23
9279#[inline(always)]
9280#[rustc_legacy_const_generics(2)]
9281#[cfg_attr(test, assert_instr(asr, IU6 = 0))]
9282#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9283pub unsafe fn Q6_P_asror_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
9284    static_assert_uimm_bits!(IU6, 6);
9285    hexagon_S2_asr_i_p_or(rxx, rss, IU6 as i32)
9286}
9287
9288/// `Rdd32=asr(Rss32,#u6):rnd`
9289///
9290/// Instruction Type: S_2op
9291/// Execution Slots: SLOT23
9292#[inline(always)]
9293#[rustc_legacy_const_generics(1)]
9294#[cfg_attr(test, assert_instr(asr, IU6 = 0))]
9295#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9296pub unsafe fn Q6_P_asr_PI_rnd<const IU6: u32>(rss: i64) -> i64 {
9297    static_assert_uimm_bits!(IU6, 6);
9298    hexagon_S2_asr_i_p_rnd(rss, IU6 as i32)
9299}
9300
9301/// `Rdd32=asrrnd(Rss32,#u6)`
9302///
9303/// Instruction Type: S_2op
9304/// Execution Slots: SLOT0123
9305#[inline(always)]
9306#[rustc_legacy_const_generics(1)]
9307#[cfg_attr(test, assert_instr(asrrnd, IU6 = 0))]
9308#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9309pub unsafe fn Q6_P_asrrnd_PI<const IU6: u32>(rss: i64) -> i64 {
9310    static_assert_uimm_bits!(IU6, 6);
9311    hexagon_S2_asr_i_p_rnd_goodsyntax(rss, IU6 as i32)
9312}
9313
9314/// `Rd32=asr(Rs32,#u5)`
9315///
9316/// Instruction Type: S_2op
9317/// Execution Slots: SLOT23
9318#[inline(always)]
9319#[rustc_legacy_const_generics(1)]
9320#[cfg_attr(test, assert_instr(asr, IU5 = 0))]
9321#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9322pub unsafe fn Q6_R_asr_RI<const IU5: u32>(rs: i32) -> i32 {
9323    static_assert_uimm_bits!(IU5, 5);
9324    hexagon_S2_asr_i_r(rs, IU5 as i32)
9325}
9326
9327/// `Rx32+=asr(Rs32,#u5)`
9328///
9329/// Instruction Type: S_2op
9330/// Execution Slots: SLOT23
9331#[inline(always)]
9332#[rustc_legacy_const_generics(2)]
9333#[cfg_attr(test, assert_instr(asr, IU5 = 0))]
9334#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9335pub unsafe fn Q6_R_asracc_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
9336    static_assert_uimm_bits!(IU5, 5);
9337    hexagon_S2_asr_i_r_acc(rx, rs, IU5 as i32)
9338}
9339
9340/// `Rx32&=asr(Rs32,#u5)`
9341///
9342/// Instruction Type: S_2op
9343/// Execution Slots: SLOT23
9344#[inline(always)]
9345#[rustc_legacy_const_generics(2)]
9346#[cfg_attr(test, assert_instr(asr, IU5 = 0))]
9347#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9348pub unsafe fn Q6_R_asrand_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
9349    static_assert_uimm_bits!(IU5, 5);
9350    hexagon_S2_asr_i_r_and(rx, rs, IU5 as i32)
9351}
9352
9353/// `Rx32-=asr(Rs32,#u5)`
9354///
9355/// Instruction Type: S_2op
9356/// Execution Slots: SLOT23
9357#[inline(always)]
9358#[rustc_legacy_const_generics(2)]
9359#[cfg_attr(test, assert_instr(asr, IU5 = 0))]
9360#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9361pub unsafe fn Q6_R_asrnac_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
9362    static_assert_uimm_bits!(IU5, 5);
9363    hexagon_S2_asr_i_r_nac(rx, rs, IU5 as i32)
9364}
9365
9366/// `Rx32|=asr(Rs32,#u5)`
9367///
9368/// Instruction Type: S_2op
9369/// Execution Slots: SLOT23
9370#[inline(always)]
9371#[rustc_legacy_const_generics(2)]
9372#[cfg_attr(test, assert_instr(asr, IU5 = 0))]
9373#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9374pub unsafe fn Q6_R_asror_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
9375    static_assert_uimm_bits!(IU5, 5);
9376    hexagon_S2_asr_i_r_or(rx, rs, IU5 as i32)
9377}
9378
9379/// `Rd32=asr(Rs32,#u5):rnd`
9380///
9381/// Instruction Type: S_2op
9382/// Execution Slots: SLOT23
9383#[inline(always)]
9384#[rustc_legacy_const_generics(1)]
9385#[cfg_attr(test, assert_instr(asr, IU5 = 0))]
9386#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9387pub unsafe fn Q6_R_asr_RI_rnd<const IU5: u32>(rs: i32) -> i32 {
9388    static_assert_uimm_bits!(IU5, 5);
9389    hexagon_S2_asr_i_r_rnd(rs, IU5 as i32)
9390}
9391
9392/// `Rd32=asrrnd(Rs32,#u5)`
9393///
9394/// Instruction Type: S_2op
9395/// Execution Slots: SLOT0123
9396#[inline(always)]
9397#[rustc_legacy_const_generics(1)]
9398#[cfg_attr(test, assert_instr(asrrnd, IU5 = 0))]
9399#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9400pub unsafe fn Q6_R_asrrnd_RI<const IU5: u32>(rs: i32) -> i32 {
9401    static_assert_uimm_bits!(IU5, 5);
9402    hexagon_S2_asr_i_r_rnd_goodsyntax(rs, IU5 as i32)
9403}
9404
9405/// `Rd32=vasrw(Rss32,#u5)`
9406///
9407/// Instruction Type: S_2op
9408/// Execution Slots: SLOT23
9409#[inline(always)]
9410#[rustc_legacy_const_generics(1)]
9411#[cfg_attr(test, assert_instr(vasrw, IU5 = 0))]
9412#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9413pub unsafe fn Q6_R_vasrw_PI<const IU5: u32>(rss: i64) -> i32 {
9414    static_assert_uimm_bits!(IU5, 5);
9415    hexagon_S2_asr_i_svw_trun(rss, IU5 as i32)
9416}
9417
9418/// `Rdd32=vasrh(Rss32,#u4)`
9419///
9420/// Instruction Type: S_2op
9421/// Execution Slots: SLOT23
9422#[inline(always)]
9423#[rustc_legacy_const_generics(1)]
9424#[cfg_attr(test, assert_instr(vasrh, IU4 = 0))]
9425#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9426pub unsafe fn Q6_P_vasrh_PI<const IU4: u32>(rss: i64) -> i64 {
9427    static_assert_uimm_bits!(IU4, 4);
9428    hexagon_S2_asr_i_vh(rss, IU4 as i32)
9429}
9430
9431/// `Rdd32=vasrw(Rss32,#u5)`
9432///
9433/// Instruction Type: S_2op
9434/// Execution Slots: SLOT23
9435#[inline(always)]
9436#[rustc_legacy_const_generics(1)]
9437#[cfg_attr(test, assert_instr(vasrw, IU5 = 0))]
9438#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9439pub unsafe fn Q6_P_vasrw_PI<const IU5: u32>(rss: i64) -> i64 {
9440    static_assert_uimm_bits!(IU5, 5);
9441    hexagon_S2_asr_i_vw(rss, IU5 as i32)
9442}
9443
9444/// `Rdd32=asr(Rss32,Rt32)`
9445///
9446/// Instruction Type: S_3op
9447/// Execution Slots: SLOT23
9448#[inline(always)]
9449#[cfg_attr(test, assert_instr(asr))]
9450#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9451pub unsafe fn Q6_P_asr_PR(rss: i64, rt: i32) -> i64 {
9452    hexagon_S2_asr_r_p(rss, rt)
9453}
9454
9455/// `Rxx32+=asr(Rss32,Rt32)`
9456///
9457/// Instruction Type: S_3op
9458/// Execution Slots: SLOT23
9459#[inline(always)]
9460#[cfg_attr(test, assert_instr(asr))]
9461#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9462pub unsafe fn Q6_P_asracc_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
9463    hexagon_S2_asr_r_p_acc(rxx, rss, rt)
9464}
9465
9466/// `Rxx32&=asr(Rss32,Rt32)`
9467///
9468/// Instruction Type: S_3op
9469/// Execution Slots: SLOT23
9470#[inline(always)]
9471#[cfg_attr(test, assert_instr(asr))]
9472#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9473pub unsafe fn Q6_P_asrand_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
9474    hexagon_S2_asr_r_p_and(rxx, rss, rt)
9475}
9476
9477/// `Rxx32-=asr(Rss32,Rt32)`
9478///
9479/// Instruction Type: S_3op
9480/// Execution Slots: SLOT23
9481#[inline(always)]
9482#[cfg_attr(test, assert_instr(asr))]
9483#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9484pub unsafe fn Q6_P_asrnac_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
9485    hexagon_S2_asr_r_p_nac(rxx, rss, rt)
9486}
9487
9488/// `Rxx32|=asr(Rss32,Rt32)`
9489///
9490/// Instruction Type: S_3op
9491/// Execution Slots: SLOT23
9492#[inline(always)]
9493#[cfg_attr(test, assert_instr(asr))]
9494#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9495pub unsafe fn Q6_P_asror_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
9496    hexagon_S2_asr_r_p_or(rxx, rss, rt)
9497}
9498
9499/// `Rxx32^=asr(Rss32,Rt32)`
9500///
9501/// Instruction Type: S_3op
9502/// Execution Slots: SLOT23
9503#[inline(always)]
9504#[cfg_attr(test, assert_instr(asr))]
9505#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9506pub unsafe fn Q6_P_asrxacc_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
9507    hexagon_S2_asr_r_p_xor(rxx, rss, rt)
9508}
9509
9510/// `Rd32=asr(Rs32,Rt32)`
9511///
9512/// Instruction Type: S_3op
9513/// Execution Slots: SLOT23
9514#[inline(always)]
9515#[cfg_attr(test, assert_instr(asr))]
9516#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9517pub unsafe fn Q6_R_asr_RR(rs: i32, rt: i32) -> i32 {
9518    hexagon_S2_asr_r_r(rs, rt)
9519}
9520
9521/// `Rx32+=asr(Rs32,Rt32)`
9522///
9523/// Instruction Type: S_3op
9524/// Execution Slots: SLOT23
9525#[inline(always)]
9526#[cfg_attr(test, assert_instr(asr))]
9527#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9528pub unsafe fn Q6_R_asracc_RR(rx: i32, rs: i32, rt: i32) -> i32 {
9529    hexagon_S2_asr_r_r_acc(rx, rs, rt)
9530}
9531
9532/// `Rx32&=asr(Rs32,Rt32)`
9533///
9534/// Instruction Type: S_3op
9535/// Execution Slots: SLOT23
9536#[inline(always)]
9537#[cfg_attr(test, assert_instr(asr))]
9538#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9539pub unsafe fn Q6_R_asrand_RR(rx: i32, rs: i32, rt: i32) -> i32 {
9540    hexagon_S2_asr_r_r_and(rx, rs, rt)
9541}
9542
9543/// `Rx32-=asr(Rs32,Rt32)`
9544///
9545/// Instruction Type: S_3op
9546/// Execution Slots: SLOT23
9547#[inline(always)]
9548#[cfg_attr(test, assert_instr(asr))]
9549#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9550pub unsafe fn Q6_R_asrnac_RR(rx: i32, rs: i32, rt: i32) -> i32 {
9551    hexagon_S2_asr_r_r_nac(rx, rs, rt)
9552}
9553
9554/// `Rx32|=asr(Rs32,Rt32)`
9555///
9556/// Instruction Type: S_3op
9557/// Execution Slots: SLOT23
9558#[inline(always)]
9559#[cfg_attr(test, assert_instr(asr))]
9560#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9561pub unsafe fn Q6_R_asror_RR(rx: i32, rs: i32, rt: i32) -> i32 {
9562    hexagon_S2_asr_r_r_or(rx, rs, rt)
9563}
9564
9565/// `Rd32=asr(Rs32,Rt32):sat`
9566///
9567/// Instruction Type: S_3op
9568/// Execution Slots: SLOT23
9569#[inline(always)]
9570#[cfg_attr(test, assert_instr(asr))]
9571#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9572pub unsafe fn Q6_R_asr_RR_sat(rs: i32, rt: i32) -> i32 {
9573    hexagon_S2_asr_r_r_sat(rs, rt)
9574}
9575
9576/// `Rd32=vasrw(Rss32,Rt32)`
9577///
9578/// Instruction Type: S_3op
9579/// Execution Slots: SLOT23
9580#[inline(always)]
9581#[cfg_attr(test, assert_instr(vasrw))]
9582#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9583pub unsafe fn Q6_R_vasrw_PR(rss: i64, rt: i32) -> i32 {
9584    hexagon_S2_asr_r_svw_trun(rss, rt)
9585}
9586
9587/// `Rdd32=vasrh(Rss32,Rt32)`
9588///
9589/// Instruction Type: S_3op
9590/// Execution Slots: SLOT23
9591#[inline(always)]
9592#[cfg_attr(test, assert_instr(vasrh))]
9593#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9594pub unsafe fn Q6_P_vasrh_PR(rss: i64, rt: i32) -> i64 {
9595    hexagon_S2_asr_r_vh(rss, rt)
9596}
9597
9598/// `Rdd32=vasrw(Rss32,Rt32)`
9599///
9600/// Instruction Type: S_3op
9601/// Execution Slots: SLOT23
9602#[inline(always)]
9603#[cfg_attr(test, assert_instr(vasrw))]
9604#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9605pub unsafe fn Q6_P_vasrw_PR(rss: i64, rt: i32) -> i64 {
9606    hexagon_S2_asr_r_vw(rss, rt)
9607}
9608
9609/// `Rd32=brev(Rs32)`
9610///
9611/// Instruction Type: S_2op
9612/// Execution Slots: SLOT23
9613#[inline(always)]
9614#[cfg_attr(test, assert_instr(brev))]
9615#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9616pub unsafe fn Q6_R_brev_R(rs: i32) -> i32 {
9617    hexagon_S2_brev(rs)
9618}
9619
9620/// `Rdd32=brev(Rss32)`
9621///
9622/// Instruction Type: S_2op
9623/// Execution Slots: SLOT23
9624#[inline(always)]
9625#[cfg_attr(test, assert_instr(brev))]
9626#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9627pub unsafe fn Q6_P_brev_P(rss: i64) -> i64 {
9628    hexagon_S2_brevp(rss)
9629}
9630
9631/// `Rd32=cl0(Rs32)`
9632///
9633/// Instruction Type: S_2op
9634/// Execution Slots: SLOT23
9635#[inline(always)]
9636#[cfg_attr(test, assert_instr(cl0))]
9637#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9638pub unsafe fn Q6_R_cl0_R(rs: i32) -> i32 {
9639    hexagon_S2_cl0(rs)
9640}
9641
9642/// `Rd32=cl0(Rss32)`
9643///
9644/// Instruction Type: S_2op
9645/// Execution Slots: SLOT23
9646#[inline(always)]
9647#[cfg_attr(test, assert_instr(cl0))]
9648#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9649pub unsafe fn Q6_R_cl0_P(rss: i64) -> i32 {
9650    hexagon_S2_cl0p(rss)
9651}
9652
9653/// `Rd32=cl1(Rs32)`
9654///
9655/// Instruction Type: S_2op
9656/// Execution Slots: SLOT23
9657#[inline(always)]
9658#[cfg_attr(test, assert_instr(cl1))]
9659#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9660pub unsafe fn Q6_R_cl1_R(rs: i32) -> i32 {
9661    hexagon_S2_cl1(rs)
9662}
9663
9664/// `Rd32=cl1(Rss32)`
9665///
9666/// Instruction Type: S_2op
9667/// Execution Slots: SLOT23
9668#[inline(always)]
9669#[cfg_attr(test, assert_instr(cl1))]
9670#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9671pub unsafe fn Q6_R_cl1_P(rss: i64) -> i32 {
9672    hexagon_S2_cl1p(rss)
9673}
9674
9675/// `Rd32=clb(Rs32)`
9676///
9677/// Instruction Type: S_2op
9678/// Execution Slots: SLOT23
9679#[inline(always)]
9680#[cfg_attr(test, assert_instr(clb))]
9681#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9682pub unsafe fn Q6_R_clb_R(rs: i32) -> i32 {
9683    hexagon_S2_clb(rs)
9684}
9685
9686/// `Rd32=normamt(Rs32)`
9687///
9688/// Instruction Type: S_2op
9689/// Execution Slots: SLOT23
9690#[inline(always)]
9691#[cfg_attr(test, assert_instr(normamt))]
9692#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9693pub unsafe fn Q6_R_normamt_R(rs: i32) -> i32 {
9694    hexagon_S2_clbnorm(rs)
9695}
9696
9697/// `Rd32=clb(Rss32)`
9698///
9699/// Instruction Type: S_2op
9700/// Execution Slots: SLOT23
9701#[inline(always)]
9702#[cfg_attr(test, assert_instr(clb))]
9703#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9704pub unsafe fn Q6_R_clb_P(rss: i64) -> i32 {
9705    hexagon_S2_clbp(rss)
9706}
9707
9708/// `Rd32=clrbit(Rs32,#u5)`
9709///
9710/// Instruction Type: S_2op
9711/// Execution Slots: SLOT23
9712#[inline(always)]
9713#[rustc_legacy_const_generics(1)]
9714#[cfg_attr(test, assert_instr(clrbit, IU5 = 0))]
9715#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9716pub unsafe fn Q6_R_clrbit_RI<const IU5: u32>(rs: i32) -> i32 {
9717    static_assert_uimm_bits!(IU5, 5);
9718    hexagon_S2_clrbit_i(rs, IU5 as i32)
9719}
9720
9721/// `Rd32=clrbit(Rs32,Rt32)`
9722///
9723/// Instruction Type: S_3op
9724/// Execution Slots: SLOT23
9725#[inline(always)]
9726#[cfg_attr(test, assert_instr(clrbit))]
9727#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9728pub unsafe fn Q6_R_clrbit_RR(rs: i32, rt: i32) -> i32 {
9729    hexagon_S2_clrbit_r(rs, rt)
9730}
9731
9732/// `Rd32=ct0(Rs32)`
9733///
9734/// Instruction Type: S_2op
9735/// Execution Slots: SLOT23
9736#[inline(always)]
9737#[cfg_attr(test, assert_instr(ct0))]
9738#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9739pub unsafe fn Q6_R_ct0_R(rs: i32) -> i32 {
9740    hexagon_S2_ct0(rs)
9741}
9742
9743/// `Rd32=ct0(Rss32)`
9744///
9745/// Instruction Type: S_2op
9746/// Execution Slots: SLOT23
9747#[inline(always)]
9748#[cfg_attr(test, assert_instr(ct0))]
9749#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9750pub unsafe fn Q6_R_ct0_P(rss: i64) -> i32 {
9751    hexagon_S2_ct0p(rss)
9752}
9753
9754/// `Rd32=ct1(Rs32)`
9755///
9756/// Instruction Type: S_2op
9757/// Execution Slots: SLOT23
9758#[inline(always)]
9759#[cfg_attr(test, assert_instr(ct1))]
9760#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9761pub unsafe fn Q6_R_ct1_R(rs: i32) -> i32 {
9762    hexagon_S2_ct1(rs)
9763}
9764
9765/// `Rd32=ct1(Rss32)`
9766///
9767/// Instruction Type: S_2op
9768/// Execution Slots: SLOT23
9769#[inline(always)]
9770#[cfg_attr(test, assert_instr(ct1))]
9771#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9772pub unsafe fn Q6_R_ct1_P(rss: i64) -> i32 {
9773    hexagon_S2_ct1p(rss)
9774}
9775
9776/// `Rdd32=deinterleave(Rss32)`
9777///
9778/// Instruction Type: S_2op
9779/// Execution Slots: SLOT23
9780#[inline(always)]
9781#[cfg_attr(test, assert_instr(deinterleave))]
9782#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9783pub unsafe fn Q6_P_deinterleave_P(rss: i64) -> i64 {
9784    hexagon_S2_deinterleave(rss)
9785}
9786
9787/// `Rd32=extractu(Rs32,#u5,#U5)`
9788///
9789/// Instruction Type: S_2op
9790/// Execution Slots: SLOT23
9791#[inline(always)]
9792#[rustc_legacy_const_generics(1, 2)]
9793#[cfg_attr(test, assert_instr(extractu, IU5 = 0, IU5_2 = 0))]
9794#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9795pub unsafe fn Q6_R_extractu_RII<const IU5: u32, const IU5_2: u32>(rs: i32) -> i32 {
9796    static_assert_uimm_bits!(IU5, 5);
9797    static_assert_uimm_bits!(IU5_2, 5);
9798    hexagon_S2_extractu(rs, IU5 as i32, IU5_2 as i32)
9799}
9800
9801/// `Rd32=extractu(Rs32,Rtt32)`
9802///
9803/// Instruction Type: S_3op
9804/// Execution Slots: SLOT23
9805#[inline(always)]
9806#[cfg_attr(test, assert_instr(extractu))]
9807#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9808pub unsafe fn Q6_R_extractu_RP(rs: i32, rtt: i64) -> i32 {
9809    hexagon_S2_extractu_rp(rs, rtt)
9810}
9811
9812/// `Rdd32=extractu(Rss32,#u6,#U6)`
9813///
9814/// Instruction Type: S_2op
9815/// Execution Slots: SLOT23
9816#[inline(always)]
9817#[rustc_legacy_const_generics(1, 2)]
9818#[cfg_attr(test, assert_instr(extractu, IU6 = 0, IU6_2 = 0))]
9819#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9820pub unsafe fn Q6_P_extractu_PII<const IU6: u32, const IU6_2: u32>(rss: i64) -> i64 {
9821    static_assert_uimm_bits!(IU6, 6);
9822    static_assert_uimm_bits!(IU6_2, 6);
9823    hexagon_S2_extractup(rss, IU6 as i32, IU6_2 as i32)
9824}
9825
9826/// `Rdd32=extractu(Rss32,Rtt32)`
9827///
9828/// Instruction Type: S_3op
9829/// Execution Slots: SLOT23
9830#[inline(always)]
9831#[cfg_attr(test, assert_instr(extractu))]
9832#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9833pub unsafe fn Q6_P_extractu_PP(rss: i64, rtt: i64) -> i64 {
9834    hexagon_S2_extractup_rp(rss, rtt)
9835}
9836
9837/// `Rx32=insert(Rs32,#u5,#U5)`
9838///
9839/// Instruction Type: S_2op
9840/// Execution Slots: SLOT23
9841#[inline(always)]
9842#[rustc_legacy_const_generics(2, 3)]
9843#[cfg_attr(test, assert_instr(insert, IU5 = 0, IU5_2 = 0))]
9844#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9845pub unsafe fn Q6_R_insert_RII<const IU5: u32, const IU5_2: u32>(rx: i32, rs: i32) -> i32 {
9846    static_assert_uimm_bits!(IU5, 5);
9847    static_assert_uimm_bits!(IU5_2, 5);
9848    hexagon_S2_insert(rx, rs, IU5 as i32, IU5_2 as i32)
9849}
9850
9851/// `Rx32=insert(Rs32,Rtt32)`
9852///
9853/// Instruction Type: S_3op
9854/// Execution Slots: SLOT23
9855#[inline(always)]
9856#[cfg_attr(test, assert_instr(insert))]
9857#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9858pub unsafe fn Q6_R_insert_RP(rx: i32, rs: i32, rtt: i64) -> i32 {
9859    hexagon_S2_insert_rp(rx, rs, rtt)
9860}
9861
9862/// `Rxx32=insert(Rss32,#u6,#U6)`
9863///
9864/// Instruction Type: S_2op
9865/// Execution Slots: SLOT23
9866#[inline(always)]
9867#[rustc_legacy_const_generics(2, 3)]
9868#[cfg_attr(test, assert_instr(insert, IU6 = 0, IU6_2 = 0))]
9869#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9870pub unsafe fn Q6_P_insert_PII<const IU6: u32, const IU6_2: u32>(rxx: i64, rss: i64) -> i64 {
9871    static_assert_uimm_bits!(IU6, 6);
9872    static_assert_uimm_bits!(IU6_2, 6);
9873    hexagon_S2_insertp(rxx, rss, IU6 as i32, IU6_2 as i32)
9874}
9875
9876/// `Rxx32=insert(Rss32,Rtt32)`
9877///
9878/// Instruction Type: S_3op
9879/// Execution Slots: SLOT23
9880#[inline(always)]
9881#[cfg_attr(test, assert_instr(insert))]
9882#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9883pub unsafe fn Q6_P_insert_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
9884    hexagon_S2_insertp_rp(rxx, rss, rtt)
9885}
9886
9887/// `Rdd32=interleave(Rss32)`
9888///
9889/// Instruction Type: S_2op
9890/// Execution Slots: SLOT23
9891#[inline(always)]
9892#[cfg_attr(test, assert_instr(interleave))]
9893#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9894pub unsafe fn Q6_P_interleave_P(rss: i64) -> i64 {
9895    hexagon_S2_interleave(rss)
9896}
9897
9898/// `Rdd32=lfs(Rss32,Rtt32)`
9899///
9900/// Instruction Type: S_3op
9901/// Execution Slots: SLOT23
9902#[inline(always)]
9903#[cfg_attr(test, assert_instr(lfs))]
9904#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9905pub unsafe fn Q6_P_lfs_PP(rss: i64, rtt: i64) -> i64 {
9906    hexagon_S2_lfsp(rss, rtt)
9907}
9908
9909/// `Rdd32=lsl(Rss32,Rt32)`
9910///
9911/// Instruction Type: S_3op
9912/// Execution Slots: SLOT23
9913#[inline(always)]
9914#[cfg_attr(test, assert_instr(lsl))]
9915#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9916pub unsafe fn Q6_P_lsl_PR(rss: i64, rt: i32) -> i64 {
9917    hexagon_S2_lsl_r_p(rss, rt)
9918}
9919
9920/// `Rxx32+=lsl(Rss32,Rt32)`
9921///
9922/// Instruction Type: S_3op
9923/// Execution Slots: SLOT23
9924#[inline(always)]
9925#[cfg_attr(test, assert_instr(lsl))]
9926#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9927pub unsafe fn Q6_P_lslacc_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
9928    hexagon_S2_lsl_r_p_acc(rxx, rss, rt)
9929}
9930
9931/// `Rxx32&=lsl(Rss32,Rt32)`
9932///
9933/// Instruction Type: S_3op
9934/// Execution Slots: SLOT23
9935#[inline(always)]
9936#[cfg_attr(test, assert_instr(lsl))]
9937#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9938pub unsafe fn Q6_P_lsland_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
9939    hexagon_S2_lsl_r_p_and(rxx, rss, rt)
9940}
9941
9942/// `Rxx32-=lsl(Rss32,Rt32)`
9943///
9944/// Instruction Type: S_3op
9945/// Execution Slots: SLOT23
9946#[inline(always)]
9947#[cfg_attr(test, assert_instr(lsl))]
9948#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9949pub unsafe fn Q6_P_lslnac_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
9950    hexagon_S2_lsl_r_p_nac(rxx, rss, rt)
9951}
9952
9953/// `Rxx32|=lsl(Rss32,Rt32)`
9954///
9955/// Instruction Type: S_3op
9956/// Execution Slots: SLOT23
9957#[inline(always)]
9958#[cfg_attr(test, assert_instr(lsl))]
9959#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9960pub unsafe fn Q6_P_lslor_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
9961    hexagon_S2_lsl_r_p_or(rxx, rss, rt)
9962}
9963
9964/// `Rxx32^=lsl(Rss32,Rt32)`
9965///
9966/// Instruction Type: S_3op
9967/// Execution Slots: SLOT23
9968#[inline(always)]
9969#[cfg_attr(test, assert_instr(lsl))]
9970#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9971pub unsafe fn Q6_P_lslxacc_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
9972    hexagon_S2_lsl_r_p_xor(rxx, rss, rt)
9973}
9974
9975/// `Rd32=lsl(Rs32,Rt32)`
9976///
9977/// Instruction Type: S_3op
9978/// Execution Slots: SLOT23
9979#[inline(always)]
9980#[cfg_attr(test, assert_instr(lsl))]
9981#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9982pub unsafe fn Q6_R_lsl_RR(rs: i32, rt: i32) -> i32 {
9983    hexagon_S2_lsl_r_r(rs, rt)
9984}
9985
9986/// `Rx32+=lsl(Rs32,Rt32)`
9987///
9988/// Instruction Type: S_3op
9989/// Execution Slots: SLOT23
9990#[inline(always)]
9991#[cfg_attr(test, assert_instr(lsl))]
9992#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9993pub unsafe fn Q6_R_lslacc_RR(rx: i32, rs: i32, rt: i32) -> i32 {
9994    hexagon_S2_lsl_r_r_acc(rx, rs, rt)
9995}
9996
9997/// `Rx32&=lsl(Rs32,Rt32)`
9998///
9999/// Instruction Type: S_3op
10000/// Execution Slots: SLOT23
10001#[inline(always)]
10002#[cfg_attr(test, assert_instr(lsl))]
10003#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10004pub unsafe fn Q6_R_lsland_RR(rx: i32, rs: i32, rt: i32) -> i32 {
10005    hexagon_S2_lsl_r_r_and(rx, rs, rt)
10006}
10007
10008/// `Rx32-=lsl(Rs32,Rt32)`
10009///
10010/// Instruction Type: S_3op
10011/// Execution Slots: SLOT23
10012#[inline(always)]
10013#[cfg_attr(test, assert_instr(lsl))]
10014#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10015pub unsafe fn Q6_R_lslnac_RR(rx: i32, rs: i32, rt: i32) -> i32 {
10016    hexagon_S2_lsl_r_r_nac(rx, rs, rt)
10017}
10018
10019/// `Rx32|=lsl(Rs32,Rt32)`
10020///
10021/// Instruction Type: S_3op
10022/// Execution Slots: SLOT23
10023#[inline(always)]
10024#[cfg_attr(test, assert_instr(lsl))]
10025#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10026pub unsafe fn Q6_R_lslor_RR(rx: i32, rs: i32, rt: i32) -> i32 {
10027    hexagon_S2_lsl_r_r_or(rx, rs, rt)
10028}
10029
10030/// `Rdd32=vlslh(Rss32,Rt32)`
10031///
10032/// Instruction Type: S_3op
10033/// Execution Slots: SLOT23
10034#[inline(always)]
10035#[cfg_attr(test, assert_instr(vlslh))]
10036#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10037pub unsafe fn Q6_P_vlslh_PR(rss: i64, rt: i32) -> i64 {
10038    hexagon_S2_lsl_r_vh(rss, rt)
10039}
10040
10041/// `Rdd32=vlslw(Rss32,Rt32)`
10042///
10043/// Instruction Type: S_3op
10044/// Execution Slots: SLOT23
10045#[inline(always)]
10046#[cfg_attr(test, assert_instr(vlslw))]
10047#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10048pub unsafe fn Q6_P_vlslw_PR(rss: i64, rt: i32) -> i64 {
10049    hexagon_S2_lsl_r_vw(rss, rt)
10050}
10051
10052/// `Rdd32=lsr(Rss32,#u6)`
10053///
10054/// Instruction Type: S_2op
10055/// Execution Slots: SLOT23
10056#[inline(always)]
10057#[rustc_legacy_const_generics(1)]
10058#[cfg_attr(test, assert_instr(lsr, IU6 = 0))]
10059#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10060pub unsafe fn Q6_P_lsr_PI<const IU6: u32>(rss: i64) -> i64 {
10061    static_assert_uimm_bits!(IU6, 6);
10062    hexagon_S2_lsr_i_p(rss, IU6 as i32)
10063}
10064
10065/// `Rxx32+=lsr(Rss32,#u6)`
10066///
10067/// Instruction Type: S_2op
10068/// Execution Slots: SLOT23
10069#[inline(always)]
10070#[rustc_legacy_const_generics(2)]
10071#[cfg_attr(test, assert_instr(lsr, IU6 = 0))]
10072#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10073pub unsafe fn Q6_P_lsracc_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
10074    static_assert_uimm_bits!(IU6, 6);
10075    hexagon_S2_lsr_i_p_acc(rxx, rss, IU6 as i32)
10076}
10077
10078/// `Rxx32&=lsr(Rss32,#u6)`
10079///
10080/// Instruction Type: S_2op
10081/// Execution Slots: SLOT23
10082#[inline(always)]
10083#[rustc_legacy_const_generics(2)]
10084#[cfg_attr(test, assert_instr(lsr, IU6 = 0))]
10085#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10086pub unsafe fn Q6_P_lsrand_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
10087    static_assert_uimm_bits!(IU6, 6);
10088    hexagon_S2_lsr_i_p_and(rxx, rss, IU6 as i32)
10089}
10090
10091/// `Rxx32-=lsr(Rss32,#u6)`
10092///
10093/// Instruction Type: S_2op
10094/// Execution Slots: SLOT23
10095#[inline(always)]
10096#[rustc_legacy_const_generics(2)]
10097#[cfg_attr(test, assert_instr(lsr, IU6 = 0))]
10098#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10099pub unsafe fn Q6_P_lsrnac_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
10100    static_assert_uimm_bits!(IU6, 6);
10101    hexagon_S2_lsr_i_p_nac(rxx, rss, IU6 as i32)
10102}
10103
10104/// `Rxx32|=lsr(Rss32,#u6)`
10105///
10106/// Instruction Type: S_2op
10107/// Execution Slots: SLOT23
10108#[inline(always)]
10109#[rustc_legacy_const_generics(2)]
10110#[cfg_attr(test, assert_instr(lsr, IU6 = 0))]
10111#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10112pub unsafe fn Q6_P_lsror_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
10113    static_assert_uimm_bits!(IU6, 6);
10114    hexagon_S2_lsr_i_p_or(rxx, rss, IU6 as i32)
10115}
10116
10117/// `Rxx32^=lsr(Rss32,#u6)`
10118///
10119/// Instruction Type: S_2op
10120/// Execution Slots: SLOT23
10121#[inline(always)]
10122#[rustc_legacy_const_generics(2)]
10123#[cfg_attr(test, assert_instr(lsr, IU6 = 0))]
10124#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10125pub unsafe fn Q6_P_lsrxacc_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
10126    static_assert_uimm_bits!(IU6, 6);
10127    hexagon_S2_lsr_i_p_xacc(rxx, rss, IU6 as i32)
10128}
10129
10130/// `Rd32=lsr(Rs32,#u5)`
10131///
10132/// Instruction Type: S_2op
10133/// Execution Slots: SLOT23
10134#[inline(always)]
10135#[rustc_legacy_const_generics(1)]
10136#[cfg_attr(test, assert_instr(lsr, IU5 = 0))]
10137#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10138pub unsafe fn Q6_R_lsr_RI<const IU5: u32>(rs: i32) -> i32 {
10139    static_assert_uimm_bits!(IU5, 5);
10140    hexagon_S2_lsr_i_r(rs, IU5 as i32)
10141}
10142
10143/// `Rx32+=lsr(Rs32,#u5)`
10144///
10145/// Instruction Type: S_2op
10146/// Execution Slots: SLOT23
10147#[inline(always)]
10148#[rustc_legacy_const_generics(2)]
10149#[cfg_attr(test, assert_instr(lsr, IU5 = 0))]
10150#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10151pub unsafe fn Q6_R_lsracc_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
10152    static_assert_uimm_bits!(IU5, 5);
10153    hexagon_S2_lsr_i_r_acc(rx, rs, IU5 as i32)
10154}
10155
10156/// `Rx32&=lsr(Rs32,#u5)`
10157///
10158/// Instruction Type: S_2op
10159/// Execution Slots: SLOT23
10160#[inline(always)]
10161#[rustc_legacy_const_generics(2)]
10162#[cfg_attr(test, assert_instr(lsr, IU5 = 0))]
10163#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10164pub unsafe fn Q6_R_lsrand_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
10165    static_assert_uimm_bits!(IU5, 5);
10166    hexagon_S2_lsr_i_r_and(rx, rs, IU5 as i32)
10167}
10168
10169/// `Rx32-=lsr(Rs32,#u5)`
10170///
10171/// Instruction Type: S_2op
10172/// Execution Slots: SLOT23
10173#[inline(always)]
10174#[rustc_legacy_const_generics(2)]
10175#[cfg_attr(test, assert_instr(lsr, IU5 = 0))]
10176#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10177pub unsafe fn Q6_R_lsrnac_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
10178    static_assert_uimm_bits!(IU5, 5);
10179    hexagon_S2_lsr_i_r_nac(rx, rs, IU5 as i32)
10180}
10181
10182/// `Rx32|=lsr(Rs32,#u5)`
10183///
10184/// Instruction Type: S_2op
10185/// Execution Slots: SLOT23
10186#[inline(always)]
10187#[rustc_legacy_const_generics(2)]
10188#[cfg_attr(test, assert_instr(lsr, IU5 = 0))]
10189#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10190pub unsafe fn Q6_R_lsror_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
10191    static_assert_uimm_bits!(IU5, 5);
10192    hexagon_S2_lsr_i_r_or(rx, rs, IU5 as i32)
10193}
10194
10195/// `Rx32^=lsr(Rs32,#u5)`
10196///
10197/// Instruction Type: S_2op
10198/// Execution Slots: SLOT23
10199#[inline(always)]
10200#[rustc_legacy_const_generics(2)]
10201#[cfg_attr(test, assert_instr(lsr, IU5 = 0))]
10202#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10203pub unsafe fn Q6_R_lsrxacc_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
10204    static_assert_uimm_bits!(IU5, 5);
10205    hexagon_S2_lsr_i_r_xacc(rx, rs, IU5 as i32)
10206}
10207
10208/// `Rdd32=vlsrh(Rss32,#u4)`
10209///
10210/// Instruction Type: S_2op
10211/// Execution Slots: SLOT23
10212#[inline(always)]
10213#[rustc_legacy_const_generics(1)]
10214#[cfg_attr(test, assert_instr(vlsrh, IU4 = 0))]
10215#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10216pub unsafe fn Q6_P_vlsrh_PI<const IU4: u32>(rss: i64) -> i64 {
10217    static_assert_uimm_bits!(IU4, 4);
10218    hexagon_S2_lsr_i_vh(rss, IU4 as i32)
10219}
10220
10221/// `Rdd32=vlsrw(Rss32,#u5)`
10222///
10223/// Instruction Type: S_2op
10224/// Execution Slots: SLOT23
10225#[inline(always)]
10226#[rustc_legacy_const_generics(1)]
10227#[cfg_attr(test, assert_instr(vlsrw, IU5 = 0))]
10228#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10229pub unsafe fn Q6_P_vlsrw_PI<const IU5: u32>(rss: i64) -> i64 {
10230    static_assert_uimm_bits!(IU5, 5);
10231    hexagon_S2_lsr_i_vw(rss, IU5 as i32)
10232}
10233
10234/// `Rdd32=lsr(Rss32,Rt32)`
10235///
10236/// Instruction Type: S_3op
10237/// Execution Slots: SLOT23
10238#[inline(always)]
10239#[cfg_attr(test, assert_instr(lsr))]
10240#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10241pub unsafe fn Q6_P_lsr_PR(rss: i64, rt: i32) -> i64 {
10242    hexagon_S2_lsr_r_p(rss, rt)
10243}
10244
10245/// `Rxx32+=lsr(Rss32,Rt32)`
10246///
10247/// Instruction Type: S_3op
10248/// Execution Slots: SLOT23
10249#[inline(always)]
10250#[cfg_attr(test, assert_instr(lsr))]
10251#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10252pub unsafe fn Q6_P_lsracc_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
10253    hexagon_S2_lsr_r_p_acc(rxx, rss, rt)
10254}
10255
10256/// `Rxx32&=lsr(Rss32,Rt32)`
10257///
10258/// Instruction Type: S_3op
10259/// Execution Slots: SLOT23
10260#[inline(always)]
10261#[cfg_attr(test, assert_instr(lsr))]
10262#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10263pub unsafe fn Q6_P_lsrand_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
10264    hexagon_S2_lsr_r_p_and(rxx, rss, rt)
10265}
10266
10267/// `Rxx32-=lsr(Rss32,Rt32)`
10268///
10269/// Instruction Type: S_3op
10270/// Execution Slots: SLOT23
10271#[inline(always)]
10272#[cfg_attr(test, assert_instr(lsr))]
10273#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10274pub unsafe fn Q6_P_lsrnac_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
10275    hexagon_S2_lsr_r_p_nac(rxx, rss, rt)
10276}
10277
10278/// `Rxx32|=lsr(Rss32,Rt32)`
10279///
10280/// Instruction Type: S_3op
10281/// Execution Slots: SLOT23
10282#[inline(always)]
10283#[cfg_attr(test, assert_instr(lsr))]
10284#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10285pub unsafe fn Q6_P_lsror_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
10286    hexagon_S2_lsr_r_p_or(rxx, rss, rt)
10287}
10288
10289/// `Rxx32^=lsr(Rss32,Rt32)`
10290///
10291/// Instruction Type: S_3op
10292/// Execution Slots: SLOT23
10293#[inline(always)]
10294#[cfg_attr(test, assert_instr(lsr))]
10295#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10296pub unsafe fn Q6_P_lsrxacc_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
10297    hexagon_S2_lsr_r_p_xor(rxx, rss, rt)
10298}
10299
10300/// `Rd32=lsr(Rs32,Rt32)`
10301///
10302/// Instruction Type: S_3op
10303/// Execution Slots: SLOT23
10304#[inline(always)]
10305#[cfg_attr(test, assert_instr(lsr))]
10306#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10307pub unsafe fn Q6_R_lsr_RR(rs: i32, rt: i32) -> i32 {
10308    hexagon_S2_lsr_r_r(rs, rt)
10309}
10310
10311/// `Rx32+=lsr(Rs32,Rt32)`
10312///
10313/// Instruction Type: S_3op
10314/// Execution Slots: SLOT23
10315#[inline(always)]
10316#[cfg_attr(test, assert_instr(lsr))]
10317#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10318pub unsafe fn Q6_R_lsracc_RR(rx: i32, rs: i32, rt: i32) -> i32 {
10319    hexagon_S2_lsr_r_r_acc(rx, rs, rt)
10320}
10321
10322/// `Rx32&=lsr(Rs32,Rt32)`
10323///
10324/// Instruction Type: S_3op
10325/// Execution Slots: SLOT23
10326#[inline(always)]
10327#[cfg_attr(test, assert_instr(lsr))]
10328#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10329pub unsafe fn Q6_R_lsrand_RR(rx: i32, rs: i32, rt: i32) -> i32 {
10330    hexagon_S2_lsr_r_r_and(rx, rs, rt)
10331}
10332
10333/// `Rx32-=lsr(Rs32,Rt32)`
10334///
10335/// Instruction Type: S_3op
10336/// Execution Slots: SLOT23
10337#[inline(always)]
10338#[cfg_attr(test, assert_instr(lsr))]
10339#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10340pub unsafe fn Q6_R_lsrnac_RR(rx: i32, rs: i32, rt: i32) -> i32 {
10341    hexagon_S2_lsr_r_r_nac(rx, rs, rt)
10342}
10343
10344/// `Rx32|=lsr(Rs32,Rt32)`
10345///
10346/// Instruction Type: S_3op
10347/// Execution Slots: SLOT23
10348#[inline(always)]
10349#[cfg_attr(test, assert_instr(lsr))]
10350#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10351pub unsafe fn Q6_R_lsror_RR(rx: i32, rs: i32, rt: i32) -> i32 {
10352    hexagon_S2_lsr_r_r_or(rx, rs, rt)
10353}
10354
10355/// `Rdd32=vlsrh(Rss32,Rt32)`
10356///
10357/// Instruction Type: S_3op
10358/// Execution Slots: SLOT23
10359#[inline(always)]
10360#[cfg_attr(test, assert_instr(vlsrh))]
10361#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10362pub unsafe fn Q6_P_vlsrh_PR(rss: i64, rt: i32) -> i64 {
10363    hexagon_S2_lsr_r_vh(rss, rt)
10364}
10365
10366/// `Rdd32=vlsrw(Rss32,Rt32)`
10367///
10368/// Instruction Type: S_3op
10369/// Execution Slots: SLOT23
10370#[inline(always)]
10371#[cfg_attr(test, assert_instr(vlsrw))]
10372#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10373pub unsafe fn Q6_P_vlsrw_PR(rss: i64, rt: i32) -> i64 {
10374    hexagon_S2_lsr_r_vw(rss, rt)
10375}
10376
10377/// `Rdd32=packhl(Rs32,Rt32)`
10378///
10379/// Instruction Type: ALU32_3op
10380/// Execution Slots: SLOT0123
10381#[inline(always)]
10382#[cfg_attr(test, assert_instr(packhl))]
10383#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10384pub unsafe fn Q6_P_packhl_RR(rs: i32, rt: i32) -> i64 {
10385    hexagon_S2_packhl(rs, rt)
10386}
10387
10388/// `Rd32=parity(Rss32,Rtt32)`
10389///
10390/// Instruction Type: ALU64
10391/// Execution Slots: SLOT23
10392#[inline(always)]
10393#[cfg_attr(test, assert_instr(parity))]
10394#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10395pub unsafe fn Q6_R_parity_PP(rss: i64, rtt: i64) -> i32 {
10396    hexagon_S2_parityp(rss, rtt)
10397}
10398
10399/// `Rd32=setbit(Rs32,#u5)`
10400///
10401/// Instruction Type: S_2op
10402/// Execution Slots: SLOT23
10403#[inline(always)]
10404#[rustc_legacy_const_generics(1)]
10405#[cfg_attr(test, assert_instr(setbit, IU5 = 0))]
10406#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10407pub unsafe fn Q6_R_setbit_RI<const IU5: u32>(rs: i32) -> i32 {
10408    static_assert_uimm_bits!(IU5, 5);
10409    hexagon_S2_setbit_i(rs, IU5 as i32)
10410}
10411
10412/// `Rd32=setbit(Rs32,Rt32)`
10413///
10414/// Instruction Type: S_3op
10415/// Execution Slots: SLOT23
10416#[inline(always)]
10417#[cfg_attr(test, assert_instr(setbit))]
10418#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10419pub unsafe fn Q6_R_setbit_RR(rs: i32, rt: i32) -> i32 {
10420    hexagon_S2_setbit_r(rs, rt)
10421}
10422
10423/// `Rdd32=shuffeb(Rss32,Rtt32)`
10424///
10425/// Instruction Type: S_3op
10426/// Execution Slots: SLOT23
10427#[inline(always)]
10428#[cfg_attr(test, assert_instr(shuffeb))]
10429#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10430pub unsafe fn Q6_P_shuffeb_PP(rss: i64, rtt: i64) -> i64 {
10431    hexagon_S2_shuffeb(rss, rtt)
10432}
10433
10434/// `Rdd32=shuffeh(Rss32,Rtt32)`
10435///
10436/// Instruction Type: S_3op
10437/// Execution Slots: SLOT23
10438#[inline(always)]
10439#[cfg_attr(test, assert_instr(shuffeh))]
10440#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10441pub unsafe fn Q6_P_shuffeh_PP(rss: i64, rtt: i64) -> i64 {
10442    hexagon_S2_shuffeh(rss, rtt)
10443}
10444
10445/// `Rdd32=shuffob(Rtt32,Rss32)`
10446///
10447/// Instruction Type: S_3op
10448/// Execution Slots: SLOT23
10449#[inline(always)]
10450#[cfg_attr(test, assert_instr(shuffob))]
10451#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10452pub unsafe fn Q6_P_shuffob_PP(rtt: i64, rss: i64) -> i64 {
10453    hexagon_S2_shuffob(rtt, rss)
10454}
10455
10456/// `Rdd32=shuffoh(Rtt32,Rss32)`
10457///
10458/// Instruction Type: S_3op
10459/// Execution Slots: SLOT23
10460#[inline(always)]
10461#[cfg_attr(test, assert_instr(shuffoh))]
10462#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10463pub unsafe fn Q6_P_shuffoh_PP(rtt: i64, rss: i64) -> i64 {
10464    hexagon_S2_shuffoh(rtt, rss)
10465}
10466
10467/// `Rd32=vsathb(Rs32)`
10468///
10469/// Instruction Type: S_2op
10470/// Execution Slots: SLOT23
10471#[inline(always)]
10472#[cfg_attr(test, assert_instr(vsathb))]
10473#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10474pub unsafe fn Q6_R_vsathb_R(rs: i32) -> i32 {
10475    hexagon_S2_svsathb(rs)
10476}
10477
10478/// `Rd32=vsathub(Rs32)`
10479///
10480/// Instruction Type: S_2op
10481/// Execution Slots: SLOT23
10482#[inline(always)]
10483#[cfg_attr(test, assert_instr(vsathub))]
10484#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10485pub unsafe fn Q6_R_vsathub_R(rs: i32) -> i32 {
10486    hexagon_S2_svsathub(rs)
10487}
10488
10489/// `Rx32=tableidxb(Rs32,#u4,#U5)`
10490///
10491/// Instruction Type: S_2op
10492/// Execution Slots: SLOT0123
10493#[inline(always)]
10494#[rustc_legacy_const_generics(2, 3)]
10495#[cfg_attr(test, assert_instr(tableidxb, IU4 = 0, IU5 = 0))]
10496#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10497pub unsafe fn Q6_R_tableidxb_RII<const IU4: u32, const IU5: u32>(rx: i32, rs: i32) -> i32 {
10498    static_assert_uimm_bits!(IU4, 4);
10499    static_assert_uimm_bits!(IU5, 5);
10500    hexagon_S2_tableidxb_goodsyntax(rx, rs, IU4 as i32, IU5 as i32)
10501}
10502
10503/// `Rx32=tableidxd(Rs32,#u4,#U5)`
10504///
10505/// Instruction Type: S_2op
10506/// Execution Slots: SLOT0123
10507#[inline(always)]
10508#[rustc_legacy_const_generics(2, 3)]
10509#[cfg_attr(test, assert_instr(tableidxd, IU4 = 0, IU5 = 0))]
10510#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10511pub unsafe fn Q6_R_tableidxd_RII<const IU4: u32, const IU5: u32>(rx: i32, rs: i32) -> i32 {
10512    static_assert_uimm_bits!(IU4, 4);
10513    static_assert_uimm_bits!(IU5, 5);
10514    hexagon_S2_tableidxd_goodsyntax(rx, rs, IU4 as i32, IU5 as i32)
10515}
10516
10517/// `Rx32=tableidxh(Rs32,#u4,#U5)`
10518///
10519/// Instruction Type: S_2op
10520/// Execution Slots: SLOT0123
10521#[inline(always)]
10522#[rustc_legacy_const_generics(2, 3)]
10523#[cfg_attr(test, assert_instr(tableidxh, IU4 = 0, IU5 = 0))]
10524#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10525pub unsafe fn Q6_R_tableidxh_RII<const IU4: u32, const IU5: u32>(rx: i32, rs: i32) -> i32 {
10526    static_assert_uimm_bits!(IU4, 4);
10527    static_assert_uimm_bits!(IU5, 5);
10528    hexagon_S2_tableidxh_goodsyntax(rx, rs, IU4 as i32, IU5 as i32)
10529}
10530
10531/// `Rx32=tableidxw(Rs32,#u4,#U5)`
10532///
10533/// Instruction Type: S_2op
10534/// Execution Slots: SLOT0123
10535#[inline(always)]
10536#[rustc_legacy_const_generics(2, 3)]
10537#[cfg_attr(test, assert_instr(tableidxw, IU4 = 0, IU5 = 0))]
10538#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10539pub unsafe fn Q6_R_tableidxw_RII<const IU4: u32, const IU5: u32>(rx: i32, rs: i32) -> i32 {
10540    static_assert_uimm_bits!(IU4, 4);
10541    static_assert_uimm_bits!(IU5, 5);
10542    hexagon_S2_tableidxw_goodsyntax(rx, rs, IU4 as i32, IU5 as i32)
10543}
10544
10545/// `Rd32=togglebit(Rs32,#u5)`
10546///
10547/// Instruction Type: S_2op
10548/// Execution Slots: SLOT23
10549#[inline(always)]
10550#[rustc_legacy_const_generics(1)]
10551#[cfg_attr(test, assert_instr(togglebit, IU5 = 0))]
10552#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10553pub unsafe fn Q6_R_togglebit_RI<const IU5: u32>(rs: i32) -> i32 {
10554    static_assert_uimm_bits!(IU5, 5);
10555    hexagon_S2_togglebit_i(rs, IU5 as i32)
10556}
10557
10558/// `Rd32=togglebit(Rs32,Rt32)`
10559///
10560/// Instruction Type: S_3op
10561/// Execution Slots: SLOT23
10562#[inline(always)]
10563#[cfg_attr(test, assert_instr(togglebit))]
10564#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10565pub unsafe fn Q6_R_togglebit_RR(rs: i32, rt: i32) -> i32 {
10566    hexagon_S2_togglebit_r(rs, rt)
10567}
10568
10569/// `Pd4=tstbit(Rs32,#u5)`
10570///
10571/// Instruction Type: S_2op
10572/// Execution Slots: SLOT23
10573#[inline(always)]
10574#[rustc_legacy_const_generics(1)]
10575#[cfg_attr(test, assert_instr(tstbit, IU5 = 0))]
10576#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10577pub unsafe fn Q6_p_tstbit_RI<const IU5: u32>(rs: i32) -> i32 {
10578    static_assert_uimm_bits!(IU5, 5);
10579    hexagon_S2_tstbit_i(rs, IU5 as i32)
10580}
10581
10582/// `Pd4=tstbit(Rs32,Rt32)`
10583///
10584/// Instruction Type: S_3op
10585/// Execution Slots: SLOT23
10586#[inline(always)]
10587#[cfg_attr(test, assert_instr(tstbit))]
10588#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10589pub unsafe fn Q6_p_tstbit_RR(rs: i32, rt: i32) -> i32 {
10590    hexagon_S2_tstbit_r(rs, rt)
10591}
10592
10593/// `Rdd32=valignb(Rtt32,Rss32,#u3)`
10594///
10595/// Instruction Type: S_3op
10596/// Execution Slots: SLOT23
10597#[inline(always)]
10598#[rustc_legacy_const_generics(2)]
10599#[cfg_attr(test, assert_instr(valignb, IU3 = 0))]
10600#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10601pub unsafe fn Q6_P_valignb_PPI<const IU3: u32>(rtt: i64, rss: i64) -> i64 {
10602    static_assert_uimm_bits!(IU3, 3);
10603    hexagon_S2_valignib(rtt, rss, IU3 as i32)
10604}
10605
10606/// `Rdd32=valignb(Rtt32,Rss32,Pu4)`
10607///
10608/// Instruction Type: S_3op
10609/// Execution Slots: SLOT23
10610#[inline(always)]
10611#[cfg_attr(test, assert_instr(valignb))]
10612#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10613pub unsafe fn Q6_P_valignb_PPp(rtt: i64, rss: i64, pu: i32) -> i64 {
10614    hexagon_S2_valignrb(rtt, rss, pu)
10615}
10616
10617/// `Rdd32=vcnegh(Rss32,Rt32)`
10618///
10619/// Instruction Type: S_3op
10620/// Execution Slots: SLOT23
10621#[inline(always)]
10622#[cfg_attr(test, assert_instr(vcnegh))]
10623#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10624pub unsafe fn Q6_P_vcnegh_PR(rss: i64, rt: i32) -> i64 {
10625    hexagon_S2_vcnegh(rss, rt)
10626}
10627
10628/// `Rdd32=vcrotate(Rss32,Rt32)`
10629///
10630/// Instruction Type: S_3op
10631/// Execution Slots: SLOT23
10632#[inline(always)]
10633#[cfg_attr(test, assert_instr(vcrotate))]
10634#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10635pub unsafe fn Q6_P_vcrotate_PR(rss: i64, rt: i32) -> i64 {
10636    hexagon_S2_vcrotate(rss, rt)
10637}
10638
10639/// `Rxx32+=vrcnegh(Rss32,Rt32)`
10640///
10641/// Instruction Type: S_3op
10642/// Execution Slots: SLOT23
10643#[inline(always)]
10644#[cfg_attr(test, assert_instr(vrcnegh))]
10645#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10646pub unsafe fn Q6_P_vrcneghacc_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
10647    hexagon_S2_vrcnegh(rxx, rss, rt)
10648}
10649
10650/// `Rd32=vrndwh(Rss32)`
10651///
10652/// Instruction Type: S_2op
10653/// Execution Slots: SLOT23
10654#[inline(always)]
10655#[cfg_attr(test, assert_instr(vrndwh))]
10656#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10657pub unsafe fn Q6_R_vrndwh_P(rss: i64) -> i32 {
10658    hexagon_S2_vrndpackwh(rss)
10659}
10660
10661/// `Rd32=vrndwh(Rss32):sat`
10662///
10663/// Instruction Type: S_2op
10664/// Execution Slots: SLOT23
10665#[inline(always)]
10666#[cfg_attr(test, assert_instr(vrndwh))]
10667#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10668pub unsafe fn Q6_R_vrndwh_P_sat(rss: i64) -> i32 {
10669    hexagon_S2_vrndpackwhs(rss)
10670}
10671
10672/// `Rd32=vsathb(Rss32)`
10673///
10674/// Instruction Type: S_2op
10675/// Execution Slots: SLOT23
10676#[inline(always)]
10677#[cfg_attr(test, assert_instr(vsathb))]
10678#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10679pub unsafe fn Q6_R_vsathb_P(rss: i64) -> i32 {
10680    hexagon_S2_vsathb(rss)
10681}
10682
10683/// `Rdd32=vsathb(Rss32)`
10684///
10685/// Instruction Type: S_2op
10686/// Execution Slots: SLOT23
10687#[inline(always)]
10688#[cfg_attr(test, assert_instr(vsathb))]
10689#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10690pub unsafe fn Q6_P_vsathb_P(rss: i64) -> i64 {
10691    hexagon_S2_vsathb_nopack(rss)
10692}
10693
10694/// `Rd32=vsathub(Rss32)`
10695///
10696/// Instruction Type: S_2op
10697/// Execution Slots: SLOT23
10698#[inline(always)]
10699#[cfg_attr(test, assert_instr(vsathub))]
10700#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10701pub unsafe fn Q6_R_vsathub_P(rss: i64) -> i32 {
10702    hexagon_S2_vsathub(rss)
10703}
10704
10705/// `Rdd32=vsathub(Rss32)`
10706///
10707/// Instruction Type: S_2op
10708/// Execution Slots: SLOT23
10709#[inline(always)]
10710#[cfg_attr(test, assert_instr(vsathub))]
10711#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10712pub unsafe fn Q6_P_vsathub_P(rss: i64) -> i64 {
10713    hexagon_S2_vsathub_nopack(rss)
10714}
10715
10716/// `Rd32=vsatwh(Rss32)`
10717///
10718/// Instruction Type: S_2op
10719/// Execution Slots: SLOT23
10720#[inline(always)]
10721#[cfg_attr(test, assert_instr(vsatwh))]
10722#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10723pub unsafe fn Q6_R_vsatwh_P(rss: i64) -> i32 {
10724    hexagon_S2_vsatwh(rss)
10725}
10726
10727/// `Rdd32=vsatwh(Rss32)`
10728///
10729/// Instruction Type: S_2op
10730/// Execution Slots: SLOT23
10731#[inline(always)]
10732#[cfg_attr(test, assert_instr(vsatwh))]
10733#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10734pub unsafe fn Q6_P_vsatwh_P(rss: i64) -> i64 {
10735    hexagon_S2_vsatwh_nopack(rss)
10736}
10737
10738/// `Rd32=vsatwuh(Rss32)`
10739///
10740/// Instruction Type: S_2op
10741/// Execution Slots: SLOT23
10742#[inline(always)]
10743#[cfg_attr(test, assert_instr(vsatwuh))]
10744#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10745pub unsafe fn Q6_R_vsatwuh_P(rss: i64) -> i32 {
10746    hexagon_S2_vsatwuh(rss)
10747}
10748
10749/// `Rdd32=vsatwuh(Rss32)`
10750///
10751/// Instruction Type: S_2op
10752/// Execution Slots: SLOT23
10753#[inline(always)]
10754#[cfg_attr(test, assert_instr(vsatwuh))]
10755#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10756pub unsafe fn Q6_P_vsatwuh_P(rss: i64) -> i64 {
10757    hexagon_S2_vsatwuh_nopack(rss)
10758}
10759
10760/// `Rd32=vsplatb(Rs32)`
10761///
10762/// Instruction Type: S_2op
10763/// Execution Slots: SLOT23
10764#[inline(always)]
10765#[cfg_attr(test, assert_instr(vsplatb))]
10766#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10767pub unsafe fn Q6_R_vsplatb_R(rs: i32) -> i32 {
10768    hexagon_S2_vsplatrb(rs)
10769}
10770
10771/// `Rdd32=vsplath(Rs32)`
10772///
10773/// Instruction Type: S_2op
10774/// Execution Slots: SLOT23
10775#[inline(always)]
10776#[cfg_attr(test, assert_instr(vsplath))]
10777#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10778pub unsafe fn Q6_P_vsplath_R(rs: i32) -> i64 {
10779    hexagon_S2_vsplatrh(rs)
10780}
10781
10782/// `Rdd32=vspliceb(Rss32,Rtt32,#u3)`
10783///
10784/// Instruction Type: S_3op
10785/// Execution Slots: SLOT23
10786#[inline(always)]
10787#[rustc_legacy_const_generics(2)]
10788#[cfg_attr(test, assert_instr(vspliceb, IU3 = 0))]
10789#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10790pub unsafe fn Q6_P_vspliceb_PPI<const IU3: u32>(rss: i64, rtt: i64) -> i64 {
10791    static_assert_uimm_bits!(IU3, 3);
10792    hexagon_S2_vspliceib(rss, rtt, IU3 as i32)
10793}
10794
10795/// `Rdd32=vspliceb(Rss32,Rtt32,Pu4)`
10796///
10797/// Instruction Type: S_3op
10798/// Execution Slots: SLOT23
10799#[inline(always)]
10800#[cfg_attr(test, assert_instr(vspliceb))]
10801#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10802pub unsafe fn Q6_P_vspliceb_PPp(rss: i64, rtt: i64, pu: i32) -> i64 {
10803    hexagon_S2_vsplicerb(rss, rtt, pu)
10804}
10805
10806/// `Rdd32=vsxtbh(Rs32)`
10807///
10808/// Instruction Type: S_2op
10809/// Execution Slots: SLOT23
10810#[inline(always)]
10811#[cfg_attr(test, assert_instr(vsxtbh))]
10812#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10813pub unsafe fn Q6_P_vsxtbh_R(rs: i32) -> i64 {
10814    hexagon_S2_vsxtbh(rs)
10815}
10816
10817/// `Rdd32=vsxthw(Rs32)`
10818///
10819/// Instruction Type: S_2op
10820/// Execution Slots: SLOT23
10821#[inline(always)]
10822#[cfg_attr(test, assert_instr(vsxthw))]
10823#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10824pub unsafe fn Q6_P_vsxthw_R(rs: i32) -> i64 {
10825    hexagon_S2_vsxthw(rs)
10826}
10827
10828/// `Rd32=vtrunehb(Rss32)`
10829///
10830/// Instruction Type: S_2op
10831/// Execution Slots: SLOT23
10832#[inline(always)]
10833#[cfg_attr(test, assert_instr(vtrunehb))]
10834#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10835pub unsafe fn Q6_R_vtrunehb_P(rss: i64) -> i32 {
10836    hexagon_S2_vtrunehb(rss)
10837}
10838
10839/// `Rdd32=vtrunewh(Rss32,Rtt32)`
10840///
10841/// Instruction Type: S_3op
10842/// Execution Slots: SLOT23
10843#[inline(always)]
10844#[cfg_attr(test, assert_instr(vtrunewh))]
10845#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10846pub unsafe fn Q6_P_vtrunewh_PP(rss: i64, rtt: i64) -> i64 {
10847    hexagon_S2_vtrunewh(rss, rtt)
10848}
10849
10850/// `Rd32=vtrunohb(Rss32)`
10851///
10852/// Instruction Type: S_2op
10853/// Execution Slots: SLOT23
10854#[inline(always)]
10855#[cfg_attr(test, assert_instr(vtrunohb))]
10856#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10857pub unsafe fn Q6_R_vtrunohb_P(rss: i64) -> i32 {
10858    hexagon_S2_vtrunohb(rss)
10859}
10860
10861/// `Rdd32=vtrunowh(Rss32,Rtt32)`
10862///
10863/// Instruction Type: S_3op
10864/// Execution Slots: SLOT23
10865#[inline(always)]
10866#[cfg_attr(test, assert_instr(vtrunowh))]
10867#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10868pub unsafe fn Q6_P_vtrunowh_PP(rss: i64, rtt: i64) -> i64 {
10869    hexagon_S2_vtrunowh(rss, rtt)
10870}
10871
10872/// `Rdd32=vzxtbh(Rs32)`
10873///
10874/// Instruction Type: S_2op
10875/// Execution Slots: SLOT23
10876#[inline(always)]
10877#[cfg_attr(test, assert_instr(vzxtbh))]
10878#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10879pub unsafe fn Q6_P_vzxtbh_R(rs: i32) -> i64 {
10880    hexagon_S2_vzxtbh(rs)
10881}
10882
10883/// `Rdd32=vzxthw(Rs32)`
10884///
10885/// Instruction Type: S_2op
10886/// Execution Slots: SLOT23
10887#[inline(always)]
10888#[cfg_attr(test, assert_instr(vzxthw))]
10889#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10890pub unsafe fn Q6_P_vzxthw_R(rs: i32) -> i64 {
10891    hexagon_S2_vzxthw(rs)
10892}
10893
10894/// `Rd32=add(Rs32,add(Ru32,#s6))`
10895///
10896/// Instruction Type: ALU64
10897/// Execution Slots: SLOT23
10898#[inline(always)]
10899#[rustc_legacy_const_generics(2)]
10900#[cfg_attr(test, assert_instr(add, IS6 = 0))]
10901#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10902pub unsafe fn Q6_R_add_add_RRI<const IS6: i32>(rs: i32, ru: i32) -> i32 {
10903    static_assert_simm_bits!(IS6, 6);
10904    hexagon_S4_addaddi(rs, ru, IS6)
10905}
10906
10907/// `Rx32=add(#u8,asl(Rx32,#U5))`
10908///
10909/// Instruction Type: ALU64
10910/// Execution Slots: SLOT23
10911#[inline(always)]
10912#[rustc_legacy_const_generics(0, 2)]
10913#[cfg_attr(test, assert_instr(add, IU8 = 0, IU5 = 0))]
10914#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10915pub unsafe fn Q6_R_add_asl_IRI<const IU8: u32, const IU5: u32>(rx: i32) -> i32 {
10916    static_assert_uimm_bits!(IU8, 8);
10917    static_assert_uimm_bits!(IU5, 5);
10918    hexagon_S4_addi_asl_ri(IU8 as i32, rx, IU5 as i32)
10919}
10920
10921/// `Rx32=add(#u8,lsr(Rx32,#U5))`
10922///
10923/// Instruction Type: ALU64
10924/// Execution Slots: SLOT23
10925#[inline(always)]
10926#[rustc_legacy_const_generics(0, 2)]
10927#[cfg_attr(test, assert_instr(add, IU8 = 0, IU5 = 0))]
10928#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10929pub unsafe fn Q6_R_add_lsr_IRI<const IU8: u32, const IU5: u32>(rx: i32) -> i32 {
10930    static_assert_uimm_bits!(IU8, 8);
10931    static_assert_uimm_bits!(IU5, 5);
10932    hexagon_S4_addi_lsr_ri(IU8 as i32, rx, IU5 as i32)
10933}
10934
10935/// `Rx32=and(#u8,asl(Rx32,#U5))`
10936///
10937/// Instruction Type: ALU64
10938/// Execution Slots: SLOT23
10939#[inline(always)]
10940#[rustc_legacy_const_generics(0, 2)]
10941#[cfg_attr(test, assert_instr(and, IU8 = 0, IU5 = 0))]
10942#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10943pub unsafe fn Q6_R_and_asl_IRI<const IU8: u32, const IU5: u32>(rx: i32) -> i32 {
10944    static_assert_uimm_bits!(IU8, 8);
10945    static_assert_uimm_bits!(IU5, 5);
10946    hexagon_S4_andi_asl_ri(IU8 as i32, rx, IU5 as i32)
10947}
10948
10949/// `Rx32=and(#u8,lsr(Rx32,#U5))`
10950///
10951/// Instruction Type: ALU64
10952/// Execution Slots: SLOT23
10953#[inline(always)]
10954#[rustc_legacy_const_generics(0, 2)]
10955#[cfg_attr(test, assert_instr(and, IU8 = 0, IU5 = 0))]
10956#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10957pub unsafe fn Q6_R_and_lsr_IRI<const IU8: u32, const IU5: u32>(rx: i32) -> i32 {
10958    static_assert_uimm_bits!(IU8, 8);
10959    static_assert_uimm_bits!(IU5, 5);
10960    hexagon_S4_andi_lsr_ri(IU8 as i32, rx, IU5 as i32)
10961}
10962
10963/// `Rd32=add(clb(Rs32),#s6)`
10964///
10965/// Instruction Type: S_2op
10966/// Execution Slots: SLOT23
10967#[inline(always)]
10968#[rustc_legacy_const_generics(1)]
10969#[cfg_attr(test, assert_instr(add, IS6 = 0))]
10970#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10971pub unsafe fn Q6_R_add_clb_RI<const IS6: i32>(rs: i32) -> i32 {
10972    static_assert_simm_bits!(IS6, 6);
10973    hexagon_S4_clbaddi(rs, IS6)
10974}
10975
10976/// `Rd32=add(clb(Rss32),#s6)`
10977///
10978/// Instruction Type: S_2op
10979/// Execution Slots: SLOT23
10980#[inline(always)]
10981#[rustc_legacy_const_generics(1)]
10982#[cfg_attr(test, assert_instr(add, IS6 = 0))]
10983#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10984pub unsafe fn Q6_R_add_clb_PI<const IS6: i32>(rss: i64) -> i32 {
10985    static_assert_simm_bits!(IS6, 6);
10986    hexagon_S4_clbpaddi(rss, IS6)
10987}
10988
10989/// `Rd32=normamt(Rss32)`
10990///
10991/// Instruction Type: S_2op
10992/// Execution Slots: SLOT23
10993#[inline(always)]
10994#[cfg_attr(test, assert_instr(normamt))]
10995#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10996pub unsafe fn Q6_R_normamt_P(rss: i64) -> i32 {
10997    hexagon_S4_clbpnorm(rss)
10998}
10999
11000/// `Rd32=extract(Rs32,#u5,#U5)`
11001///
11002/// Instruction Type: S_2op
11003/// Execution Slots: SLOT23
11004#[inline(always)]
11005#[rustc_legacy_const_generics(1, 2)]
11006#[cfg_attr(test, assert_instr(extract, IU5 = 0, IU5_2 = 0))]
11007#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11008pub unsafe fn Q6_R_extract_RII<const IU5: u32, const IU5_2: u32>(rs: i32) -> i32 {
11009    static_assert_uimm_bits!(IU5, 5);
11010    static_assert_uimm_bits!(IU5_2, 5);
11011    hexagon_S4_extract(rs, IU5 as i32, IU5_2 as i32)
11012}
11013
11014/// `Rd32=extract(Rs32,Rtt32)`
11015///
11016/// Instruction Type: S_3op
11017/// Execution Slots: SLOT23
11018#[inline(always)]
11019#[cfg_attr(test, assert_instr(extract))]
11020#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11021pub unsafe fn Q6_R_extract_RP(rs: i32, rtt: i64) -> i32 {
11022    hexagon_S4_extract_rp(rs, rtt)
11023}
11024
11025/// `Rdd32=extract(Rss32,#u6,#U6)`
11026///
11027/// Instruction Type: S_2op
11028/// Execution Slots: SLOT23
11029#[inline(always)]
11030#[rustc_legacy_const_generics(1, 2)]
11031#[cfg_attr(test, assert_instr(extract, IU6 = 0, IU6_2 = 0))]
11032#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11033pub unsafe fn Q6_P_extract_PII<const IU6: u32, const IU6_2: u32>(rss: i64) -> i64 {
11034    static_assert_uimm_bits!(IU6, 6);
11035    static_assert_uimm_bits!(IU6_2, 6);
11036    hexagon_S4_extractp(rss, IU6 as i32, IU6_2 as i32)
11037}
11038
11039/// `Rdd32=extract(Rss32,Rtt32)`
11040///
11041/// Instruction Type: S_3op
11042/// Execution Slots: SLOT23
11043#[inline(always)]
11044#[cfg_attr(test, assert_instr(extract))]
11045#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11046pub unsafe fn Q6_P_extract_PP(rss: i64, rtt: i64) -> i64 {
11047    hexagon_S4_extractp_rp(rss, rtt)
11048}
11049
11050/// `Rd32=lsl(#s6,Rt32)`
11051///
11052/// Instruction Type: S_3op
11053/// Execution Slots: SLOT23
11054#[inline(always)]
11055#[rustc_legacy_const_generics(0)]
11056#[cfg_attr(test, assert_instr(lsl, IS6 = 0))]
11057#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11058pub unsafe fn Q6_R_lsl_IR<const IS6: i32>(rt: i32) -> i32 {
11059    static_assert_simm_bits!(IS6, 6);
11060    hexagon_S4_lsli(IS6, rt)
11061}
11062
11063/// `Pd4=!tstbit(Rs32,#u5)`
11064///
11065/// Instruction Type: S_2op
11066/// Execution Slots: SLOT23
11067#[inline(always)]
11068#[rustc_legacy_const_generics(1)]
11069#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11070pub unsafe fn Q6_p_not_tstbit_RI<const IU5: u32>(rs: i32) -> i32 {
11071    static_assert_uimm_bits!(IU5, 5);
11072    hexagon_S4_ntstbit_i(rs, IU5 as i32)
11073}
11074
11075/// `Pd4=!tstbit(Rs32,Rt32)`
11076///
11077/// Instruction Type: S_3op
11078/// Execution Slots: SLOT23
11079#[inline(always)]
11080#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11081pub unsafe fn Q6_p_not_tstbit_RR(rs: i32, rt: i32) -> i32 {
11082    hexagon_S4_ntstbit_r(rs, rt)
11083}
11084
11085/// `Rx32|=and(Rs32,#s10)`
11086///
11087/// Instruction Type: ALU64
11088/// Execution Slots: SLOT23
11089#[inline(always)]
11090#[rustc_legacy_const_generics(2)]
11091#[cfg_attr(test, assert_instr(and, IS10 = 0))]
11092#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11093pub unsafe fn Q6_R_andor_RI<const IS10: i32>(rx: i32, rs: i32) -> i32 {
11094    static_assert_simm_bits!(IS10, 10);
11095    hexagon_S4_or_andi(rx, rs, IS10)
11096}
11097
11098/// `Rx32=or(Ru32,and(Rx32,#s10))`
11099///
11100/// Instruction Type: ALU64
11101/// Execution Slots: SLOT23
11102#[inline(always)]
11103#[rustc_legacy_const_generics(2)]
11104#[cfg_attr(test, assert_instr(or, IS10 = 0))]
11105#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11106pub unsafe fn Q6_R_or_and_RRI<const IS10: i32>(ru: i32, rx: i32) -> i32 {
11107    static_assert_simm_bits!(IS10, 10);
11108    hexagon_S4_or_andix(ru, rx, IS10)
11109}
11110
11111/// `Rx32|=or(Rs32,#s10)`
11112///
11113/// Instruction Type: ALU64
11114/// Execution Slots: SLOT23
11115#[inline(always)]
11116#[rustc_legacy_const_generics(2)]
11117#[cfg_attr(test, assert_instr(or, IS10 = 0))]
11118#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11119pub unsafe fn Q6_R_oror_RI<const IS10: i32>(rx: i32, rs: i32) -> i32 {
11120    static_assert_simm_bits!(IS10, 10);
11121    hexagon_S4_or_ori(rx, rs, IS10)
11122}
11123
11124/// `Rx32=or(#u8,asl(Rx32,#U5))`
11125///
11126/// Instruction Type: ALU64
11127/// Execution Slots: SLOT23
11128#[inline(always)]
11129#[rustc_legacy_const_generics(0, 2)]
11130#[cfg_attr(test, assert_instr(or, IU8 = 0, IU5 = 0))]
11131#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11132pub unsafe fn Q6_R_or_asl_IRI<const IU8: u32, const IU5: u32>(rx: i32) -> i32 {
11133    static_assert_uimm_bits!(IU8, 8);
11134    static_assert_uimm_bits!(IU5, 5);
11135    hexagon_S4_ori_asl_ri(IU8 as i32, rx, IU5 as i32)
11136}
11137
11138/// `Rx32=or(#u8,lsr(Rx32,#U5))`
11139///
11140/// Instruction Type: ALU64
11141/// Execution Slots: SLOT23
11142#[inline(always)]
11143#[rustc_legacy_const_generics(0, 2)]
11144#[cfg_attr(test, assert_instr(or, IU8 = 0, IU5 = 0))]
11145#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11146pub unsafe fn Q6_R_or_lsr_IRI<const IU8: u32, const IU5: u32>(rx: i32) -> i32 {
11147    static_assert_uimm_bits!(IU8, 8);
11148    static_assert_uimm_bits!(IU5, 5);
11149    hexagon_S4_ori_lsr_ri(IU8 as i32, rx, IU5 as i32)
11150}
11151
11152/// `Rd32=parity(Rs32,Rt32)`
11153///
11154/// Instruction Type: ALU64
11155/// Execution Slots: SLOT23
11156#[inline(always)]
11157#[cfg_attr(test, assert_instr(parity))]
11158#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11159pub unsafe fn Q6_R_parity_RR(rs: i32, rt: i32) -> i32 {
11160    hexagon_S4_parity(rs, rt)
11161}
11162
11163/// `Rd32=add(Rs32,sub(#s6,Ru32))`
11164///
11165/// Instruction Type: ALU64
11166/// Execution Slots: SLOT23
11167#[inline(always)]
11168#[rustc_legacy_const_generics(1)]
11169#[cfg_attr(test, assert_instr(add, IS6 = 0))]
11170#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11171pub unsafe fn Q6_R_add_sub_RIR<const IS6: i32>(rs: i32, ru: i32) -> i32 {
11172    static_assert_simm_bits!(IS6, 6);
11173    hexagon_S4_subaddi(rs, IS6, ru)
11174}
11175
11176/// `Rx32=sub(#u8,asl(Rx32,#U5))`
11177///
11178/// Instruction Type: ALU64
11179/// Execution Slots: SLOT23
11180#[inline(always)]
11181#[rustc_legacy_const_generics(0, 2)]
11182#[cfg_attr(test, assert_instr(sub, IU8 = 0, IU5 = 0))]
11183#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11184pub unsafe fn Q6_R_sub_asl_IRI<const IU8: u32, const IU5: u32>(rx: i32) -> i32 {
11185    static_assert_uimm_bits!(IU8, 8);
11186    static_assert_uimm_bits!(IU5, 5);
11187    hexagon_S4_subi_asl_ri(IU8 as i32, rx, IU5 as i32)
11188}
11189
11190/// `Rx32=sub(#u8,lsr(Rx32,#U5))`
11191///
11192/// Instruction Type: ALU64
11193/// Execution Slots: SLOT23
11194#[inline(always)]
11195#[rustc_legacy_const_generics(0, 2)]
11196#[cfg_attr(test, assert_instr(sub, IU8 = 0, IU5 = 0))]
11197#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11198pub unsafe fn Q6_R_sub_lsr_IRI<const IU8: u32, const IU5: u32>(rx: i32) -> i32 {
11199    static_assert_uimm_bits!(IU8, 8);
11200    static_assert_uimm_bits!(IU5, 5);
11201    hexagon_S4_subi_lsr_ri(IU8 as i32, rx, IU5 as i32)
11202}
11203
11204/// `Rdd32=vrcrotate(Rss32,Rt32,#u2)`
11205///
11206/// Instruction Type: S_3op
11207/// Execution Slots: SLOT23
11208#[inline(always)]
11209#[rustc_legacy_const_generics(2)]
11210#[cfg_attr(test, assert_instr(vrcrotate, IU2 = 0))]
11211#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11212pub unsafe fn Q6_P_vrcrotate_PRI<const IU2: u32>(rss: i64, rt: i32) -> i64 {
11213    static_assert_uimm_bits!(IU2, 2);
11214    hexagon_S4_vrcrotate(rss, rt, IU2 as i32)
11215}
11216
11217/// `Rxx32+=vrcrotate(Rss32,Rt32,#u2)`
11218///
11219/// Instruction Type: S_3op
11220/// Execution Slots: SLOT23
11221#[inline(always)]
11222#[rustc_legacy_const_generics(3)]
11223#[cfg_attr(test, assert_instr(vrcrotate, IU2 = 0))]
11224#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11225pub unsafe fn Q6_P_vrcrotateacc_PRI<const IU2: u32>(rxx: i64, rss: i64, rt: i32) -> i64 {
11226    static_assert_uimm_bits!(IU2, 2);
11227    hexagon_S4_vrcrotate_acc(rxx, rss, rt, IU2 as i32)
11228}
11229
11230/// `Rdd32=vxaddsubh(Rss32,Rtt32):sat`
11231///
11232/// Instruction Type: S_3op
11233/// Execution Slots: SLOT23
11234#[inline(always)]
11235#[cfg_attr(test, assert_instr(vxaddsubh))]
11236#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11237pub unsafe fn Q6_P_vxaddsubh_PP_sat(rss: i64, rtt: i64) -> i64 {
11238    hexagon_S4_vxaddsubh(rss, rtt)
11239}
11240
11241/// `Rdd32=vxaddsubh(Rss32,Rtt32):rnd:>>1:sat`
11242///
11243/// Instruction Type: S_3op
11244/// Execution Slots: SLOT23
11245#[inline(always)]
11246#[cfg_attr(test, assert_instr(vxaddsubh))]
11247#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11248pub unsafe fn Q6_P_vxaddsubh_PP_rnd_rs1_sat(rss: i64, rtt: i64) -> i64 {
11249    hexagon_S4_vxaddsubhr(rss, rtt)
11250}
11251
11252/// `Rdd32=vxaddsubw(Rss32,Rtt32):sat`
11253///
11254/// Instruction Type: S_3op
11255/// Execution Slots: SLOT23
11256#[inline(always)]
11257#[cfg_attr(test, assert_instr(vxaddsubw))]
11258#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11259pub unsafe fn Q6_P_vxaddsubw_PP_sat(rss: i64, rtt: i64) -> i64 {
11260    hexagon_S4_vxaddsubw(rss, rtt)
11261}
11262
11263/// `Rdd32=vxsubaddh(Rss32,Rtt32):sat`
11264///
11265/// Instruction Type: S_3op
11266/// Execution Slots: SLOT23
11267#[inline(always)]
11268#[cfg_attr(test, assert_instr(vxsubaddh))]
11269#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11270pub unsafe fn Q6_P_vxsubaddh_PP_sat(rss: i64, rtt: i64) -> i64 {
11271    hexagon_S4_vxsubaddh(rss, rtt)
11272}
11273
11274/// `Rdd32=vxsubaddh(Rss32,Rtt32):rnd:>>1:sat`
11275///
11276/// Instruction Type: S_3op
11277/// Execution Slots: SLOT23
11278#[inline(always)]
11279#[cfg_attr(test, assert_instr(vxsubaddh))]
11280#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11281pub unsafe fn Q6_P_vxsubaddh_PP_rnd_rs1_sat(rss: i64, rtt: i64) -> i64 {
11282    hexagon_S4_vxsubaddhr(rss, rtt)
11283}
11284
11285/// `Rdd32=vxsubaddw(Rss32,Rtt32):sat`
11286///
11287/// Instruction Type: S_3op
11288/// Execution Slots: SLOT23
11289#[inline(always)]
11290#[cfg_attr(test, assert_instr(vxsubaddw))]
11291#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11292pub unsafe fn Q6_P_vxsubaddw_PP_sat(rss: i64, rtt: i64) -> i64 {
11293    hexagon_S4_vxsubaddw(rss, rtt)
11294}
11295
11296/// `Rd32=vasrhub(Rss32,#u4):rnd:sat`
11297///
11298/// Instruction Type: S_2op
11299/// Execution Slots: SLOT0123
11300#[inline(always)]
11301#[rustc_legacy_const_generics(1)]
11302#[cfg_attr(test, assert_instr(vasrhub, IU4 = 0))]
11303#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11304pub unsafe fn Q6_R_vasrhub_PI_rnd_sat<const IU4: u32>(rss: i64) -> i32 {
11305    static_assert_uimm_bits!(IU4, 4);
11306    hexagon_S5_asrhub_rnd_sat_goodsyntax(rss, IU4 as i32)
11307}
11308
11309/// `Rd32=vasrhub(Rss32,#u4):sat`
11310///
11311/// Instruction Type: S_2op
11312/// Execution Slots: SLOT23
11313#[inline(always)]
11314#[rustc_legacy_const_generics(1)]
11315#[cfg_attr(test, assert_instr(vasrhub, IU4 = 0))]
11316#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11317pub unsafe fn Q6_R_vasrhub_PI_sat<const IU4: u32>(rss: i64) -> i32 {
11318    static_assert_uimm_bits!(IU4, 4);
11319    hexagon_S5_asrhub_sat(rss, IU4 as i32)
11320}
11321
11322/// `Rd32=popcount(Rss32)`
11323///
11324/// Instruction Type: S_2op
11325/// Execution Slots: SLOT23
11326#[inline(always)]
11327#[cfg_attr(test, assert_instr(popcount))]
11328#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11329pub unsafe fn Q6_R_popcount_P(rss: i64) -> i32 {
11330    hexagon_S5_popcountp(rss)
11331}
11332
11333/// `Rdd32=vasrh(Rss32,#u4):rnd`
11334///
11335/// Instruction Type: S_2op
11336/// Execution Slots: SLOT0123
11337#[inline(always)]
11338#[rustc_legacy_const_generics(1)]
11339#[cfg_attr(test, assert_instr(vasrh, IU4 = 0))]
11340#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11341pub unsafe fn Q6_P_vasrh_PI_rnd<const IU4: u32>(rss: i64) -> i64 {
11342    static_assert_uimm_bits!(IU4, 4);
11343    hexagon_S5_vasrhrnd_goodsyntax(rss, IU4 as i32)
11344}
11345
11346/// `dccleana(Rs32)`
11347///
11348/// Instruction Type: ST
11349/// Execution Slots: SLOT0
11350#[inline(always)]
11351#[cfg_attr(test, assert_instr(dccleana))]
11352#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11353pub unsafe fn Q6_dccleana_A(rs: i32) {
11354    hexagon_Y2_dccleana(rs)
11355}
11356
11357/// `dccleaninva(Rs32)`
11358///
11359/// Instruction Type: ST
11360/// Execution Slots: SLOT0
11361#[inline(always)]
11362#[cfg_attr(test, assert_instr(dccleaninva))]
11363#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11364pub unsafe fn Q6_dccleaninva_A(rs: i32) {
11365    hexagon_Y2_dccleaninva(rs)
11366}
11367
11368/// `dcfetch(Rs32)`
11369///
11370/// Instruction Type: MAPPING
11371/// Execution Slots: SLOT0123
11372#[inline(always)]
11373#[cfg_attr(test, assert_instr(dcfetch))]
11374#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11375pub unsafe fn Q6_dcfetch_A(rs: i32) {
11376    hexagon_Y2_dcfetch(rs)
11377}
11378
11379/// `dcinva(Rs32)`
11380///
11381/// Instruction Type: ST
11382/// Execution Slots: SLOT0
11383#[inline(always)]
11384#[cfg_attr(test, assert_instr(dcinva))]
11385#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11386pub unsafe fn Q6_dcinva_A(rs: i32) {
11387    hexagon_Y2_dcinva(rs)
11388}
11389
11390/// `dczeroa(Rs32)`
11391///
11392/// Instruction Type: ST
11393/// Execution Slots: SLOT0
11394#[inline(always)]
11395#[cfg_attr(test, assert_instr(dczeroa))]
11396#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11397pub unsafe fn Q6_dczeroa_A(rs: i32) {
11398    hexagon_Y2_dczeroa(rs)
11399}
11400
11401/// `l2fetch(Rs32,Rt32)`
11402///
11403/// Instruction Type: ST
11404/// Execution Slots: SLOT0
11405#[inline(always)]
11406#[cfg_attr(test, assert_instr(l2fetch))]
11407#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11408pub unsafe fn Q6_l2fetch_AR(rs: i32, rt: i32) {
11409    hexagon_Y4_l2fetch(rs, rt)
11410}
11411
11412/// `l2fetch(Rs32,Rtt32)`
11413///
11414/// Instruction Type: ST
11415/// Execution Slots: SLOT0
11416#[inline(always)]
11417#[cfg_attr(test, assert_instr(l2fetch))]
11418#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11419pub unsafe fn Q6_l2fetch_AP(rs: i32, rtt: i64) {
11420    hexagon_Y5_l2fetch(rs, rtt)
11421}
11422
11423/// `Rdd32=rol(Rss32,#u6)`
11424///
11425/// Instruction Type: S_2op
11426/// Execution Slots: SLOT23
11427/// Requires: V60
11428#[inline(always)]
11429#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))]
11430#[rustc_legacy_const_generics(1)]
11431#[cfg_attr(test, assert_instr(rol, IU6 = 0))]
11432#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11433pub unsafe fn Q6_P_rol_PI<const IU6: u32>(rss: i64) -> i64 {
11434    static_assert_uimm_bits!(IU6, 6);
11435    hexagon_S6_rol_i_p(rss, IU6 as i32)
11436}
11437
11438/// `Rxx32+=rol(Rss32,#u6)`
11439///
11440/// Instruction Type: S_2op
11441/// Execution Slots: SLOT23
11442/// Requires: V60
11443#[inline(always)]
11444#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))]
11445#[rustc_legacy_const_generics(2)]
11446#[cfg_attr(test, assert_instr(rol, IU6 = 0))]
11447#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11448pub unsafe fn Q6_P_rolacc_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
11449    static_assert_uimm_bits!(IU6, 6);
11450    hexagon_S6_rol_i_p_acc(rxx, rss, IU6 as i32)
11451}
11452
11453/// `Rxx32&=rol(Rss32,#u6)`
11454///
11455/// Instruction Type: S_2op
11456/// Execution Slots: SLOT23
11457/// Requires: V60
11458#[inline(always)]
11459#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))]
11460#[rustc_legacy_const_generics(2)]
11461#[cfg_attr(test, assert_instr(rol, IU6 = 0))]
11462#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11463pub unsafe fn Q6_P_roland_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
11464    static_assert_uimm_bits!(IU6, 6);
11465    hexagon_S6_rol_i_p_and(rxx, rss, IU6 as i32)
11466}
11467
11468/// `Rxx32-=rol(Rss32,#u6)`
11469///
11470/// Instruction Type: S_2op
11471/// Execution Slots: SLOT23
11472/// Requires: V60
11473#[inline(always)]
11474#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))]
11475#[rustc_legacy_const_generics(2)]
11476#[cfg_attr(test, assert_instr(rol, IU6 = 0))]
11477#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11478pub unsafe fn Q6_P_rolnac_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
11479    static_assert_uimm_bits!(IU6, 6);
11480    hexagon_S6_rol_i_p_nac(rxx, rss, IU6 as i32)
11481}
11482
11483/// `Rxx32|=rol(Rss32,#u6)`
11484///
11485/// Instruction Type: S_2op
11486/// Execution Slots: SLOT23
11487/// Requires: V60
11488#[inline(always)]
11489#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))]
11490#[rustc_legacy_const_generics(2)]
11491#[cfg_attr(test, assert_instr(rol, IU6 = 0))]
11492#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11493pub unsafe fn Q6_P_rolor_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
11494    static_assert_uimm_bits!(IU6, 6);
11495    hexagon_S6_rol_i_p_or(rxx, rss, IU6 as i32)
11496}
11497
11498/// `Rxx32^=rol(Rss32,#u6)`
11499///
11500/// Instruction Type: S_2op
11501/// Execution Slots: SLOT23
11502/// Requires: V60
11503#[inline(always)]
11504#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))]
11505#[rustc_legacy_const_generics(2)]
11506#[cfg_attr(test, assert_instr(rol, IU6 = 0))]
11507#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11508pub unsafe fn Q6_P_rolxacc_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
11509    static_assert_uimm_bits!(IU6, 6);
11510    hexagon_S6_rol_i_p_xacc(rxx, rss, IU6 as i32)
11511}
11512
11513/// `Rd32=rol(Rs32,#u5)`
11514///
11515/// Instruction Type: S_2op
11516/// Execution Slots: SLOT23
11517/// Requires: V60
11518#[inline(always)]
11519#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))]
11520#[rustc_legacy_const_generics(1)]
11521#[cfg_attr(test, assert_instr(rol, IU5 = 0))]
11522#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11523pub unsafe fn Q6_R_rol_RI<const IU5: u32>(rs: i32) -> i32 {
11524    static_assert_uimm_bits!(IU5, 5);
11525    hexagon_S6_rol_i_r(rs, IU5 as i32)
11526}
11527
11528/// `Rx32+=rol(Rs32,#u5)`
11529///
11530/// Instruction Type: S_2op
11531/// Execution Slots: SLOT23
11532/// Requires: V60
11533#[inline(always)]
11534#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))]
11535#[rustc_legacy_const_generics(2)]
11536#[cfg_attr(test, assert_instr(rol, IU5 = 0))]
11537#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11538pub unsafe fn Q6_R_rolacc_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
11539    static_assert_uimm_bits!(IU5, 5);
11540    hexagon_S6_rol_i_r_acc(rx, rs, IU5 as i32)
11541}
11542
11543/// `Rx32&=rol(Rs32,#u5)`
11544///
11545/// Instruction Type: S_2op
11546/// Execution Slots: SLOT23
11547/// Requires: V60
11548#[inline(always)]
11549#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))]
11550#[rustc_legacy_const_generics(2)]
11551#[cfg_attr(test, assert_instr(rol, IU5 = 0))]
11552#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11553pub unsafe fn Q6_R_roland_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
11554    static_assert_uimm_bits!(IU5, 5);
11555    hexagon_S6_rol_i_r_and(rx, rs, IU5 as i32)
11556}
11557
11558/// `Rx32-=rol(Rs32,#u5)`
11559///
11560/// Instruction Type: S_2op
11561/// Execution Slots: SLOT23
11562/// Requires: V60
11563#[inline(always)]
11564#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))]
11565#[rustc_legacy_const_generics(2)]
11566#[cfg_attr(test, assert_instr(rol, IU5 = 0))]
11567#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11568pub unsafe fn Q6_R_rolnac_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
11569    static_assert_uimm_bits!(IU5, 5);
11570    hexagon_S6_rol_i_r_nac(rx, rs, IU5 as i32)
11571}
11572
11573/// `Rx32|=rol(Rs32,#u5)`
11574///
11575/// Instruction Type: S_2op
11576/// Execution Slots: SLOT23
11577/// Requires: V60
11578#[inline(always)]
11579#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))]
11580#[rustc_legacy_const_generics(2)]
11581#[cfg_attr(test, assert_instr(rol, IU5 = 0))]
11582#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11583pub unsafe fn Q6_R_rolor_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
11584    static_assert_uimm_bits!(IU5, 5);
11585    hexagon_S6_rol_i_r_or(rx, rs, IU5 as i32)
11586}
11587
11588/// `Rx32^=rol(Rs32,#u5)`
11589///
11590/// Instruction Type: S_2op
11591/// Execution Slots: SLOT23
11592/// Requires: V60
11593#[inline(always)]
11594#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))]
11595#[rustc_legacy_const_generics(2)]
11596#[cfg_attr(test, assert_instr(rol, IU5 = 0))]
11597#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11598pub unsafe fn Q6_R_rolxacc_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
11599    static_assert_uimm_bits!(IU5, 5);
11600    hexagon_S6_rol_i_r_xacc(rx, rs, IU5 as i32)
11601}
11602
11603/// `Rdd32=vabsdiffb(Rtt32,Rss32)`
11604///
11605/// Instruction Type: M
11606/// Execution Slots: SLOT23
11607/// Requires: V62
11608#[inline(always)]
11609#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v62"))]
11610#[cfg_attr(test, assert_instr(vabsdiffb))]
11611#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11612pub unsafe fn Q6_P_vabsdiffb_PP(rtt: i64, rss: i64) -> i64 {
11613    hexagon_M6_vabsdiffb(rtt, rss)
11614}
11615
11616/// `Rdd32=vabsdiffub(Rtt32,Rss32)`
11617///
11618/// Instruction Type: M
11619/// Execution Slots: SLOT23
11620/// Requires: V62
11621#[inline(always)]
11622#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v62"))]
11623#[cfg_attr(test, assert_instr(vabsdiffub))]
11624#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11625pub unsafe fn Q6_P_vabsdiffub_PP(rtt: i64, rss: i64) -> i64 {
11626    hexagon_M6_vabsdiffub(rtt, rss)
11627}
11628
11629/// `Rdd32=vsplatb(Rs32)`
11630///
11631/// Instruction Type: S_2op
11632/// Execution Slots: SLOT23
11633/// Requires: V62
11634#[inline(always)]
11635#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v62"))]
11636#[cfg_attr(test, assert_instr(vsplatb))]
11637#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11638pub unsafe fn Q6_P_vsplatb_R(rs: i32) -> i64 {
11639    hexagon_S6_vsplatrbp(rs)
11640}
11641
11642/// `Rdd32=vtrunehb(Rss32,Rtt32)`
11643///
11644/// Instruction Type: S_3op
11645/// Execution Slots: SLOT23
11646/// Requires: V62
11647#[inline(always)]
11648#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v62"))]
11649#[cfg_attr(test, assert_instr(vtrunehb))]
11650#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11651pub unsafe fn Q6_P_vtrunehb_PP(rss: i64, rtt: i64) -> i64 {
11652    hexagon_S6_vtrunehb_ppp(rss, rtt)
11653}
11654
11655/// `Rdd32=vtrunohb(Rss32,Rtt32)`
11656///
11657/// Instruction Type: S_3op
11658/// Execution Slots: SLOT23
11659/// Requires: V62
11660#[inline(always)]
11661#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v62"))]
11662#[cfg_attr(test, assert_instr(vtrunohb))]
11663#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11664pub unsafe fn Q6_P_vtrunohb_PP(rss: i64, rtt: i64) -> i64 {
11665    hexagon_S6_vtrunohb_ppp(rss, rtt)
11666}
11667
11668/// `Pd4=!any8(vcmpb.eq(Rss32,Rtt32))`
11669///
11670/// Instruction Type: ALU64
11671/// Execution Slots: SLOT23
11672/// Requires: V65
11673#[inline(always)]
11674#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v65"))]
11675#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11676pub unsafe fn Q6_p_not_any8_vcmpb_eq_PP(rss: i64, rtt: i64) -> i32 {
11677    hexagon_A6_vcmpbeq_notany(rss, rtt)
11678}
11679
11680/// `Rdd32=dfadd(Rss32,Rtt32)`
11681///
11682/// Instruction Type: M
11683/// Execution Slots: SLOT23
11684/// Requires: V66
11685#[inline(always)]
11686#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v66"))]
11687#[cfg_attr(test, assert_instr(dfadd))]
11688#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11689pub unsafe fn Q6_P_dfadd_PP(rss: f64, rtt: f64) -> f64 {
11690    hexagon_F2_dfadd(rss, rtt)
11691}
11692
11693/// `Rdd32=dfsub(Rss32,Rtt32)`
11694///
11695/// Instruction Type: M
11696/// Execution Slots: SLOT23
11697/// Requires: V66
11698#[inline(always)]
11699#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v66"))]
11700#[cfg_attr(test, assert_instr(dfsub))]
11701#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11702pub unsafe fn Q6_P_dfsub_PP(rss: f64, rtt: f64) -> f64 {
11703    hexagon_F2_dfsub(rss, rtt)
11704}
11705
11706/// `Rx32-=mpyi(Rs32,Rt32)`
11707///
11708/// Instruction Type: M
11709/// Execution Slots: SLOT23
11710/// Requires: V66
11711#[inline(always)]
11712#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v66"))]
11713#[cfg_attr(test, assert_instr(mpyi))]
11714#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11715pub unsafe fn Q6_R_mpyinac_RR(rx: i32, rs: i32, rt: i32) -> i32 {
11716    hexagon_M2_mnaci(rx, rs, rt)
11717}
11718
11719/// `Rd32=mask(#u5,#U5)`
11720///
11721/// Instruction Type: S_2op
11722/// Execution Slots: SLOT23
11723/// Requires: V66
11724#[inline(always)]
11725#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v66"))]
11726#[rustc_legacy_const_generics(0, 1)]
11727#[cfg_attr(test, assert_instr(mask, IU5 = 0, IU5_2 = 0))]
11728#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11729pub unsafe fn Q6_R_mask_II<const IU5: u32, const IU5_2: u32>() -> i32 {
11730    static_assert_uimm_bits!(IU5, 5);
11731    static_assert_uimm_bits!(IU5_2, 5);
11732    hexagon_S2_mask(IU5 as i32, IU5_2 as i32)
11733}
11734
11735/// `Rd32=clip(Rs32,#u5)`
11736///
11737/// Instruction Type: S_2op
11738/// Execution Slots: SLOT23
11739/// Requires: V67, Audio
11740#[inline(always)]
11741#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
11742#[rustc_legacy_const_generics(1)]
11743#[cfg_attr(test, assert_instr(clip, IU5 = 0))]
11744#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11745pub unsafe fn Q6_R_clip_RI<const IU5: u32>(rs: i32) -> i32 {
11746    static_assert_uimm_bits!(IU5, 5);
11747    hexagon_A7_clip(rs, IU5 as i32)
11748}
11749
11750/// `Rdd32=cround(Rss32,#u6)`
11751///
11752/// Instruction Type: S_2op
11753/// Execution Slots: SLOT23
11754/// Requires: V67, Audio
11755#[inline(always)]
11756#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
11757#[rustc_legacy_const_generics(1)]
11758#[cfg_attr(test, assert_instr(cround, IU6 = 0))]
11759#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11760pub unsafe fn Q6_P_cround_PI<const IU6: u32>(rss: i64) -> i64 {
11761    static_assert_uimm_bits!(IU6, 6);
11762    hexagon_A7_croundd_ri(rss, IU6 as i32)
11763}
11764
11765/// `Rdd32=cround(Rss32,Rt32)`
11766///
11767/// Instruction Type: S_3op
11768/// Execution Slots: SLOT23
11769/// Requires: V67, Audio
11770#[inline(always)]
11771#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
11772#[cfg_attr(test, assert_instr(cround))]
11773#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11774pub unsafe fn Q6_P_cround_PR(rss: i64, rt: i32) -> i64 {
11775    hexagon_A7_croundd_rr(rss, rt)
11776}
11777
11778/// `Rdd32=vclip(Rss32,#u5)`
11779///
11780/// Instruction Type: S_2op
11781/// Execution Slots: SLOT23
11782/// Requires: V67, Audio
11783#[inline(always)]
11784#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
11785#[rustc_legacy_const_generics(1)]
11786#[cfg_attr(test, assert_instr(vclip, IU5 = 0))]
11787#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11788pub unsafe fn Q6_P_vclip_PI<const IU5: u32>(rss: i64) -> i64 {
11789    static_assert_uimm_bits!(IU5, 5);
11790    hexagon_A7_vclip(rss, IU5 as i32)
11791}
11792
11793/// `Rdd32=dfmax(Rss32,Rtt32)`
11794///
11795/// Instruction Type: M
11796/// Execution Slots: SLOT23
11797/// Requires: V67
11798#[inline(always)]
11799#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67"))]
11800#[cfg_attr(test, assert_instr(dfmax))]
11801#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11802pub unsafe fn Q6_P_dfmax_PP(rss: f64, rtt: f64) -> f64 {
11803    hexagon_F2_dfmax(rss, rtt)
11804}
11805
11806/// `Rdd32=dfmin(Rss32,Rtt32)`
11807///
11808/// Instruction Type: M
11809/// Execution Slots: SLOT23
11810/// Requires: V67
11811#[inline(always)]
11812#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67"))]
11813#[cfg_attr(test, assert_instr(dfmin))]
11814#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11815pub unsafe fn Q6_P_dfmin_PP(rss: f64, rtt: f64) -> f64 {
11816    hexagon_F2_dfmin(rss, rtt)
11817}
11818
11819/// `Rdd32=dfmpyfix(Rss32,Rtt32)`
11820///
11821/// Instruction Type: M
11822/// Execution Slots: SLOT23
11823/// Requires: V67
11824#[inline(always)]
11825#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67"))]
11826#[cfg_attr(test, assert_instr(dfmpyfix))]
11827#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11828pub unsafe fn Q6_P_dfmpyfix_PP(rss: f64, rtt: f64) -> f64 {
11829    hexagon_F2_dfmpyfix(rss, rtt)
11830}
11831
11832/// `Rxx32+=dfmpyhh(Rss32,Rtt32)`
11833///
11834/// Instruction Type: M
11835/// Execution Slots: SLOT23
11836/// Requires: V67
11837#[inline(always)]
11838#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67"))]
11839#[cfg_attr(test, assert_instr(dfmpyhh))]
11840#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11841pub unsafe fn Q6_P_dfmpyhhacc_PP(rxx: f64, rss: f64, rtt: f64) -> f64 {
11842    hexagon_F2_dfmpyhh(rxx, rss, rtt)
11843}
11844
11845/// `Rxx32+=dfmpylh(Rss32,Rtt32)`
11846///
11847/// Instruction Type: M
11848/// Execution Slots: SLOT23
11849/// Requires: V67
11850#[inline(always)]
11851#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67"))]
11852#[cfg_attr(test, assert_instr(dfmpylh))]
11853#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11854pub unsafe fn Q6_P_dfmpylhacc_PP(rxx: f64, rss: f64, rtt: f64) -> f64 {
11855    hexagon_F2_dfmpylh(rxx, rss, rtt)
11856}
11857
11858/// `Rdd32=dfmpyll(Rss32,Rtt32)`
11859///
11860/// Instruction Type: M
11861/// Execution Slots: SLOT23
11862/// Requires: V67
11863#[inline(always)]
11864#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67"))]
11865#[cfg_attr(test, assert_instr(dfmpyll))]
11866#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11867pub unsafe fn Q6_P_dfmpyll_PP(rss: f64, rtt: f64) -> f64 {
11868    hexagon_F2_dfmpyll(rss, rtt)
11869}
11870
11871/// `Rdd32=cmpyiw(Rss32,Rtt32)`
11872///
11873/// Instruction Type: M
11874/// Execution Slots: SLOT3
11875/// Requires: V67, Audio
11876#[inline(always)]
11877#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
11878#[cfg_attr(test, assert_instr(cmpyiw))]
11879#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11880pub unsafe fn Q6_P_cmpyiw_PP(rss: i64, rtt: i64) -> i64 {
11881    hexagon_M7_dcmpyiw(rss, rtt)
11882}
11883
11884/// `Rxx32+=cmpyiw(Rss32,Rtt32)`
11885///
11886/// Instruction Type: M
11887/// Execution Slots: SLOT3
11888/// Requires: V67, Audio
11889#[inline(always)]
11890#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
11891#[cfg_attr(test, assert_instr(cmpyiw))]
11892#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11893pub unsafe fn Q6_P_cmpyiwacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
11894    hexagon_M7_dcmpyiw_acc(rxx, rss, rtt)
11895}
11896
11897/// `Rdd32=cmpyiw(Rss32,Rtt32*)`
11898///
11899/// Instruction Type: M
11900/// Execution Slots: SLOT3
11901/// Requires: V67, Audio
11902#[inline(always)]
11903#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
11904#[cfg_attr(test, assert_instr(cmpyiw))]
11905#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11906pub unsafe fn Q6_P_cmpyiw_PP_conj(rss: i64, rtt: i64) -> i64 {
11907    hexagon_M7_dcmpyiwc(rss, rtt)
11908}
11909
11910/// `Rxx32+=cmpyiw(Rss32,Rtt32*)`
11911///
11912/// Instruction Type: M
11913/// Execution Slots: SLOT3
11914/// Requires: V67, Audio
11915#[inline(always)]
11916#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
11917#[cfg_attr(test, assert_instr(cmpyiw))]
11918#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11919pub unsafe fn Q6_P_cmpyiwacc_PP_conj(rxx: i64, rss: i64, rtt: i64) -> i64 {
11920    hexagon_M7_dcmpyiwc_acc(rxx, rss, rtt)
11921}
11922
11923/// `Rdd32=cmpyrw(Rss32,Rtt32)`
11924///
11925/// Instruction Type: M
11926/// Execution Slots: SLOT3
11927/// Requires: V67, Audio
11928#[inline(always)]
11929#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
11930#[cfg_attr(test, assert_instr(cmpyrw))]
11931#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11932pub unsafe fn Q6_P_cmpyrw_PP(rss: i64, rtt: i64) -> i64 {
11933    hexagon_M7_dcmpyrw(rss, rtt)
11934}
11935
11936/// `Rxx32+=cmpyrw(Rss32,Rtt32)`
11937///
11938/// Instruction Type: M
11939/// Execution Slots: SLOT3
11940/// Requires: V67, Audio
11941#[inline(always)]
11942#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
11943#[cfg_attr(test, assert_instr(cmpyrw))]
11944#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11945pub unsafe fn Q6_P_cmpyrwacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
11946    hexagon_M7_dcmpyrw_acc(rxx, rss, rtt)
11947}
11948
11949/// `Rdd32=cmpyrw(Rss32,Rtt32*)`
11950///
11951/// Instruction Type: M
11952/// Execution Slots: SLOT3
11953/// Requires: V67, Audio
11954#[inline(always)]
11955#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
11956#[cfg_attr(test, assert_instr(cmpyrw))]
11957#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11958pub unsafe fn Q6_P_cmpyrw_PP_conj(rss: i64, rtt: i64) -> i64 {
11959    hexagon_M7_dcmpyrwc(rss, rtt)
11960}
11961
11962/// `Rxx32+=cmpyrw(Rss32,Rtt32*)`
11963///
11964/// Instruction Type: M
11965/// Execution Slots: SLOT3
11966/// Requires: V67, Audio
11967#[inline(always)]
11968#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
11969#[cfg_attr(test, assert_instr(cmpyrw))]
11970#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11971pub unsafe fn Q6_P_cmpyrwacc_PP_conj(rxx: i64, rss: i64, rtt: i64) -> i64 {
11972    hexagon_M7_dcmpyrwc_acc(rxx, rss, rtt)
11973}
11974
11975/// `Rdd32=vdmpyw(Rss32,Rtt32)`
11976///
11977/// Instruction Type: M
11978/// Execution Slots: SLOT3
11979/// Requires: V67, Audio
11980#[inline(always)]
11981#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
11982#[cfg_attr(test, assert_instr(vdmpyw))]
11983#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11984pub unsafe fn Q6_P_vdmpyw_PP(rss: i64, rtt: i64) -> i64 {
11985    hexagon_M7_vdmpy(rss, rtt)
11986}
11987
11988/// `Rxx32+=vdmpyw(Rss32,Rtt32)`
11989///
11990/// Instruction Type: M
11991/// Execution Slots: SLOT3
11992/// Requires: V67, Audio
11993#[inline(always)]
11994#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
11995#[cfg_attr(test, assert_instr(vdmpyw))]
11996#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11997pub unsafe fn Q6_P_vdmpywacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
11998    hexagon_M7_vdmpy_acc(rxx, rss, rtt)
11999}
12000
12001/// `Rd32=cmpyiw(Rss32,Rtt32):<<1:sat`
12002///
12003/// Instruction Type: M
12004/// Execution Slots: SLOT3
12005/// Requires: V67, Audio
12006#[inline(always)]
12007#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
12008#[cfg_attr(test, assert_instr(cmpyiw))]
12009#[unstable(feature = "stdarch_hexagon", issue = "151523")]
12010pub unsafe fn Q6_R_cmpyiw_PP_s1_sat(rss: i64, rtt: i64) -> i32 {
12011    hexagon_M7_wcmpyiw(rss, rtt)
12012}
12013
12014/// `Rd32=cmpyiw(Rss32,Rtt32):<<1:rnd:sat`
12015///
12016/// Instruction Type: M
12017/// Execution Slots: SLOT3
12018/// Requires: V67, Audio
12019#[inline(always)]
12020#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
12021#[cfg_attr(test, assert_instr(cmpyiw))]
12022#[unstable(feature = "stdarch_hexagon", issue = "151523")]
12023pub unsafe fn Q6_R_cmpyiw_PP_s1_rnd_sat(rss: i64, rtt: i64) -> i32 {
12024    hexagon_M7_wcmpyiw_rnd(rss, rtt)
12025}
12026
12027/// `Rd32=cmpyiw(Rss32,Rtt32*):<<1:sat`
12028///
12029/// Instruction Type: M
12030/// Execution Slots: SLOT3
12031/// Requires: V67, Audio
12032#[inline(always)]
12033#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
12034#[cfg_attr(test, assert_instr(cmpyiw))]
12035#[unstable(feature = "stdarch_hexagon", issue = "151523")]
12036pub unsafe fn Q6_R_cmpyiw_PP_conj_s1_sat(rss: i64, rtt: i64) -> i32 {
12037    hexagon_M7_wcmpyiwc(rss, rtt)
12038}
12039
12040/// `Rd32=cmpyiw(Rss32,Rtt32*):<<1:rnd:sat`
12041///
12042/// Instruction Type: M
12043/// Execution Slots: SLOT3
12044/// Requires: V67, Audio
12045#[inline(always)]
12046#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
12047#[cfg_attr(test, assert_instr(cmpyiw))]
12048#[unstable(feature = "stdarch_hexagon", issue = "151523")]
12049pub unsafe fn Q6_R_cmpyiw_PP_conj_s1_rnd_sat(rss: i64, rtt: i64) -> i32 {
12050    hexagon_M7_wcmpyiwc_rnd(rss, rtt)
12051}
12052
12053/// `Rd32=cmpyrw(Rss32,Rtt32):<<1:sat`
12054///
12055/// Instruction Type: M
12056/// Execution Slots: SLOT3
12057/// Requires: V67, Audio
12058#[inline(always)]
12059#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
12060#[cfg_attr(test, assert_instr(cmpyrw))]
12061#[unstable(feature = "stdarch_hexagon", issue = "151523")]
12062pub unsafe fn Q6_R_cmpyrw_PP_s1_sat(rss: i64, rtt: i64) -> i32 {
12063    hexagon_M7_wcmpyrw(rss, rtt)
12064}
12065
12066/// `Rd32=cmpyrw(Rss32,Rtt32):<<1:rnd:sat`
12067///
12068/// Instruction Type: M
12069/// Execution Slots: SLOT3
12070/// Requires: V67, Audio
12071#[inline(always)]
12072#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
12073#[cfg_attr(test, assert_instr(cmpyrw))]
12074#[unstable(feature = "stdarch_hexagon", issue = "151523")]
12075pub unsafe fn Q6_R_cmpyrw_PP_s1_rnd_sat(rss: i64, rtt: i64) -> i32 {
12076    hexagon_M7_wcmpyrw_rnd(rss, rtt)
12077}
12078
12079/// `Rd32=cmpyrw(Rss32,Rtt32*):<<1:sat`
12080///
12081/// Instruction Type: M
12082/// Execution Slots: SLOT3
12083/// Requires: V67, Audio
12084#[inline(always)]
12085#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
12086#[cfg_attr(test, assert_instr(cmpyrw))]
12087#[unstable(feature = "stdarch_hexagon", issue = "151523")]
12088pub unsafe fn Q6_R_cmpyrw_PP_conj_s1_sat(rss: i64, rtt: i64) -> i32 {
12089    hexagon_M7_wcmpyrwc(rss, rtt)
12090}
12091
12092/// `Rd32=cmpyrw(Rss32,Rtt32*):<<1:rnd:sat`
12093///
12094/// Instruction Type: M
12095/// Execution Slots: SLOT3
12096/// Requires: V67, Audio
12097#[inline(always)]
12098#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
12099#[cfg_attr(test, assert_instr(cmpyrw))]
12100#[unstable(feature = "stdarch_hexagon", issue = "151523")]
12101pub unsafe fn Q6_R_cmpyrw_PP_conj_s1_rnd_sat(rss: i64, rtt: i64) -> i32 {
12102    hexagon_M7_wcmpyrwc_rnd(rss, rtt)
12103}
12104
12105/// `dmlink(Rs32,Rt32)`
12106///
12107/// Instruction Type: ST
12108/// Execution Slots: SLOT0
12109/// Requires: V68
12110#[inline(always)]
12111#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v68"))]
12112#[cfg_attr(test, assert_instr(dmlink))]
12113#[unstable(feature = "stdarch_hexagon", issue = "151523")]
12114pub unsafe fn Q6_dmlink_AA(rs: i32, rt: i32) {
12115    hexagon_Y6_dmlink(rs, rt)
12116}
12117
12118/// `Rd32=dmpause`
12119///
12120/// Instruction Type: ST
12121/// Execution Slots: SLOT0
12122/// Requires: V68
12123#[inline(always)]
12124#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v68"))]
12125#[cfg_attr(test, assert_instr(dmpause))]
12126#[unstable(feature = "stdarch_hexagon", issue = "151523")]
12127pub unsafe fn Q6_R_dmpause() -> i32 {
12128    hexagon_Y6_dmpause()
12129}
12130
12131/// `Rd32=dmpoll`
12132///
12133/// Instruction Type: ST
12134/// Execution Slots: SLOT0
12135/// Requires: V68
12136#[inline(always)]
12137#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v68"))]
12138#[cfg_attr(test, assert_instr(dmpoll))]
12139#[unstable(feature = "stdarch_hexagon", issue = "151523")]
12140pub unsafe fn Q6_R_dmpoll() -> i32 {
12141    hexagon_Y6_dmpoll()
12142}
12143
12144/// `dmresume(Rs32)`
12145///
12146/// Instruction Type: ST
12147/// Execution Slots: SLOT0
12148/// Requires: V68
12149#[inline(always)]
12150#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v68"))]
12151#[cfg_attr(test, assert_instr(dmresume))]
12152#[unstable(feature = "stdarch_hexagon", issue = "151523")]
12153pub unsafe fn Q6_dmresume_A(rs: i32) {
12154    hexagon_Y6_dmresume(rs)
12155}
12156
12157/// `dmstart(Rs32)`
12158///
12159/// Instruction Type: ST
12160/// Execution Slots: SLOT0
12161/// Requires: V68
12162#[inline(always)]
12163#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v68"))]
12164#[cfg_attr(test, assert_instr(dmstart))]
12165#[unstable(feature = "stdarch_hexagon", issue = "151523")]
12166pub unsafe fn Q6_dmstart_A(rs: i32) {
12167    hexagon_Y6_dmstart(rs)
12168}
12169
12170/// `Rd32=dmwait`
12171///
12172/// Instruction Type: ST
12173/// Execution Slots: SLOT0
12174/// Requires: V68
12175#[inline(always)]
12176#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v68"))]
12177#[cfg_attr(test, assert_instr(dmwait))]
12178#[unstable(feature = "stdarch_hexagon", issue = "151523")]
12179pub unsafe fn Q6_R_dmwait() -> i32 {
12180    hexagon_Y6_dmwait()
12181}
core/stdarch/crates/core_arch/src/hexagon/scalar.rs

core/stdarch/crates/core_arch/src/hexagon/
scalar.rs
