core/stdarch/crates/core_arch/src/aarch64/
tme.rs

1//! ARM's Transactional Memory Extensions (TME).
2//!
3//! This CPU feature is available on Aarch64 - A architecture profile.
4//! This feature is in the non-neon feature set. TME specific vendor documentation can
5//! be found [TME Intrinsics Introduction][tme_intrinsics_intro].
6//!
7//! The reference is [ACLE Q4 2019][acle_q4_2019_ref].
8//!
9//! ACLE has a section for TME extensions and state masks for aborts and failure codes.
10//! [ARM A64 Architecture Register Datasheet][a_profile_future] also describes possible failure code scenarios.
11//!
12//! [acle_q4_2019_ref]: https://static.docs.arm.com/101028/0010/ACLE_2019Q4_release-0010.pdf
13//! [tme_intrinsics_intro]: https://developer.arm.com/docs/101028/0010/transactional-memory-extension-tme-intrinsics
14//! [llvm_aarch64_int]: https://github.com/llvm/llvm-project/commit/a36d31478c182903523e04eb271bbf102bfab2cc#diff-ff24e1c35f4d54f1110ce5d90c709319R626-R646
15//! [a_profile_future]: https://static.docs.arm.com/ddi0601/a/SysReg_xml_futureA-2019-04.pdf?_ga=2.116560387.441514988.1590524918-1110153136.1588469296
16
17#[cfg(test)]
18use stdarch_test::assert_instr;
19
20extern "unadjusted" {
21    #[link_name = "llvm.aarch64.tstart"]
22    fn aarch64_tstart() -> u64;
23    #[link_name = "llvm.aarch64.tcommit"]
24    fn aarch64_tcommit();
25    #[link_name = "llvm.aarch64.tcancel"]
26    fn aarch64_tcancel(imm0: u64);
27    #[link_name = "llvm.aarch64.ttest"]
28    fn aarch64_ttest() -> u64;
29}
30
31/// Transaction successfully started.
32#[unstable(feature = "stdarch_aarch64_tme", issue = "117216")]
33pub const _TMSTART_SUCCESS: u64 = 0x00_u64;
34
35/// Extraction mask for failure reason
36#[unstable(feature = "stdarch_aarch64_tme", issue = "117216")]
37pub const _TMFAILURE_REASON: u64 = 0x00007FFF_u64;
38
39/// Transaction retry is possible.
40#[unstable(feature = "stdarch_aarch64_tme", issue = "117216")]
41pub const _TMFAILURE_RTRY: u64 = 1 << 15;
42
43/// Transaction executed a TCANCEL instruction
44#[unstable(feature = "stdarch_aarch64_tme", issue = "117216")]
45pub const _TMFAILURE_CNCL: u64 = 1 << 16;
46
47/// Transaction aborted because a conflict occurred
48#[unstable(feature = "stdarch_aarch64_tme", issue = "117216")]
49pub const _TMFAILURE_MEM: u64 = 1 << 17;
50
51/// Fallback error type for any other reason
52#[unstable(feature = "stdarch_aarch64_tme", issue = "117216")]
53pub const _TMFAILURE_IMP: u64 = 1 << 18;
54
55/// Transaction aborted because a non-permissible operation was attempted
56#[unstable(feature = "stdarch_aarch64_tme", issue = "117216")]
57pub const _TMFAILURE_ERR: u64 = 1 << 19;
58
59/// Transaction aborted due to read or write set limit was exceeded
60#[unstable(feature = "stdarch_aarch64_tme", issue = "117216")]
61pub const _TMFAILURE_SIZE: u64 = 1 << 20;
62
63/// Transaction aborted due to transactional nesting level was exceeded
64#[unstable(feature = "stdarch_aarch64_tme", issue = "117216")]
65pub const _TMFAILURE_NEST: u64 = 1 << 21;
66
67/// Transaction aborted due to a debug trap.
68#[unstable(feature = "stdarch_aarch64_tme", issue = "117216")]
69pub const _TMFAILURE_DBG: u64 = 1 << 22;
70
71/// Transaction failed from interrupt
72#[unstable(feature = "stdarch_aarch64_tme", issue = "117216")]
73pub const _TMFAILURE_INT: u64 = 1 << 23;
74
75/// Indicates a TRIVIAL version of TM is available
76#[unstable(feature = "stdarch_aarch64_tme", issue = "117216")]
77pub const _TMFAILURE_TRIVIAL: u64 = 1 << 24;
78
79// NOTE: Tests for these instructions are disabled on MSVC as dumpbin doesn't
80// understand these instructions.
81
82/// Starts a new transaction. When the transaction starts successfully the return value is 0.
83/// If the transaction fails, all state modifications are discarded and a cause of the failure
84/// is encoded in the return value.
85///
86/// [ARM TME Intrinsics](https://developer.arm.com/docs/101028/0010/transactional-memory-extension-tme-intrinsics).
87#[inline]
88#[target_feature(enable = "tme")]
89#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(tstart))]
90#[unstable(feature = "stdarch_aarch64_tme", issue = "117216")]
91pub unsafe fn __tstart() -> u64 {
92    aarch64_tstart()
93}
94
95/// Commits the current transaction. For a nested transaction, the only effect is that the
96/// transactional nesting depth is decreased. For an outer transaction, the state modifications
97/// performed transactionally are committed to the architectural state.
98///
99/// [ARM TME Intrinsics](https://developer.arm.com/docs/101028/0010/transactional-memory-extension-tme-intrinsics).
100#[inline]
101#[target_feature(enable = "tme")]
102#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(tcommit))]
103#[unstable(feature = "stdarch_aarch64_tme", issue = "117216")]
104pub unsafe fn __tcommit() {
105    aarch64_tcommit()
106}
107
108/// Cancels the current transaction and discards all state modifications that were performed transactionally.
109///
110/// [ARM TME Intrinsics](https://developer.arm.com/docs/101028/0010/transactional-memory-extension-tme-intrinsics).
111#[inline]
112#[target_feature(enable = "tme")]
113#[cfg_attr(
114    all(test, not(target_env = "msvc")),
115    assert_instr(tcancel, IMM16 = 0x0)
116)]
117#[rustc_legacy_const_generics(0)]
118#[unstable(feature = "stdarch_aarch64_tme", issue = "117216")]
119pub unsafe fn __tcancel<const IMM16: u64>() {
120    static_assert!(IMM16 <= 65535);
121    aarch64_tcancel(IMM16);
122}
123
124/// Tests if executing inside a transaction. If no transaction is currently executing,
125/// the return value is 0. Otherwise, this intrinsic returns the depth of the transaction.
126///
127/// [ARM TME Intrinsics](https://developer.arm.com/docs/101028/0010/transactional-memory-extension-tme-intrinsics).
128#[inline]
129#[target_feature(enable = "tme")]
130#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ttest))]
131#[unstable(feature = "stdarch_aarch64_tme", issue = "117216")]
132pub unsafe fn __ttest() -> u64 {
133    aarch64_ttest()
134}
135
136#[cfg(test)]
137mod tests {
138    use stdarch_test::simd_test;
139
140    use crate::core_arch::aarch64::*;
141
142    const CANCEL_CODE: u64 = (0 | (0x123 & _TMFAILURE_REASON) as u64) as u64;
143
144    #[simd_test(enable = "tme")]
145    unsafe fn test_tstart() {
146        let mut x = 0;
147        for i in 0..10 {
148            let code = tme::__tstart();
149            if code == _TMSTART_SUCCESS {
150                x += 1;
151                assert_eq!(x, i + 1);
152                break;
153            }
154            assert_eq!(x, 0);
155        }
156    }
157
158    #[simd_test(enable = "tme")]
159    unsafe fn test_tcommit() {
160        let mut x = 0;
161        for i in 0..10 {
162            let code = tme::__tstart();
163            if code == _TMSTART_SUCCESS {
164                x += 1;
165                assert_eq!(x, i + 1);
166                tme::__tcommit();
167            }
168            assert_eq!(x, i + 1);
169        }
170    }
171
172    #[simd_test(enable = "tme")]
173    unsafe fn test_tcancel() {
174        let mut x = 0;
175
176        for i in 0..10 {
177            let code = tme::__tstart();
178            if code == _TMSTART_SUCCESS {
179                x += 1;
180                assert_eq!(x, i + 1);
181                tme::__tcancel::<CANCEL_CODE>();
182                break;
183            }
184        }
185
186        assert_eq!(x, 0);
187    }
188
189    #[simd_test(enable = "tme")]
190    unsafe fn test_ttest() {
191        for _ in 0..10 {
192            let code = tme::__tstart();
193            if code == _TMSTART_SUCCESS {
194                if tme::__ttest() == 2 {
195                    tme::__tcancel::<CANCEL_CODE>();
196                    break;
197                }
198            }
199        }
200    }
201}
core/stdarch/crates/core_arch/src/aarch64/tme.rs

core/stdarch/crates/core_arch/src/aarch64/
tme.rs
