thumbv6m-none-eabi
Tier: 2
Bare-metal target for CPUs in the Armv6-M architecture family, supporting a subset of the T32 ISA.
Processors in this family include the:
See arm-none-eabi for information applicable to all
arm-none-eabi targets.
This target uses the soft-float ABI: functions which take f32 or f64 as
arguments will have those values packed into integer registers. This is the
only option because there is no FPU support in Armv6-M.
Target maintainers
- Rust Embedded Devices Working Group Cortex-M
Team,
cortex-m@teams.rust-embedded.org
Target CPU and Target Feature options
See the bare-metal Arm docs for details on how to use these flags.
Table of supported CPUs
| CPU | FPU | Target CPU | Target Features |
|---|---|---|---|
| Cortex-M0 | No | cortex-m0 | None |
| Cortex-M0+ | No | cortex-m0plus | None |
| Cortex-M1 | No | cortex-m1 | None |
Arm Cortex-M0
The target CPU option is cortex-m0.
There are no relevant feature flags, and the FPU is not available.
Arm Cortex-M0+
The target CPU option is cortex-m0plus.
There are no relevant feature flags, and the FPU is not available.
Arm Cortex-M1
The target CPU option is cortex-m1.
There are no relevant feature flags, and the FPU is not available.